Unified modeling method and storage medium of hybrid modular multilevel converter

Abstract

The application relates to a unified modeling method of a hybrid modular multilevel converter and a storage medium, wherein the method comprises the following steps: constructing a unified conduction function for a half-bridge and a full-bridge switch group of each bridge arm; constructing a unified variable resistance equivalent function based on the conduction function; performing discretization processing on capacitors in each sub-module based on a capacitor dynamic equation to obtain a sub-module capacitor Thevenin branch; performing discretization processing on inductors in the bridge arm based on an inductor dynamic equation to obtain a bridge arm inductor Thevenin branch; according to the variable resistance equivalent function and the sub-module capacitor Thevenin branch, the half-bridge sub-module Thevenin equivalent model and the full-bridge sub-module Thevenin equivalent model in normal operation, blocking and restarting states are uniformly constructed; and the half-bridge and full-bridge sub-module Thevenin equivalent model and the bridge arm inductor Thevenin branch are connected in series to obtain a bridge arm Thevenin equivalent model. Through the application, the problems of poor model reusability and weak multi-working condition adaptation capability are solved.

Description

Technical Field

[0001] This application relates to the field of electromagnetic transient simulation modeling of high voltage direct current transmission systems, and in particular to a unified modeling method and storage medium for hybrid modular multilevel converters. Background Technology

[0002] Modular multilevel converters (MMCs) have been widely used in high-voltage flexible DC transmission, renewable energy grid connection, and medium-voltage power quality management due to their advantages such as low output harmonic content, modularity and easy expansion, low voltage requirements for switching devices, and ability to achieve flexible multilevel voltage regulation. Among them, the hybrid MMC, composed of cascaded half-bridge and full-bridge submodules, retains the low cost and low loss advantages of half-bridge submodules while leveraging the reverse output voltage capability of full-bridge submodules to achieve DC fault self-clearing and fault current blocking, making it irreplaceable in high-voltage DC grid engineering. However, related technologies generally only derive equivalent formulas for single operating conditions and single submodule types, lacking a complete and unified modeling framework, resulting in poor model reusability and difficulty in simultaneously simulating multiple operating conditions such as normal operation, lockout, and restart.

[0003] Currently, no effective solution has been proposed to address the issues of poor model reusability and weak adaptability to multiple operating conditions in related technologies. Summary of the Invention

[0004] This application provides a unified modeling method and storage medium for hybrid modular multilevel converters, which at least solves the problems of poor model reusability and weak multi-condition adaptability in related technologies.

[0005] In a first aspect, embodiments of this application provide a unified modeling method for a hybrid modular multilevel converter, wherein the hybrid modular multilevel converter includes multiple bridge arms, each bridge arm including multiple half-bridge submodules and multiple full-bridge submodules; the half-bridge submodules and the full-bridge submodules are connected in series on the bridge arm; each half-bridge submodule includes multiple half-bridge switch groups; each full-bridge submodule includes multiple full-bridge switch groups; the method includes:

[0006] For each half-bridge switch group and each full-bridge switch group of each bridge arm, a unified form of conduction function is constructed;

[0007] Based on the conduction function, a unified form of variable resistance equivalent function is constructed for the half-bridge switch group and the full-bridge switch group;

[0008] Based on the preset capacitance dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized to obtain the Thevenin branch of the submodule capacitor.

[0009] Based on the preset inductance dynamic equation, the inductance in the bridge arm is discretized to obtain the Thevenin branch of the bridge arm inductance.

[0010] Based on the equivalent function of the variable resistor and the Thevenin branch of the submodule capacitor, Thevenin equivalent models of the half-bridge submodule and the full-bridge submodule under different states are uniformly constructed; the different states include normal operation state, locked state and restart state;

[0011] The Thevenin equivalent model of the half-bridge submodule, the Thevenin equivalent model of the full-bridge submodule, and the Thevenin branch of the bridge arm inductor are connected in series to obtain the Thevenin equivalent model of the bridge arm.

[0012] In some embodiments, the expression for the conduction function is:

[0013] ;

[0014] Where k is the switch group number; The conduction function coefficients of the k-th switch group; is the gate drive signal for the k-th switch group; s is the bridge arm current direction indicator; The conduction characteristic coefficients of the submodule; =1 indicates that when s=1, the diode in the k-th switch group is forward-biased; =-1 indicates that when s=-1, the diode in the k-th switch group is forward-biased.

[0015] In some embodiments, the expression for the equivalent function of the variable resistance is:

[0016] ;

[0017] in, The variable resistor is the k-th switch group; This is the resistance value when the switch group is turned on; This is the resistance value when the switch group is turned off.

[0018] In some embodiments, the discretization of the capacitors in the half-bridge submodule and the full-bridge submodule based on a preset capacitance dynamic equation to obtain the Thevenin branch of the submodule capacitor includes:

[0019] The conduction characteristic coefficients of the half-bridge submodule are obtained based on the gate drive signal and the direction of the bridge arm current of the half-bridge switch group.

[0020] The conduction characteristic coefficients of the full-bridge submodules are obtained based on the gate drive signal of the full-bridge switch group and the direction of the bridge arm current.

[0021] Based on the conduction characteristic coefficients of the half-bridge submodule and the full-bridge submodule, the capacitor current is obtained.

[0022] Based on the capacitor current and the capacitor dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized using the implicit trapezoidal integral method to obtain the Thevenin branch of the submodule capacitor, which is formed by the discrete equivalent resistance of the capacitor and the historical equivalent voltage source of the capacitor connected in series.

[0023] In some embodiments, the expression for the conduction characteristic coefficient of the half-bridge submodule is:

[0024] ;

[0025] in, The conduction characteristic coefficient of the half-bridge submodule; This is the gate drive signal for the first switching group in the half-bridge submodule; is the gate drive signal for the second switching group in the half-bridge submodule; s is the bridge arm current direction indicator.

[0026] The expression for the conduction characteristic coefficient of the full-bridge submodule is:

[0027] ;

[0028] in, These are the conduction characteristic coefficients of the full-bridge submodule; This is the gate drive signal for the first switching group in the full-bridge submodule; This is the gate drive signal for the second switching group in the full-bridge submodule; This is the gate drive signal for the third switch group in the full-bridge submodule; This is the gate drive signal for the fourth switch group in the full-bridge submodule.

[0029] In some embodiments, the expression for the Thevenin branch of the submodule capacitor is:

[0030] ;

[0031] ;

[0032] in, Let be the port output voltage of the Thevenin branch of the capacitor at time t; The discrete equivalent resistance of the capacitor; This is for simulating step size; Let t be the capacitor current. Let be the equivalent voltage source of the capacitor at time t; This is the equivalent voltage source of the capacitor history from the previous simulation step.

[0033] In some embodiments, the expression for the Thevenin branch of the bridge arm inductor is:

[0034] ;

[0035] ;

[0036] in, This is for simulating step size; The discrete equivalent resistance of the bridge arm inductance; The inductor history current in the previous simulation step; The historical voltage source of the bridge arm inductance at time t; Let t be the port output voltage of the Thevenin branch of the bridge arm inductor; Let t be the bridge arm current.

[0037] In some embodiments, the expression for the Thevenin equivalent model of the half-bridge submodule is:

[0038] ;

[0039] ;

[0040] in, Thevenin equivalent resistance of the half-bridge submodule; Let be the conduction characteristic coefficient of the half-bridge submodule at time t; The resistance of the switch group when it is turned on; The discrete equivalent resistance of the capacitor; Thevenin equivalent voltage source for the half-bridge submodule; This is for simulating step size; The equivalent voltage source of the capacitor history in the previous simulation step;

[0041] The expression for the Thevenin equivalent model of the full-bridge submodule is:

[0042] ;

[0043] ;

[0044] in, The Thevenin equivalent resistance of the full-bridge submodule; Let be the conduction characteristic coefficient of the full-bridge submodule at time t; It is the Thevenin equivalent voltage source for the full-bridge submodule.

[0045] In some embodiments, the expression for the Thevenin equivalent model of the bridge arm is:

[0046] ;

[0047] ;

[0048] in, The Thevenin total equivalent resistance of the bridge arm; This represents the total number of half-bridge sub-modules within the bridge arm. This represents the total number of all bridge sub-modules within the bridge arm; This is the resistance value when the switch group is turned on; Let be the conduction characteristic coefficient of the i-th half-bridge submodule at time t; Let be the conduction characteristic coefficient of the j-th full-bridge submodule at time t; The discrete equivalent resistance of the bridge arm inductance; The equivalent resistance of the bridge arm; The Thevenin total equivalent voltage source for the bridge arm; For the Thevenin equivalent voltage source of the i-th half-bridge submodule; For the j-th full-bridge submodule, the Thevenin equivalent voltage source is used. The voltage source of the bridge arm inductance at time t is the historical voltage source.

[0049] Secondly, embodiments of this application provide a storage medium storing a computer program that, when executed by a processor, implements the unified modeling method for hybrid modular multilevel converters as described in the first aspect above.

[0050] Compared to related technologies, the unified modeling method and storage medium for hybrid modular multilevel converters provided in this application construct a unified form of conduction function for each half-bridge switch group and each full-bridge switch group of each bridge arm; based on the conduction function, a unified form of variable resistance equivalent function is constructed for the half-bridge switch groups and full-bridge switch groups; based on a preset capacitor dynamic equation, the capacitors in the half-bridge submodules and full-bridge submodules are discretized to obtain the Thevenin branch of the submodule capacitor; based on a preset inductor dynamic equation, the inductors in the bridge arm are discretized to obtain... The Thevenin branch of the bridge arm inductor is used; based on the equivalent function of the variable resistor and the Thevenin branch of the submodule capacitor, Thevenin equivalent models of the half-bridge submodule and the full-bridge submodule under different states are uniformly constructed; the different states include normal operation, locked state and restart state; the Thevenin equivalent models of the half-bridge submodule, the full-bridge submodule, and the bridge arm inductor are connected in series to obtain the bridge arm Thevenin equivalent model, which solves the problems of poor model reusability and weak multi-condition adaptability, and realizes unified Thevenin equivalent modeling in the entire process of locked and restart.

[0051] Details of one or more embodiments of this application are set forth in the following drawings and description to make other features, objects and advantages of this application more readily apparent. Attached Figure Description

[0052] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0053] Figure 1 This is a topology diagram of a hybrid modular multilevel converter according to an embodiment of this application;

[0054] Figure 2 This is a topology diagram of a half-bridge submodule according to an embodiment of this application;

[0055] Figure 3 This is a topology diagram of the full-bridge submodule according to an embodiment of this application;

[0056] Figure 4 This is a flowchart of a unified modeling method for a hybrid modular multilevel converter according to an embodiment of this application;

[0057] Figure 5 This is a flowchart of step S430. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this application clearer, the application is described and illustrated below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the application. All other embodiments obtained by those skilled in the art based on the embodiments provided in this application without inventive effort are within the scope of protection of this application. Furthermore, it is understood that although the efforts made in such a development process may be complex and lengthy, for those skilled in the art related to the content disclosed in this application, modifications to design, manufacturing, or production based on the technical content disclosed in this application are merely conventional technical means and should not be construed as insufficient disclosure of the content of this application.

[0059] In this application, the reference to "embodiment" means that a specific feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that is mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described in this application may be combined with other embodiments without conflict.

[0060] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms “a,” “an,” “an,” “the,” and similar words used in this application do not indicate quantity limitation and may indicate singular or plural. The terms “comprising,” “including,” “having,” and any variations thereof used in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or device that includes a series of steps or modules (units) is not limited to the listed steps or units, but may also include steps or units not listed, or may include other steps or units inherent to these processes, methods, products, or devices. The terms “connected,” “linked,” “coupled,” and similar words used in this application are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. “Multiple” used in this application means two or more. “And / or” describes the relationship between related objects, indicating that three relationships may exist; for example, “A and / or B” can represent: A alone, A and B simultaneously, and B alone. The terms “first,” “second,” “third,” etc., used in this application are merely to distinguish similar objects and do not represent a specific ordering of the objects.

[0061] Compared to AC transmission, DC transmission offers advantages in long-distance scenarios, including smaller transmission corridor footprint, lower line losses, more flexible power control, and freedom from system synchronization stability constraints. These advantages make it a significant techno-economic advantage for long-distance, high-capacity power transmission. Modular multilevel converters (MMCs) are the core topology of voltage source converter high-voltage direct current (VSC-HVDC) systems and have become the mainstream technology in flexible DC transmission. The basic building block of an MMC is a sub-module (SM), with each arm consisting of dozens to hundreds of cascaded sub-modules. By controlling the activation and bypass states of each sub-module, the MMC can achieve an approximately continuous sinusoidal stepped wave approximation between the arm voltage and the AC side voltage, thus obtaining a high-quality output voltage waveform.

[0062] Hybrid MMC refers to a converter topology that uses different types of submodules in the same bridge arm. Common submodule types include: (1) Half-Bridge SM (HBSM), which has a simple structure and low loss, but does not have DC fault self-clearing capability; (2) Full-Bridge SM (FBSM), which has DC fault self-clearing capability, but requires twice the number of devices and is less economical. In engineering practice, although pure full-bridge MMC has strong fault ride-through capability, its investment cost and operating loss are too high; pure half-bridge MMC does not have DC fault self-clearing capability and has low fault protection requirements. Therefore, hybrid MMC mixes half-bridge submodules and full-bridge submodules in a certain proportion in one bridge arm, which has both DC fault self-clearing capability and good economic efficiency, and is widely used in many current projects.

[0063] Currently, the electromagnetic transient models proposed by scholars at home and abroad are mainly divided into four categories: ① Device-level detailed model: directly models each IGBT, diode and capacitor of each submodule, simulates the charging and discharging process of the submodule capacitor and switching transients, with the highest accuracy, but the computational efficiency drops sharply as the number of levels increases, and it is not suitable for fast electromagnetic transient simulation of large-scale AC and DC power grids; ② Average value model: ignores the independent charging and discharging process of submodules, capacitor voltage equalization dynamics and converter blocking behavior, so it cannot simulate abnormal operating conditions such as DC faults; ③ Efficient model based on Thevenin equivalent: simplifies each submodule into a two-terminal network of equivalent resistance and equivalent voltage source in series, and uses the algebraic superposition of the series relationship of submodules in the bridge arm to reduce the entire bridge arm to a single Thevenin branch, which not only retains the capacitor voltage and current information at the submodule level, but also reduces the system complexity and improves the simulation efficiency.

[0064] Existing Thevenin equivalent models for MMC generally derive equivalent formulas only for a single operating condition and a single submodule type, lacking a unified Thevenin equivalent method that can uniformly cover the entire process of normal operation, latch-up, and restart of hybrid MMC.

[0065] This embodiment provides a unified modeling method for a hybrid modular multilevel converter, wherein the hybrid modular multilevel converter includes multiple bridge arms, each bridge arm includes multiple half-bridge sub-modules and multiple full-bridge sub-modules; the half-bridge sub-modules and full-bridge sub-modules are connected in series on the bridge arm; each half-bridge sub-module includes multiple half-bridge switch groups; each full-bridge sub-module includes multiple full-bridge switch groups.

[0066] Specifically, the hybrid MMC adopts a three-phase six-arm structure, with each phase consisting of upper and lower arms, as shown in the specific topology diagram. Figure 1 As shown. Each bridge arm consists of bridge arm inductance L0, bridge arm equivalent resistance R0, and N. h One half-bridge submodule and N fThe bridge arm submodules are connected in series, and the total number of bridge arm submodules is N = N h +N f In the diagram, SM represents a submodule.

[0067] The half-bridge submodule consists of two IGBT / diode switch groups (upper T1 / D1, lower T2 / D2, where T represents IGBT and D represents diode) and a DC capacitor C, as shown in the specific topology. Figure 2 The full-bridge submodule consists of four IGBT / diode switch groups (top left T1 / D1, bottom left T2 / D2, top right T3 / D3, bottom right T4 / D4) and a DC capacitor C, forming an H-bridge structure. The specific topology is as follows: Figure 3 The positive direction of the bridge arm current is defined as flowing into port A and out of port B.

[0068] Figure 4 This is a flowchart of a unified modeling method for hybrid modular multilevel converters according to embodiments of this application, such as... Figure 4 As shown, the process includes the following steps:

[0069] Step S410: For each half-bridge switch group and each full-bridge switch group of each bridge arm, construct a uniform form of conduction function.

[0070] Specifically, the topology and number of switch groups in different types of submodules are inconsistent. Traditional modeling schemes write separate conduction discrimination formulas for half-bridge switch groups and full-bridge switch groups, requiring formula changes when switching operating conditions, making it impossible to achieve unified calculations for the entire process of normal operation, lockout, and restart. This application abandons the approach of separate modeling for different types and adopts a unified variable system to construct the conduction function. The variables mainly include: switch group gate drive signal, global bridge arm current direction indicator, and switch group conduction characteristic coefficient. Among them, the gate drive signal is output in real time by the MMC modulation module. During normal operation, it outputs 0 / 1 according to the modulation wave, and all values ​​are assigned to 0 in the lockout state; the current direction indicator is dynamically updated in real time according to the positive and negative values ​​of the bridge arm current; the conduction characteristic coefficient is pre-calibrated according to the state of the switch group within the submodule. The same set of mathematical expressions can be used to solve the conduction state of any half-bridge switch group and full-bridge switch group, uniformly covering two types of conduction mechanisms: IGBT controllable conduction and diode freewheeling conduction. Under the blocking and restart transition conditions, there is no need to modify the conduction function structure. Only the gate signal and current label need to be updated to complete the conduction state update. The output is a unified conduction coefficient, which is used as the input of the equivalent function of the variable resistance of the subsequent switch group, realizing the integrated equivalent modeling of the switch branches of the half-bridge and full-bridge sub-modules.

[0071] Step S420: Based on the conduction function, construct a unified form of variable resistance equivalent function for the half-bridge switch group and the full-bridge switch group.

[0072] Specifically, the conduction coefficient output from the general conduction function constructed in the above steps is used as the core input variable of the equivalent function. Combined with two types of fixed parameters (resistance when the switch group is on and resistance when the switch group is off), a variable resistance equivalent function is constructed. This variable resistance equivalent function uses a unified mathematical expression, regardless of whether the current switch group belongs to a half-bridge or full-bridge submodule. It relies solely on the value of the conduction coefficient to determine the switch's on / off state and automatically outputs the corresponding equivalent resistance. Regardless of whether the operation is under normal controllable operation, fault lockout, or fault clearing and restart conditions, only the input variables of the conduction function (gate drive signal, bridge arm current direction indicator) need to be updated. All switch group resistance parameters can be updated using the same set of variable resistance equivalent functions without switching calculation logic.

[0073] Step S430: Based on the preset capacitor dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized to obtain the Thevenin branch of the submodule capacitor.

[0074] Specifically, the bridge arm contains both half-bridge and full-bridge submodules. While the topologies of these two types of submodules differ, the voltage and current dynamics of the internal energy storage capacitors follow completely consistent differential constraints, thus allowing for processing using the same discretization process. An implicit trapezoidal integral method can be used to differentially discretize the preset capacitor dynamic equations. After discretization, the capacitor differential equations are transformed into an algebraic two-terminal Thevenin equivalent circuit. This equivalent circuit consists of a discrete equivalent capacitor resistance and a historical equivalent voltage source connected in series. The discrete equivalent capacitor resistance is uniquely determined by the simulation step size and capacitor parameters, remaining constant within a single simulation duration. The historical equivalent voltage source stores the capacitor voltage information from the previous simulation step, enabling time-series recursion of the capacitor's energy storage state. This Thevenin branch is uniformly applicable to both half-bridge and full-bridge submodules, and the discretization process remains unchanged under three operating conditions: normal controllable operation, fault blocking, and fault clearing and restart.

[0075] Step S440: Based on the preset inductance dynamic equation, the inductance in the bridge arm is discretized to obtain the Thevenin branch of the bridge arm inductance.

[0076] Specifically, each bridge arm is connected in series with its inductor. Regardless of the ratio of half-bridge submodules or full-bridge submodules within the bridge arm, the voltage and current dynamic constraints of the bridge arm inductor satisfy the same set of inductor dynamic differential equations, exhibiting no topological differences. Using a single bridge arm as the computational unit, the implicit trapezoidal integral method can be used to perform differential discretization on the preset inductor dynamic equations, transforming them into an algebraic two-terminal equivalent circuit. This equivalent circuit consists of the discrete equivalent resistance of the inductor and the historical voltage source of the bridge arm inductor connected in series. The discrete equivalent resistance of the inductor is uniquely determined by the simulation step size and the inherent parameters of the bridge arm inductor, remaining unchanged during the simulation. The historical voltage source of the bridge arm inductor is iteratively generated by the inductor current of the previous time step, realizing the time-series recursion of the inductor's magnetic energy state. The resulting thevenin branch of the bridge arm inductor has universality across all operating conditions. The discretization calculation process does not need to be modified under the three operating conditions of normal controllable operation, fault blocking, and fault clearing and restart; only the historical voltage source of the inductor needs to be updated step by step.

[0077] Step S450: Based on the equivalent function of the variable resistor and the Thevenin branch of the submodule capacitor, construct the Thevenin equivalent models of the half-bridge submodule and the full-bridge submodule under different states; the different states include normal operation state, locked state and restart state.

[0078] Specifically, combining the output parameters of the equivalent function of the variable resistance of the aforementioned switch group with the Thevenin branch of the submodule capacitor obtained after discretization, a unified modeling logic is used to construct Thevenin equivalent models of the half-bridge submodule and the full-bridge submodule, respectively, to adapt to normal operation, locked-out, and restart states. For the normal operation state, the gate drive signal is output in real time by the modulation algorithm, and the equivalent function of the variable resistance updates the switch on / off resistance value according to the conduction coefficient. Combining the equivalent resistance of the capacitor Thevenin branch and the historical voltage source, the total equivalent resistance and equivalent voltage source of the submodule port are solved using Thevenin's theorem. For the locked-out state, all switch gate signals are set to zero, and the switch conduction state is determined only by the bridge arm current and diode freewheeling characteristics. The variable resistance is synchronously switched to the locked-out operating resistance value, and the same set of circuit superposition logic is used to solve the equivalent parameters. For the restart state, the gate signal gradually recovers after the fault is cleared, and the equivalent resistance and the historical voltage source of the capacitor directly inherit the values ​​of the last time step of the locked-out state, ensuring continuous capacitor voltage during state switching. The entire construction process uses a single set of circuit superposition rules. It distinguishes between half-bridge and full-bridge submodule topologies only by using conduction characteristic coefficients. There is no need to change the circuit equivalent calculation logic. Finally, it outputs the Thevenin equivalent resistance and equivalent voltage source of the half-bridge submodule and the Thevenin equivalent resistance and equivalent voltage source of the full-bridge submodule under three operating conditions, realizing integrated equivalent modeling of two types of submodules under three operating conditions.

[0079] Step S460: Connect the Thevenin equivalent model of the half-bridge submodule, the Thevenin equivalent model of the full-bridge submodule, and the Thevenin branch of the bridge arm inductor in series to obtain the Thevenin equivalent model of the bridge arm.

[0080] Specifically, after separately solving for the Thevenin equivalent models of a single half-bridge submodule, a single full-bridge submodule, and the independent bridge arm inductor Thevenin branch, all the above equivalent units are sequentially connected in series according to the series relationship of the actual topology of the hybrid MMC bridge arm, finally obtaining the bridge arm Thevenin equivalent model corresponding to the entire bridge arm. From the hardware topology perspective, a single bridge arm of the hybrid MMC consists of several half-bridge submodules, several full-bridge submodules, and bridge arm inductors connected in series end to end. Circuitally, it belongs to a pure series branch, satisfying the series superposition rule of Thevenin equivalent circuit. For multiple series-connected Thevenin two-terminal networks, the total equivalent resistance is equal to the direct sum of the equivalent resistances of all units, and the total equivalent voltage source is equal to the algebraic sum of the equivalent voltage sources of all units. This application first connects and superimposes all the half-bridge submodule Thevenin models and full-bridge submodule Thevenin models one by one to obtain the overall Thevenin equivalent parameters of the submodule cluster; then, the equivalent branch of the submodule cluster and the bridge arm inductor Thevenin branch are connected in series for calculation to complete the equivalent merging of the entire bridge arm. The entire superposition calculation logic does not distinguish whether the current converter is in normal operation, locked-out, or restart condition. It simply calls the equivalent resistance, equivalent voltage source, and equivalent parameters of the inductor branch output from the previous step for algebraic accumulation. The Thevenin equivalent model of the bridge arm obtained by series aggregation retains only one set of total equivalent resistance and one set of total equivalent historical voltage sources, significantly reducing the scale of circuit nodes. In subsequent electromagnetic transient simulations, the unified equivalent branch of this bridge arm can be directly used to construct the system node admittance equations, while fully preserving the transient characteristics brought about by the energy storage of sub-module capacitors, the magnetic energy storage of bridge arm inductors, and the switching conduction state, thus achieving high-precision and rapid simulation of the bridge arm under all operating conditions.

[0081] In the above steps, a unified conduction function and variable resistance equivalent model are constructed for all switches. The implicit trapezoidal integral is used to perform standardized Thevenin discretization of the sub-module capacitors and bridge arm inductors respectively. Based on the same set of circuit superposition logic, a unified equivalent model of half-bridge and full-bridge sub-modules is established to adapt to the three types of working conditions: normal, locked, and restart. Then, the unified Thevenin equivalent branch of a single bridge arm is obtained by aggregating according to the actual series topology. This overcomes the defects of traditional modeling, which sets separate formulas for half-bridge and full-bridge sub-modules and cannot be compatible with the complete transition process from locked to restart. While fully preserving the charging and discharging of sub-module capacitors, the circulating current of bridge arm inductors, and the transient details of faults, the simulation circuit order is greatly reduced. This achieves high-precision and high-efficiency electromagnetic transient simulation of the entire process of hybrid MMC locked-fault clearing-restart, improving the model's versatility and numerical stability of working condition switching.

[0082] In some embodiments, the expression for the conduction function is:

[0083] ;

[0084] Where k is the switch group number; The conduction function coefficients of the k-th switch group; is the gate drive signal for the k-th switch group; s is the bridge arm current direction indicator; The conduction characteristic coefficients of the submodule; =1 indicates that when s=1, the diode in the k-th switch group is forward-biased; =-1 indicates that when s=-1, the diode in the k-th switch group is forward-biased.

[0085] The specific derivation method is as follows: First, define the bridge arm current i arm The flow from port A to port B is considered positive. Therefore, for the half-bridge submodule, the conduction function expression for the switch group is:

[0086] ;

[0087] ;

[0088] Where s is the current direction indicator for the bridge arm, when i arm When s > 0 (positive direction), s = 1, i arm When s < 0 (opposite direction), s = -1; This is the conduction function for the first switch group of the half-bridge submodule; This is the gate drive signal for the first switching group in the half-bridge submodule; This is the conduction function for the second switch group of the half-bridge submodule; This is the gate drive signal for the second switch group in the half-bridge submodule.

[0089] For the full-bridge submodule, the on-function expression of the switch group is:

[0090] ;

[0091] ;

[0092] ;

[0093] ;

[0094] in, This is the gate drive signal for the first switching group in the full-bridge submodule; This is the gate drive signal for the second switching group in the full-bridge submodule; This is the gate drive signal for the third switch group in the full-bridge submodule; This is the gate drive signal for the fourth switch group in the full-bridge submodule.

[0095] Comparing the discrete switch conduction expressions for the half-bridge and full-bridge submodules reveals that the underlying mechanisms for determining the conduction of the switch groups in both types of submodules are completely identical, differing only in the number of switches and the diode conduction polarity parameters. Therefore, introducing submodule conduction characteristic coefficients can address this issue. By parametrically representing the topological differences and eliminating the formulaic differences between half-bridge and full-bridge submodules, a unified on-function general expression compatible with all switch groups of both types of submodules is obtained:

[0096] ;

[0097] Where k is the switch group number; The conduction function coefficients of the k-th switch group; is the gate drive signal for the k-th switch group; s is the bridge arm current direction indicator; The conduction characteristic coefficients of the submodule; =1 indicates that when s=1, the diode in the k-th switch group is forward-biased; =-1 indicates that when s=-1, the diode in the k-th switch group is forward-biased.

[0098] The above steps introduce a unified conduction function to standardize the conduction state of all switch groups in the half-bridge and full-bridge sub-modules. This eliminates the need to design independent conduction discrimination formulas for the two types of sub-modules, thus removing the model fragmentation problem caused by different sub-module topologies and improving modeling reusability and simulation program versatility.

[0099] In some embodiments, the expression for the equivalent function of the variable resistance is:

[0100] ;

[0101] Where k is the switch group number; The variable resistor is the k-th switch group; This is the resistance value when the switch group is turned on; This is the resistance value when the switch group is turned off.

[0102] Specifically, based on the switching group conduction function obtained above, an equivalent model of the variable resistance of the switching branch is further established. When the conduction function... When =1, the switch group is in a fully conducting state, and the equivalent resistance is... = This corresponds to the low-resistance operating condition of IGBT forward conduction or diode freewheeling conduction; when the conduction function When =0, the switch group is in the off-blocking state, and the equivalent resistance is... = This corresponds to the high-resistance operating condition where the switch branch is open and blocked.

[0103] This can be understood as performing an equivalent treatment on each switch group in the submodule, replacing it with a variable resistor. For the half-bridge submodule, the switch groups are replaced by R1 and R2; for the full-bridge submodule, they are replaced by R1, R2, R3, and R4. When the switch group is on, the variable resistor is set to R. on (On-resistance, take 0.01Ω), R when off. off (Switch-off resistor, set to 10) 6 Ω). Whether the switch group is turned on or off is determined by two conditions: if the IGBT gate signal g=1, the switch group is turned on; if g=0, but the anti-parallel diode is forward biased, the switch group is still turned on; the switch group is turned off only when g=0 and the anti-parallel diode is reverse biased and cut off.

[0104] In the above embodiments, the equivalent expression of the variable resistance is constructed based on the conduction function, which enables the impedance of the switching branch to transition smoothly and continuously between the on-resistance and off-resistance as the conduction state changes. There is no need to set segmented logic for the controllable conduction of IGBTs and the freewheeling conduction of diodes. One set of formulas can be adapted to all switching branches of the half-bridge and full-bridge sub-modules, effectively avoiding impedance abrupt changes during operating condition switching, suppressing numerical oscillations in electromagnetic transient simulation, realizing continuous equivalent modeling of the entire process of normal operation, lockout, and restart of the converter, greatly simplifying the unified equivalent process of the hybrid MMC sub-module, and improving the model's versatility and simulation numerical stability.

[0105] In some of these embodiments, such as Figure 5 As shown, in step S430, based on the preset capacitor dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized to obtain the Thevenin branch of the submodule capacitor, including the following process:

[0106] Step S431: Based on the gate drive signal of the half-bridge switch group and the direction of the bridge arm current, obtain the conduction characteristic coefficient of the half-bridge submodule;

[0107] Step S432: Based on the gate drive signal of the full-bridge switch group and the direction of the bridge arm current, obtain the conduction characteristic coefficient of the full-bridge submodule;

[0108] Step S433: Based on the conduction characteristic coefficients of the half-bridge submodule and the full-bridge submodule, the capacitor current is obtained.

[0109] Step S434: Based on the capacitor current and capacitor dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized using the implicit trapezoidal integral method to obtain the Thevenin branch of the submodule capacitor, which is composed of the discrete equivalent resistance of the capacitor and the historical equivalent voltage source of the capacitor connected in series.

[0110] Specifically, firstly, the gate drive signals of each switch group in the half-bridge submodule are read, and the conduction characteristic coefficient of the half-bridge submodule is calculated in combination with the predefined bridge arm current direction indicator; then, the gate drive signals of the four switch groups in the full-bridge submodule are read, and the conduction characteristic coefficient of the full-bridge submodule is calculated based on the positive and negative determination results of the bridge arm current.

[0111] Subsequently, the conduction characteristic coefficients of the two types of submodules were substituted into the branch current expression to obtain the capacitor current flowing through the submodule in a unified solution. Based on this, the capacitor current was substituted into the original capacitor dynamic differential equation, and the implicit trapezoidal integral method, which has better numerical stability, was used to simultaneously perform discretization and iterative solution of the capacitor equations of the half-bridge and full-bridge submodules. Finally, the continuous capacitor branch was equivalent to a Thevenin branch in series with a discrete equivalent resistor and a historical voltage source, resulting in a capacitor equivalent model applicable to all submodule topologies of the hybrid MMC.

[0112] Through the above steps, there is no need to design discrete iterative logic for the half-bridge and full-bridge sub-modules separately. The two types of topological capacitance equations are solved synchronously based on unified parameters. Implicit integration is used to ensure numerical stability, and finally, the topology-independent Thevenin equivalent branch is obtained, which greatly simplifies the process of building the overall electromagnetic transient model of the hybrid modular multilevel converter.

[0113] In some embodiments, the expression for the conduction characteristic coefficient of the half-bridge submodule is:

[0114] ;

[0115] in, The conduction characteristic coefficient of the half-bridge submodule; This is the gate drive signal for the first switching group in the half-bridge submodule; is the gate drive signal for the second switching group in the half-bridge submodule; s is the bridge arm current direction indicator.

[0116] The expression for the conduction characteristic coefficient of the full-bridge submodule is:

[0117] ;

[0118] in, These are the conduction characteristic coefficients of the full-bridge submodule; This is the gate drive signal for the first switching group in the full-bridge submodule; This is the gate drive signal for the second switching group in the full-bridge submodule; This is the gate drive signal for the third switch group in the full-bridge submodule; This is the gate drive signal for the fourth switch group in the full-bridge submodule.

[0119] Understandably, during normal operation and The gate drive signal given by the modulation determines the latch-up, while the current direction determines the latch-up. A unified modeling process was used for the dynamics of the capacitor.

[0120] By using this set of conduction characteristic coefficients, the capacitor switching status of half-bridge and full-bridge submodules under all operating conditions of normal modulation, blocking, and restart can be uniformly identified using only two variables: gate drive signal and current direction. There is no need to set the operating condition discrimination logic in segments, providing standardized parameters for the unified solution of capacitor current of the two types of submodules.

[0121] In some embodiments, the expression for the Thevenin branch of the submodule capacitor is:

[0122] ;

[0123] ;

[0124] in, Let be the port output voltage of the Thevenin branch of the capacitor at time t; The discrete equivalent resistance of the capacitor; This is for simulating step size; Let t be the capacitor current. Let be the equivalent voltage source of the capacitor at time t; This is the equivalent voltage source of the capacitor history from the previous simulation step.

[0125] Specifically, the conduction characteristic coefficients of the half-bridge submodule are defined. and the conduction characteristic coefficient of the full-bridge submodule For the half-bridge submodule: i c =k HB i arm For the full-bridge submodule: The conduction characteristic coefficients of the half-bridge submodule and the full-bridge submodule can be determined by the gate drive signal and the current direction.

[0126] For the submodule capacitor dynamic equation On the interval [0, 1], the implicit trapezoidal rule is used to perform a difference operation on the differential equation, yielding:

[0127] ;

[0128] ;

[0129] in, Let be the port output voltage of the Thevenin branch of the capacitor at time t; This is for simulating step size; Let t be the capacitor current. Let be the equivalent voltage source of the capacitor at time t; The equivalent voltage source of the capacitor history in the previous simulation step; The discrete equivalent resistance of the capacitor. The step size is determined by the simulation step size.

[0130] Therefore, the capacitors of the submodules are equivalent to resistors. Series voltage source David South Branch Road.

[0131] In the above embodiments, the implicit trapezoidal integral method is used to discretely solve the capacitor differential equation, and the continuously changing dynamic capacitor branch is equivalent to a Thevenin branch consisting of a discrete equivalent resistance and a historical voltage source in series. On the one hand, the implicit trapezoidal integral has the advantage of unconditional numerical stability, which can effectively avoid numerical divergence and oscillation problems during transient processes such as blocking and operating condition switching, and significantly improve the stability of electromagnetic transient simulation. On the other hand, by solving the capacitor current based on the unified conduction characteristic coefficient of the half-bridge and full-bridge sub-modules, the same set of discrete iterative calculation logic can be executed on the capacitor branches of the half-bridge topology and the full-bridge topology. There is no need to build different numerical iterative models for the two types of sub-modules, realizing the unified Thevenin equivalence of capacitor branches of different sub-modules in the hybrid MMC, simplifying the overall modeling process, improving the model's versatility and code reusability, and using only the historical voltage source of the previous moment to complete the iterative calculation, thus balancing simulation accuracy and computational efficiency.

[0132] In some embodiments, the expression for the Thevenin branch of the bridge arm inductor is:

[0133] ;

[0134] ;

[0135] in, This is for simulating step size; The inductor history current in the previous simulation step; The historical voltage source of the bridge arm inductance at time t; Let t be the port output voltage of the Thevenin branch of the bridge arm inductor; Let t be the bridge arm current; The discrete equivalent resistance of the bridge arm inductance. , is a constant after the simulation step size is fixed; L0 is the bridge arm inductance.

[0136] Specifically, for the dynamic equation of the bridge arm inductor In the interval To obtain the following, we use the implicit trapezoidal rule to perform finite difference processing on the differential equation:

[0137] ;

[0138] ;

[0139] Within each simulation step, it is only necessary to read the historical inductor current saved in the previous time step to update the historical voltage source, thus transforming the differential equation into a simple algebraic equation.

[0140] In the above embodiments, the bridge arm inductor adopts the Thevenin equivalent structure that is completely consistent with the capacitor, which unifies the discrete format of all dynamic elements in the bridge arm. It relies only on historical state variables to complete the recursive iteration, which not only ensures the stability of numerical calculation, but also realizes the integrated network assembly of sub-modules and bridge arm inductors, greatly reducing the difficulty of building equations for large-scale converter simulation.

[0141] In some embodiments, the Thevenin equivalent model of the half-bridge submodule is expressed as follows:

[0142] ;

[0143] ;

[0144] in, Thevenin equivalent resistance of the half-bridge submodule; Let be the conduction characteristic coefficient of the half-bridge submodule at time t; The resistance of the switch group when it is turned on; The discrete equivalent resistance of the capacitor; Thevenin equivalent voltage source for the half-bridge submodule; This is for simulating step size; The equivalent voltage source of the capacitor history in the previous simulation step;

[0145] The expression for the Thevenin equivalent model of the full-bridge submodule is:

[0146] ;

[0147] ;

[0148] in, The Thevenin equivalent resistance of the full-bridge submodule; Let be the conduction characteristic coefficient of the full-bridge submodule at time t; It is the Thevenin equivalent voltage source for the full-bridge submodule.

[0149] Specifically, the derivation of the Thevenin equivalent model of the half-bridge submodule is as follows: replace the switch group in the half-bridge submodule with variable resistors R1 and R2, and replace the capacitor with a discretized Thevenin branch. Apply the Thevenin equivalent theorem to this discrete circuit from port A and port B, and its port equivalent impedance is equal to the equivalent resistance seen from the port after short-circuiting the internal independent sources, and the port equivalent voltage source is equal to the open-circuit voltage between ports A and B. The equivalent model of the half-bridge submodule considering normal operation, latch-up, and restart states is given below.

[0150] Under normal operating conditions, the gate signal is given by the modulation strategy. When the submodule is activated, =1, =0; when the submodule is bypassed =0, =1, therefore, the Thevenin equivalent parameter under normal operating conditions is: under the input condition, , In bypass mode, , .

[0151] In the locked state, the gate signals of T1 and T2 are both 0 ( =0, =0), there are two current conduction directions, positive and negative. Combining these, the Thevenin equivalent parameter expression for the half-bridge submodule in the locked state can be obtained as follows:

[0152] ;

[0153] ;

[0154] In restart mode, the IGBT gate signal is restored at the restart trigger moment. The equivalent parameter calculation formula is the same as in normal operation, only requiring... Inherited from the last time step of the latch. R in the above formula... sm e is the Thevenin equivalent resistance. sm This is the Thevenin equivalent voltage source.

[0155] Combining the above three states, the Thevenin equivalent parameter of the half-bridge submodule in any state can be uniformly expressed as:

[0156] ;

[0157] ;

[0158] in, Thevenin equivalent resistance of the half-bridge submodule; Let be the conduction characteristic coefficient of the half-bridge submodule at time t; The resistance of the switch group when it is turned on; The discrete equivalent resistance of the capacitor; Thevenin equivalent voltage source for the half-bridge submodule; This is for simulating step size; This is the equivalent voltage source of the capacitor history from the previous simulation step.

[0159] The derivation of the Thevenin equivalent model of the full-bridge submodule is as follows: replace the switch group of the full-bridge submodule with variable resistors R1-R4, and the capacitor with a discretized Thevenin branch, to obtain the discrete circuit of the full-bridge submodule. Under normal operating conditions, the gate signal is given by the modulation strategy. When the circuit is actively engaged, the gate signal is... =1, =1, =0, =0; the gate signal during negative input is =1, =1, =0, =0; In bypass mode, the gate signal is = =1 or = =1. Therefore, the Thevenin equivalent parameters under various states during normal operation are: under the positive input state, , Under negative input conditions, , In bypass mode, , ;

[0160] In the latched state, all four IGBT gate signals are set to zero. = = = =0), indicating that there are both positive and negative current conduction directions. Combining the two directions, the Thevenin equivalent parameters of the full-bridge submodule in the locked state are expressed as: , ;

[0161] In the restart state, the gate signal is restored, and the equivalent parameters are consistent with normal operation. Inherited from the final locked state. R in the above formula... sm e is the Thevenin equivalent resistance. sm This is the Thevenin equivalent voltage source.

[0162] Combining the above three states, the Thevenin equivalent parameters of the full-bridge submodule in any state can be uniformly expressed as:

[0163] ;

[0164] ;

[0165] in, The Thevenin equivalent resistance of the full-bridge submodule; Let be the conduction characteristic coefficient of the full-bridge submodule at time t; Thevenin equivalent voltage source for the full-bridge submodule; The resistance of the switch group when it is turned on; The discrete equivalent resistance of the capacitor; This is the equivalent voltage source of the capacitor history from the previous simulation step.

[0166] In the above embodiments, based on the conduction characteristic coefficients of the half-bridge and full-bridge submodules, the switch conduction resistance and the discrete equivalent resistance of the capacitor are parametrically coupled to construct a unified Thevenin equivalent circuit for both types of submodules. This enables the half-bridge and full-bridge submodules to have isomorphic Thevenin branches, achieving undifferentiated modeling of the two topologies, simplifying the overall process, and improving the stability and modeling efficiency of electromagnetic transient simulation of large-scale hybrid modular multilevel converters.

[0167] In some embodiments, the expression for the Thevenin equivalent model of the bridge arm is:

[0168] ;

[0169] ;

[0170] in, The Thevenin total equivalent resistance of the bridge arm; This represents the total number of half-bridge sub-modules within the bridge arm. This represents the total number of all bridge sub-modules within the bridge arm; This is the resistance value when the switch group is turned on; Let be the conduction characteristic coefficient of the i-th half-bridge submodule at time t; Let be the conduction characteristic coefficient of the j-th full-bridge submodule at time t; The discrete equivalent resistance of the bridge arm inductance; The equivalent resistance of the bridge arm; The Thevenin total equivalent voltage source for the bridge arm; For the Thevenin equivalent voltage source of the i-th half-bridge submodule; For the j-th full-bridge submodule, the Thevenin equivalent voltage source is used. The voltage source of the bridge arm inductance at time t is the historical voltage source.

[0171] Specifically, since each submodule branch and the bridge arm inductor branch are equivalent to a Thevenin series branch with the same structure, under series circuit conditions, the total equivalent resistance is equal to the direct sum of the equivalent resistances of all branches, and the total equivalent voltage source is equal to the direct sum of the equivalent voltage sources of all branches. This aggregation method does not require splitting the half-bridge and full-bridge topologies; it directly sums the submodule branches one by one, completing the overall equivalence of the hybrid bridge arm in one go, and finally compressing the entire bridge arm containing a large number of submodules into a single Thevenin branch. It can be understood as connecting the Thevenin equivalent branches of the half-bridge submodules, the Thevenin equivalent branches of the full-bridge MMC, and the equivalent Thevenin parameters of the bridge arm inductors in series. The same bridge arm current flows through each branch within the same bridge arm, and the Thevenin equivalent parameters of the series network are the sum of the parameters of each branch.

[0172] Therefore, a unified Thevenin equivalent model of the bridge arm can be obtained, which constitutes the dynamics of the capacitor in the covering submodule, the dynamics of the bridge arm inductor, the switching of the variable resistance of the switching group, and the entire process of blocking and restarting. Each of the six bridge arms obtains an equivalent Thevenin branch, and after further forming a complete MMC topology, the nodal admittance equation is solved.

[0173] In the above embodiments, a large number of sub-module branches are aggregated into a single bridge arm Thevenin branch, which significantly improves the calculation speed of large-scale hybrid MMC electromagnetic transient simulation. At the same time, the half-bridge and full-bridge sub-modules share the same set of summation and aggregation logic, which has strong topology adaptability and makes it easy to flexibly adjust the ratio of the two types of sub-modules in the bridge arm, resulting in higher model versatility.

[0174] This application unifies the Thevenin equivalent modeling for three states: normal operation, latched state, and restart process. In the latched state, the Thevenin equivalent parameters of the submodule are jointly determined by the bridge arm current direction and the submodule topology. In the restart state, the switching of equivalent parameters is performed under capacitor voltage continuity constraints and inductor current continuity constraints, covering the complete state cycle of normal operation, fault latching, fault clearing, and restart recovery, thus overcoming the shortcomings of existing methods that only model a single operating condition. Furthermore, the switching state of the half-bridge and full-bridge submodules is uniformly expressed as an algebraic function of the gate signal and the bridge arm current direction. By introducing coefficients, a unified equivalent modeling is performed for both types of submodules under the three operating conditions of normal operation, latching, and restart.

[0175] This application first establishes Thevenin equivalent mathematical models of the half-bridge submodule and the full-bridge submodule under three states: normal operation, lockout, and restart. Then, the equivalent models under the three states are summarized into a unified parameterized expression and aggregated to obtain the bridge arm-level Thevenin equivalent model. Finally, the boundary conditions of the state switching process are established to ensure the continuity of the capacitor voltage throughout the process.

[0176] Capacitor dynamics and inductor dynamics are two sets of fundamental differential constraints in the electromagnetic transient process of the bridge arm. This invention first discretizes these two types of dynamic elements using trapezoidal integrals to obtain their respective Thevenin equivalent branches. Then, the switching group is equivalent to a variable resistor and combined with the discretized capacitor branch to obtain a sub-module-level Thevenin equivalent model. Finally, all sub-module Thevenin branches in the bridge arm are connected in series with the discretized bridge arm inductor branches to obtain a bridge arm-level Thevenin equivalent model. The equivalent models under normal operation, latching, and restart states are considered respectively, and combined with the state switching boundary conditions, a unified bridge arm Thevenin equivalent model covering the sub-module capacitor dynamics, bridge arm inductor dynamics, variable resistor switching of the switching group, and the entire process of latching and restarting is finally obtained.

[0177] It should be noted that the state switching boundary conditions refer to: switching from normal operation to latch-up (all IGBTs are blocked after a fault occurs) and switching from latch-up to restart (IGBTs resume control after the fault is cleared). At the instant of switching, the gate signal or current direction of the submodule undergoes a momentary jump, causing a change in the conduction path and a sudden change in the equivalent resistance. However, the capacitor voltage and inductor current, as state variables of energy storage elements, cannot change abruptly. Therefore, under the condition of a sudden change in equivalent resistance, it is necessary to ensure the continuity of the capacitor voltage and inductor current before and after the boundary. This essentially involves updating the coefficients corresponding to the gate signal or current direction according to a unified formula. The historical voltage source (the capacitor's voltage) is... c , inductance e L The equivalent impedance is derived recursively from the voltage and current of the previous time step, calculated at the end of each step and automatically carried over at the beginning of the next step. During state transitions, changes in the gate signal or current direction update the value of the equivalent impedance (via...). and (Expression), but the historical voltage source and historical current are used as independent recursive quantities, and are directly used in the next time step.

[0178] This application unifies the modeling of hybrid MMC under three operating conditions—normal operation, DC blocking, and fault restart—within the same Thevenin equivalent framework. First, the submodule capacitors and bridge arm inductors are discretized using trapezoidal integration to obtain their respective Thevenin equivalent branches. At the same time, the switching group is equivalent to a variable resistor, the value of which is determined by the gate signal and the direction of the bridge arm current through a unified expression.

[0179] Then, the discretized capacitor branch is combined with the variable resistor to obtain the port Thevenin equivalent models of the half-bridge and full-bridge submodules, respectively. The equivalent parameters in the three states are further reduced to a unified form. Finally, the Thevenin branches and inductor branches of all submodules in the bridge arm are connected in series and aggregated to obtain the complete equivalent model.

[0180] Compared with existing methods, the technical advantages of this method are as follows: (1) Existing methods only model a single operating condition of locked-in state or normal operation, while this method extends the modeling scope from locked-in state to cover the complete timing process of normal operation, DC fault lock-in, and restart after fault clearing. (2) Existing methods usually derive independent equivalent formulas for half-bridge submodules and full-bridge submodules under different conduction modes in locked-in state, while this method uses a unified algebraic expression for gate signal and bridge arm current direction to uniformly describe the equivalent parameters of half-bridge and full-bridge submodules under different operating conditions.

[0181] Furthermore, in conjunction with the unified modeling method for hybrid modular multilevel converters in the above embodiments, this application embodiment can provide a storage medium for implementation. This storage medium stores a computer program; when executed by a processor, the computer program implements any of the unified modeling methods for hybrid modular multilevel converters in the above embodiments.

[0182] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, data stored, data displayed, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties.

[0183] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium. When executed, the computer program can include the processes of the embodiments described above. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0184] Those skilled in the art should understand that the technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments have been described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0185] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A unified modeling method for hybrid modular multilevel converters, characterized in that, The hybrid modular multilevel converter includes multiple bridge arms, each bridge arm including multiple half-bridge submodules and multiple full-bridge submodules; the half-bridge submodules and the full-bridge submodules are connected in series on the bridge arm; each half-bridge submodule includes multiple half-bridge switch groups; each full-bridge submodule includes multiple full-bridge switch groups; the method includes: For each half-bridge switch group and each full-bridge switch group of each bridge arm, a unified form of conduction function is constructed; Based on the conduction function, a unified form of variable resistance equivalent function is constructed for the half-bridge switch group and the full-bridge switch group; Based on the preset capacitance dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized to obtain the Thevenin branch of the submodule capacitor. Based on the preset inductance dynamic equation, the inductance in the bridge arm is discretized to obtain the Thevenin branch of the bridge arm inductance. Based on the equivalent function of the variable resistor and the Thevenin branch of the submodule capacitor, Thevenin equivalent models of the half-bridge submodule and the full-bridge submodule under different states are uniformly constructed; the different states include normal operation state, locked state and restart state; The Thevenin equivalent model of the half-bridge submodule, the Thevenin equivalent model of the full-bridge submodule, and the Thevenin branch of the bridge arm inductor are connected in series to obtain the Thevenin equivalent model of the bridge arm.

2. The unified modeling method for hybrid modular multilevel converters according to claim 1, characterized in that, The expression for the conduction function is: ； Where k is the switch group number; The conduction function coefficients of the k-th switch group; is the gate drive signal for the k-th switch group; s is the bridge arm current direction indicator; The conduction characteristic coefficients of the submodule; =1 indicates that when s=1, the diode in the k-th switch group is forward-biased; =-1 indicates that when s=-1, the diode in the k-th switch group is forward-biased.

3. The unified modeling method for hybrid modular multilevel converters according to claim 2, characterized in that, The expression for the equivalent function of the variable resistance is: ； in, The variable resistor is the k-th switch group; This is the resistance value when the switch group is turned on; This is the resistance value when the switch group is turned off.

4. The unified modeling method for hybrid modular multilevel converters according to claim 1, characterized in that, Based on a preset capacitance dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized to obtain the Thevenin branch of the submodule capacitor, including: The conduction characteristic coefficients of the half-bridge submodule are obtained based on the gate drive signal and the direction of the bridge arm current of the half-bridge switch group. The conduction characteristic coefficients of the full-bridge submodules are obtained based on the gate drive signal of the full-bridge switch group and the direction of the bridge arm current. Based on the conduction characteristic coefficients of the half-bridge submodule and the full-bridge submodule, the capacitor current is obtained. Based on the capacitor current and the capacitor dynamic equation, the capacitors in the half-bridge submodule and the full-bridge submodule are discretized using the implicit trapezoidal integral method to obtain the Thevenin branch of the submodule capacitor, which is formed by the discrete equivalent resistance of the capacitor and the historical equivalent voltage source of the capacitor connected in series.

5. The unified modeling method for hybrid modular multilevel converters according to claim 4, characterized in that, The expression for the conduction characteristic coefficient of the half-bridge submodule is: ； in, The conduction characteristic coefficient of the half-bridge submodule; This is the gate drive signal for the first switching group in the half-bridge submodule; is the gate drive signal for the second switching group in the half-bridge submodule; s is the bridge arm current direction indicator. The expression for the conduction characteristic coefficient of the full-bridge submodule is: ； in, These are the conduction characteristic coefficients of the full-bridge submodule; This is the gate drive signal for the first switching group in the full-bridge submodule; This is the gate drive signal for the second switching group in the full-bridge submodule; This is the gate drive signal for the third switch group in the full-bridge submodule; This is the gate drive signal for the fourth switch group in the full-bridge submodule.

6. The unified modeling method for hybrid modular multilevel converters according to claim 4, characterized in that, The expression for the Thevenin branch of the submodule capacitor is: ； ； in, Let be the port output voltage of the Thevenin branch of the capacitor at time t; The discrete equivalent resistance of the capacitor; This is for simulating step size; Let t be the capacitor current. Let be the equivalent voltage source of the capacitor at time t; This is the equivalent voltage source of the capacitor history from the previous simulation step.

7. The unified modeling method for hybrid modular multilevel converters according to claim 1, characterized in that, The expression for the Thevenin branch of the bridge arm inductor is: ； ； in, This is for simulating step size; The discrete equivalent resistance of the bridge arm inductance; The inductor history current in the previous simulation step; The historical voltage source of the bridge arm inductor at time t; Let t be the port output voltage of the Thevenin branch of the bridge arm inductor; Let t be the bridge arm current.

8. The unified modeling method for hybrid modular multilevel converters according to claim 1, characterized in that, The expression for the Thevenin equivalent model of the half-bridge submodule is: ； ； in, Thevenin equivalent resistance of the half-bridge submodule; Let be the conduction characteristic coefficient of the half-bridge submodule at time t; The resistance of the switch group when it is turned on; The discrete equivalent resistance of the capacitor; Thevenin equivalent voltage source for the half-bridge submodule; This is for simulating step size; The equivalent voltage source of the capacitor history in the previous simulation step; The expression for the Thevenin equivalent model of the full-bridge submodule is: ； ； in, The Thevenin equivalent resistance of the full-bridge submodule; Let be the conduction characteristic coefficient of the full-bridge submodule at time t; It is the Thevenin equivalent voltage source for the full-bridge submodule.

9. The unified modeling method for hybrid modular multilevel converters according to claim 1, characterized in that, The expression for the Thevenin equivalent model of the bridge arm is: ； ； in, The Thevenin total equivalent resistance of the bridge arm; This represents the total number of half-bridge sub-modules within the bridge arm. This represents the total number of all bridge sub-modules within the bridge arm; This is the resistance value when the switch group is turned on; Let be the conduction characteristic coefficient of the i-th half-bridge submodule at time t; Let be the conduction characteristic coefficient of the j-th full-bridge submodule at time t; The discrete equivalent resistance of the bridge arm inductance; The equivalent resistance of the bridge arm; The Thevenin total equivalent voltage source for the bridge arm; For the Thevenin equivalent voltage source of the i-th half-bridge submodule; For the j-th full-bridge submodule, the Thevenin equivalent voltage source is used. The historical voltage source of the bridge arm inductance at time t.

10. A storage medium, characterized in that, The storage medium stores a computer program, wherein the computer program is configured to execute the unified modeling method for the hybrid modular multilevel converter according to any one of claims 1 to 9 when it runs.

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