A pulse neural network hardware accelerator

Abstract

This invention discloses a hardware accelerator for spiking neural networks, relating to the field of neural network chip technology. The accelerator includes a two-dimensional mesh on-chip network and multiple interconnected computing cores. Each computing core comprises a weight calculation module, a pulse scheduling module, a LIF neuron module, and a pulse address translation module. The weight calculation module adopts a fixed-cycle pipeline structure, with built-in, mutually separate RL, CO, and WV memory units. It divides the structured sparse weight data into square blocks, retains weights at row and column intersections, and performs weighted accumulation. The pulse address translation module converts AER pulse addresses into corresponding memory read addresses, and the pulse scheduling module implements timing synchronization. The LIF neuron module performs leakage attenuation and threshold judgment on the accumulation results, generates pulses, and allows configuration of thresholds and attenuation coefficients. Each computing core transmits pulses and calculation results through the mesh on-chip network.

Description

Technical Field

[0001] This invention belongs to the field of hardware acceleration technology for spiking neural networks (SNN), and specifically relates to a hardware accelerator for spiking neural networks. Background Technology

[0002] Spiking neural networks, as the third generation of artificial neural networks, are widely used in edge intelligence scenarios due to their event-driven and low-power computing characteristics. To adapt to large-scale neural network deployments, structured sparsity is typically used to prune and optimize weights. However, existing hardware accelerators are mostly designed for traditional artificial neural networks and have poor adaptability to sparse weight operations in spiking neural networks.

[0003] Existing architectures generally suffer from low efficiency in storing and retrieving sparse weights, inconsistent pipeline timing, and high latency in data interaction between cores, making it difficult to efficiently achieve parallel computation of fine-grained sparse weights. Furthermore, some hardware lacks address adaptation for AER (Address Event Representation) format pulses, and neuron leakage decay and threshold parameters are not configurable, resulting in insufficient hardware flexibility and low utilization of computational resources. This fails to meet the acceleration requirements of spiking neural networks in low-power, high-real-time scenarios.

[0004] Existing technologies lack dedicated hardware acceleration architectures for fine-grained structured sparse features, making it impossible to achieve efficient addressing, parallel computing, and dynamic configuration of structured sparse weights. Furthermore, the lack of unified hardware support for weight blocks, address mapping, data caching, and neuron update mechanisms results in limited overall acceleration efficiency, high power consumption, and unbalanced timing. Summary of the Invention

[0005] This invention provides a hardware accelerator for spiking neural networks, comprising: a two-dimensional mesh network-on-chip (NoC), and multiple computing cores interconnected through the two-dimensional mesh network-on-chip; each computing core includes a weight calculation module for performing fine-grained structured sparse weight operations; the weight calculation module is configured to perform block processing and calculation of structured sparse weight data using a fixed-cycle pipeline structure; each computing core transmits the generated pulses and sparse calculation results to adjacent computing cores through the two-dimensional mesh network-on-chip.

[0006] According to one embodiment of the present invention, the weight calculation module is configured with an RL storage unit, a CO storage unit, and a WV storage unit, wherein the RL storage unit, the CO storage unit, and the WV storage unit are disposed separately from each other; the address of the CO storage unit corresponds one-to-one with the address of the WV storage unit.

[0007] According to one embodiment of the present invention, the computing core further includes a pulse scheduling module; the pulse scheduling module is configured with a timing control unit, the timing control unit being synchronized with the clock cycle of the fixed-cycle pipeline structure, and each execution stage of the fixed-cycle pipeline structure occupying a fixed clock cycle.

[0008] According to one embodiment of the present invention, the RL storage unit stores row validity identifiers in bitmap form, with each row corresponding to one bit; the weight calculation module performs the following operations sequentially within the clock cycle of the fixed-cycle pipeline structure: reading the row validity identifier from the RL storage unit, reading the column offset and weight value at the same address from the CO storage unit and the WV storage unit, and accumulating the weight value.

[0009] According to one embodiment of the present invention, the fine-grained structured sparse weight operation includes: dividing the structured sparse weight data into portions of size . Configurable square blocks, each block retains the weights of the intersection points of rows and columns at a preset ratio; where, The value is an integer; the column offset is numbered sequentially to the right, with the leftmost column in the square block as column 0. The column offset corresponds one-to-one with the weight values ​​stored in the WV storage unit in address order.

[0010] According to one embodiment of the present invention, the computing core further includes a LIF neuron module; after the weight calculation module accumulates the weight values ​​to obtain the neuron accumulation result, the LIF neuron module confirms that the neuron accumulation result is greater than or equal to a preset threshold, generates a pulse signal, and clears the neuron accumulation result to zero.

[0011] According to one embodiment of the present invention, the LIF neuron module performs a fixed-proportion leakage attenuation on the accumulated result of the neuron, compares the attenuated result with a preset threshold, and performs a pulse signal generation operation.

[0012] According to one embodiment of the present invention, the preset threshold is a configurable threshold, and the LIF neuron module is configured with a threshold register for storing and updating the preset threshold.

[0013] According to one embodiment of the present invention, the fixed ratio coefficient of leakage attenuation is configurable, and the LIF neuron module is configured with a leakage coefficient register for storing and adjusting the ratio of leakage attenuation.

[0014] According to one embodiment of the present invention, the computing core further includes a pulse address conversion module; the pulse address conversion module is configured to convert the address signal of the AER format pulse into the corresponding read address of the RL memory unit and the CO memory unit.

[0015] This invention improves the efficiency of pulse and data transmission between computing cores by employing a two-dimensional mesh on-chip network to achieve multi-core interconnection. The weight calculation module adopts a fixed-cycle pipeline structure, combined with separate storage and address mapping of RL, CO, and WV, significantly improving the efficiency of reading and calculating fine-grained structured sparse weights. The configurable block partitioning and row / column intersection weight retention methods reduce storage and computational overhead while ensuring computational accuracy. The pulse address translation module can directly adapt to AER format pulses, reducing address parsing time. The LIF neuron module supports configurable thresholds and leakage attenuation coefficients, improving hardware adaptability and flexibility. The overall solution achieves fixed-time, low-latency, and high-resource-utilization sparse computation of spiking neural networks, effectively reducing hardware power consumption and meeting the real-time inference requirements of edge computing. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the hardware accelerator for spiking neural networks provided by the present invention; wherein (a) is a topology diagram of the overall architecture of the accelerator, showing the interconnection relationship between the two-dimensional Mesh on-chip network and multiple computing cores; (b) is an internal structure diagram of a single computing core, showing the connection relationship between the pulse scheduling module, pulse address translation module, weight calculation module, LIF neuron module, FIFO module and cross switch module; (c) is a schematic diagram of the internal storage structure of the weight calculation module, showing the separate layout of the three types of storage units: RL, CO and WV.

[0018] Figure 2 This is a fixed-cycle pipeline timing diagram of the weight calculation module of the present invention, showing the timing overlap of stages such as RL reading, CO / WV synchronous reading, weight accumulation, and data output, reflecting the bubble-free continuous operation characteristics.

[0019] Figure 3 This is a schematic diagram illustrating the sparse weight matrix partitioning, row and column filtering, and storage mapping of the present invention. The block partitioning method, the effective row / column filtering rules, and the data correspondence between the three storage units RL / CO / WV.

[0020] Figure 4 This is a schematic diagram of the reconfigurable RL / CO / WV three-cell storage structure of the present invention; wherein (a) is the bitmap storage structure of the RL storage cell; (b) is the column offset storage structure of the CO storage cell; and (c) is the weight storage structure of the WV storage cell, showing the reconfigurable configuration under different block sizes.

[0021] Figure label: 100: Spiking Neural Network Hardware Accelerator; 110: Two-Dimensional Mesh On-Chip Network; 120: Computational Core; 121: Spiking Scheduling Module; 122: Spiking Address Translation Module; 123: Weight Calculation Module; 124: LIF Neuron Module; 1231: RL Storage Unit; 1232: CO Storage Unit; 1233: WV Storage Unit. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0023] This invention addresses the problems of low sparse computation efficiency, poor timing synchronization, and inflexible parameter configuration in existing spiking neural network hardware accelerators, and proposes a hardware accelerator for fine-grained structured sparse spiking neural networks. The specific structure, workflow, and technical effects of this invention are further described in detail below with reference to the accompanying drawings.

[0024] This embodiment uses a two-dimensional mesh on-chip network, multiple computing cores, three separate storage units, and a fixed-cycle pipeline as its architecture, and fully discloses the hardware composition, module connection relationship, data processing flow, and timing control method of the present invention, so that those skilled in the art can clearly understand and implement the technical solution described in the present invention.

[0025] Below, please refer to the appendix. Figure 1-4 The hardware accelerator for the spiking neural network of the present invention will be described. Figure 1 This is a schematic diagram of the hardware accelerator for spiking neural networks provided by the present invention; wherein, (a) is an overall architecture diagram of the hardware accelerator for spiking neural networks; (b) is an internal structure diagram of a single computing core 120; and (c) is the internal storage structure of the weight calculation module. Figure 1As shown in (a) and (b), the spiking neural network hardware accelerator 100 provided by the present invention includes: a two-dimensional mesh on-chip network 110, and multiple computing cores 120 interconnected through the two-dimensional mesh on-chip network 110; the computing core 120 includes a weight calculation module 123, which is used to perform fine-grained structured sparse weight operations; the weight calculation module 123 adopts a fixed-cycle pipeline structure to perform block processing and calculation on the structured sparse weight data; each computing core 120 transmits the generated pulses and sparse calculation results to the adjacent computing core 120 through the two-dimensional mesh on-chip network 110.

[0026] Specifically, the spiking neural network hardware accelerator 100 provided by this invention includes a two-dimensional mesh on-chip network 110 and multiple computing cores 120. All computing cores 120 establish a stable connection through the two-dimensional mesh on-chip network 110, enabling continuous signal and data interaction during device operation. Each computing core 120 internally includes a weighted calculation module 123, specifically designed to handle fine-grained structured sparse weight-related computational tasks, improving overall computational efficiency while maintaining computational accuracy. The computing core 120 also includes a FIFO module, a cross-switching module, and an input decoding module. The FIFO module comprises four 8-depth asynchronous FIFOs and one 8-depth synchronous FIFO, used for packet buffering and cross-clock domain data isolation in the local direction, east, west, south, and north directions. The cross-switching module employs an XY-dimensional routing algorithm to achieve deadlock-free and livelock-free routing and forwarding of AER format packets. The weight calculation module 123 employs a fixed-cycle pipeline structure to perform operations. This structure ensures a stable timing state during data processing. It also systematically divides the structured sparse weight data entering the module into blocks before completing all calculation steps according to a defined process. After completing internal data processing and computation, each computing core 120 outputs its generated pulse signal and the results obtained from sparse computation. These signals and results are transmitted via the two-dimensional mesh on-chip network 110 to other nearby computing cores 120, forming a distributed computing system and achieving efficient and stable continuous operation.

[0027] Reference Figure 1 As shown in (a), the two-dimensional mesh on-chip network 110 adopts a two-dimensional mesh topology, distributing multiple computing cores 120 across mesh nodes to achieve low-latency, non-blocking transmission of pulses and data between cores. (Refer to...) Figure 1As shown in (b), a single computing core 120 integrates a pulse scheduling module 121, a pulse address translation module 122, a weight calculation module 123, a LIF neuron module (Leaky Integrate-and-Fire) 124, a FIFO module, and a crossbar switch module, forming a complete spiking neural network computing node. (Refer to...) Figure 1 As shown in (c), the weight calculation module 123 adopts a separate layout of RL storage unit (Row Location) 1231, CO storage unit (Column Offset) 1232, and WV storage unit (Weight Value) 1233. The three types of storage units are physically independent and address aligned, supporting parallel reading of sparse weights.

[0028] According to an embodiment of the present invention, the weight calculation module 123 is configured with an RL storage unit 1231, a CO storage unit 1232 and a WV storage unit 1233. The RL storage unit 1231, the CO storage unit 1232 and the WV storage unit 1233 are set separately from each other, and the address of the CO storage unit 1232 corresponds one-to-one with the address of the WV storage unit 1233.

[0029] Specifically, such as Figure 1 (c) and Figure 4 As shown in (a), (b), and (c), the weight calculation module 123 has three independent storage structures, each undertaking different data storage functions. The RL storage unit 1231 uses a bitmap structure to record data and stores row validity identifiers. Each row of data corresponds to an independent bit, which can compactly mark the valid row information participating in the calculation. The CO storage unit 1232 stores column offset data, and the WV storage unit 1233 stores weight data. The two types of storage units maintain independent storage paths and control logic. The CO storage unit 1232 and the WV storage unit 1233 adopt an address synchronization setting. The column offset information and weight information stored at the same address location are strictly matched, ensuring that the weight calculation module 123 can synchronously read the corresponding data during operation, improving the stability and execution efficiency of fine-grained structured sparse weight calculation.

[0030] In this embodiment, the RL storage unit 1231 is a 32×64 RAM, the CO storage unit 1232 is a 16×192 RAM, and the WV storage unit 1233 is composed of eight 128×32 RAMs. The three types of storage units are physically isolated, have independent clocks, and independent read / write control.

[0031] Reference Figure 4As shown in (a), the RL storage unit 1231 adopts a bitmap reconfigurable storage structure, and the bit length is dynamically adjusted according to the weight block size; refer to Figure 4 As shown in (b), the CO memory cell 1232 adopts a continuous address incrementing structure, with the column offset number starting from the leftmost column 0 within the block and incrementing sequentially; refer to Figure 4 As shown in (c), the WV storage cell 1233 adopts a storage structure that is fully aligned with the column offset address. The same address can be synchronously output with matching weights to achieve single-cycle parallel reading.

[0032] like Figure 4 As shown in (a), the RL storage unit 1231 uses a bitmap method to implement reconfigurable storage of row validity identifiers. The storage depth is consistent with the block size of the weight matrix. Each row corresponds to a bit. A bit of "1" indicates that the current row is a valid row, and a bit of "0" indicates that the current row is an invalid row. The storage structure is dynamically adjusted according to the block size in 8×8, 16×16, 32×32, and 64×64 modes.

[0033] like Figure 4 As shown in (b), the CO storage unit 1232 adopts a continuous address increment method to realize the reconfigurable storage of column offsets. The column offsets are numbered starting from the leftmost column of each block and increasing sequentially to the right. The storage depth is consistent with the number of columns in the block, and the address and the number of column offsets are in one-to-one correspondence. It supports synchronous addressing with the RL storage unit 1231.

[0034] like Figure 4 As shown in (c), the WV storage unit 1233 adopts the address alignment with the CO storage unit 1232 to realize the reconfigurable storage of weight values. The weight values ​​output at the same address are precisely matched with the column offset information. The storage depth is consistent with the number of effective weights. All effective weights are stored continuously in ascending order of address. Invalid weights do not occupy storage space.

[0035] The RL storage unit 1231, CO storage unit 1232, and WV storage unit 1233 adopt a reconfigurable structure design, which can dynamically adjust the storage depth and bit width according to the block size of the weight matrix. The three are fully aligned in address and fully synchronized in timing, providing stable and reliable storage support for the continuous and efficient operation of the fixed-cycle pipeline.

[0036] According to an embodiment of the present invention, the computing core 120 further includes a pulse scheduling module 121, which is configured with a timing control unit. The timing control unit is synchronized with the clock cycle of the fixed-cycle pipeline structure, and each execution stage of the fixed-cycle pipeline structure occupies a fixed clock cycle.

[0037] Specifically, the timing control unit inside the pulse scheduling module 121 provides a unified timing reference for the overall computation process. The clock signal output by the timing control unit maintains synchronous operation with the fixed-cycle pipeline structure adopted by the weight calculation module 123, ensuring that the data processing flow proceeds at a stable pace. During operation, the fixed-cycle pipeline structure allocates a clock cycle of consistent length to each execution stage to complete the corresponding operation. Different stages are sequentially connected according to a preset order, preventing timing offsets or inconsistent stage durations. This stable timing control method allows a series of operations such as sparse weight partitioning, data reading, and weight accumulation to be executed in an orderly manner, avoiding data conflicts and operational disorder, and improving the overall reliability and consistency of the spiking neural network hardware accelerator.

[0038] The fixed-cycle pipeline has five stages. In the first cycle, the RL storage unit is read. In the second cycle, the CO and WV storage units are read simultaneously. In the third to fifth cycles, the weight accumulation and result output are completed. The entire pipeline is bubble-free and has no waiting time.

[0039] Reference Figure 2 As shown, the weight calculation module is driven by a single clock from the same source, and all execution stages are aligned with the same clock signal, with no phase offset or timing jitter between stages.

[0040] The pipeline first accesses the RL memory unit based on the pulse address signal, reads the row validity identification information of the current row, and then enters the RAM read stabilization stage, waiting for reliable data output.

[0041] After completing the reading of RL memory cell 1231, the pipeline combines the pulse address and row validity identification information to simultaneously access CO memory cell 1232 and WV memory cell 1233 to read the column offset information and corresponding weight data of the current row.

[0042] Once the column offset information and weight data are ready, the pipeline enters the weight accumulation stage, using the one-to-one correspondence between CO storage unit 1232 and WV storage unit 1233 to complete the membrane potential accumulation calculation for the current row.

[0043] Because the production line uses a row-overlapping design, when the first... When the row enters the weight accumulation phase, the first The line has entered the reading stage of CO storage unit 1232 and WV storage unit 1233, the first... The algorithm has entered the reading stage of RL storage unit 1231. There are no pauses or bubbles between each stage, which can make full use of hardware resources and achieve continuous and efficient weight calculation.

[0044] The weight calculation pipeline sequentially completes five execution stages: reading row valid identifiers, outputting column offset addresses, reading weight data, performing weight accumulation calculations, and temporarily storing the accumulation results. Each execution stage occupies a fixed clock phase, and the stages are sequentially connected without resource conflicts or data contention.

[0045] At the beginning of each clock cycle, the timing control unit outputs a unified synchronization signal to control the synchronous execution of row valid identifier reading, column offset address output, weight data reading, and weight accumulation calculation.

[0046] The row validity identifier reading unit reads the current row validity identifier, the column offset address output unit outputs the corresponding column offset address, the weight data reading unit reads the weight data according to the row validity identifier and the column offset address, the weight accumulation operation unit accumulates the weight data, and the accumulation result is written to the temporary register before the end of the current clock cycle.

[0047] At the start of the next clock cycle, the accumulated result in the temporary register is synchronously output to the subsequent processing unit, providing time-aligned computation results for subsequent neuron processing.

[0048] Through the aforementioned fixed-period, strongly synchronized, and sequentially connected pipeline timing mechanism, this invention can ensure that pulse sending, address translation, data reading, weight calculation, and inter-core transmission are fully aligned when processing multiple structured sparse blocks continuously, significantly improving the hardware stability and throughput of fine-grained sparse computing.

[0049] Reference Figure 2 As shown, the present invention adopts a five-level fixed-cycle pipeline timing, with seamless overlap between each stage of the pipeline. The first cycle completes the reading of the row valid identifier, the second cycle completes the reading of the column offset and weight synchronization, and the third to fifth cycles complete the weighted accumulation and result output. There are no idle cycles throughout the process, ensuring that the sparse operation timing is fixed and the throughput is stable.

[0050] According to an embodiment of the present invention, the RL storage unit 1231 stores row valid identifiers in the form of a bitmap, with each row corresponding to one bit; the weight calculation module 123 performs the following operations sequentially within the clock cycle of the fixed-cycle pipeline structure: reading row valid identifiers from the RL storage unit 1231, reading column offsets and weight values ​​at the same address from the CO storage unit 1232 and the WV storage unit 1233, and accumulating the weight values.

[0051] Specifically, the RL storage unit 1231 uses a bitmap format to store row validity identifiers, with each row of data corresponding to an independent bit, enabling the marking of valid row positions for computation in a concise storage manner. Under the control of a fixed-cycle pipeline structure, the weight calculation module 123 advances the computation process according to a unified clock cycle. It first reads the row validity identifiers from the RL storage unit 1231 to determine the row information to be included in the calculation. Simultaneously, it reads column offset data and weight data from the CO storage unit 1232 and WV storage unit 1233 at the same address, respectively, ensuring the synchronization and matching of data reading. After completing the data reading, the weight calculation module 123 performs an accumulation operation on the obtained weight values, completing the numerical processing according to the operation rules of fine-grained structured sparse weights, providing accurate calculation results for the subsequent pulse generation stage.

[0052] The accumulated result of the neurons is first added to the membrane potential of the previous time step, and then sent to the LIF neuron module for leakage attenuation and threshold determination.

[0053] In one specific embodiment, for the input structured sparse weighted data, the positions of the valid rows participating in the calculation are first determined according to preset filtering conditions, and then the corresponding bitmap information is generated according to the distribution of the valid rows. The bits corresponding to the valid rows are set to the valid state, and the bits corresponding to the invalid rows are set to the invalid state. All bits are arranged sequentially according to the row number to form bitmap information that can be stored in RL storage unit 1231. The bitmap information generated in this way occupies little space, has a fast positioning speed, and can quickly complete the identification and reading of valid rows when the weight calculation module 123 is running, thus improving the overall data processing efficiency.

[0054] According to an embodiment of the present invention, fine-grained structured sparse weight operation includes: dividing the structured sparse weight data into portions of size . Configurable square blocks, each block retains the weights of the intersection points of rows and columns at a preset ratio, where... The column offset is an integer; the column offset is numbered sequentially from the leftmost column in the square block to the right, with the column offset corresponding one-to-one with the weight values ​​stored in WV storage unit 1233 in address order.

[0055] Specifically, the structured sparse weighted data is partitioned according to configurable size rules, forming a 2x2 matrix. Square data blocks of power 1 The value can be adjusted according to actual computational needs. Within each divided data block, only the weight information of the intersection positions of rows and columns is retained according to a preset proportion, while invalid data in other positions is discarded, thereby reducing data storage and computational load. In this embodiment, the preset proportion is 50% for rows and 50% for columns, retaining only the weights of the intersection points of valid rows and columns, ultimately achieving a fixed weight sparsity of 75%. (Refer to...) Figure 3 As shown, structured sparse weights are based on The system divides data into configurable square blocks, retaining only the weights at the intersections of valid rows and columns, while invalid weights are discarded. Row validity identifiers are stored in the RL storage unit in bitmap format, column offsets in the CO storage unit, and valid weights in the WV storage unit, forming a dedicated sparse storage mapping relationship. Column offset information starts at the leftmost column of the current data block, numbered 0, and increments sequentially from left to right. Column offset information is stored sequentially according to address order, with each column offset corresponding one-to-one with the weight value stored at the same address in WV storage unit 1233. This ensures the weight calculation module can quickly match data, improving the efficiency and accuracy of fine-grained structured sparse weight calculations.

[0056] The weight matrix can be divided into configurable square regions of various sizes, such as 8×8, 16×16, 32×32, and 64×64, to adapt to different network models and sparse computing requirements. If the weight matrix is ​​divided into 1×1 squares, the overall weight distribution transforms into an unstructured sparse form. In this form, each weight can be independently selected and controlled, achieving the highest degree of freedom in sparse configuration. Simultaneously, relying on the separate storage structure and fixed-cycle pipeline of this invention, stable access timing and efficient computation rhythm can still be maintained, significantly improving hardware utilization in unstructured sparse scenarios. The above block specifications are only preferred embodiments; the specific block size can be flexibly adjusted according to the actual network scale and sparsity.

[0057] In one specific embodiment, the weight matrix is ​​divided into 8×8 square regions, and the preset proportion retained within each block is set to 50%. Figure 3For example, within the currently divided square area, the system filters valid weights in both row and column directions, retaining only the weights at the intersection of valid rows and columns, and discarding all other non-intersection weights. First, rows are filtered. A cumulative value is calculated for each row, and all rows are sorted based on their cumulative values. The half of the rows with the highest cumulative values ​​are selected as valid rows according to a preset ratio, and their corresponding flags are set to valid. The remaining half of the rows are marked as invalid, and their corresponding weights are discarded. The calculation of the cumulative value for each row is based on the sum of all valid weights within that row. This sum directly reflects the current row's contribution to the overall calculation result. After calculating the cumulative values ​​for all rows, all rows are sorted in descending order of cumulative value. Rows at the beginning of the sorted results have a higher calculation contribution, while rows at the end have a relatively lower contribution. According to a preset retention ratio, the first half of the sorted results are selected as valid rows, and their corresponding flags are set to "1," indicating that the current row participates in the subsequent weight reading and calculation process. The remaining half of the sorted results are determined to be invalid rows. The flag bit corresponding to the invalid row is set to invalid state "0". All values ​​in the current row will no longer participate in storage and calculation, thereby reducing the consumption of hardware resources by invalid data.

[0058] After row filtering, the same filtering logic is applied to columns, sorting based on the cumulative value of each column and selecting 50% of the columns as valid columns in the same proportion. After filtering by rows and columns, the system only retains the weight data at the intersection of valid rows and columns; weights at other positions are not stored or calculated. Taking an 8×8 area as an example, with eight rows and eight columns, after filtering by 50% each, the number of valid rows and columns is reduced to four, resulting in sixteen valid weights, achieving a 75% weight pruning ratio. This structured filtering method significantly reduces the amount of weight data while maintaining calculation accuracy, lowering storage and computational overhead, and maintaining the regularity of data access and computation processes.

[0059] like Figure 3 As shown in (a), within each configurable square block formed by dividing the weight matrix, the leftmost column of the square block is used as the starting reference for column offset, and the offset number of the reference column is fixed as column 0. As the column position extends horizontally to the right within the square block, the corresponding column offset number is automatically incremented by 1 for each column moved to the right, thus forming a continuous and regular sequence of column offset numbers.

[0060] After generation, the column offset numbers are arranged in ascending order from left to right, forming a strict address sequence correspondence with the weight values ​​stored in WV memory cell 1233. When the weight calculation module 123 performs read operations in a fixed-cycle pipeline, for each column offset address input to CO memory cell 1232, WV memory cell 1233 will output a weight value that perfectly matches the column offset at the same address, ensuring that the column offset number and the weight value are perfectly aligned in address, timing, and quantity.

[0061] Within the same square block, the column offsets corresponding to all valid columns are consecutively numbered according to the above rules, with no jumps, repetitions, or misalignments. A one-to-one mapping relationship is maintained between valid column offsets and valid weight values. Offsets and weight values ​​corresponding to invalid columns are masked and do not occupy storage units or data paths.

[0062] This column offset numbering method and storage correspondence method can ensure that column offset reading, weight value reading, and weight accumulation operations are completed synchronously within the same pipeline cycle in fine-grained structured sparse computing scenarios, without causing address misalignment, timing deviation, or data mismatch issues, and further improve the timing stability and computational accuracy of hardware accelerators in the structured sparse computing process.

[0063] According to an embodiment of the present invention, the calculation core 120 further includes a LIF neuron module 124. After the weight calculation module 123 accumulates the weight values ​​to obtain the neuron accumulation result, the LIF neuron module 124 confirms that the neuron accumulation result is greater than or equal to a preset threshold, generates a pulse signal, and clears the neuron accumulation result to zero.

[0064] Specifically, after the weight calculation module 123 completes the weight accumulation operation, it transmits the obtained neuron accumulation result to the LIF neuron module 124. The LIF neuron module 124 performs a numerical judgment on the received neuron accumulation result. When the neuron accumulation result is greater than or equal to a preset threshold, the module immediately generates a corresponding pulse signal and outputs it. After the pulse signal is generated, the LIF neuron module 124 performs a zeroing operation on the current neuron accumulation result, restoring the value to the initial state, preparing for the next round of weight accumulation and pulse judgment process, ensuring that the spiking neural network hardware accelerator can continuously and stably complete continuous computation and pulse output. After the pulse signal is encoded into AER format by the output packaging module, it is sent to the cross-switch module, and then forwarded to the adjacent computing core through the two-dimensional mesh on-chip network.

[0065] According to an embodiment of the present invention, the LIF neuron module 124 performs a fixed-proportion leakage attenuation on the accumulated neuron result, compares the attenuated result with a preset threshold, and performs a pulse signal generation operation.

[0066] Specifically, after receiving the neuron accumulation result output by the weight calculation module 123, the LIF neuron module 124 performs leakage attenuation processing on the neuron accumulation result according to a fixed ratio, causing the relevant values ​​to gradually decrease over time. After the attenuation processing is completed, the LIF neuron module 124 compares the attenuated result with a preset threshold. If the attenuated result meets the condition, the LIF neuron module 124 generates and outputs a pulse signal. If the attenuated result does not meet the condition, the LIF neuron module 124 does not generate a pulse signal, but only retains the current attenuated result to enter the next working stage. The entire processing flow proceeds in an orderly manner under the control of a unified clock, and each step maintains strict timing synchronization to ensure that the pulse signal generation process is stable and reliable.

[0067] The LIF neuron module 124 executes its computational steps sequentially. First, it receives the accumulated neuron result output by the weight calculation module 123. The internal leakage attenuation unit processes this accumulated result according to a pre-configured fixed ratio coefficient to obtain the attenuated neuron potential value. Then, the threshold comparison unit compares the attenuated neuron potential value with a preset threshold stored internally, determining the current neuron activation state based on the comparison result. Finally, the pulse generation unit performs corresponding operations based on the threshold comparison result. If the neuron potential value reaches or exceeds the preset threshold, a pulse signal is generated and output; if the neuron potential value does not reach the preset threshold, no pulse signal is output, and the current neuron potential state is maintained until the next accumulation operation.

[0068] The above-mentioned step sequence limits ensure that the processing flow of the LIF neuron module 124 is precisely aligned with the fixed-cycle pipeline of the weight calculation module 123, ensuring that continuous operations such as decay, comparison and pulse generation are completed within the same clock cycle, avoiding timing misalignment or logical ambiguity between different steps, thereby guaranteeing the timing stability and computational accuracy of the accelerator in fine-grained structured sparse computing scenarios.

[0069] After receiving the accumulated result of the neurons, the LIF neuron module 124 compares it with the preset threshold pre-configured in the internal threshold register in real time.

[0070] When the accumulated result of the neurons is greater than or equal to the preset threshold, the LIF neuron module 124 determines that the current neuron has been successfully activated, immediately outputs a valid pulse signal, and transmits the pulse event to the subsequent computing core 120 and the two-dimensional Mesh on-chip network 110. At the same time, the LIF neuron module 124 performs a zeroing operation on the accumulated result of the neurons inside, resetting the accumulated value to zero, in order to prepare for the weight accumulation and pulse judgment of the next structured sparse block.

[0071] When the accumulated result of the neuron is less than the preset threshold, the LIF neuron module 124 determines that the current neuron is not activated, does not generate a pulse signal, only maintains the current accumulated result, and waits for the weight data of the next clock cycle to continue to participate in the accumulation operation until the accumulated result meets the threshold condition or the current calculation block is completed.

[0072] Through this working mechanism of first accumulating, then comparing, triggering when the condition is met, and clearing when triggered, the LIF neuron module 124 can accurately achieve pulse trigger control, avoid repeated triggering and false triggering, and at the same time ensure that the pipeline timing is clean, stable and without accumulated errors, so that the entire accelerator maintains stable timing and high execution efficiency in fine-grained structured sparse computing.

[0073] According to an embodiment of the present invention, the preset threshold is a configurable threshold, and the LIF neuron module 124 is configured with a threshold register for storing and updating the preset threshold.

[0074] Specifically, the LIF neuron module 124 integrates a dedicated threshold register. This register can be written to and updated in real time via an external configuration interface, storing flexibly adjustable preset thresholds. The threshold register remains stable and readable throughout hardware operation, providing a unified and accurate reference standard for pulse generation judgment. The system can directly modify the threshold parameters in the register according to different network models, computational scenarios, and accuracy requirements, without altering the overall hardware architecture, thus adapting to diverse sparse computation and pulse generation tasks. Register update operations are time-isolated from weight calculation and attenuation judgment processes, ensuring no interference with normal computation and guaranteeing that the LIF neuron module 124 maintains a stable and continuous operating state while dynamically adjusting the judgment standard.

[0075] The LIF neuron module 124 integrates an independent threshold register with a read-write configuration structure, capable of receiving numerical write operations through an external configuration interface. During system power-on initialization, the threshold register loads default threshold parameters. During runtime, it receives new threshold configuration data in real time and updates the parameters based on the requirements of the spiking neural network model and the sparse computation scenario. The updated threshold data is stably latched within the register, continuously providing a reference for the numerical comparison unit of the LIF neuron module 124. The numerical comparison unit compares the leak-attenuated neuron potential with the real-time threshold stored in the threshold register, determining whether the neuron triggers a pulse output based on the comparison result. The configurable nature of the threshold register allows the LIF neuron module 124 to adapt to the computational needs of different levels and types of neurons, compatible with various spiking neural network models and sparse weight structures, improving the overall accelerator's applicability and flexibility without altering the hardware circuitry.

[0076] According to an embodiment of the present invention, the fixed ratio coefficient of leakage attenuation is configurable, and the LIF neuron module 124 is configured with a leakage coefficient register for storing and adjusting the ratio of leakage attenuation.

[0077] Specifically, the LIF neuron module 124 integrates a leakage coefficient register, which is a read-write configuration register that supports dynamic setting and real-time adjustment of the leakage attenuation ratio coefficient through a hardware configuration interface. The value stored in the leakage coefficient register directly determines the decay rate of the neuron's accumulated result. The system can modify the configuration parameters in the register according to the computational scenario, network model, and real-time task requirements, thereby flexibly changing the leakage attenuation magnitude. The register maintains synchronous timing with the LIF neuron module 124 and participates in the attenuation calculation in each neuron update cycle, ensuring that the attenuation ratio is stable, controllable, and configurable online, without interfering with the weight calculation and pulse generation process. This significantly improves the adaptability and operational flexibility of the spiking neural network hardware accelerator in different sparse computing and low-power inference scenarios.

[0078] The LIF neuron module 124 integrates an independent leakage coefficient register. This register employs a read-write configuration structure and can receive proportional coefficient write operations through an external configuration interface. During system power-on initialization, the leakage coefficient register loads default leakage attenuation ratio parameters. During runtime, it can receive new leakage attenuation ratio configuration data in real time and update the parameters based on the spiking neural network model requirements, sparse computation scenarios, and neuron response characteristics. The updated leakage attenuation ratio is stably latched within the register, continuously providing a proportional reference for the leakage attenuation calculation unit of the LIF neuron module 124.

[0079] The leakage decay calculation unit performs a fixed-proportion decay operation on the neuron accumulation result output by the weight calculation module based on the scaling factor stored in the register in real time, generating the decayed neuron potential. The magnitude of the scaling factor directly determines the decay amplitude of the neuron potential, and different scaling factors can adapt to the computational needs of neurons of different types, levels, and dynamic ranges.

[0080] Within the same clock cycle, the LIF neuron module 124 synchronously completes leakage decay, threshold comparison, and pulse judgment operations. The decay process maintains strict timing alignment with the fixed-cycle pipeline of the weight calculation module. The configurable nature of the leakage coefficient register enables the LIF neuron module 124 to flexibly adapt to various spiking neural network models, various sparse weight structures, and various neuron operating modes. Without changing the hardware circuitry, it improves the overall accelerator's adaptability, computational flexibility, and hardware utilization in fine-grained structured sparse computing scenarios.

[0081] According to an embodiment of the present invention, the computing core 120 further includes a pulse address conversion module 122, which is configured to convert the address signal of the AER format pulse into the corresponding read address of the RL storage unit 1231 and the CO storage unit 1232.

[0082] Specifically, the pulse address conversion module 122 has a built-in address mapping and timing synchronization unit. After receiving the AER standard pulse address signal, it first performs timing alignment and bit width conversion on the address signal, and then converts the AER format pulse address into a physical read address that can be directly recognized by the two sets of storage units according to the physical address encoding rules of RL storage unit 1231 and CO storage unit 1232.

[0083] During the conversion process, the pulse address conversion module 122 maintains a fixed clock cycle synchronization with the weight calculation module 123, preventing address offset, timing delay, or bit width mismatch issues. The converted read address is directly used to read the row valid identifier from the RL storage unit 1231 and the column offset information from the CO storage unit 1232, ensuring that the address signal and data signal arrive synchronously within the same clock cycle. This maintains a continuous and stable reading and calculation process for fine-grained structured sparse weights. The pulse address conversion module resolves the AER address into a block select signal, row address, and column address, which are mapped to the physical addresses of the RL and CO storage units respectively, achieving precise addressing.

[0084] The pulse address conversion module 122 parses and reconstructs the address signal carried by the input AER format pulse, separating and extracting the neuron identification information, timing identification information, and channel identification information contained in the pulse address. According to a pre-set address mapping rule, the pulse address conversion module 122 converts the extracted information into physical read addresses that match the RL storage unit 1231 and the CO storage unit 1232, enabling the converted read addresses to directly address the target storage location in the corresponding storage unit.

[0085] While performing address conversion, the pulse address conversion module 122 maintains strict synchronization with the system clock and pipeline timing to ensure that the converted read address can be delivered to the RL memory unit 1231 and the CO memory unit 1232 synchronously within the same clock cycle, thus avoiding addressing errors or abnormal data reading due to timing deviations.

[0086] The pulse address translation module 122 simplifies the addressing logic of the memory unit through a unified address mapping mechanism, reduces the complexity of the hardware circuit, and improves the addressing efficiency and operational stability of the overall system when processing large-scale sparse pulse signals.

[0087] This module can directly adapt to AER format pulse address input without additional configuration or intermediate conversion steps, greatly simplifying the address parsing process and improving the address response speed and data reading efficiency of spiking neural network hardware accelerators in event-driven sparse computing scenarios.

[0088] In summary, this invention achieves multi-core collaborative computing through a two-dimensional mesh on-chip network, adapts fine-grained structured sparse weights through reconfigurable discrete storage units, ensures timing stability and efficient operation through a fixed-cycle pipeline, enhances model adaptability through a configurable LIF neuron module, and achieves efficient AER pulse addressing through a pulse address translation module. The overall architecture significantly reduces the storage overhead and hardware resource consumption of sparse weight operations while maintaining computational accuracy, improving the inference speed, operational stability, and hardware utilization of the spiking neural network at the edge. It effectively meets the requirements of low-power, high-real-time, and high-sparseness neural network acceleration applications.

[0089] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A hardware accelerator for a spiking neural network, characterized in that, include: A two-dimensional mesh on-chip network, and multiple computing cores interconnected through the two-dimensional mesh on-chip network; The computational core includes a weight calculation module, which is used to perform fine-grained structured sparse weight operations; The weight calculation module is configured to use a fixed-cycle pipeline structure to perform block processing and calculation on structured sparse weight data. Each computing core will transmit the generated pulses and sparse computation results to adjacent computing cores through the two-dimensional mesh on-chip network.

2. The spiking neural network hardware accelerator according to claim 1, characterized in that, The weight calculation module is configured with an RL storage unit, a CO storage unit, and a WV storage unit, which are set separately from each other. The address of the CO storage unit corresponds one-to-one with the address of the WV storage unit.

3. The spiking neural network hardware accelerator according to claim 1, characterized in that, The computing core also includes a pulse scheduling module; The pulse scheduling module is equipped with a timing control unit, which is synchronized with the clock cycle of the fixed-cycle pipeline structure. Each execution stage of the fixed-cycle pipeline structure occupies a fixed clock cycle.

4. The spiking neural network hardware accelerator according to claim 2, characterized in that, The RL storage unit stores row valid identifiers in bitmap form, with each row corresponding to one bit. The weight calculation module executes sequentially within the clock cycle of the fixed-cycle pipeline structure: The operation involves reading the row validity identifier from the RL storage unit, reading the column offset and weight value at the same address from the CO storage unit and the WV storage unit, and accumulating the weight value.

5. The spiking neural network hardware accelerator according to claim 4, characterized in that, The fine-grained structured sparse weighting operation includes: The structured sparse weight data is divided into portions of size [value missing]. Configurable square blocks, each block retains the weights of the intersection points of rows and columns at a preset ratio; where, It is an integer; The column offset is numbered sequentially from the leftmost column within the square block as column 0, and the column offset corresponds one-to-one with the weight values ​​stored in the WV storage unit according to their address order.

6. The spiking neural network hardware accelerator according to claim 4, characterized in that, The computational core also includes a LIF neuron module; After the weight calculation module accumulates the weight values ​​to obtain the neuron accumulation result, the LIF neuron module confirms that the neuron accumulation result is greater than or equal to a preset threshold, generates a pulse signal, and clears the neuron accumulation result to zero.

7. The spiking neural network hardware accelerator according to claim 6, characterized in that, The LIF neuron module performs a fixed-proportion leakage attenuation on the accumulated results of the neurons, compares the attenuated results with a preset threshold, and performs a pulse signal generation operation.

8. The spiking neural network hardware accelerator according to claim 6, characterized in that, The preset threshold is a configurable threshold, and the LIF neuron module is configured with a threshold register for storing and updating the preset threshold.

9. The spiking neural network hardware accelerator according to claim 7, characterized in that, The fixed ratio coefficient for leakage attenuation is configurable, and the LIF neuron module is configured with a leakage coefficient register for storing and adjusting the ratio of leakage attenuation.

10. The spiking neural network hardware accelerator according to claim 2, characterized in that, The computing core also includes a pulse address conversion module; The pulse address conversion module is configured to convert the address signal of the AER format pulse into the corresponding read address of the RL storage unit and the CO storage unit.

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