A graphics processor, a task execution method, an electronic device, and a storage medium

Abstract

The application discloses a graphics processor, a task execution method, an electronic device and a storage medium. The graphics processor comprises an execution unit group, an instruction cache unit and an instruction pipeline. The execution unit group comprises an accumulation register, a running register and an execution unit. The instruction cache unit is used for storing a task instruction sequence. The accumulation register receives and stores a control flow read by the instruction pipeline from the instruction cache unit. When the running register is in an unoccupied state, and the control flow stored in the accumulation register corresponds to a to-be-executed task, and the to-be-executed task corresponds to the execution unit group, the running register reads and configures the control flow from the accumulation register. When the running register successfully configures the control flow, the to-be-executed task is executed by the execution unit. The graphics processor provided by the application can effectively reduce useless resource overhead and computing power occupation, and significantly improve task execution efficiency.

Description

Technical Field

[0001] This application belongs to the field of graphics processor technology, and particularly relates to a graphics processor, a task execution method, an electronic device, and a storage medium. Background Technology

[0002] In current Graphics Processing Unit (GPU) technology, task execution typically follows a basic pattern of control flow first, followed by data flow processing. Control flow information is first written to registers, and the execution unit then processes the data flow according to the configuration information in the registers. This staged execution can effectively improve task throughput.

[0003] However, current graphics processing unit (GPU) technologies tend to integrate multiple execution unit groups to achieve higher parallel processing capabilities. These execution unit groups typically share the same instruction cache and maintain independent read pointers to support parallel task execution. During task execution, if an execution unit group is blocked due to a long task execution time, it slows down the overall task execution and causes other execution unit groups that have completed their tasks to become idle and wait for new instructions, severely impacting task execution efficiency. Furthermore, when a task only sends control flow information to some execution unit groups without actual data flow, context state synchronization is still required for such empty tasks, resulting in additional unnecessary resource overhead and computational cost.

[0004] Therefore, how to achieve more efficient task execution through graphics processing units is an important problem that urgently needs to be solved. Summary of the Invention

[0005] This application provides a graphics processor, a task execution method, an electronic device, and a storage medium, which can effectively reduce the waste of resources and computing power during the execution of graphics processing tasks, and significantly improve task execution efficiency.

[0006] A first aspect of this application provides a graphics processor, including: at least two execution unit groups and an instruction cache unit shared by at least two execution unit groups, each execution unit group including: an accumulation register, at least one run register and at least one execution unit; An instruction cache unit is used to store a sequence of task instructions corresponding to at least one task to be executed. Each task to be executed corresponds to at least one group of execution units. The sequence of task instructions includes at least the control flow corresponding to the task to be executed. The instruction pipeline is used to transfer the control flow corresponding to the task to be executed stored in the instruction cache unit to the accumulation register; Accumulator registers are used to receive and store the control flow transmitted through the instruction pipeline. The run register is used to copy and configure the control flow from the cumulative register when the run register is unoccupied and the task to be executed corresponding to the control flow stored in the cumulative register is the task to be executed corresponding to the execution unit group in which it is located. An execution unit is used to execute the task to be executed corresponding to its execution unit group after the control flow has been configured in the run register.

[0007] In some embodiments, the instruction cache unit is also configured to release the space occupied by the stored task instruction sequence and update the task instruction sequence, and cache the new task instruction sequence corresponding to the new task to be executed, provided that all cumulative registers have successfully received and stored the control flow.

[0008] In some embodiments, the instruction pipeline is also used to transfer the new control flow corresponding to the new task to be executed stored in the instruction cache unit to the accumulation register when the task to be executed has finished executing; The accumulator register is also used to receive new control flow transmitted from the instruction pipeline, store new control flow, or merge and update the control flow stored in the accumulator register based on the new control flow to obtain an updated control flow.

[0009] In some embodiments, the accumulation register includes multiple register units for storing control flow, and each register unit corresponds to each run register with an instruction validity flag, which indicates whether the register unit stores control flow. The accumulator register is used to update the instruction validity flags corresponding to the register cells and the run register when the control flow is stored in the register cells.

[0010] In some embodiments, the run register is used to detect the instruction validity flag corresponding to the register unit and the run register when the run register is in an unoccupied state and the task to be executed corresponding to the control flow stored in the accumulation register is the task to be executed corresponding to the execution unit group. If the instruction validity flag indicates that the register unit stores control flow, the control flow stored in the register unit is copied to the run register, and the instruction validity flag corresponding to the register unit and the run register is updated.

[0011] In some embodiments, the task instruction sequence may further include a data stream corresponding to the task to be executed; The instruction pipeline is also used to transfer the data stream corresponding to the task to be executed stored in the instruction cache unit to the execution unit after the control flow has been configured in the run register; An execution unit is used to execute tasks based on data streams.

[0012] In some embodiments, for each execution unit group, when the execution unit group includes a single run register and an execution unit, the instruction pipeline is also used to transfer the control flow corresponding to the preceding task to be executed by the execution unit group to the run register, and after successfully transferring the data flow corresponding to the preceding task to the execution unit, transfer the control flow corresponding to the subsequent task to be executed by the execution unit group to the accumulation register. The run register is used to copy the control flow corresponding to the subsequent task from the accumulation register after the previous task has finished executing. At the same time, the instruction pipeline is also used to transfer the data stream corresponding to the subsequent task to the execution unit so that the execution unit can execute the subsequent task after the previous task has finished executing.

[0013] A second aspect of this application provides a task execution method. The method is applied to a graphics processor, which includes: at least two execution unit groups, an instruction cache unit shared by the at least two execution unit groups, and an instruction pipeline. Each execution unit group includes: an accumulation register, at least one run register, and at least one execution unit. The method includes: Through the instruction pipeline, the control flow of the task instruction sequence corresponding to at least one task to be executed stored in the instruction cache unit is transferred to the accumulation register for storage, and each task to be executed corresponds to at least one execution unit group. When the run register is unoccupied and the task to be executed corresponding to the control flow stored in the accumulator register is the task to be executed corresponding to the execution unit group, the control flow is read and configured from the accumulator register through the run register. If the control flow is successfully configured in the run register, the task to be executed is executed through the execution unit corresponding to the execution unit group.

[0014] A third aspect of this application provides an electronic device, the electronic device comprising: at least one graphics processor; and a memory communicatively connected to the at least one graphics processor; wherein the memory stores a computer program executable by the at least one graphics processor, the computer program being executed by the at least one graphics processor to enable the at least one graphics processor to perform the task execution method of the second aspect.

[0015] A fourth aspect of this application provides a computer-readable storage medium storing computer instructions that are used to cause a graphics processor to execute the task execution method of the second aspect.

[0016] The graphics processor provided in this application includes: at least two execution unit groups, an instruction cache unit shared by the at least two execution unit groups, and an instruction pipeline. Each execution unit group includes: a accumulator register, at least one execution register, and at least one execution unit. The instruction cache unit stores a sequence of task instructions corresponding to at least one task to be executed. Each task to be executed corresponds to at least one execution unit group, and the task instruction sequence includes at least the control flow corresponding to the task to be executed. The control flow corresponding to the task to be executed, stored in the instruction cache unit, is transferred to the accumulator register via the instruction pipeline. The accumulator register can receive and store the control flow transferred by the instruction pipeline. Then, when the execution register is unoccupied and the task to be executed corresponding to the control flow stored in the accumulator register is the task to be executed corresponding to the execution unit group, the control flow can be copied and configured from the accumulator register via the execution register. Further, when the control flow is successfully configured in the execution register, the task to be executed corresponding to the execution unit group is executed by the execution unit.

[0017] In the graphics processor provided in this application embodiment, an independent accumulator register can be configured for each execution unit group, and the run register can accurately and efficiently read the control flow corresponding to the task instruction from the accumulator register according to the task affiliation. This application constructs an independent instruction buffer space between the instruction cache unit and the run register through the accumulator register, so that when the run register is occupied, the control flow in the subsequent task instruction sequence in the instruction cache unit can be read into the accumulator register for temporary storage through the instruction pipeline, thereby effectively hiding the delay in the control flow, reducing the idle waiting time of other execution units and the delay in the release of the instruction cache unit caused by the slow execution of a single execution unit group, and reducing the useless resource overhead and computing power occupation caused by context control flow synchronization of idle tasks, significantly improving the task execution efficiency when multiple execution unit groups execute tasks in parallel. Attached Figure Description

[0018] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of the structure of a graphics processor provided in some embodiments of this application; Figure 2 One of the flowcharts illustrating multitasking using a single run register and a single execution unit, provided in some embodiments of this application; Figure 3 This is a second schematic diagram illustrating the multitasking process using a single run register and a single execution unit, as provided in some embodiments of this application. Figure 4 A flowchart illustrating the task execution process provided for some embodiments of this application; Figure 5 This is one of the flowcharts illustrating a multi-stage task execution process provided in some embodiments of this application; Figure 6 The second flowchart illustrates the multi-stage task execution process provided in some embodiments of this application; Figure 7 A flowchart illustrating a task execution method provided for some embodiments of this application; Figure 8 This is a schematic diagram of the structure of an electronic device provided in some embodiments of this application. Detailed Implementation

[0020] The features and exemplary embodiments of various aspects of this application will be described in detail below. To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain this application and not to limit it. For those skilled in the art, this application can be implemented without some of these specific details. The following description of the embodiments is merely to provide a better understanding of this application by illustrating examples.

[0021] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes said element.

[0022] It should be noted that the acquisition, storage, use, and processing of data in the technical solution of this application all comply with the relevant provisions of national laws and regulations. In the embodiments of this application, certain existing industry solutions such as software, components, and models may be mentioned. These should be considered exemplary, intended only to illustrate the feasibility of implementing the technical solution of this application, and do not imply that the applicant has already used or necessarily used such solutions.

[0023] In current Graphics Processing Unit (GPU) technology, task execution typically follows a basic pattern of control flow first, followed by data flow processing. Control flow information is first written to registers, and the execution unit then processes the data flow according to the configuration information in the registers. This staged execution can effectively improve task throughput.

[0024] However, current graphics processing units (GPUs) tend to integrate multiple execution unit groups to achieve higher parallel processing capabilities. These execution unit groups typically share the same instruction cache and each maintains its own independent read pointer to support parallel task execution. During task execution, if an execution unit group's read pointer cannot move forward due to the current task taking too long, even if other execution unit groups have completed their tasks and are idle, the task execution will still be forced to wait due to the slow execution of that particular execution unit group, severely impacting task execution efficiency.

[0025] In addition, in multi-context switching scenarios, some tasks may only send control flow information to unrelated execution unit groups without including the actual data flow corresponding to the task. This causes these execution unit groups to receive control flow but not actually execute the corresponding task, resulting in the problem of empty tasks. For empty tasks, context state synchronization between registers is also required, which further causes useless resource overhead and computing power occupation.

[0026] Based on the aforementioned technical problems, embodiments of this application provide a graphics processor, a task execution method, an electronic device, and a storage medium. The graphics processor includes: at least two execution unit groups, an instruction cache unit shared by the at least two execution unit groups, and an instruction pipeline (CMD pipe). Each execution unit group includes: an accumulator register, at least one running register, and at least one processing unit. The instruction cache unit stores a sequence of task instructions corresponding to at least one task to be executed. Each task to be executed corresponds to at least one execution unit group, and the task instruction sequence includes at least the control flow corresponding to the task to be executed. The control flow corresponding to the task to be executed, stored in the instruction cache unit, is transmitted to the accumulator register via the instruction pipeline. The accumulator register can receive and store the control flow transmitted by the instruction pipeline. Then, when the running register is unoccupied and the task to be executed corresponding to the control flow stored in the accumulator register is the task to be executed corresponding to the execution unit group, the control flow can be copied and configured from the accumulator register via the running register. Further, when the control flow is successfully configured in the running register, the task to be executed corresponding to the execution unit group is executed by the processing unit.

[0027] In the graphics processor provided in this application embodiment, an independent accumulator register can be configured for each execution unit group, and the run register can accurately and efficiently read the control flow corresponding to the task instruction from the accumulator register according to the task affiliation. This application constructs an independent instruction buffer space between the instruction cache unit and the run register through the accumulator register, so that when the run register is occupied, the subsequent task instruction sequence in the instruction cache unit can be read into the accumulator register for temporary storage through the instruction pipeline, thereby effectively hiding the delay in the control flow, reducing the idle waiting time of other execution units and the delay in the release of the instruction cache unit caused by the slow execution of a single execution unit group, and reducing the useless resource overhead and computing power occupation caused by the context control flow synchronization of idle tasks, significantly improving the task execution efficiency when multiple execution unit groups execute tasks in parallel.

[0028] It should be noted that the specific application scenarios of the graphics processor, task execution method, electronic device and storage medium provided in the embodiments of this application are not limited. The technical solutions provided in the embodiments of this application can be flexibly applied to various actual scenarios that require parallel task execution according to actual needs.

[0029] For example, in a 3D game rendering scene, each frame of the game contains a large number of rendering tasks, which can be distributed to multiple execution unit groups for parallel processing. Due to the differences in complexity between different scenes, the tasks handled by each execution unit group vary greatly. Some execution unit groups take a long time to process complex material shading, while others can complete simple geometry very quickly.

[0030] By applying the graphics processor described in this application, each execution unit group temporarily stores the control flow of the task to be executed through an independent accumulator register, so that the control flow reading of each execution unit group is no longer constrained by the shared instruction cache. When an execution unit group is slow to execute due to a complex rendering task, other groups can still obtain the temporarily stored task instructions from the corresponding accumulator register to continue the execution of subsequent tasks, no longer being idle due to waiting for the instruction cache unit to be released and updated. At the same time, for empty tasks that only update the state, the control flow information only needs to be written to the accumulator register, without triggering the run register to perform a complete context copy and synchronization, avoiding invalid resource occupation and wasted computing power, and significantly improving frame rendering efficiency.

[0031] It should be noted that the application scenarios described in the above embodiments of this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. Those skilled in the art will understand that with the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0032] Figure 1 This is a schematic diagram of the structure of a graphics processor provided in some embodiments of this application.

[0033] like Figure 1 As shown, the graphics processor 100 includes at least two execution unit groups: execution unit group A110, execution unit group B120, etc., as well as an instruction cache unit 130 and an instruction pipeline 140 shared by all or some of the execution unit groups.

[0034] Execution unit group A110 includes an accumulation register A111, at least one run register A112, and at least one execution unit A113. Similarly, execution unit group B120 includes an accumulation register B121, at least one run register B122, and at least one execution unit B123.

[0035] In the embodiments provided in this application, the instruction cache unit 130 is used to store a sequence of task instructions corresponding to at least one task to be executed by the graphics processor 100, specifically a command buffer (CMD buffer). In some embodiments, the task instruction sequence may include at least the control flow corresponding to the task to be executed, which is used to configure data in the run register to guide the execution unit to execute the task. In other embodiments, the task instruction sequence may also include a data flow corresponding to the task to be executed, which is sent to the execution unit through the instruction pipeline 140 for task execution.

[0036] Each task to be executed is handled by at least one execution unit group. For example, if there are two tasks to be executed, task 1 can be executed by execution unit group A110, and task 2 can be executed jointly by execution unit group A110 and execution unit group B120.

[0037] In traditional task execution, control flow is transmitted between the instruction cache unit 130 and the run registers in the execution unit group via the instruction pipeline 140. However, when the execution unit group performs a complex or abnormal task that causes slow execution, the pointer indicating the task execution progress in the instruction cache unit 130 cannot move, and the space occupied by the corresponding task instruction sequence cannot be released. If other execution unit groups have already completed their corresponding tasks, the instruction sequence in the instruction cache unit 130 cannot be updated because the pointer of the slow-running execution unit group has not moved, forcing other execution unit groups that have completed their tasks to wait, severely wasting computing resources and reducing task execution efficiency. Furthermore, for execution unit groups that do not execute the task instruction sequence in the instruction cache unit 130, the control flow of the empty task needs to be configured to update the context state of the run register, while the execution unit is completely idle, further wasting computing power and slowing down task execution efficiency.

[0038] Based on this, in the embodiments provided in this application, an accumulation register for temporarily storing the control flow in the task instruction sequence is provided between the execution unit group's run register and the instruction cache unit 130, i.e. Figure 1 The cumulative register A111 of execution unit group A110 and the cumulative register B121 of execution unit group B120.

[0039] For each execution unit group, the instruction pipeline 140 can transfer the control flow corresponding to the task to be executed stored in the instruction cache unit 130 to the accumulation register in that execution unit group. The accumulation register can receive and store the control flow corresponding to at least one task to be executed transmitted by the instruction pipeline 140. In some embodiments, if storage space permits, accumulation registers A111 and B121 can copy and store the control flow of all task instruction sequences currently stored in the instruction cache unit 130 through the instruction pipeline 140.

[0040] Furthermore, after the cumulative registers A111 and B121 are successfully read, the pointers in the instruction cache unit 130 that indicate the task execution progress of execution unit group A110 and execution unit group B120 can be moved to the end of the read task instruction sequence, so that the instruction cache unit 130 can update the instruction sequence and corresponding control flow immediately without waiting for the task execution of any execution unit group.

[0041] Specifically, in the embodiments provided in this application, the instruction cache unit 130 can also be used to move the task execution pointer of all execution unit groups in the instruction cache unit 130 to the end position of the read task instruction sequence after the cumulative registers of all execution unit groups in the graphics processor 100 have been successfully read and stored through the instruction pipeline 140. This releases the space occupied by the stored task instruction sequence in the instruction cache unit 130.

[0042] Then, the instruction cache unit 130 does not need to wait for the execution units of each execution unit group to actually finish executing the task. It can immediately update the task instruction sequence based on the released occupied space, cache the new task instruction sequence corresponding to the new task to be executed, and include the control flow corresponding to the new task to be executed.

[0043] In the above embodiments, by releasing the space occupied in the instruction cache unit 130 after the control flow has been successfully read by all the accumulation registers, the update rate of the instruction cache unit is significantly improved, avoiding the long-term occupation of cache space due to the slow execution of a single execution unit group task, reducing the invalid occupation of the instruction cache unit 130, and enabling the instruction sequence of a new task to be executed to be loaded into the instruction cache unit 130 in a timely manner. This reduces the occurrence of instruction stagnation in other execution unit groups due to insufficient cache space or update blocking, thereby improving the utilization rate of the instruction cache unit 130 and the overall task execution efficiency.

[0044] Furthermore, in the embodiments provided in this application, the run register of each execution unit group can directly read the control flow of the task to be executed from the accumulation register in its execution unit group, instead of obtaining the control flow of the task to be executed from the instruction cache unit 130 through the instruction pipeline 140 as in the traditional task execution process.

[0045] Specifically, the run register provided in this application embodiment can be used to read and configure the control flow of the task to be executed from the accumulation register when it is in an unoccupied state, that is, when no control flow data is configured or after the previous task has been executed, and the accumulation register stores the control flow of the task to be executed that needs to be executed by the execution unit group.

[0046] In some embodiments, both the accumulator register A111 and the accumulator register B121 may store the control flow corresponding to the execution unit group A110 and the execution unit group B120 respectively, which are read by the instruction pipeline 140 from the instruction cache unit 130.

[0047] Run register A112 can read and configure the control flow corresponding to the task to be executed by execution unit group A110 from the accumulation register A111. Run register B122 can read and configure the control flow corresponding to the task to be executed by execution unit group B120 from the accumulation register B121. For control flows that do not belong to the execution unit group, the run registers do not need to be read or have their context states updated, thus avoiding the generation of empty tasks where only the run registers are configured for control flow but the execution unit does not perform data flow processing.

[0048] Regarding the specific processing of the run register reading control flow from the accumulator register, in the embodiments provided in this application, the accumulator register in each execution unit group may contain multiple register units, and each register unit may be used to store the control flow read by the instruction pipeline 140 from the instruction cache unit 130. The number of register units in the accumulator register can be flexibly selected according to actual needs and application scenarios, for example, equal to or greater than the maximum number of task instruction sequences that can be stored in the instruction cache unit 130.

[0049] Furthermore, each register unit corresponds to an instruction validity flag in each run register within its execution unit group. For each run register, the instruction validity flag indicates whether the corresponding register unit stores the control flow corresponding to the task to be executed. Specifically, it can be represented by a one-bit valid bit array (Dirty Mask). For example, an instruction validity flag of "1" indicates that the register unit stores the control flow to be executed, while "0" indicates that the register unit does not store the control flow corresponding to the task to be executed.

[0050] In the embodiments provided in this application, when the accumulator registers (such as accumulator registers A111 and B121 mentioned above) receive the control flow read from the instruction cache unit 130 by the instruction pipeline 140, the received control flow can be stored in the register unit. Simultaneously, the instruction validity flag corresponding to the register unit whose stored content has changed is updated; that is, the instruction validity flag indicating that no control flow to be executed is stored is changed to an instruction validity flag indicating that control flow to be executed is stored. In subsequent processes, the run register corresponding to the accumulator register can read the control flow from the register unit containing the control flow based on each register unit and its corresponding instruction validity flag.

[0051] In the above embodiments, by setting an independent instruction validity identifier between each register unit in the accumulator register and the run register, the control flow can be accurately read. When reading control flow information, the run register can obtain the truly valid control flow based on the instruction validity identifier, avoiding misreading or repeated copying of invalid or expired control flow, and further improving the accuracy of control flow information distribution and task execution efficiency.

[0052] Furthermore, in the embodiments provided in this application, for each execution unit group, when each run register reads the control flow corresponding to its execution unit group from the accumulator register, it can determine which register unit in the accumulator register to read the control flow of the task to be executed from based on the instruction validity identifier corresponding to each register unit in the accumulator register and this run register.

[0053] Specifically, each execution register in each execution unit group (e.g., execution register A112 and execution register B122 mentioned above) can, when in an unoccupied state and the task to be executed corresponding to the control flow stored in the accumulation register is the task to be executed corresponding to the execution unit group, check whether the instruction validity flag corresponding to each register unit and the execution register indicates that the register unit stores control flow to be executed. For register units storing control flow that the execution unit group does not need to execute, the instruction validity flag corresponding to the execution register can skip the check, or directly display an instruction validity flag indicating that no control flow to be executed is stored.

[0054] When the execution register determines that the instruction validity flag of a register cell indicates that a control flow containing a task to be executed is stored, it can copy and configure the control flow stored in the register cell. Simultaneously, the execution register can update the instruction validity flag of the register cell to indicate that no control flow to be executed is stored, thus preventing the execution register from repeatedly copying the same control flow.

[0055] In some embodiments, when a single execution unit group includes two or more execution registers and execution units, and two or more execution registers are simultaneously unoccupied, for the register unit storing the control flow to be executed, a preset allocation algorithm can be used to determine the execution register that actually reads the control flow of the task to be executed, and after reading, the instruction validity identifiers corresponding to the register unit and the two or more free execution registers are updated simultaneously. In some embodiments, the preset allocation algorithm may be the Ping-Pong Buffer (PP), Round-Robin Scheduling (RR), Random Allocation (RA), etc., which can be flexibly selected according to actual needs and application scenarios.

[0056] In the above embodiments, the run register can copy the control flow that actually needs to be executed from the accumulator register to the run register based on the instruction validity flag, and update the instruction validity flag in a timely manner. This ensures that the control flow information in the accumulator register is immediately marked as invalid after being consumed, avoiding repeated reading and misuse of the same control flow, and reducing redundant data handling and invalid configuration operations. Simultaneously, this embodiment achieves precise matching between the control flow information stored in the accumulator register and the actual task to be executed, improving the accuracy of control flow configuration and the resource utilization efficiency of the run register.

[0057] Furthermore, regarding the context state update of the control flow in the register, in the embodiments provided in this application, the control flow unrelated to the task to be executed by the execution unit group can be stored in the accumulation register, and when the task execution is completed and the task instruction sequence in the instruction cache unit 130 is updated, the context update and adjustment of the control flow can be performed directly in the accumulation register, so that the run register can be directly configured with the updated control flow when the task is executed subsequently.

[0058] Specifically, in the embodiments provided in this application, after the execution unit completes the task to be executed and the instruction cache unit 130 is updated with a new task instruction sequence, the cumulative register of each execution unit group can obtain the control flow in the new task instruction sequence from the updated instruction cache unit 130. For the cumulative register of each execution unit group, in some embodiments, if the cumulative register does not store the control flow corresponding to the old task, or if the control flow in the new task instruction sequence does not overlap with the old task, the cumulative register can directly store or overwrite the useless old control flow.

[0059] In other embodiments, if the accumulator register stores the control flow corresponding to the old task that will be used by subsequent tasks, and the control flow in the new task instruction sequence overlaps with the old control flow in at least part, the accumulator register can merge and update the stored old control flow based on the acquired new control flow, that is, update the context state of the control flow in the accumulator register to obtain the updated control flow.

[0060] Subsequently, the run register of each execution unit group can read the updated control flow or new control flow of the new task to be executed from the updated accumulator register, as described in the above embodiment, and configure it. The execution unit can then execute the new task to be executed based on the corresponding data flow. This embodiment allows the update of the register context state to be migrated from the traditional empty task update of the run register to the update of the accumulator register, effectively avoiding the empty task problem caused by the context state update without data flow.

[0061] In the above embodiments, the accumulator register can be directly stored or merged and updated according to the flexible selection of the new control flow. This ensures that the control flow information generated by an idle task is not sent to the run register, but rather the context state is updated in the accumulator register. This embodiment effectively avoids repeated synchronization of the context state between run registers triggered by idle tasks, reduces invalid register moving operations and context update overhead, reduces the invalid occupation of computing resources, and improves the flexibility of control flow information transmission in multi-task scenarios, further improving the task processing efficiency of multi-execution unit groups.

[0062] In the embodiments provided in this application, after the execution unit in each execution unit group has successfully configured the control flow read from the accumulation register in the corresponding run register, it can receive the data flow corresponding to the task to be executed read from the instruction cache unit 130 by the instruction pipeline 140, and execute the corresponding task to be executed based on the data flow.

[0063] In some embodiments, execution unit A113 can receive and execute the data stream transmitted by instruction pipeline 140 after the control flow corresponding to execution unit group A110 is successfully configured in run register A112. Similarly, execution unit B123 can receive and execute the data stream transmitted by instruction pipeline 140 after the control flow corresponding to execution unit group B120 is successfully configured in run register B122. In other embodiments, the data stream can also be stored in the video memory or other storage space of the graphics processor 100 and read and transmitted by instruction pipeline 140. The specific choice can be flexibly made according to actual needs and application scenarios.

[0064] In addition to the above embodiments, this application also considers that when a single execution unit group contains only a single run register and an execution unit, in the case of executing multiple tasks consecutively, after configuring the control flow of a single task, the single run register must wait for the execution unit to finish processing the corresponding data flow before it can configure the control flow of subsequent tasks.

[0065] The execution unit also needs to wait for the run register to complete the control flow configuration for subsequent tasks before it can receive the corresponding data stream for processing. This results in idle time for the execution unit while waiting for the run register configuration, and idle time occurs with each new task execution, causing significant resource waste. For details on the above technical issues, please refer to [link / reference needed]. Figure 2 As shown.

[0066] Figure 2 This is one of the flowcharts illustrating multitasking using a single run register and a single execution unit, as provided in some embodiments of this application.

[0067] like Figure 2As shown, in a conventional multitasking process, control flow can be transmitted from the conventional instruction pipeline 210 to the conventional execution register 220. After the conventional execution register 220 is configured with control flow, the data flow corresponding to the control flow can be transmitted from the conventional instruction pipeline 210 to the conventional execution unit 230, so that the conventional execution unit 230 can execute the corresponding task.

[0068] Furthermore, after the first task is completed, the control flow corresponding to the second task needs to be transferred to the traditional execution register 220 via the traditional instruction pipeline 210. For example... Figure 2 As shown, when the conventional execution register 220 is configuring the control flow corresponding to the second task, the conventional execution unit 230 cannot receive the data flow corresponding to the second task. It can only receive and execute the data flow after the conventional execution register 220 has been configured. Both the conventional instruction pipeline 210 and the conventional execution unit 230 must wait for the conventional execution register 220 to complete its configuration before proceeding with subsequent operations, resulting in idle time. Furthermore, as... Figure 2 There was also idle time during the execution of the third task, which caused the overall task execution time to be extended multiple times, seriously reducing the task execution efficiency.

[0069] To address the technical problems existing in multi-task execution using a single run register and a single execution unit, the embodiments provided in this application allow for advance configuration of the control flow of subsequent tasks through an accumulation register while the execution unit is executing a preceding task.

[0070] Furthermore, after the instruction pipeline 140 transmits the data stream of the preceding task to the execution unit and completes its execution, the run register can directly copy the register state corresponding to the subsequent task from the pre-configured accumulation register, directly skipping the time for self-configuration of instructions. This allows the instruction pipeline 140 to immediately send the data stream corresponding to the subsequent task to the execution unit, thereby eliminating the idle time mentioned in the above technical problems.

[0071] In some embodiments, taking the above-mentioned execution unit group A110 as an example, the multi-task execution process of a single running register and a single execution unit based on the cumulative register optimization in this application can be referred to Figure 3 As shown.

[0072] Figure 3 This is the second schematic diagram illustrating the multitasking process using a single run register and a single execution unit, as provided in some embodiments of this application.

[0073] like Figure 3As shown in the embodiments provided in this application, when performing continuous multi-task execution, the instruction pipeline 140 can transmit the control flow corresponding to the first task to the run register A112 in the execution unit group A110, so that the run register A112 can perform control flow configuration based on the control flow.

[0074] After configuration, instruction pipeline 140 can transmit the data stream corresponding to the first task to execution unit A113 in execution unit group A110. When the data stream transmission is complete, instruction pipeline 140 can skip waiting for the first task to complete and directly transmit the control flow corresponding to the second task to the accumulation register A111, and configure the register state of the second task in advance through the accumulation register A111.

[0075] When execution unit A113 completes the first task, the run register A112 no longer needs to retrieve the control flow and execution time for the second task from the instruction pipeline 140 for configuration. Instead, it can directly copy the pre-configured register state from the accumulation register A111, skipping the instruction configuration process. Simultaneously, the instruction pipeline 140 can immediately transfer the data stream corresponding to the second task to execution unit A113, and execute the second task through execution unit A113. Similarly, after the second task is completed, the third task can be executed quickly, and so on up to the fourth task.

[0076] like Figure 3 As shown, compared to Figure 2 In the traditional multitasking execution process shown, the embodiments provided in this application can realize the advance configuration of control flow information corresponding to subsequent tasks through the accumulation register, thereby effectively eliminating the idle waiting time of the execution unit caused by waiting for the execution of the preceding task.

[0077] In the above embodiments, during the execution of the preceding task, the control flow information of the subsequent task can be transmitted to the accumulator register in advance for configuration. After the execution of the preceding task is completed, the run register can immediately copy the register state of the subsequent task from the accumulator register, enabling the execution unit to seamlessly connect and process the data flow of the subsequent task. This effectively eliminates the idle time caused by the execution unit waiting for the control flow to be sent, realizing efficient continuous task execution in a single run register scenario, and improving task execution efficiency and resource utilization.

[0078] To further understand the overall process of task execution using the graphics processor provided in this application's embodiments, a comprehensive description of the task execution process is provided below, based on the above embodiments. For details, please refer to... Figure 4 As shown.

[0079] Figure 4 This is a flowchart illustrating the task execution process provided in some embodiments of this application.

[0080] like Figure 4 As shown, for each group of execution units on the graphics processor 100, the task execution process includes steps S401 to S411.

[0081] S401: The instruction cache unit distributes control flow through the instruction pipeline.

[0082] S402: Check if the cumulative register is writable.

[0083] S403: Write control flow to the accumulation register.

[0084] S404: When the execution unit group contains only a single run register and a single execution unit, the instruction validity flag for updating the accumulator register.

[0085] S405: When the execution unit group contains multiple run registers and multiple execution units, update the cumulative register and the instruction validity flag corresponding to each run register.

[0086] S406: Select the run register for configuring control flow.

[0087] S407: The run register checks the instruction validity flag in the accumulator register to determine whether the control flow of the task to be executed is stored.

[0088] S408: The run register performs control flow reading and configuration of the accumulator register, as well as resets the instruction validity flag.

[0089] S409: Data stream is sent down via the command pipeline.

[0090] S410: Perform the task.

[0091] S411: Continue executing the preceding task or wait.

[0092] As shown in steps S401 to S411, this application can achieve efficient task execution based on the cumulative register, significantly improve the processing efficiency of the graphics processor in multi-task execution scenarios, reduce idle waiting and empty task problems, and effectively improve resource utilization efficiency.

[0093] To further demonstrate the significant advantages of the graphics processor provided in this application embodiment compared to traditional task execution processes, the following will illustrate... Figure 5 and Figure 6 This paper compares and introduces the multi-stage task execution process.

[0094] Figure 5 This is one of the flowcharts illustrating a multi-stage task execution process provided in some embodiments of this application.

[0095] Figure 5This represents a multi-stage process change in the traditional task execution procedure. The traditional graphics processor contains two traditional unit groups: traditional unit group A510 and traditional unit group B520, as well as a traditional cache unit 530. Traditional unit group A510 includes registers A511 and C513, and corresponding execution units a512 and c514. Traditional unit group B520 includes registers B521 and D523, and corresponding execution units b522 and d524. In this example, both traditional unit groups A510 and B520 can execute task C. Traditional unit group B520 can execute tasks A and B independently. Task C corresponds to the task instruction sequence of tasks C1-C3, task A corresponds to the task instruction sequence of tasks A1 and A2, and task B corresponds to the task instruction sequence of tasks B1 and B2.

[0096] like Figure 5 During the execution of a traditional task, in Phase 1, both registers in traditional unit group A510 are executing preceding tasks, so the A group pointer in traditional cache unit 530 cannot move. In traditional unit group B520, register B521 is executing a preceding task, while register D523 is idle. Therefore, register D523 can obtain the control flow of task A from traditional cache unit 530 and the register context state from register B521.

[0097] In phase two, the two registers in traditional unit group A510 are still executing their preceding tasks, and the A group pointer cannot move. Meanwhile, in traditional unit group B520, register B521 has completed its preceding task and is idle. However, because the A group pointer cannot move, traditional cache unit 530 cannot update the subsequent task instruction sequence. This results in register B521 only being able to obtain the control flow of task B1, unable to fully execute task B, and simultaneously obtaining the register context state from register D523.

[0098] In phase three, the two registers in traditional unit group A510 complete their preceding tasks and are in an idle state. Although traditional unit group A510 is not responsible for executing task A, register C513 still needs to read the control flow of task A from traditional cache unit 530 in order to move the A group pointer and update the context state. Register A511 can copy and update the register context state from register C513. Since traditional unit group A510 does not execute task A, execution units a512 and c514 will not receive data input, resulting in an empty task.

[0099] In the traditional unit group B520, register B521 did not obtain the complete control flow of task B, and the corresponding execution unit b522 was also unable to execute the task. There were no instruction updates in the traditional cache unit 530, register D523 could not obtain the new task instruction sequence, and execution unit d524 was also unable to execute the task, all of which were in a forced idle state.

[0100] In phase four, after the two registers in traditional unit group A510 have updated the register context state of task A, traditional cache unit 530 updates the task instruction sequence. Similarly, although traditional unit group A510 is not responsible for executing task B, in order to move the group A pointer and update the context state, register A511 still needs to read the control flow of task B from traditional cache unit 530, and register C513 can copy and update the register context state from register A511. At this point, register B521 in traditional unit group B520 can obtain the complete control flow of task B, and execution unit b522 can obtain the corresponding data flow to execute task B.

[0101] In phase five, after the two registers in traditional unit group A510 have mutually updated the register context state of task B, traditional cache unit 530 updates the task instruction sequence. Task C needs to be executed by both traditional unit group A510 and traditional unit group B520, so register C513 can obtain the control flow of task C, and execution unit c514 obtains the corresponding data flow to execute task C. At the same time, it can copy and update the register context state from register A511. Register D523 in traditional unit group B520 can obtain the control flow of task C, and execution unit d524 obtains the corresponding data flow to execute task C. At the same time, it can copy and update the register context state from register B521.

[0102] based on Figure 5 The multi-stage task execution process reveals that in traditional task execution, when multiple execution units execute tasks in parallel, slow execution of individual execution units leads to slow updates in the instruction cache, resulting in idle time for other execution units. This severely impacts execution efficiency and wastes computing resources. Furthermore, register configurations without actual data flow cause frequent occurrences of empty tasks, further wasting computing power.

[0103] Figure 6 This is the second flowchart illustrating a multi-stage task execution process provided in some embodiments of this application.

[0104] Figure 6 This application describes a multi-stage process variation for task execution using the graphics processor provided. For example... Figure 6As shown, in the embodiments provided in this application, execution unit group A110 may further include a run register C114 and an execution unit C115, and execution unit group B120 may further include a run register D124 and an execution unit D125. The correspondence between task AC and execution unit groups can be... Figure 5 The example is consistent.

[0105] In phase one, the run registers A112 and C114 in execution unit group A110 are occupied due to the execution of preceding tasks. However, the accumulator register A111 can read and store the control flow of task A in instruction cache unit 130. Although run registers C114 and D124 are not actually configured or updated, the A group pointer in instruction cache unit 130 can move so that instruction cache unit 130 can update instructions in a timely manner.

[0106] Similarly, the accumulator register B121 in the execution unit group B120 can read and store the control flow of task A in the instruction cache unit 130 through the instruction pipeline 140. The run register D124, which is in an idle state, can directly read and configure the control flow from the accumulator register B121. The execution unit D125 can execute task A according to the data flow.

[0107] In phase two, the run registers A112 and C114 in execution unit group A110 are still occupied due to the execution of preceding tasks. Since execution unit group A110 is not responsible for executing tasks A and B, the accumulator register A111 can read and store the updated control flow of task B in instruction cache unit 130 through instruction pipeline 140, and update the register context state within accumulator register A111. At the same time, the A group pointer in instruction cache unit 130 can move, allowing instruction cache unit 130 to update instructions for subsequent tasks.

[0108] Similarly, the accumulator register B121 in the execution unit group B120 can read and store the control flow of task B in the instruction cache unit 130 through the instruction pipeline 140. The run register B122, which is in an idle state, can directly read and configure the control flow from the accumulator register B121. The execution unit B123 can execute task B according to the data flow.

[0109] In phase three, the run registers A112 and C114 in execution unit group A110 complete their preceding tasks and are in an idle state. The instruction cache unit 130 is updated with the instruction sequence for task C. Accumulator registers A111 and B121 can read and store the control flow of task C in the instruction cache unit 130 through the instruction pipeline 140. Run registers C114 and D124 can read and configure the control flow from their respective accumulator registers. Execution units C115 and D125 can execute task C according to the corresponding data flow.

[0110] like Figure 6 The multi-stage task execution process shown is compared to Figure 5 Compared to the traditional execution process shown, this application achieves more efficient task execution through the accumulation register. This effectively reduces idle execution unit groups and empty tasks caused by the instruction cache unit's inability to be updated, improving both task execution efficiency and computing resource utilization efficiency.

[0111] The above describes the specific implementation of the graphics processor provided in this application. In the graphics processor provided in this application, each execution unit group can be configured with an independent accumulator register, and the run register can accurately and efficiently read the control flow corresponding to the task instruction from the accumulator register according to the task affiliation. This application constructs an independent instruction buffer space between the instruction cache unit and the run register through the accumulator register. This allows the subsequent task instruction sequence in the instruction cache unit to be temporarily stored in the accumulator register through the instruction pipeline when the run register is occupied, thereby effectively hiding the delay in the control flow, reducing the idle waiting time of other execution units and the delay in releasing the instruction cache unit caused by the slow execution of a single execution unit group, and reducing the useless resource overhead and computing power occupation caused by context control flow synchronization of idle tasks. This significantly improves the task execution efficiency when multiple execution unit groups execute tasks in parallel.

[0112] Based on the same technical concept as the aforementioned graphics processor, this application also provides a task execution method, which can be applied to the aforementioned graphics processor. For details, please refer to... Figure 7 The flowchart shown is shown.

[0113] Figure 7 This is a flowchart illustrating a task execution method provided in some embodiments of this application. For example... Figure 7 As shown, the task execution method provided in this application embodiment includes steps S701 to S703.

[0114] S701: Through the instruction pipeline, the control flow of at least one task instruction sequence corresponding to the task to be executed stored in the instruction cache unit is transferred to the accumulation register for storage.

[0115] S702: When the run register is unoccupied and the task to be executed corresponding to the control flow stored in the accumulator register is the task to be executed corresponding to the execution unit group, the control flow is read and configured from the accumulator register through the run register.

[0116] S703: If the control flow is successfully configured in the run register, the execution unit executes the task to be executed corresponding to the execution unit group in which it is located.

[0117] In some embodiments, the method further includes: If all cumulative registers are successfully read and the control flow is stored, the space occupied by the stored task instruction sequence is released through the instruction cache unit, and the task instruction sequence is updated to cache the new task instruction sequence corresponding to the new task to be executed.

[0118] In some embodiments, the method further includes: When the task to be executed has finished, the new control flow in the instruction sequence of the new task is read from the instruction cache unit through the accumulation register, and the new control flow is stored, or the control flow stored in the accumulation register is merged and updated based on the new control flow to obtain the updated control flow.

[0119] In some embodiments, the accumulation register includes multiple register units for storing control flow, and each register unit corresponds to each run register with an instruction validity flag, which indicates whether the register unit stores control flow. The control flow corresponding to at least one task to be executed is retrieved and stored from the instruction cache unit through the accumulation register, including: By using the accumulation register, while storing the control flow in the register cell, the instruction validity flag corresponding to the run register is updated.

[0120] In some embodiments, when the run register is unoccupied and the task to be executed corresponding to the control flow stored in the accumulator register is the task to be executed corresponding to the execution unit group, the control flow is read and configured from the accumulator register through the run register, including: By using the run register, when the run register is in an unoccupied state and the task to be executed corresponding to the control flow stored in the accumulation register is the task to be executed corresponding to the execution unit group, the instruction validity flag corresponding to the register unit and the run register is detected. If the instruction validity flag indicates that the register unit stores control flow, the control flow stored in the register unit is copied to the run register, and the instruction validity flag corresponding to the register unit and the run register is updated.

[0121] In some embodiments, the task instruction sequence may further include a data stream corresponding to the task to be executed; The instruction pipeline is also used to transfer the data stream corresponding to the task to be executed stored in the instruction cache unit to the execution unit after the control flow has been configured in the run register.

[0122] In some embodiments, the method further includes: For each execution unit group, if the execution unit group includes a single run register and an execution unit, the control flow corresponding to the preceding task to be executed by the execution unit group is transferred to the run register through the instruction pipeline. After the data flow corresponding to the preceding task is successfully transferred to the execution unit, the control flow corresponding to the following task to be executed by the execution unit group is transferred to the accumulation register. The execution register is used to copy the control flow corresponding to the subsequent task from the accumulation register after the previous task has been executed. At the same time, the data flow corresponding to the subsequent task is transmitted to the execution unit through the instruction pipeline so that the execution unit can execute the subsequent task after the previous task has been executed.

[0123] Figure 8 This is a schematic diagram of the structure of an electronic device provided for some embodiments of this application. The electronic device 800 is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices (such as helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present application described and / or claimed herein.

[0124] like Figure 8As shown, the electronic device 800 includes at least one graphics processor 100 and a memory, such as a read-only memory (ROM) 802 or a random access memory (RAM) 803, communicatively connected to the at least one graphics processor 100. The memory stores computer programs executable by the at least one graphics processor. The graphics processor 100 can perform various appropriate actions and processes based on the computer program stored in the ROM 802 or loaded from the storage unit 808 into the RAM 803. The RAM 803 can also store various programs and data required for the operation of the electronic device 800. The graphics processor 100, the ROM 802, and the RAM 803 are interconnected via a bus 804. An input / output interface 805 (I / O) is also connected to the bus 804.

[0125] Multiple components in electronic device 800 are connected to input / output interface 805, including: input unit 806, such as keyboard, mouse, etc.; output unit 807, such as various types of monitors, speakers, etc.; storage unit 808, such as disk, optical disk, etc.; and communication unit 809, such as network card, modem, wireless transceiver, etc. Communication unit 809 allows electronic device 800 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0126] The graphics processor 100 can be any dedicated graphics processing component with processing and computing capabilities. The graphics processor 100 executes the various methods and processes described above, such as the key-value cache read / write method mentioned above.

[0127] In some embodiments, the key-value cache read / write method described above can be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 800 via read-only memory 802 and / or communication unit 809. When the computer program is loaded into random access memory 803 and executed by graphics processor 100, one or more steps of the key-value cache read / write method described above can be performed. Alternatively, in other embodiments, graphics processor 100 can be configured to perform the key-value cache read / write method described above by any other suitable means (e.g., by means of firmware).

[0128] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: implementation in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable graphics processor, which may be an application-specific programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0129] Computer programs used to implement the methods of this application may be written in any combination of one or more programming languages. These computer programs may be provided to the graphics processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the graphics processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0130] In the context of this application, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium can be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory, read-only memory, erasable programmable read-only memory (EPROM), optical fiber, compact disc read-only memory (CD ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0131] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a cathode ray tube (CRT) or liquid crystal display (LCD) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0132] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or computing systems that include middleware components (e.g., application servers), or computing systems that include frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include: Local Area Networks (LANs), Wide Area Networks (WANs), blockchain networks, and the Internet.

[0133] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is established by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system. It addresses the shortcomings of traditional physical hosts and Virtual Private Server (VPS) services, such as high management difficulty and weak business scalability.

[0134] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this application can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this application can be achieved, and this is not limited herein.

[0135] The specific embodiments described above do not constitute a limitation on the scope of protection of this application. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A graphics processor, characterized in that, include: At least two execution unit groups, an instruction cache unit shared by the at least two execution unit groups, and an instruction pipeline, wherein each execution unit group includes: an accumulation register, at least one run register, and at least one execution unit; The instruction cache unit is used to store a task instruction sequence corresponding to at least one task to be executed, each task to be executed corresponds to at least one execution unit group, and the task instruction sequence includes at least the control flow corresponding to the task to be executed; The instruction pipeline is used to transfer the control flow corresponding to the task to be executed stored in the instruction cache unit to the accumulation register; The accumulator register is used to receive and store the control flow transmitted by the instruction pipeline. The accumulator register includes multiple register units for storing the control flow, and each register unit corresponds to an instruction validity identifier for each run register. The instruction validity identifier indicates whether the register unit stores the control flow. The accumulator register is used to update the instruction validity identifier corresponding to the register unit and the run register when the control flow is stored in the register unit. The run register is used to copy and configure the control flow from the accumulation register when the run register is in an unoccupied state and the task to be executed corresponding to the control flow stored in the accumulation register is the task to be executed corresponding to the execution unit group. In the case that the execution unit group includes two or more run registers and at least two run registers are in an unoccupied state at the same time, the run register for reading the control flow is determined based on a preset allocation algorithm for the register unit that stores the control flow to be executed, and after reading the control flow from the run register, the instruction validity identifier corresponding to the register unit and the at least two run registers is updated simultaneously. The execution unit is configured to execute the task to be executed corresponding to its execution unit group when the control flow is configured in the running register.

2. The graphics processor according to claim 1, characterized in that, The instruction cache unit is also used to release the space occupied by the stored task instruction sequence and update the task instruction sequence when all cumulative registers have successfully received and stored the control flow, and to cache the new task instruction sequence corresponding to the new task to be executed.

3. The graphics processor according to claim 2, characterized in that, The instruction pipeline is also used to transfer the new control flow corresponding to the new task to be executed stored in the instruction cache unit to the accumulation register when the task to be executed has finished executing. The accumulator register is also used to receive the new control flow transmitted by the instruction pipeline, and to store the new control flow, or to merge and update the control flow stored in the accumulator register based on the new control flow to obtain an updated control flow.

4. The graphics processor according to claim 1, characterized in that, The run register is used to detect the instruction validity flag corresponding to the register unit and the run register when the run register is in an unoccupied state and the task to be executed corresponding to the control flow stored in the accumulation register is the task to be executed corresponding to the execution unit group. If the instruction validity flag indicates that the register unit stores the control flow, the run register copies the control flow stored in the register unit to the run register and updates the instruction validity flag corresponding to the register unit and the run register.

5. The graphics processor according to claim 1, characterized in that, The task instruction sequence also includes the data stream corresponding to the task to be executed; The instruction pipeline is also used to transmit the data stream corresponding to the task to be executed stored in the instruction cache unit to the execution unit when the control flow is configured in the run register; The execution unit is used to execute the task to be executed based on the data stream.

6. The graphics processor according to claim 5, characterized in that, For each execution unit group, when both the run register and the execution unit are single, the instruction pipeline is further configured to transmit the control flow corresponding to the preceding task to be executed by the execution unit group to the run register, and after successfully transmitting the data flow corresponding to the preceding task to the execution unit, transmit the control flow corresponding to the subsequent task to be executed by the execution unit group to the accumulation register. The run register is used to copy the control flow corresponding to the subsequent task from the accumulation register after the execution of the preceding task. At the same time, the instruction pipeline is also used to transmit the data flow corresponding to the subsequent task to the execution unit so that the execution unit executes the subsequent task after the execution of the preceding task.

7. A task execution method, characterized in that, The method is applied to a graphics processing unit (GPU), which includes: at least two execution unit groups, an instruction cache unit shared by the at least two execution unit groups, and an instruction pipeline. Each execution unit group includes: an accumulation register, at least one run register, and at least one execution unit. The method includes: Through the instruction pipeline, the control flow of the task instruction sequence corresponding to at least one task to be executed stored in the instruction cache unit is transferred to the accumulation register for storage. Each task to be executed corresponds to at least one execution unit group. The accumulation register includes multiple register units for storing the control flow, and each register unit corresponds to an instruction validity identifier in each run register. The instruction validity identifier indicates whether the register unit stores the control flow. Through the accumulation register, when the control flow is stored in the register unit, the instruction validity identifier corresponding to the register unit and the run register is updated. When the run register is in an unoccupied state and the task to be executed corresponding to the control flow stored in the accumulator is the task to be executed corresponding to the execution unit group, the control flow is read and configured from the accumulator through the run register. Where the execution unit group includes two or more run registers and at least two run registers are in an unoccupied state at the same time, the run register for reading the control flow is determined based on a preset allocation algorithm for the register unit that stores the control flow to be executed, and after reading the control flow from the run register, the instruction validity identifier corresponding to the register unit and the at least two run registers is updated simultaneously. If the control flow is successfully configured in the run register, the execution unit executes the task to be executed corresponding to the execution unit group it belongs to.

8. An electronic device, characterized in that, The electronic device includes: at least one graphics processor; and a memory communicatively connected to the at least one graphics processor; wherein the memory stores a computer program executable by the at least one graphics processor, the computer program being executed by the at least one graphics processor to enable the at least one graphics processor to perform the task execution method of claim 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions that cause the graphics processor to execute the task execution method of claim 7.

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