Pixel circuit and display panel

Abstract

Embodiments of the present application disclose a pixel circuit and a display panel. The pixel circuit comprises a driving module, a compensation module, a light-emitting control module and a reset module. The light-emitting control module is used for being turned on in a first reset stage, a second reset stage and a light-emitting stage. The compensation module is used for being turned on in the first reset stage and a threshold voltage compensation and data writing stage, and being turned off in the second reset stage. The reset module is used for being turned on in the first reset stage, transmitting a first reset voltage on a reset signal line to a control end of the driving module and a first end of a light-emitting device, and being turned on in the second reset stage, transmitting a second reset voltage on the reset signal line to the first end of the light-emitting device. In a frame, the first reset stage is located before the threshold voltage compensation and data writing stage, and the second reset stage is located between the first reset stage and the light-emitting stage. The display panel can improve display effect.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a pixel circuit and a display panel. Background Technology

[0002] With the continuous development of display technology, people have increasingly higher requirements for display quality.

[0003] However, existing display panels currently suffer from poor display quality. Summary of the Invention

[0004] This invention provides a pixel circuit and a display panel to improve the display effect of the display panel.

[0005] In a first aspect, embodiments of the present invention provide a pixel circuit, comprising: a driving module, a compensation module, a light-emitting control module, and a reset module; a first end of the driving module is connected to a first power line, the first power line being used to transmit a first power supply voltage and a data voltage to the first end of the driving module in a time-division multiplexing manner; a first end of the light-emitting control module is connected to a second end of the driving module, the second end of the light-emitting control module is connected to a first end of a light-emitting device, and the light-emitting control module is used to be turned on in a first reset phase, a second reset phase, and a light-emitting phase; a compensation module is connected between the second end of the driving module and a control end of the driving module, and the compensation module is used to be turned on in the first reset phase and in a threshold voltage compensation and data writing phase, and turned off in the second reset phase; a first end of the reset module is connected to a reset signal line, the second end of the reset module is connected to the second end of the driving module or the second end of the light-emitting control module, and the reset module is used to be turned on in the first reset phase, transmitting a first reset voltage on the reset signal line to the control end of the driving module and the first end of the light-emitting device; and turned on in the second reset phase, transmitting a second reset voltage on the reset signal line to the first end of the light-emitting device; wherein the first reset voltage and the second reset voltage are different; within one frame, the first reset phase is located before the threshold voltage compensation and data writing phase, and the second reset phase is located between the first reset phase and the light-emitting phase.

[0006] Optionally, the first power line is used to transmit a data voltage to the first end of the driving module during the threshold voltage compensation and data writing stage; and to transmit a first power supply voltage to the first end of the driving module during the light emission stage; the second end of the light-emitting device is connected to the second power line.

[0007] Optionally, the reset module is connected between the reset signal line and the second terminal of the drive module. The control terminal of the reset module is connected to the first scan line, which transmits a first scan signal. The control terminal of the light emission control module is connected to the light emission control line, which transmits a light emission control signal. The light emission control module is used to turn on in response to the light emission control signal during the first reset phase. The reset module is used to turn on in response to the first pulse of the first scan signal, transmitting a first reset voltage to the second terminal of the drive module and then to the first terminal of the light-emitting device via the light emission control module. The control terminal of the compensation module is connected to the second scan line, which transmits a second scan signal. The compensation module is used to turn on in response to the first pulse of the second scan signal during the first reset phase, transmitting the first reset voltage to the control terminal of the drive module. The conduction duration of the first pulse of the first scan signal is greater than or equal to the conduction duration of the first pulse of the second scan signal.

[0008] Optionally, within one frame, the start time of the first pulse of the first scan signal is the same as the start time of the first pulse of the second scan signal, and is earlier than the start time of the invalid level of the light emission control signal; the end time of the first pulse of the first scan signal is earlier than the start time of the second pulse of the second scan signal; the start time of the second pulse of the second scan signal is later than the start time of the invalid level of the light emission control signal; the end time of the second pulse of the second scan signal is earlier than the end time of the invalid level of the light emission control signal; and the start time of the second pulse of the first scan signal is later than the end time of the invalid level of the light emission control signal.

[0009] Optionally, a reset module is connected between a reset signal line and a first terminal of the light-emitting device. The control terminal of the reset module is connected to a first scan line, which transmits a first scan signal. During the first reset phase, the reset module is activated in response to a first pulse of the first scan signal, transmitting a first reset voltage to the first terminal of the light-emitting device. The control terminal of the light-emitting control module is connected to a light-emitting control line, which transmits a light-emitting control signal. The light-emitting control module is activated during the first reset phase in response to the light-emitting control signal. The control terminal of the compensation module is connected to a second scan line, which transmits a second scan signal. The compensation module is activated in response to a first pulse of the second scan signal, so that the first reset voltage is transmitted to the control terminal of the drive module via the light-emitting control module and the compensation module. The duration of the first pulse of the first scan signal is greater than or equal to the duration of the first pulse of the second scan signal.

[0010] Optionally, within one frame, the start time of the first pulse of the first scan signal is earlier than the start time of the invalid level of the light emission control signal, the end time of the first pulse of the first scan signal is earlier than the end time of the invalid level of the light emission control signal, and later than the end time of the second pulse of the second scan signal; or, the start time of the valid level of the first scan signal is earlier than the start time of the invalid level of the light emission control signal, and the end time of the valid level of the first scan signal is later than the end time of the invalid level of the light emission control signal.

[0011] Optionally, the pixel circuit also includes a storage module, which is connected between the reference signal line and the control terminal of the drive module; Within one frame, during the process of the compensation module responding to the second pulse of the second scan signal and being turned on, the first terminal of the drive module is configured with a data voltage so that the data voltage and the threshold voltage of the drive module are written to the control terminal of the drive module, and the storage module stores the threshold voltage. The storage module includes a first capacitor, the first terminal of which is connected to a reference signal line, and the second terminal of which is connected to the control terminal of the drive module.

[0012] The driving module includes a first transistor, with its first terminal serving as the first end of the driving module, its second terminal serving as the second end of the driving module, and its gate serving as the control terminal of the driving module; the compensation module includes a second transistor, with its gate connected to a second scan line, its first terminal connected to the gate of the first transistor, and its second terminal connected to the second terminal of the first transistor; the reset module includes a third transistor, with its gate connected to the first scan line, its first terminal connected to a reset signal line, and its second terminal connected to the second terminal of the first transistor or the first end of the light-emitting device; the light-emitting control module includes a fourth transistor, with its gate connected to a light-emitting control line, its first terminal connected to the second terminal of the first transistor, and its second terminal connected to the first end of the light-emitting device.

[0013] Secondly, embodiments of the present invention provide a display panel, which includes a plurality of pixel circuits provided in any embodiment of the present invention.

[0014] Optionally, the display panel further includes multiple gating circuits, each gating circuit including a data voltage terminal, a first power supply voltage terminal, and an output terminal. The output terminal of the gating circuit is connected to at least one column of pixel circuits, the data voltage terminal is connected to a data voltage, the first power supply voltage terminal is connected to a first power supply voltage, and the gating circuit is used to transmit the data voltage to the first power line in response to the effective level of the first control signal; and to transmit the first power supply voltage to the first power line in response to the effective level of the second control signal, wherein, within one frame, the first control signal and the second control signal are at effective levels at different times.

[0015] Optionally, the selection circuit includes a first switching unit and a second switching unit. The first switching unit is connected between the first power supply line and the data voltage terminal, and is used to transmit the data voltage to the first power supply line in response to the effective level of the first control signal. The second switching unit is connected between the first power supply line and the first power supply voltage terminal, and is used to transmit the first power supply voltage to the first power supply line in response to the effective level of the second control signal.

[0016] Optionally, the first control signal and the second control signal are global signals.

[0017] Optionally, the first switching unit includes a fifth transistor, and the second switching unit includes a sixth transistor; the gate of the fifth transistor is connected to a first control signal, the first terminal of the fifth transistor is connected to a data voltage terminal, and the second terminal of the fifth transistor is connected to a first power supply line; the gate of the sixth transistor is connected to a second control signal, the first terminal of the sixth transistor is connected to a first power supply voltage terminal, and the second terminal of the sixth transistor is connected to a first power supply line.

[0018] Optionally, within a frame, the first control signal is at an active level during the threshold voltage compensation and data writing phase, and the second control signal is at an active level at least during the light emission phase.

[0019] Optionally, the working process of a pixel circuit in one frame includes a first reset stage, a threshold voltage characteristic adjustment stage, a threshold voltage compensation and data writing stage, a second reset stage, and a light emission stage performed sequentially; the first reset stage of each pixel circuit is performed simultaneously, the threshold voltage characteristic adjustment stage of each pixel circuit is performed simultaneously, the threshold voltage compensation and data writing stage of each row of pixel circuits is performed row by row, the second reset stage of each row of pixel circuits is performed simultaneously, and the light emission stage of each pixel circuit is performed simultaneously.

[0020] Optionally, the start time of the light emission control signal for each row of pixel circuits is the same.

[0021] Optionally, the display panel includes a display area and a non-display area, with multiple pixel circuits located in the display area and arranged in multiple rows of pixel circuit groups. The display panel also includes multiple shift registers and multiple second scan lines. The multiple shift registers are cascaded and located in the non-display area of ​​the display panel. Each shift register is connected to the control terminal of a compensation module for multiple pixel circuits in a row of pixel circuit groups via a corresponding second scan line. The shift registers are configured to generate second scan signals. The second scan signals generated by the multiple shift registers simultaneously generate a first pulse and then generate second pulses sequentially.

[0022] The pixel circuit provided in this embodiment of the invention includes a first power line, a driving module, a compensation module, a light-emitting control module, and a reset module. By setting the first power line to transmit the first power supply voltage and the data voltage to the first terminal of the driving module in a time-division manner, it is not necessary to set separate signal lines for the data voltage and the first power supply voltage, which reduces the number of signal lines required for the pixel circuit, simplifies signal routing, saves layout space, and facilitates the achievement of higher pixel density. At the same time, by setting the reset module to be connected between the reset signal line and the second terminal of the driving module or the first terminal of the light-emitting device, and the reset signal line to provide the first reset voltage and the second reset voltage in a time-division manner, it is also not necessary to set multiple separate reset signal lines for different reset voltages, further reducing the number of signal lines, which is conducive to achieving ultra-high PPI display layout and meeting the high-resolution display requirements of VR / AR, etc. In the first reset stage, the compensation module and the reset module are turned on, and the first reset voltage is transmitted to the second terminal of the driving module and the first terminal of the light-emitting device, so that the second terminal of the driving module and the first terminal of the light-emitting device are reset simultaneously, effectively eliminating residual charge from the previous frame and solving the ghosting problem. The compensation module is activated during the first reset phase and the threshold voltage compensation and data writing phases. By using the same compensation module to perform reset and compensation functions in different phases, no additional functional modules are needed, further reducing the number of transistors. Simultaneously, the first power line transmits data voltage to the first terminal of the driving module during the threshold voltage compensation and data writing phases. The activation of the compensation module compensates for the threshold voltage of the driving module, making the driving current generated by the driving module independent of the threshold voltage, significantly improving display uniformity. Furthermore, the reset module transmits a second reset voltage to the first terminal of the light-emitting device during the second reset phase, performing a secondary reset on the first terminal of the light-emitting device before emission, which helps improve the brightness of the first frame. The reset module can be located at the second terminal of the driving module or at the first terminal of the light-emitting device, allowing for flexible selection based on layout space while ensuring circuit performance, further enhancing the flexibility of layout design. Through the above methods, the pixel circuit provided by this embodiment of the invention effectively solves the problems of poor display uniformity, ghosting, and low brightness in the first frame while reducing the number of transistors and signal traces to achieve ultra-high PPI display arrangement, thus improving the display effect.

[0023] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 2 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 3 This is a driving timing waveform diagram of a pixel circuit provided in an embodiment of the present invention; Figure 4 This is a simulation waveform diagram of the timing node voltage of a pixel circuit drive provided by an embodiment of the present invention; Figure 5 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 6 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 7 This is a simulation waveform diagram of the timing node voltage of a pixel circuit drive provided by an embodiment of the present invention; Figure 8 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 9 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 10 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention; Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 12 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention; Figure 13 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention; Figure 14 This is a schematic diagram of the connection structure between a gating circuit and a pixel circuit provided in an embodiment of the present invention; Figure 15This is a driving timing diagram of a display panel provided in an embodiment of the present invention; Figure 16 This is a driving timing diagram for another display panel provided in an embodiment of the present invention; Figure 17 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. Detailed Implementation

[0026] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion.

[0028] With the continuous development of display technology, the application range of organic light-emitting diode (OLED) display panels is becoming more and more widespread, such as virtual reality (VR) and augmented reality (AR) display solutions, bringing users a brand-new visual experience.

[0029] However, existing OLED display panels suffer from large bezels, failing to meet the application requirements of AR / VR and other display solutions. While mature pixel driving circuits such as the 7T1C circuit offer comprehensive functionality, their large number of thin-film transistors (TFTs) limits the achievement of ultra-high pixel density (Pixel Per Inch, PPI) due to process limitations. The conventional 2T1C circuit solution, with fewer TFT devices, can significantly improve PPI, but it lacks functions such as gate initialization and anode initialization, or cannot achieve threshold voltage compensation within the pixel, thus failing to meet application requirements.

[0030] Based on this, this application provides a pixel circuit design scheme suitable for high PPI display panels, with the aim of achieving higher pixel density to at least meet the display requirements of VR devices.

[0031] Figure 1 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 2 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 1 and Figure 2 As shown, the pixel circuit 10 includes a driving module 110, a compensation module 120, an emissive control module 130, and a reset module 140.

[0032] The first terminal of the drive module 110 is connected to the first power line L1, which is used to transmit the first power supply voltage VDD and the data voltage Vdata to the first terminal S of the drive module 110 in a time-division manner.

[0033] The first end of the light-emitting control module 130 is connected to the second end D of the driving module 110, and the second end of the light-emitting control module 130 is connected to the first end of the light-emitting device D1. The light-emitting control module 130 is used to conduct during the first reset phase, the second reset phase, and the light-emitting phase.

[0034] The compensation module 120 is connected between the second terminal D of the drive module 110 and the control terminal G of the drive module 110. The compensation module 120 is turned on during the first reset phase and the threshold voltage compensation and data writing phase, and turned off during the second reset phase.

[0035] The first terminal of the reset module 140 is connected to the reset signal line AC_Vref, and the second terminal of the reset module 140 is connected to the second terminal D of the drive module 110 or the second terminal of the light-emitting control module 130. The reset module 140 is used to conduct during the first reset phase, transmitting the first reset voltage Vref1 on the reset signal line AC_Vref to the control terminal G of the drive module 110 and the first terminal of the light-emitting device D1; and to conduct during the second reset phase, transmitting the second reset voltage Vref2 on the reset signal line AC_Vref to the first terminal of the light-emitting device D1. The first reset voltage Vref1 and the second reset voltage Vref2 are different.

[0036] Within a frame, the first reset phase is located before the threshold voltage compensation and data writing phase, and the second reset phase is located between the first reset phase and the light emission phase.

[0037] Specifically, Figure 1 The diagram illustrates the connection of the reset module 140 between the reset signal line AC_Vref and the second terminal D of the drive module 110. Figure 2The diagram illustrates the connection of the reset module 140 between the reset signal line AC_Vref and the first terminal of the light-emitting device D1.

[0038] The light-emitting device D1 can be a light-emitting diode (LED), an organic light-emitting diode (OLED), or other electroluminescent device. The first terminal of the light-emitting device D1 is the anode, and the second terminal is the cathode. The second terminal of the light-emitting device D1 is connected to a second power supply line L2, which can provide a second power supply voltage VSS. For example, the first power supply voltage VDD can be zero or positive, and the second power supply voltage VSS can be negative; or, the first power supply voltage VDD can be positive, and the second power supply voltage VSS can be zero or negative.

[0039] The driving module 110 may include a first transistor M1, the gate of the first transistor M1 serving as the control terminal of the driving module 110, the source of the first transistor M1 serving as the first terminal of the driving module 110, and the drain of the first transistor M1 serving as the second terminal of the driving module 110.

[0040] In some embodiments, the first power line L1 is used to transmit a data voltage Vdata to the first terminal S of the driving module 110 during the threshold voltage compensation and data writing phase; and to transmit a first power supply voltage VDD to the first terminal S of the driving module 110 during the light emission phase.

[0041] Optionally, both the first power supply voltage VDD and the second power supply voltage VSS are DC signals, which can enable the normal operation of each stage of the pixel circuit without the need for complex AC function ICs.

[0042] The following will combine Figure 1 and Figure 2 The pixel circuit structure shown illustrates the detailed operation of the pixel circuit 10 provided in this embodiment of the invention within one frame. Within one frame, the operation of the pixel circuit includes at least a first reset stage, a threshold voltage compensation and data writing stage, a second reset stage, and a light emission stage, performed sequentially.

[0043] During the first reset phase, the compensation module 120, the light-emitting control module 130, and the reset module 140 are all turned on. For example... Figure 1 As shown, the reset module 140 transmits the first reset voltage Vref1 on the reset signal line AC_Vref to the control terminal G of the drive module 110 via the supplementary module 120; simultaneously, since the light-emitting control module 130 is turned on, the first reset voltage Vref1 is further transmitted to the first terminal of the light-emitting device D1 via the light-emitting control module 130. Figure 2As shown, the reset module 140 transmits the first reset voltage Vref1 on the reset signal line AC_Vref to the first terminal of the light-emitting device D1. Simultaneously, since the light-emitting control module 130 is turned on, this first reset voltage Vref1 is further transmitted via the light-emitting control module 130 and the compensation module 120 to the control terminal G of the drive module 110, thereby achieving synchronous reset of the control terminal G of the drive module 110 and the first terminal of the light-emitting device D1. Furthermore, since the compensation module 120 is turned on, the first reset voltage Vref1 is also transmitted via the compensation module 120 to the control terminal G of the drive module 110 to initialize the control terminal G of the drive module 110, thereby eliminating the influence of residual charge from the previous frame on the display of the current frame.

[0044] During the threshold voltage compensation and data writing phase, the compensation module 120 is turned on, while the light-emitting control module 130 and the reset module 140 are turned off. The first power line L1 transmits the data voltage Vdata to the first terminal of the drive module 110. At this time, since the control terminal G of the drive module 110 has been reset in the first reset phase, and the compensation module 120 is connected to the control terminal G and the second terminal of the drive module 110, the current flowing through the drive module 110 charges or discharges the control terminal G of the drive module 110 through the compensation module 120 until the voltage of the control terminal G of the drive module 110 is equal to the sum of the data voltage Vdata and the threshold voltage of the drive module 110 (i.e., VG = Vdata + Vth). The threshold voltage information of the drive module 110 is then stored in the control terminal G of the drive module 110. This completes the threshold voltage compensation of the drive module 110 and writes the data voltage Vdata to the control terminal G of the drive module 110.

[0045] During the second reset phase, the light-emitting control module 130 and the reset module 140 are turned on, while the compensation module 120 is turned off. The reset module 140 transmits the second reset voltage Vref2 on the reset signal line AC_Vref to the first terminal of the light-emitting device D1. Since the compensation module 120 is turned off, the second reset voltage Vref2 is not transmitted to the control terminal G of the drive module 110, thereby avoiding interference with the already written compensation voltage. The first reset voltage Vref1 is less than or equal to the second reset voltage Vref2, and the second reset voltage Vref2 is less than or equal to 0. This ensures that during the second reset phase, the first terminal of the light-emitting device D1 is reset to a voltage not lower than the first reset voltage Vref1 and not positive. This helps prevent the light-emitting device D1 from erroneously emitting light due to excessive voltage before subsequent light emission, and also improves the problem of low brightness in the first frame.

[0046] During the light-emitting phase, the light-emitting control module 130 is turned on, the reset module 140 is turned off, and the compensation module 120 is turned off. The first power supply line L1 transmits the first power supply voltage VDD to the first terminal of the drive module 110. The drive module 110 generates a drive current based on the voltage at the control terminal G and the first power supply voltage VDD received at the first terminal. This drive current is transmitted to the first terminal of the light-emitting device D1 via the turned-on light-emitting control module 130 to drive the light-emitting device D1 to emit light.

[0047] At this time, the difference between the gate-source voltage VGS and the threshold voltage Vth of the drive module 110 is Vdata-VDD, which makes the drive current independent of the threshold voltage of the drive module 110 and improves the current uniformity.

[0048] The pixel circuit provided in this embodiment of the invention includes a first power line, a driving module, a compensation module, a light-emitting control module, and a reset module. By setting the first power line to transmit the first power supply voltage and the data voltage to the first terminal of the driving module in a time-division manner, it is not necessary to set separate signal lines for the data voltage and the first power supply voltage, which reduces the number of signal lines required for the pixel circuit, simplifies signal routing, saves layout space, and facilitates the achievement of higher pixel density. At the same time, by setting the reset module to be connected between the reset signal line and the second terminal of the driving module or the first terminal of the light-emitting device, and the reset signal line to provide the first reset voltage and the second reset voltage in a time-division manner, it is also not necessary to set multiple separate reset signal lines for different reset voltages, further reducing the number of signal lines, which is conducive to achieving ultra-high PPI display layout and meeting the high-resolution display requirements of VR / AR, etc. In the first reset stage, the compensation module and the reset module are turned on, and the first reset voltage is transmitted to the second terminal of the driving module and the first terminal of the light-emitting device, so that the second terminal of the driving module and the first terminal of the light-emitting device are reset simultaneously, effectively eliminating residual charge from the previous frame and solving the ghosting problem. The compensation module is activated during the first reset phase and the threshold voltage compensation and data writing phases. By using the same compensation module to perform reset and compensation functions in different phases, no additional functional modules are needed, further reducing the number of transistors. Simultaneously, the first power line transmits data voltage to the first terminal of the driving module during the threshold voltage compensation and data writing phases. The activation of the compensation module compensates for the threshold voltage of the driving module, making the driving current generated by the driving module independent of the threshold voltage, significantly improving display uniformity. Furthermore, the reset module transmits a second reset voltage to the first terminal of the light-emitting device during the second reset phase, performing a secondary reset on the first terminal of the light-emitting device before emission, which helps improve the brightness of the first frame. The reset module can be located at the second terminal of the driving module or at the first terminal of the light-emitting device, allowing for flexible selection based on layout space while ensuring circuit performance, further enhancing the flexibility of layout design. Through the above methods, the pixel circuit provided by this embodiment of the invention effectively solves the problems of poor display uniformity, ghosting, and low brightness in the first frame while reducing the number of transistors and signal traces to achieve ultra-high PPI display arrangement, thus improving the display effect.

[0049] Figure 3 This is a driving timing waveform diagram of a pixel circuit provided in an embodiment of the present invention. This driving timing can be used... Figure 1 and Figure 2 The pixel circuit shown. Figure 4 This is a simulation waveform diagram of the timing node voltage of a pixel circuit drive provided by an embodiment of the present invention. (Reference) Figure 1 , Figure 3 and Figure 4Within a frame, the operation of the pixel circuit includes the sequential execution of the first reset stage t1, the threshold voltage compensation and data writing stage t3, the second reset stage t4, and the light emission stage t5.

[0050] Wherein, VG represents the potential of the control terminal of the drive module 110, VGS represents the gate-source voltage difference of the control terminal of the drive module 110, VD represents the potential of the second terminal of the drive module 110, Vanode represents the potential of the anode of the light-emitting device D1, and I_oled represents the drive current generated by the drive module 110.

[0051] The reset module 140 is connected between the reset signal line AC_Vref and the second terminal D of the drive module 110. The control terminal of the reset module 140 is connected to the first scan line GL1, and the first scan line GL1 transmits the first scan signal S1.

[0052] The control terminal of the light-emitting control module 130 is connected to the light-emitting control line GL3. The light-emitting control line GL3 transmits the light-emitting control signal EM. The light-emitting control module 130 is used to turn on in response to the light-emitting control signal EM during the first reset phase t1.

[0053] The reset module 140 is used to turn on in response to the first pulse pulse11 of the first scan signal S1 during the first reset phase t1, and transmit the first reset voltage Vref1 to the second terminal of the drive module 110, and transmit it to the first terminal of the light-emitting device D1 via the light-emitting control module 130.

[0054] The control terminal of the compensation module 120 is connected to the second scan line GL2, and the second scan line GL2 transmits the second scan signal S2. The compensation module 120 is used to turn on in response to the first pulse pulse21 of the second scan signal S2 during the first reset phase t1, so as to transmit the first reset voltage Vref1 to the control terminal G of the drive module 110.

[0055] Specifically, in the first reset phase t1, the first scan signal S1 provides a first pulse pulse11, the second scan signal S2 provides a first pulse pulse21, and the light emission control signal EM is at an active level. At this time, the reset module 140 is activated in response to the first pulse pulse11 of the first scan signal S1, the light emission control module 130 is activated in response to the light emission control signal EM, and the compensation module 120 is activated in response to the first pulse pulse21 of the second scan signal S2. The reset module 140 transmits the first reset voltage Vref1 on the reset signal line AC_Vref to the second terminal D of the drive module 110. Simultaneously, since the light emission control module 130 is activated, the first reset voltage Vref1 is further transmitted via the light emission control module 130 to the first terminal of the light-emitting device D1, resetting the first terminal of the light-emitting device D1 to the first reset voltage Vref1. Since the compensation module 120 is activated, the first reset voltage Vref1 is also transmitted via the compensation module 120 to the control terminal G of the drive module 110, resetting the control terminal G of the drive module 110 to the first reset voltage Vref1. As a result, the second terminal D of the driving module 110, the control terminal G of the driving module 110, and the first terminal of the light-emitting device D1 are simultaneously reset to the first reset voltage Vref1, effectively eliminating the residual charge of the previous frame and solving the ghosting problem.

[0056] Optionally, the reset module 140 is also configured to turn on the second pulse pulse 12 in response to the first scan signal S1 during the second reset phase t4.

[0057] Specifically, during the second reset phase t4, the reset module 140 is activated in response to the second pulse pulse 12 of the first scan signal S1. The second scan signal S2 is at an invalid level, and the compensation module 120 is turned off; the light emission control signal EM is at an active level, and the light emission control module 130 is activated. After the reset module 140 is activated, it transmits the second reset voltage Vref2 on the reset signal line AC_Vref to the second terminal D of the drive module 110, and further transmits it to the first terminal of the light-emitting device D1 via the light emission control module 130, thus resetting the first terminal of the light-emitting device D1 to the second reset voltage Vref2. The compensation module 120 is turned off, ensuring that the second reset voltage Vref2 is not transmitted to the control terminal G of the drive module 110.

[0058] The first scan signal S1 provides a first pulse 11 in the first reset phase t1 and a second pulse 12 in the second reset phase t4. That is, the reset module 140 is activated in response to the first pulse 11 of the first scan signal S1 in the first reset phase t1 to perform a first reset, and in response to the second pulse 12 of the first scan signal S1 in the second reset phase t4 to perform a second reset. The same first scan signal S1, by providing two time-divisionally occurring pulses, controls the activation of the reset module 140 in two different reset phases, eliminating the need for an additional independent control signal line for the second reset phase t4.

[0059] Optionally, the compensation module 120 is also used to turn on the second pulse pulse22 in response to the second scan signal S2 during the threshold voltage compensation and data writing stage t3.

[0060] Specifically, during the threshold voltage compensation and data writing stage t3, the compensation module 120 is turned on in response to the second pulse pulse 22 of the second scan signal S2. The first scan signal S1 is at an invalid level, and the reset module 140 is turned off; the light emission control signal EM is at an invalid level, and the light emission control module 130 is turned off. After the compensation module 120 is turned on, the second terminal D of the drive module 110 is connected to the control terminal G of the drive module 110. At this time, the first power line L1 transmits the data voltage Vdata to the first terminal S of the drive module 110. The current flowing through the drive module 110 charges or discharges the control terminal G of the drive module 110 through the compensation module 120 until the voltage of the control terminal G of the drive module 110 is equal to the sum of the data voltage Vdata and the threshold voltage of the drive module 110, thus completing the threshold voltage compensation and data voltage writing. The compensation module 120 is turned on in response to the first pulse 21 of the second scan signal S2 during the first reset phase t1 to perform the reset function, and is turned on in response to the second pulse 22 of the second scan signal S2 during the threshold voltage compensation and data writing phase t3 to perform the compensation function. The same second scan signal S2 provides two time-division multiplexing pulses to control the conduction of the compensation module 120 in the two different phases, eliminating the need for additional independent control signal lines for the threshold voltage compensation and data writing phase t3.

[0061] Optionally, the first pulse 11 of the first scan signal S1 and the first pulse 21 of the second scan signal S2 have the same conduction duration. This configuration ensures that the reset module 140 and the compensation module 120 have the same conduction duration during the first reset phase t1. This allows the second terminal D of the drive module 110 to be reset synchronously with the control terminal G, and the reset times are consistent, avoiding problems such as insufficient reset or potential mismatch caused by differences in conduction time.

[0062] Optionally, the conduction duration of the first pulse 11 of the first scan signal S1 is greater than or equal to the conduction duration of the first pulse 21 of the second scan signal S2. When the conduction duration of the first pulse 11 of the first scan signal S1 is greater than the conduction duration of the first pulse 21 of the second scan signal S2, after the compensation module 120 is turned off, the reset module 140 continues to be turned on, continuously applying the first reset voltage Vref1 to the second terminal D of the drive module 110, so as to extend the reset time of the second terminal D of the drive module 110, ensuring that it is fully reset to the stable first reset voltage Vref1, and avoiding the residual charge from affecting the accuracy of subsequent threshold voltage characteristic adjustment or threshold voltage compensation due to insufficient reset time.

[0063] refer to Figure 2 and Figure 3 The reset module 140 is connected between the reset signal line AC_Vref and the first end of the light-emitting device D1. The control terminal of the reset module 140 is connected to the first scan line GL1, and the first scan line GL1 transmits the first scan signal. The reset module 140 is used to turn on the first pulse pulse11 of the first scan signal S1 in the first reset stage t1, and transmit the first reset voltage Vref1 to the first end of the light-emitting device D1.

[0064] The control terminal of the light-emitting control module 130 is connected to the light-emitting control line GL3. The light-emitting control line GL3 transmits the light-emitting control signal EM. The light-emitting control module 130 is used to turn on in response to the light-emitting control signal EM during the first reset phase t1.

[0065] The control terminal of the compensation module 120 is connected to the second scan line GL2, and the second scan line GL2 transmits the second scan signal S2. The compensation module 120 is used to turn on in response to the first pulse pulse 21 of the second scan signal S2 during the first reset phase t1, so that the first reset voltage Vref1 is transmitted to the control terminal of the drive module 110 via the light emission control module 130 and the compensation module 120.

[0066] Specifically, in the first reset phase t1, the reset module 140 is turned on in response to the first pulse pulse11 of the first scan signal S1, directly transmitting the first reset voltage Vref1 on the reset signal line AC_Vref to the first terminal of the light-emitting device D1, thus resetting the first terminal of the light-emitting device D1 to the first reset voltage Vref1. Since the light-emitting control module 130 is simultaneously turned on in response to the light-emitting control signal EM, a conduction path is formed between the first terminal of the light-emitting device D1 and the second terminal D of the driving module 110. The first reset voltage Vref1 is transmitted in reverse through the light-emitting control module 130 to the second terminal D of the driving module 110, thus synchronously resetting the second terminal D of the driving module 110. Since the compensation module 120 is simultaneously turned on in response to the first pulse pulse21 of the second scan signal S2, a conduction path is formed between the second terminal D of the driving module 110 and the control terminal G of the driving module 110. The first reset voltage Vref1 is further transmitted through the compensation module 120 to the control terminal G of the driving module 110, thus synchronously resetting the control terminal G of the driving module 110. Therefore, during the first reset phase t1, the first terminal of the light-emitting device D1, the second terminal D of the driving module 110, and the control terminal G of the driving module 110 are simultaneously reset to the first reset voltage Vref1.

[0067] Optionally, the conduction duration of the first pulse 11 of the first scan signal S1 is greater than or equal to the conduction duration of the first pulse 21 of the second scan signal S2. When the conduction duration of the first pulse 11 of the first scan signal S1 is greater than the conduction duration of the first pulse 21 of the second scan signal S2, the reset module 140 continues to apply the first reset voltage Vref1 to the first terminal of the light-emitting device D1 to prolong the reset time of the first terminal of the light-emitting device D1 and ensure that it is fully reset to the stable first reset voltage Vref1. At the same time, since the compensation module 120 is turned off first, the path between the control terminal G and the second terminal D of the drive module 110 is cut off. The continuous conduction of the reset module 140 only acts on the first terminal of the light-emitting device D1 and will not interfere with the potential of the already reset control terminal G. When the conduction duration of the first pulse pulse11 of the first scan signal S1 is equal to the conduction duration of the first pulse pulse21 of the second scan signal S2, the reset module 140 and the compensation module 120 are turned off simultaneously, which can also realize the synchronous reset function within the first reset stage t1.

[0068] Optionally, such as Figure 3As shown, within a frame, a threshold voltage characteristic adjustment stage t2 can also be set between the first reset stage t1 and the threshold voltage compensation and data writing stage t3. It should be noted that, through research by the inventors, it has been found that before the pixel circuit is driven to execute the current display cycle, the threshold voltage Vth of the driving module 110 may have a certain drift. Therefore, before the pixel circuit executes the threshold voltage compensation stage t3 of the current display cycle, resetting or adjusting the threshold voltage Vth of the driving module 110 to restore the threshold voltage Vth to its initial state is beneficial to ensuring the display uniformity of the display panel.

[0069] During the threshold voltage characteristic adjustment phase t2, both the compensation module 120 and the light-emitting control module 130 are turned off. The reset module 140 can remain on or off depending on the specific implementation. The first power line L1 transmits the first power supply voltage VDD to the first terminal S of the driving module 110. At this time, since the control terminal G of the driving module 110 has been reset to the first reset voltage Vref1 during the first reset phase t1, and the first terminal S of the driving module 110 is configured to the first power supply voltage VDD during the threshold voltage characteristic adjustment phase t2, the gate-source voltage VGS of the driving module 110 = VG - VS = Vref1 - VDD. Since Vref1 is less than 0 and VDD is greater than or equal to 0, VGS is a negative voltage. This negative gate-source voltage causes the transistors in the driving module 110 to experience a strong electric field perpendicular to the channel direction and a weak electric field parallel to the channel direction. Under the influence of this electric field, the traps existing at the gate oxide layer and channel interface of the transistor in the driving module 110 that cause threshold voltage Vth drift can capture or release charges, thereby accelerating the recovery speed of the threshold voltage Vth of the driving module 110 to its initial state. The duration of this threshold voltage characteristic adjustment stage t2 can be set independently according to actual needs and is not limited by the data writing time. By setting a longer adjustment time, it can be fully ensured that the threshold voltage Vth is restored to its initial state. The combination of a larger negative voltage and a longer adjustment time can effectively improve display defects such as image retention caused by threshold voltage drift, and ensure the uniformity of subsequent threshold compensation and light emission.

[0070] Figure 5 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used... Figure 1 and Figure 2 The pixel circuit shown. Figure 5 The driving timing shown is Figure 3 The difference in the driving timing shown is: Figure 5The driving timing shown does not include the threshold voltage characteristic adjustment stage t2. That is, within one frame, it only includes the first reset stage t1, the threshold voltage compensation and data writing stage t3, the second reset stage t4, and the light emission stage t5, performed sequentially. Under this timing configuration, the pixel circuit directly enters the threshold voltage compensation and data writing stage t3 after completing the first reset stage t1. This is suitable for application scenarios with low threshold voltage characteristic adjustment requirements or high frame rate requirements. The timing setup is simpler and helps reduce the timing output requirements of the driver chip.

[0071] Figure 6 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. Figure 7 This is a simulation waveform diagram of the node voltage of a pixel circuit driving timing provided in an embodiment of the present invention. This driving timing can be used... Figure 1 The pixel circuit shown. (Reference) Figure 1 , Figure 6 and Figure 7 Within one frame, the start time of the first pulse pulse11 of the first scan signal S1 is the same as the start time of the first pulse pulse21 of the second scan signal S2, and is earlier than the start time of the invalid level of the light emission control signal EM. The end time of the first pulse pulse11 of the first scan signal S1 is earlier than the start time of the second pulse pulse22 of the second scan signal S2.

[0072] The start time of the second pulse 22 of the second scan signal S2 is later than the start time of the invalid level of the light emission control signal EM, and the end time of the second pulse 22 of the second scan signal S2 is earlier than the end time of the invalid level of the light emission control signal EM; the start time of the second pulse 12 of the first scan signal S1 is later than the end time of the invalid level of the light emission control signal EM.

[0073] Specifically, the first scan signal S1 controls the on / off state of the reset module 140, and the second scan signal S2 controls the on / off state of the compensation module 120. During the first reset phase t1, the first pulse 11 of the first scan signal S1 controls the reset module 140 to turn on, transmitting the first reset voltage Vref1 to the second terminal D of the drive module 110; the first pulse 21 of the second scan signal S2 controls the compensation module 120 to turn on, connecting the second terminal D of the drive module 110 to its control terminal G. The start time of the first pulse 11 of the first scan signal S1 is the same as the start time of the first pulse 21 of the second scan signal S2, meaning that the reset module 140 and the compensation module 120 start conducting simultaneously. Since the control terminal G of the drive module 110 obtains the first reset voltage Vref1 from the second terminal D of the drive module 110 through the conduction path of the compensation module 120, if the compensation module 120 is turned on later than the reset module 140, the reset start time of the control terminal G will be later than that of the second terminal D, and the two reset times will be asynchronous. If the compensation module 120 is turned on earlier than the reset module 140, the compensation module 120 will be turned on but the second terminal D will not have received the reset voltage, and synchronous reset will also be impossible. By setting the start time of the two pulses to be the same, it is ensured that the reset module 140 and the compensation module 120 are turned on synchronously at the beginning of the first reset phase t1, and the first reset voltage Vref1 reaches the second terminal D and the control terminal G of the drive module 110 at the same time, so that the two nodes are reset synchronously. This avoids the reset asynchrony problem caused by the difference in conduction start time, and ensures that the second terminal D and the control terminal G of the drive module 110 are reset to the same potential at the same time, which is beneficial to the stable operation of the drive module 110 after reset. The start time of the first pulse pulse11 of the first scan signal S1 is earlier than the start time of the invalid level of the light emission control signal EM, which ensures that the reset module 140 and the compensation module 120 are turned on before the light emission control module 130 is turned off, so that the transmission path of the first reset voltage Vref1 is fully established before the light emission control module 130 is turned off, avoiding insufficient reset due to path establishment delay.

[0074] The start time of the second pulse 22 of the second scan signal S2 is later than the start time of the invalid level of the light emission control signal EM, and the end time of the second pulse 22 of the second scan signal S2 is earlier than the end time of the invalid level of the light emission control signal EM. This timing ensures that the threshold voltage compensation and data writing stage t3 is entirely within the time window when the light emission control module 130 is turned off. If the light emission control module 130 is still conducting during the threshold voltage compensation and data writing stage t3, the path between the second terminal D of the drive module 110 and the first terminal of the light emission device D1 is unobstructed, and some current will flow into the light emission device D1 through the light emission control module 130, causing two adverse consequences: first, the light emission device D1 is accidentally lit during the non-light emission stage, affecting the display quality; second, the current flowing into the light emission device D1 diverts the current used for compensation, resulting in a decrease in compensation accuracy, and the control terminal G of the drive module 110 cannot accurately reach Vdata+Vth. By limiting the entire duration of the second pulse pulse 22 of the second scan signal S2 within the window when the light emission control signal EM is at an invalid level (i.e., the light emission control module 130 is turned off), it is ensured that the light emission control module 130 remains in the off state during the threshold voltage compensation and data writing stage t3, completely cutting off the path between the second terminal D of the drive module 110 and the light emission device D1, so that all current is used for charging and discharging the control terminal G, thus ensuring the compensation accuracy.

[0075] The start time of the second pulse pulse12 of the first scan signal S1 is later than the end time of the invalid level of the light emission control signal EM. This timing relationship means that the second turn-on of the reset module 140 begins only after the light emission control module 130 has been turned on again. This setting ensures that at the start of the second reset phase t4, the light emission control module 130 has been turned on before the reset module 140, so that the second reset voltage Vref2 can be smoothly transmitted to the first terminal of the light-emitting device D1 via the light emission control module 130, ensuring the reliable execution of the secondary reset function.

[0076] In some embodiments, the conduction duration of the first pulse pulse11 of the first scan signal S1 and the first pulse pulse21 of the second scan signal S2 are both greater than the duration of the first reset stage t1. That is, after the first reset stage t1, the first pulse pulse11 of the first scan signal S1 and the first pulse pulse21 of the second scan signal S2 continue to maintain an effective level and extend into subsequent stages. Specifically, the first pulse pulse21 of the second scan signal S2 becomes inactive before the first pulse pulse11 of the first scan signal S1, causing the compensation module 120 to turn off first, while the reset module 140 remains on, thereby extending the reset time of the second terminal D of the drive module 110. Through the above settings, it is ensured that the reset module 140 and the compensation module 120 remain on throughout the first reset stage t1, achieving a sufficient reset of the second terminal D of the drive module 110, the control terminal G, and the first terminal of the light-emitting device D1.

[0077] Optionally, the compensation module 120 and the light emission control module 130 are further configured to turn off during the threshold voltage characteristic adjustment phase t2, and the reset module 140 is further configured to turn on in response to the first pulse pulse11 of the first scan signal S1 during the threshold voltage characteristic adjustment phase t2, transmitting the first reset voltage Vref1 or the third reset voltage Vref3 on the reset signal line AC_Vref to the first terminal of the drive module 110; the third reset voltage is greater than or equal to 0. Within one frame, the threshold voltage characteristic adjustment phase t2 is located between the first reset phase t1 and the threshold voltage compensation and data writing phase t3.

[0078] Specifically, such as Figure 6 As shown, the reset signal transmitted on the reset signal line AC_Vref includes three voltages: a first reset voltage Vref1, a second reset voltage Vref2, and a third reset voltage Vref3, where Vref1 ≤ Vref2 ≤ 0V ≤ Vref3. Specifically, the first reset voltage Vref1 is a low-level reset voltage, used to reset the second terminal D of the driving module 110, the control terminal G, and the first terminal of the light-emitting device D1 during the first reset phase t1; the second reset voltage Vref2 is a non-positive medium-level voltage, used to perform a secondary reset on the first terminal of the light-emitting device D1 during the second reset phase t4 to improve the brightness of the first frame; and the third reset voltage Vref3 is a high-level voltage, used to provide a higher reset potential during the threshold voltage characteristic adjustment phase t2.

[0079] Optionally, during the threshold voltage characteristic adjustment stage t2, the first pulse 11 of the first scan signal S1 remains high, and the reset module 140 remains on in response to the first pulse 11 of the first scan signal S1, transmitting the third reset voltage Vref3 on the reset signal line AC_Vref to the second terminal D of the drive module 110. Simultaneously, the voltage on the first power line L1 is in a floating state. At this time, because the reset module 140 is on, the third reset voltage Vref3 is written to the second terminal D and the first terminal S of the drive module 110, while the control terminal G of the drive module 110 maintains the first reset voltage Vref1 reset in the first reset stage t1, making the gate-source voltage VGS = VG - VS = Vref1 - Vref3 of the drive module 110. Since Vref1 is less than 0 and Vref3 is greater than or equal to 0, Vref1-Vref3 is a negative voltage. This negative voltage can effectively adjust the threshold voltage of the driving module 110, so that the threshold voltage is restored to the initial state, thereby improving the display effects such as afterimages, first frame, and brightness uniformity, and thus ensuring the uniformity of subsequent displays.

[0080] Figure 8 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used... Figure 2 The pixel circuit shown. (Reference) Figure 2 and Figure 8 Within one frame, the start time of the first pulse 11 of the first scan signal S1 is earlier than the start time of the invalid level of the light emission control signal EM, and the end time of the first pulse 11 of the first scan signal S1 is earlier than the end time of the invalid level of the light emission control signal EM, but later than the end time of the second pulse 22 of the second scan signal S2. The start time of the second pulse 12 of the first scan signal S1 is later than the end time of the invalid level of the light emission control signal EM.

[0081] Specifically, with Figure 3 Compared to the driving timing shown, Figure 8 In the driving timing shown, the pulse width of the first pulse pulse11 of the first scan signal S1 is longer, that is, the end time of the first pulse pulse11 of the first scan signal S1 is later than the end time of the second pulse pulse22 of the second scan signal S2. This allows the reset module 140 to remain on for a period of time after the compensation module 120 is turned off, continuously clamping the first end of the light-emitting device D1 to the first reset voltage Vref1. This helps to stabilize the potential of the first end of the light-emitting device D1 and ensures that the first end of the light-emitting device D1 is at a known and stable initial potential before the start of the second reset stage t4, thereby improving the secondary reset effect and the brightness performance of the first frame.

[0082] In embodiments of the present invention, such as Figure 3 , Figure 5 , Figure 6 and Figure 8 As shown, the second reset phase t4 begins after the end of the second pulse pulse 22 of the second scan signal S2 of the last row pixel circuit, and the duration of the second reset phase t4 is equal to the conduction duration of the second pulse pulse 12 of the first scan signal S1.

[0083] Figure 9 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used... Figure 2 The pixel circuit shown. (Reference) Figure 2 and Figure 9 The start time of the effective level of the first scan signal S1 is earlier than the start time of the invalid level of the light emission control signal EM, and the end time of the effective level of the first scan signal S1 is later than the end time of the invalid level of the light emission control signal EM.

[0084] Specifically, such as Figure 9 As shown, within one frame, the first scan signal S1 contains only one wide pulse. The start time of the effective level of this wide pulse is earlier than the start time of the ineffective level of the light emission control signal EM, and the end time of the effective level of this wide pulse is later than the end time of the ineffective level of the light emission control signal EM. That is to say, the wide pulse of the first scan signal S1 spans the first reset stage t1, the threshold voltage compensation and data writing stage t3, and the second reset stage t4, so that the reset module 140 remains on throughout the above three stages.

[0085] and Figure 3 and Figure 6 Compared to the scheme where the first scan signal S1 in the driving timing shown contains two time-division pulses, Figure 9 In the illustrated scheme, the first scan signal S1 contains only a single wide pulse, which is sufficient to control the reset module 140 to remain on throughout the first reset phase t1, the threshold voltage compensation and data writing phase t3, and the second reset phase t4. By reusing the same wide pulse of the first scan signal S1, the reset module 140 continuously maintains a low-impedance connection between the first terminal of the light-emitting device D1 and the reset signal line AC_Vref in all three phases. This ensures that the first terminal of the light-emitting device D1 is continuously clamped by the reset signal line AC_Vref throughout the entire first phase t1, the threshold voltage compensation and data writing phase t3, and the second reset phase t4. This helps stabilize the potential of the first terminal of the light-emitting device D1, suppresses potential fluctuations at the first terminal of the light-emitting device D1 caused by coupling noise or leakage current, and improves the secondary reset effect and the brightness performance of the first frame.

[0086] Optionally, the light emission control module 130 is further configured to turn off during the threshold voltage characteristic adjustment phase t2 and the threshold voltage and data writing phase, and the reset module 140 is further configured to turn on during the threshold voltage characteristic adjustment phase t2 and the threshold voltage compensation and data writing phase t3, transmitting the second reset voltage Vref2 to the first terminal of the light emission device D1; within one frame, the threshold voltage characteristic adjustment phase t2 is located between the first reset phase t1 and the threshold voltage compensation and data writing phase t3.

[0087] Specifically, in Figure 9 In the timing configuration shown, the reset module 140 remains on throughout the threshold voltage characteristic adjustment phase t2 and the threshold voltage compensation and data writing phase t3, continuously transmitting the second reset voltage Vref2 on the reset signal line AC_Vref to the first terminal of the light-emitting device D1. Since the light-emitting control module 130 is in the off state during both the threshold voltage characteristic adjustment phase t2 and the threshold voltage compensation and data writing phase t3, the path between the second terminal D of the drive module 110 and the first terminal of the light-emitting device D1 is cut off. Therefore, the second reset voltage Vref2 is only used to continuously clamp the first terminal of the light-emitting device D1 to Vref2, thereby stabilizing the potential of the first terminal of the light-emitting device D1, without interfering with the second terminal D and the control terminal G of the drive module 110. This configuration effectively suppresses potential fluctuations at the first terminal of the light-emitting device D1 caused by parasitic capacitance coupling, preventing the potential at the first terminal of the light-emitting device D1 from being coupled up due to voltage jumps in surrounding signal lines during threshold compensation and data writing. This prevents the light-emitting device from erroneously emitting light due to excessively high anode potential during the non-light-emitting phase. At the same time, it ensures that the first terminal of the light-emitting device D1 has a stable and consistent initial potential during the subsequent second reset phase t4 and light-emitting phase t5, which is beneficial for improving the brightness performance of the first frame.

[0088] Figure 10 This is a driving timing waveform diagram of another pixel circuit provided in an embodiment of the present invention. This driving timing can be used... Figure 2 The pixel circuit shown. (Reference) Figure 2 and Figure 10 Optionally, the second reset stage t4 is located between the threshold voltage characteristic adjustment stage t2 and the threshold voltage compensation and data writing stage t3. This timing arrangement shortens the time interval between the end of the threshold voltage compensation and data writing stage t3 and the light emission stage t5, which helps to reduce charge leakage at the control terminal G of the drive module 110 and improve display uniformity.

[0089] Optionally, the threshold voltage compensation and data writing phase t3 and the second reset phase t4 at least partially overlap.

[0090] Specifically, during the overlapping period, the reset module 140 is turned on, transmitting the second reset voltage Vref2 to the first terminal of the light-emitting device D1, performing a secondary reset on the first terminal of the light-emitting device D1; simultaneously, the compensation module 120 is turned on, connecting the second terminal D of the driving module 110 to the control terminal G, and the first power line L1 transmits the data voltage Vdata to the first terminal S of the driving module 110, performing threshold voltage compensation on the driving module 110. Since the light-emitting control module 130 is in the off state during the threshold voltage compensation and data writing stage t3, the path between the second terminal D of the driving module 110 and the first terminal of the light-emitting device D1 is cut off. Therefore, the reset operation of the reset module 140 and the compensation operation of the compensation module 120 are executed on two independent paths, without interfering with each other. By at least partially overlapping the second reset phase t4 with the threshold voltage compensation and data writing phase t3, the secondary reset operation of the second reset phase t4 and the threshold compensation operation of the threshold voltage compensation and data writing phase t3 are executed in parallel. There is no need to allocate a complete time period that does not overlap with other phases separately for the second reset phase t4, thereby shortening the total duration of a frame and facilitating a higher refresh rate.

[0091] refer to Figure 1 and Figure 2 The pixel circuit also includes a storage module 150, which is connected between the reference signal line L3 and the control terminal G of the drive module 110. The reference signal line L3 can be configured to a first power supply voltage VDD.

[0092] Figure 11 This is a schematic diagram of another pixel circuit provided in an embodiment of the present invention. Figure 12 This is a schematic diagram of another pixel circuit structure provided in an embodiment of the present invention. For example... Figure 11 and Figure 12 As shown, the storage module 150 includes a first capacitor C1, the first terminal of the first capacitor C1 is connected to the reference signal line L3, and the second terminal of the first capacitor C1 is connected to the control terminal G of the drive module 110.

[0093] The driving module 110 includes a first transistor M1, the first electrode of the first transistor M1 serves as the first terminal S of the driving module 110, the second electrode of the first transistor M1 serves as the second terminal D of the driving module 110, and the gate of the first transistor M1 serves as the control terminal G of the driving module 110.

[0094] The compensation module 120 includes a second transistor M2, the gate of the second transistor M2 is connected to the second scan line GL2, the first terminal of the second transistor M2 is connected to the gate of the first transistor, and the second terminal of the second transistor M2 is connected to the second terminal of the first transistor M1. The reset module 140 includes a third transistor M3, the gate of the third transistor M3 is connected to the first scan line GL1, the first terminal of the third transistor M3 is connected to the reset signal line AC_Vref, and the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1 or the first terminal of the light-emitting device D1.

[0095] The light emission control module 130 includes a fourth transistor M4, the gate of the fourth transistor M4 is connected to the light emission control line GL3, the first terminal of the fourth transistor M4 is connected to the second terminal of the first transistor M1, and the second terminal of the fourth transistor M4 is connected to the first terminal of the light emission device D1.

[0096] Specifically, such as Figure 11 As shown, the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1, meaning that the reset module 140 indirectly resets the first terminal of the light-emitting device D1 through the fourth transistor M4. In this connection configuration, the reset voltage is transmitted via the third transistor M3 to the second terminal of the first transistor M1, and then via the fourth transistor M4 to the first terminal of the light-emitting device D1.

[0097] like Figure 12 As shown, the second terminal of the third transistor M3 is connected to the first terminal of the light-emitting device D1, meaning the reset module 140 directly resets the first terminal of the light-emitting device D1. In this connection method, the reset voltage is directly transmitted to the first terminal of the light-emitting device D1 via the third transistor M3, and then transmitted in reverse via the fourth transistor M4 to the second terminal of the first transistor M1. Both connection methods can achieve synchronous reset of the second terminal D of the drive module 110, the control terminal G, and the first terminal of the light-emitting device D1. The only difference lies in the different transmission paths of the reset voltage, which can be flexibly selected according to layout design requirements.

[0098] Figure 3 and Figure 5 The driving timing shown is also applicable to Figure 11 and Figure 12 The pixel circuit structure shown. Figure 6 The driving timing shown is applicable to Figure 11 The pixel circuit structure shown. Figure 8 , Figure 9 and Figure 10 The driving timing shown is applicable to Figure 12 The pixel circuit structure shown.

[0099] Optionally, the first transistor M1 and the fourth transistor M4 are both P-type transistors, and the second transistor M2 and the third transistor M3 are both N-type transistors. For example, the first transistor M1 and the fourth transistor M4 can be low-temperature polysilicon (LTPS) thin-film transistors, which have high carrier mobility and are suitable for driving transistors and light-emitting control transistors, providing sufficient drive current and fast switching response. The second transistor M2 and the third transistor M3 can be oxide thin-film transistors (e.g., IGZO TFTs), which have extremely low leakage current and are suitable for compensation transistors and reset transistors, effectively maintaining the voltage stability of the control terminal G of the driving module 110 and preventing compensation voltage drift caused by charge leakage. The combination of P-type LTPS transistors and N-type oxide transistors fully leverages their respective advantages, ensuring both the driving capability and response speed of the pixel circuit while reducing leakage risk and improving display quality. Simultaneously, the different conduction level characteristics of P-channel and N-channel transistors allow for more flexible timing design of the control signals, simplifying the driving timing.

[0100] When the second transistor M2 and the third transistor M3 are oxide thin-film transistors, they can be either three-terminal or four-terminal devices. For example... Figure 11 As shown, the second transistor M2 and the third transistor M3 are three-terminal devices. The gate of the second transistor M2 serves as the control terminal of the compensation module 120 and is connected to the second scan line GL2. The first terminal of the second transistor M2 is connected to the second terminal D of the drive module 110, and the second terminal of the second transistor M2 is connected to the control terminal G of the drive module 110. The gate of the third transistor M3 serves as the control terminal of the reset module 140 and is connected to the first scan line GL1. The first terminal of the third transistor M3 is connected to the reset signal line AC_Vref, and the second terminal of the third transistor M3 is connected to the second terminal of the first transistor M1.

[0101] Optionally, such as Figure 12As shown, the second transistor M2 is a four-terminal device with a first gate and a second gate. The first gate of the second transistor M2 is connected to the second scan line GL2, and the second gate of the second transistor M2 is connected to the reference signal line L3. The third transistor M3 is also a four-terminal device with a first gate and a second gate. The first gate of the third transistor M3 is connected to the first scan line GL1, and the second gate of the third transistor M3 is connected to the reset signal line AC_Vref. By connecting the second gate of the second transistor M2 to the reference signal line L3, the threshold voltage of the second transistor M2 can be adjusted using the stable voltage on the reference signal line L3, further reducing the leakage current of the compensation module 120 and improving the accuracy and stability of the threshold voltage compensation. By connecting the second gate of the third transistor M3 to the reset signal line AC_Vref, the threshold voltage of the third transistor M3 can be adjusted using the voltage on the reset signal line AC_Vref, further reducing the leakage current of the reset module 140, avoiding potential fluctuations at the first terminal of the light-emitting device D1 due to leakage current during the non-reset phase, and improving display quality. Furthermore, the above connection method of the second gate eliminates the need for additional control signal lines, which helps to simplify signal routing and save layout space.

[0102] refer to Figure 3 and Figure 11 Within a single frame, the pixel circuit's operation includes, sequentially, a first reset stage t1, a threshold voltage characteristic adjustment stage t2, a threshold voltage compensation and data writing stage t3, a second reset stage t4, and a light emission stage t5. The following is a combination of... Figure 11 The pixel circuit structure shown provides a detailed explanation of the working process at each stage. Specifically, the first transistor M1 serves as the driving module 110, the second transistor M2 as the compensation module 120, the third transistor M3 as the reset module 140, and the fourth transistor M4 as the light-emitting control module 130.

[0103] During the first reset phase t1, the first scan signal S1 provides a first pulse pulse11 (high-level pulse), the second scan signal S2 provides a first pulse pulse21 (high-level pulse), and the light emission control signal EM is low. At this time, the third transistor M3 turns on in response to the first pulse pulse11 of the first scan signal S1, the second transistor M2 turns on in response to the first pulse pulse21 of the second scan signal S2, and the fourth transistor M4 turns on in response to the light emission control signal EM. The first power line L1 is in a floating state. The third transistor M3 transmits the first reset voltage Vref1 on the reset signal line AC_Vref to the second terminal of the first transistor M1; since the fourth transistor M4 is turned on, the first reset voltage Vref1 is further transmitted to the first terminal of the light-emitting device D1 via the fourth transistor M4, so that the first terminal of the light-emitting device D1 is reset to the first reset voltage Vref1; since the second transistor M2 is turned on, the first reset voltage Vref1 is also transmitted to the gate G of the first transistor M1 via the second transistor M2, so that the gate G of the first transistor M1 is reset to the first reset voltage Vref1. As a result, the second terminal of the first transistor M1, the gate G of the first transistor M1, and the first terminal of the light-emitting device D1 are simultaneously reset to the first reset voltage Vref1, effectively eliminating the residual charge of the previous frame and solving the ghosting problem.

[0104] During the threshold voltage characteristic adjustment phase t2, the first scan signal S1 is low, and the third transistor M3 is turned off; the second scan signal S2 is low, and the second transistor M2 is turned off; the light emission control signal EM is high, and the fourth transistor M4 is turned off. The first power supply line L1 transmits the first power supply voltage VDD to the first terminal of the first transistor M1. At this time, the gate G of the first transistor M1 is in a floating state, and its potential is maintained at the first reset voltage Vref1 at the end of the first reset phase t1; the first terminal of the first transistor M1 is configured with the first power supply voltage VDD, and the gate-source voltage VGS of the first transistor M1 = VG - VS = Vref1 - VDD.

[0105] During the threshold voltage compensation and data writing stage t3, the first scan signal S1 is low, and the third transistor M3 is off; the second scan signal S2 provides the second pulse pulse22, and the second transistor M2 is turned on; the light emission control signal EM is high, and the fourth transistor M4 is off. The fifth transistor M5 in the gating circuit is turned on, and the first power line L1 transmits the data voltage Vdata to the first terminal of the first transistor M1. After the second transistor M2 is turned on, it connects the second terminal of the first transistor M1 to the gate G of the first transistor M1. At this time, since the gate G of the first transistor M1 is in a floating state during the threshold voltage characteristic adjustment stage t2 and is maintained at the first reset voltage Vref1, the current flowing through the first transistor M1 charges the gate G of the first transistor M1 through the second transistor M2 until the voltage of the gate G of the first transistor M1 is equal to the sum of the data voltage Vdata and the threshold voltage of the first transistor M1 (i.e., VG = Vdata + Vth). The compensation process ends, and the threshold voltage information of the first transistor M1 is stored in the gate G of the first transistor M1 through the first capacitor C1. Simultaneously, the data voltage Vdata is written to the gate G of the first transistor M1. Since the fourth transistor M4 is turned off, the path between the second terminal of the first transistor M1 and the first terminal of the light-emitting device D1 is cut off, and all current is used to charge and discharge the gate G, ensuring compensation accuracy.

[0106] In the second reset phase t4, the first scan signal S1 provides the second pulse pulse12, and the third transistor M3 is turned on; the second scan signal S2 is low, and the second transistor M2 is turned off; the light emission control signal EM is low, and the fourth transistor M4 is turned on. The third transistor M3 transmits the second reset voltage Vref2 on the reset signal line AC_Vref to the second terminal of the first transistor M1, and further transmits it to the first terminal of the light-emitting device D1 via the fourth transistor M4, so that the first terminal of the light-emitting device D1 is reset to the second reset voltage Vref2. The first reset voltage Vref1 is less than or equal to the second reset voltage Vref2, and the second reset voltage Vref2 is less than or equal to 0. This ensures that in the second reset phase t4, the first terminal of the light-emitting device D1 is reset to a voltage not lower than the first reset voltage Vref1 and not positive. This helps prevent the light-emitting device D1 from erroneously emitting light due to excessive voltage before subsequent light emission, and also improves the problem of low brightness in the first frame. The second transistor M2 is turned off to ensure that the second reset voltage Vref2 is not transmitted to the gate G of the first transistor M1, avoiding interference with the already written compensation voltage.

[0107] During the light-emitting stage t5, the first scan signal S1 is low, and the third transistor M3 is off; the second scan signal S2 is low, and the second transistor M2 is off; the light-emitting control signal EM is low, and the fourth transistor M4 is on. The sixth transistor M6 in the gating circuit is on, and the first power supply line L1 transmits the first power supply voltage VDD to the first terminal of the first transistor M1. The first transistor M1 generates a drive current based on the voltage at its gate G and the first power supply voltage VDD received at its first terminal. At this time, the difference between the gate-source voltage VGS and the threshold voltage Vth of the first transistor M1 is: VGS-Vth=(Vdata+Vth-VDD)-Vth=Vdata-VDD; The drive current I_oled generated by the first transistor M1 is: I_oled=(1 / 2)×μ×Cox×(W / L)×(VGS-Vth) 2 ; That is: I_oled=(1 / 2)×μ×Cox×(W / L)×(Vdata-VDD) 2 ; Where μ is the carrier mobility, Cox is the gate oxide capacitance per unit area of ​​the first transistor M1, and W / L is the channel width-to-length ratio of the first transistor M1.

[0108] The driving current is transmitted to the first terminal of the light-emitting device D1 via the conducting fourth transistor M4, driving the light-emitting device D1 to emit light. As can be seen from the above formula, the driving current I_oled is independent of the threshold voltage Vth of the first transistor M1, thereby achieving compensation for the threshold voltage of the first transistor M1, ensuring the consistency of the driving current between different pixel circuits, and improving display uniformity.

[0109] Based on the same inventive concept, embodiments of the present invention also provide a display panel. Figure 13 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention. Figure 13 As shown, the display panel includes any of the pixel circuits 10 provided in the above embodiments. Therefore, this display panel also possesses the same beneficial effects as the pixel circuits 10 described in any of the above embodiments. The similarities can be understood by referring to the explanation of the pixel circuits 10 above, and will not be repeated here.

[0110] like Figure 13As shown, the display panel also includes multiple gating circuits 20 and multiple first power lines L1. Each gating circuit 20 includes a data voltage terminal, a first power supply voltage terminal, and an output terminal. The output terminal of the gating circuit 20 is connected to at least one column of pixel circuits 10. The data voltage terminal is connected to a data voltage Vdata, and the first power supply voltage terminal is connected to a first power supply voltage VDD. The gating circuit 20 is used to transmit the data voltage Vdata to the first power line L1 in response to the effective level of the first control signal SW1, and to transmit the first power supply voltage VDD to the first power line L1 in response to the effective level of the second control signal SW2. Within one frame, the first control signal SW1 and the second control signal SW2 are at effective levels at different times.

[0111] Specifically, the display panel includes a display area AA and a non-display area NAA. The output of the gating circuit 20 is connected to the first terminal S of the driving module 110 of the pixel circuit 10 via the first power line L1. The gating circuit 20 is used to transmit data voltage Vdata or first power supply voltage VDD to the first power line L1 in a time-division multiplexing manner, thereby realizing the time-division multiplexing function of the first power line L1.

[0112] In some embodiments, the display panel includes multiple gating circuits 20 and multiple first power lines L1. The gating circuits 20 are located in the non-display area NAA of the display panel, and the first power lines L1 are located in the display area AA. The output of the gating circuit 20 is connected to the first terminal S of the driving module 110 of each row of pixel circuits in a column of pixel circuits 10 via a first power line L1. During the threshold voltage compensation and data writing stage, the gating circuit 20 transmits the data voltage Vdata to the first power line L1, and the first terminal S of the driving module 110 of each pixel circuit in the column of pixel circuits 10 simultaneously receives the data voltage Vdata. During the light emission stage, the gating circuit 20 transmits the first power supply voltage VDD to the first power line L1, and the first terminal S of the driving module 110 of each pixel circuit in the column of pixel circuits 10 simultaneously receives the first power supply voltage VDD. This method results in neat wiring and is suitable for display panels with conventional resolutions.

[0113] In other embodiments, a gating circuit 20 connects two or more columns of pixel circuits 10. In this configuration, the output of the gating circuit 20 is connected to multiple first power lines L1, each first power line L1 corresponding to one column of pixel circuits 10. The gating circuit 20 simultaneously transmits the same voltage to the multiple first power lines L1, causing the first terminal S of the driving module 110 of the multiple columns of pixel circuits 10 to simultaneously receive either the data voltage Vdata or the first power supply voltage VDD. This method reduces the number of gating circuits 20, which is beneficial for reducing bezel size and is suitable for narrow bezel designs.

[0114] In other embodiments, two or more gating circuits 20 are connected to the same column of pixel circuits 10. In this configuration, the first power line L1 of the same column of pixel circuits 10 is connected to the output of at least two gating circuits 20, and the multiple gating circuits 20 provide data voltage Vdata or first power supply voltage VDD to the column of pixel circuits 10 in a time-sharing or joint manner. This approach can improve the reliability of voltage transmission, prevent the failure of a single gating circuit 20 from causing the entire column of pixel circuits 10 to fail, and reduce the load on each gating circuit 20, thereby improving the stability of voltage transmission. This method is suitable for large-size or high-resolution display panels.

[0115] Figure 14 This is a schematic diagram of the connection structure between a gating circuit and a pixel circuit provided in an embodiment of the present invention. Figure 14 As shown, the selection circuit 20 includes a first switching unit and a second switching unit.

[0116] The first switching unit is connected between the first power line L1 and the data voltage terminal, and is used to transmit the data voltage Vdata to the first power line L1 in response to the effective level of the first control signal.

[0117] The second switching unit is connected between the first power line L1 and the first power supply voltage terminal, and is used to transmit the first power supply voltage VDD to the first power line L1 in response to the effective level of the second control signal SW2.

[0118] Specifically, when the first control signal SW1 is at an active level (e.g., low level), the first switching unit is turned on, and the data voltage Vdata connected to the data voltage terminal is transmitted to the first power line L1 via the first switching unit, and then to the first terminal S of the driving module 110 in the pixel circuit 10. When the first control signal SW1 is at an inactive level (e.g., high level), the first switching unit is turned off, and the path between the data voltage Vdata and the first power line L1 is cut off.

[0119] When the second control signal SW2 is active, the second switching unit is turned on, and the first power supply voltage VDD connected to the first power supply voltage terminal is transmitted to the first power line L1 via the second switching unit, and then to the first terminal S of the driving module 110 in the pixel circuit 10. When the second control signal SW2 is inactive, the second switching unit is turned off, and the path between the first power supply voltage VDD and the first power line L1 is cut off. Within one frame, the first control signal SW1 and the second control signal SW2 are active at different times, thereby realizing the time-division multiplexing of the data voltage Vdata and the first power supply voltage VDD on the first power line L1.

[0120] Optionally, within one frame, the first control signal SW1 is at an active level during the threshold voltage compensation and data writing phase, and the second control signal SW2 is at an active level at least during the light emission phase.

[0121] Optionally, the first switching unit includes a fifth transistor M5, and the second switching unit includes a sixth transistor M6. The gate of the fifth transistor M5 is connected to a first control signal SW1, the first terminal of the fifth transistor M5 is connected to a data voltage terminal, and the second terminal of the fifth transistor M5 is connected to a first power supply line L1. The gate of the sixth transistor M6 is connected to a second control signal SW2, the first terminal of the sixth transistor M6 is connected to a first power supply voltage terminal, and the second terminal of the sixth transistor M6 is connected to the first power supply line L1.

[0122] Specifically, the fifth transistor M5 and the sixth transistor M6 can be either P-type or N-type transistors, and the specific type can be selected according to the driving timing requirements. For example, both the fifth transistor M5 and the sixth transistor M6 can be P-type transistors, and the low level of the first control signal SW1 and the second control signal SW2 is the active level. By placing the gating circuit 20 in the non-display area of ​​the display panel, the pixel circuit 10 itself does not need to have a data voltage and power supply voltage selection switch, further reducing the number of transistors in the pixel circuit 10, which is beneficial for achieving ultra-high PPI display layout.

[0123] Figure 15 This is a driving timing diagram of a display panel provided in an embodiment of the present invention. Figure 15 The driving timing shown can be used Figure 1 , Figure 2 , Figure 11 and Figure 12 The pixel circuit shown. Figure 15 The timing waveforms of the control signals of each module within the pixel circuit 10 (i.e., the first scan signal S1, the second scan signal S2, and the light emission control signal EM) and the control signals of the gating circuit 20 (i.e., the first control signal SW1 and the second control signal SW2) within one frame are shown. (Reference) Figure 1 , Figure 2 , Figure 11 , Figure 12 and Figure 15 Within a single frame, the pixel circuit's operation includes, sequentially, a first reset phase t1, a threshold voltage compensation and data writing phase t3, a second reset phase t4, and an emission phase t5. The signal level states for each phase are as follows: During the first reset phase t1, the first scan signal S1 provides the first pulse pulse11, the second scan signal S2 provides the first pulse pulse21, and the light emission control signal EM is at a low level. The first control signal SW1 and the second control signal SW2 are both at a high level, the fifth transistor M5 and the sixth transistor M6 are both turned off, and the first power line L1 is in a floating state.

[0124] During the threshold voltage characteristic adjustment stage t2, the first scan signal S1 is low, and the third transistor M3 is off; the second scan signal S2 is low, and the second transistor M2 is off; the light emission control signal EM is high, and the fourth transistor M4 is off. The first control signal SW1 is high, and the fifth transistor M5 is off; the second control signal SW2 is low, and the sixth transistor M6 is on, and the first power supply line L1 transmits the first power supply voltage VDD to the first terminal of the first transistor M1.

[0125] During the threshold voltage compensation and data writing stage t3, the first scan signal S1 is low, the second scan signal S2 provides the second pulse pulse22, and the light emission control signal EM is high. The first control signal SW1 is low, controlling the fifth transistor M5 to turn on and transmit the data voltage Vdata to the first power line L1; the second control signal SW2 is high (invalid level), and the sixth transistor M6 is turned off.

[0126] During the second reset phase t4, the first scan signal S1 provides the second pulse pulse12, the second scan signal S2 is at a low level, and the light emission control signal EM is at a low level. The first control signal SW1 and the second control signal SW2 are both at a high level, the fifth transistor M5 and the sixth transistor M6 are both turned off, and the first power line L1 is in a floating state.

[0127] During the light-emitting stage t5, the first scan signal S1 is low, the second scan signal S2 is low, and the light-emitting control signal EM is low. The first control signal SW1 is high, and the fifth transistor M5 is turned off; the second control signal SW2 is low, controlling the sixth transistor M6 to turn on, transmitting the first power supply voltage VDD to the first power supply line L1.

[0128] Figure 15 In the driving timing shown, the timing waveforms of the first control signal SW1 and the second control signal SW2 within one frame can also be compared with... Figure 8 , Figure 9 and Figure 10 The pixel circuit shown is used in conjunction with the internal signal timing. Specifically, Figure 8 , Figure 9 and Figure 10The timing waveforms of the control signals of each module within the pixel circuit 10 are shown under different operating modes, but the timing waveforms of the control signals of the gating circuit 20 are not shown. In practical applications, [the following will be used]. Figure 15 The timing waveforms of the first control signal SW1 and the second control signal SW2 shown are superimposed on... Figure 8 , Figure 9 or Figure 10 The driving timing of the display panel under the corresponding pixel circuit structure and working mode can be obtained from the signal timing waveform inside the pixel circuit shown.

[0129] Specifically, Figure 8 The driving timing shown is Figure 15 When the control signals of the gating circuit shown are combined, the signal level states at each stage are similar to those described above, with the only difference being: Figure 8 The end time of the first pulse pulse 11 of the first scan signal S1 is later than the end time of the second pulse pulse 22 of the second scan signal S2 (i.e., the pulse width of the first pulse pulse 11 of S1 is longer), so that the reset module 140 remains on for a period of time after the compensation module 120 is turned off, continuously clamping the first terminal of the light-emitting device D1 to the first reset voltage Vref1. The level states of the second scan signal S2, the light-emitting control signal EM, the first control signal SW1 and the second control signal SW2 are all the same as... Figure 15 Maintain consistency.

[0130] Similarly, Figure 9 The driving timing shown is Figure 15 When the control signals of the selection circuit shown are combined, the signal level states of each stage are similar to those described above. The only difference is that the wide pulse of the first scan signal S1 keeps the third transistor M3 conducting throughout the first reset stage t1, the threshold voltage compensation and data writing stage t3, and the second reset stage t4. The level states of the second scan signal S2, the light emission control signal EM, the first control signal SW1, and the second control signal SW2 are similar to those described above. Figure 15 Maintain consistency.

[0131] Figure 10 The driving timing shown is Figure 15 When the control signals of the gating circuit shown are combined, the signal level states at each stage are similar to those described above, with the difference being: Figure 10In the driving timing shown, the second reset phase t4 is located after the threshold voltage characteristic adjustment phase t2, and at least partially overlaps in time with the threshold voltage compensation and data writing phase t3. That is, after the threshold voltage characteristic adjustment phase t2 ends, the second reset phase t4 and the threshold voltage compensation and data writing phase t3 begin simultaneously. Specifically, the second pulse pulse 12 of the first scan signal S1 and the second pulse pulse 22 of the second scan signal S2 overlap in time. The reset module 140 and the compensation module 120 are simultaneously turned on during the overlapping period, respectively performing the secondary reset of the first terminal of the light-emitting device D1 and the threshold voltage compensation and data writing operation of the driving module 110, without interfering with each other. The specific level states of each control signal at different stages can be referred to... Figure 15 The level configuration for the corresponding stage is not described in detail here.

[0132] In conclusion, Figure 15 The timing waveforms of the first control signal SW1 and the second control signal SW2 shown can be compared with... Figure 8 , Figure 9 or Figure 10 The timing waveforms of any pixel circuit's internal signals are combined to form the driving timing sequence of the display panel. Based on the above description, those skilled in the art can, without any inventive effort, [achieve / convert / etc.]. Figure 15 The timing of the control signal for the gating circuit shown is applied to Figure 8 , Figure 9 or Figure 10 The pixel circuit shown contains internal signal timing information.

[0133] Figure 16 This is a driving timing diagram for another display panel provided in an embodiment of the present invention. Figure 16 The driving timing shown can be used Figure 1 and Figure 11 The pixel circuit shown, Figure 16 Is Figure 6 The timing waveform of the control signal from the gating circuit 20 is superimposed on the internal signal timing of the pixel circuit shown. Figure 15 The difference in the driving timing shown is that, in Figure 16 In the driving timing shown, during the threshold voltage characteristic adjustment stage t2, the first control signal SW1 and the second control signal SW2 are both at invalid levels, the fifth transistor M5 and the sixth transistor M6 are both turned off, and the first power line L1 is in a floating state.

[0134] Combination Figure 1 , Figure 6 , Figure 11 and Figure 16Within a single frame, the pixel circuit's operation includes, sequentially, a first reset phase t1, a threshold voltage characteristic adjustment phase t2, a threshold voltage compensation and data writing phase t3, a second reset phase t4, and an emission phase t5. The signal level states for each phase are as follows: In the first reset phase t1, the first scan signal S1 provides the first pulse pulse11, the second scan signal S2 provides the first pulse pulse21, and the light emission control signal EM is low. At this time, the third transistor M3 turns on in response to the high level of the first scan signal S1, the second transistor M2 turns on in response to the high level of the second scan signal S2, and the fourth transistor M4 turns on in response to the low level of the light emission control signal EM. The first control signal SW1 and the second control signal SW2 are both high, the fifth transistor M5 and the sixth transistor M6 are both off, and the first power line L1 is in a floating state. The third transistor M3 transmits the first reset voltage Vref1 on the reset signal line AC_Vref to the second terminal of the first transistor M1; since the fourth transistor M4 is on, the first reset voltage Vref1 is further transmitted to the first terminal of the light-emitting device D1 via the fourth transistor M4; since the second transistor M2 is on, the first reset voltage Vref1 is also transmitted to the gate G of the first transistor M1 via the second transistor M2, realizing the synchronous reset of the three nodes.

[0135] During the threshold voltage characteristic adjustment stage t2, the first scan signal S1 is low, and the third transistor M3 is off; the second scan signal S2 is low, and the second transistor M2 is off; the light emission control signal EM is high, and the fourth transistor M4 is off. The first control signal SW1 is high, and the fifth transistor M5 is off; the second control signal SW2 is high, and the sixth transistor M6 is off, and the first power line L1 is in a floating state. The third reset voltage Vref3 (Vref3≥0) is transmitted on the reset signal line AC_Vref. The first pulse pulse11 of the first scan signal S1 is maintained at a high level, keeping the third transistor M3 on, transmitting the third reset voltage Vref3 to the second terminal of the first transistor M1, and coupling it to the first terminal S through the first transistor M1, raising the potential of the first terminal S of the first transistor M1 to Vref3. The gate G of the first transistor M1 is maintained at the first reset voltage Vref1, and the gate-source voltage VGS=Vref1-Vref3 is a negative voltage, realizing the adjustment of the threshold voltage characteristic of the first transistor M1.

[0136] During the threshold voltage compensation and data writing stage t3, the first scan signal S1 is low, and the third transistor M3 is off; the second scan signal S2 provides the second pulse pulse22, and the second transistor M2 is on; the light emission control signal EM is high, and the fourth transistor M4 is off. The first control signal SW1 is low, controlling the fifth transistor M5 to be on, transmitting the data voltage Vdata to the first power line L1; the second control signal SW2 is high, and the sixth transistor M6 is off. The second transistor M2 connects the second terminal of the first transistor M1 to its gate G, and the current flowing through the first transistor M1 charges the gate G until VG = Vdata + Vth, completing the threshold voltage compensation and data writing.

[0137] During the second reset phase t4, the first scan signal S1 provides the second pulse pulse12, and the third transistor M3 is turned on; the second scan signal S2 is low, and the second transistor M2 is turned off; the light emission control signal EM is low, and the fourth transistor M4 is turned on. The first control signal SW1 and the second control signal SW2 are both high, the fifth transistor M5 and the sixth transistor M6 are both turned off, and the first power line L1 is in a floating state. The third transistor M3 transmits the second reset voltage Vref2 on the reset signal line AC_Vref to the second terminal of the first transistor M1, and then transmits it to the first terminal of the light-emitting device D1 via the fourth transistor M4, so that the first terminal of the light-emitting device D1 is reset to the second reset voltage Vref2.

[0138] During the light-emitting stage t5, the first scan signal S1 is low, and the third transistor M3 is off; the second scan signal S2 is low, and the second transistor M2 is off; the light-emitting control signal EM is low, and the fourth transistor M4 is on. The first control signal SW1 is high, and the fifth transistor M5 is off; the second control signal SW2 is low, controlling the sixth transistor M6 to turn on, transmitting the first power supply voltage VDD to the first power line L1. The first transistor M1 generates a driving current based on the voltage at its gate G and the first power supply voltage VDD received at its first terminal S, driving the light-emitting device D1 to emit light.

[0139] Figure 16 The timing waveforms of the first control signal SW1 and the second control signal SW2 in the driving timing sequence shown can also be compared with... Figure 5 The driving timing shown is used in combination. Figure 5 The driving timing shown is Figure 3 The difference in the driving timing shown is: Figure 5 The driving timing shown does not include the threshold voltage characteristic adjustment stage t2; that is, within one frame, it only includes the first reset stage t1, the threshold voltage compensation and data writing stage t3, the second reset stage t4, and the light emission stage t5, performed sequentially. Figure 16The timing waveforms of the first control signal SW1 and the second control signal SW2 shown are superimposed on... Figure 5 When the internal signal timing of the pixel circuit shown is such that... Figure 5 The threshold voltage characteristic adjustment stage t2 is absent, so it is directly omitted. Figure 16 The level configuration of the first control signal SW1 and the second control signal SW2 corresponding to the threshold voltage characteristic adjustment stage t2 is sufficient. At this time, the second control signal SW2 contains only one effective level pulse in one frame (corresponding to the light emission stage t5), compared to Figure 15 The second control signal SW2 needs to provide effective level pulses in both the threshold voltage characteristic adjustment stage t2 and the light emission stage t5. Figure 16 The first control signal SW1 and the second control signal SW2 and Figure 5 In the combined timing sequence, the second control signal SW2 only requires a single pulse to complete the control, which helps reduce the timing design difficulty and power consumption of the driver IC. The level states of each control signal in the remaining stages are consistent with... Figure 16 Maintain consistency.

[0140] Optionally, the first reset phase t1 of each pixel circuit is performed simultaneously, the threshold voltage characteristic adjustment phase t2 of each pixel circuit is performed simultaneously, the threshold voltage compensation and data writing phase t3 of each row of pixel circuits is performed row by row, the second reset phase t4 of each row of pixel circuits is performed simultaneously, and the light emission phase t5 of each pixel circuit is performed simultaneously. That is, the first reset phase t1 of the pixel circuit is denoted as the first reset phase t1 of the display panel, the threshold voltage characteristic adjustment phase t2 of the pixel circuit is also the threshold voltage characteristic adjustment phase t2 of the display panel, the second reset phase t4 of the pixel circuit is denoted as the second reset phase t4 of the display panel, and the light emission phase t5 of the pixel circuit is also the light emission phase of the display panel. The threshold voltage compensation and data writing phase t3 of the display panel includes the threshold voltage compensation and data writing phase t3 of each row of pixel circuits. Optionally, the start time of the light emission control signal EM of each row of pixel circuits 10 is the same.

[0141] Optionally, multiple pixel circuits 10 are located in the display area AA and arranged in multiple rows of pixel circuit groups. The display panel also includes multiple shift registers and multiple second scan lines GL2. The multiple shift registers are cascaded and located in the non-display area NAA of the display panel. The shift registers are connected to the control terminals of the compensation modules 120 of the multiple pixel circuits 10 in a row of pixel circuit groups through the corresponding second scan lines GL2. The shift registers are configured to generate a second scan signal S2. Optionally, the second scan signals S2 generated by the multiple shift registers simultaneously generate a first pulse 21 and then sequentially generate a second pulse 22.

[0142] Specifically, the i-th row of pixel circuits is connected to the i-th second scan line, and the second scan signal transmitted on the i-th second scan line is denoted as S2(row_i). Here, i is a positive integer greater than or equal to 1 and less than or equal to N, and N is the total number of rows of pixel circuits in the display panel.

[0143] Specifically, S2(row_1) represents the second scan signal corresponding to the first row of pixel circuits, and S2(row_N) represents the second scan signal corresponding to the Nth row (i.e., the last row) of pixel circuits. During the threshold voltage compensation and data writing stage t3, the second conduction pulses pulse22 on each of the second scan lines are sequentially shifted and transmitted row by row according to the order of S2(row_1) to S2(row_N), so that the compensation modules 120 of each row of pixel circuits are sequentially turned on, realizing the row-by-row writing of the data voltage Vdata. During the first reset stage t1, the first pulses pulse21 provided on each of the second scan lines GL2 appear simultaneously and overlap.

[0144] Optionally, the first scan signal S1, the light emission control signal EM, the first control signal SW1, and the second control signal SW2 are all global signals. A global signal is a common signal transmitted to all pixel circuits in the display panel, and this signal has the same level state for each pixel circuit at the same time. The global signal is directly provided by the driver chip of the non-display area NAA of the display panel and transmitted to all pixel circuits 10 through global signal lines, without needing to be generated by a gate driver circuit. The second scan signal S2 needs to be shifted line by line to achieve line-by-line data writing for each row of pixel circuits; therefore, only one set of gate driver circuits is set in the non-display area NAA to generate the second scan signal S2. Since neither the first scan signal S1 nor the light emission control signal EM needs to be provided by a gate driver circuit, compared to the traditional approach of configuring corresponding gate driver circuits for multiple sets of signals separately, this embodiment only requires one set of gate driver circuits to meet all timing control requirements, significantly reducing the number of gate driver circuits and corresponding signal traces required in the non-display area, significantly reducing the bezel size of the display panel, and further meeting the requirements of ultra-high PPI display layouts for narrow bezel design.

[0145] Figure 17 This is a partial cross-sectional schematic diagram of a display panel provided in an embodiment of the present invention. For example... Figure 12 and Figure 17 As shown, the first transistor M1 and the fourth transistor M4 are low-temperature polysilicon transistors, and the second transistor M2 and the third transistor M3 are oxide transistors.

[0146] The display panel includes a substrate 100 and a first active layer 101 and a second active layer 102 stacked along a direction away from the substrate 100. The channel regions of the first transistor M1 and the fourth transistor M4 are located in the first active layer 101, and the channel regions of the second transistor M2 and the third transistor M2 are located in the second active layer 102. The orthographic projections of the first active layer 101 onto the substrate 100 and the orthographic projections of the second active layer 102 onto the substrate 100 overlap. This facilitates saving layout space and achieving effects such as ultra-high PPI display layout.

[0147] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A pixel circuit, characterized in that, include: The module consists of a driver module, a compensation module, a light-emitting control module, and a reset module. The first end of the drive module is connected to the first power line, and the first power line is used to transmit the first power voltage and the data voltage to the first end of the drive module in a time-division manner. The first end of the light-emitting control module is connected to the second end of the driving module, and the second end of the light-emitting control module is connected to the first end of the light-emitting device. The light-emitting control module is used to turn on during the first reset phase, the second reset phase, and the light-emitting phase. The compensation module is connected between the second end of the drive module and the control end of the drive module. The compensation module is used to be turned on during the first reset phase and the threshold voltage compensation and data writing phase, and turned off during the second reset phase. The first end of the reset module is connected to the reset signal line, and the second end of the reset module is connected to the second end of the driving module or the second end of the light-emitting control module. The reset module is used to turn on during the first reset phase and transmit the first reset voltage on the reset signal line to the control end of the driving module and the first end of the light-emitting device. And during the second reset phase, the device is turned on to transmit the second reset voltage on the reset signal line to the first terminal of the light-emitting device; wherein the first reset voltage is different from the second reset voltage; Within a frame, the first reset phase is located before the threshold voltage compensation and data writing phase, and the second reset phase is located between the first reset phase and the light emission phase.

2. The pixel circuit of claim 1, wherein, The first power line is used to transmit the data voltage to the first end of the driving module during the threshold voltage compensation and data writing phase; and to transmit the first power voltage to the first end of the driving module during the light emission phase. The second end of the light-emitting device is connected to the second power line.

3. The pixel circuit according to claim 1 or 2, characterized in that, The reset module is connected between the reset signal line and the second end of the drive module, and the control end of the reset module is connected to the first scan line, which transmits the first scan signal. The control terminal of the light-emitting control module is connected to the light-emitting control line, the light-emitting control line transmits the light-emitting control signal, and the light-emitting control module is used to turn on in response to the light-emitting control signal during the first reset phase; The reset module is used to respond to the first pulse of the first scan signal to conduct, transmit the first reset voltage to the second terminal of the driving module, and transmit it to the first terminal of the light-emitting device via the light-emitting control module; The control terminal of the compensation module is connected to the second scan line, and the second scan line transmits the second scan signal; the compensation module is used to respond to the first pulse of the second scan signal during the first reset phase to transmit the first reset voltage to the control terminal of the drive module; The conduction duration of the first pulse of the first scan signal is greater than or equal to the conduction duration of the first pulse of the second scan signal; Preferably, within one frame, the start time of the first pulse of the first scan signal is the same as the start time of the first pulse of the second scan signal, and earlier than the start time of the invalid level of the light emission control signal; the end time of the first pulse of the first scan signal is earlier than the start time of the second pulse of the second scan signal. The start time of the second pulse of the second scan signal is later than the start time of the invalid level of the light emission control signal, and the end time of the second pulse of the second scan signal is earlier than the end time of the invalid level of the light emission control signal; the start time of the second pulse of the first scan signal is later than the end time of the invalid level of the light emission control signal. Preferably, the first scanning signal and the light emission control signal are global signals.

4. The pixel circuit according to claim 1 or 2, characterized in that, The reset module is connected between the reset signal line and the first end of the light-emitting device. The control end of the reset module is connected to the first scan line, and the first scan line transmits a first scan signal. The reset module is used to respond to the first pulse of the first scan signal and transmit the first reset voltage to the first end of the light-emitting device. The control terminal of the light-emitting control module is connected to the light-emitting control line, the light-emitting control line transmits the light-emitting control signal, and the light-emitting control module is used to turn on in response to the light-emitting control signal during the first reset phase; The control terminal of the compensation module is connected to the second scan line, and the second scan line transmits the second scan signal; the compensation module is used to respond to the first pulse of the second scan signal to turn on, so that the first reset voltage is transmitted to the control terminal of the driving module via the light emission control module and the compensation module; The conduction duration of the first pulse of the first scan signal is greater than or equal to the conduction duration of the first pulse of the second scan signal; Within a frame, the start time of the first pulse of the first scan signal is earlier than the start time of the invalid level of the light emission control signal, the end time of the first pulse of the first scan signal is earlier than the end time of the invalid level of the light emission control signal, and later than the end time of the second pulse of the second scan signal; or the start time of the valid level of the first scan signal is earlier than the start time of the invalid level of the light emission control signal, and the end time of the valid level of the first scan signal is later than the end time of the invalid level of the light emission control signal.

5. The pixel circuit according to claim 1, characterized in that, The pixel circuit also includes a storage module, which is connected between the reference signal line and the control terminal of the driving module; Within one frame, during the process of the compensation module responding to the second pulse of the second scan signal being turned on, the first terminal of the driving module is configured with the data voltage so that the data voltage and the threshold voltage of the driving module are written to the control terminal of the driving module, and the storage module stores the threshold voltage. The storage module includes a first capacitor, the first terminal of the first capacitor is connected to a reference signal line, and the second terminal of the first capacitor is connected to the control terminal of the drive module. The driving module includes a first transistor, the first electrode of the first transistor serves as the first terminal of the driving module, the second electrode of the first transistor serves as the second terminal of the driving module, and the gate of the first transistor serves as the control terminal of the driving module. The compensation module includes a second transistor, the gate of which is connected to a second scan line, the first terminal of which is connected to the gate of the first transistor, and the second terminal of which is connected to the second terminal of the first transistor. The reset module includes a third transistor, the gate of which is connected to the first scan line, the first terminal of which is connected to the reset signal line, and the second terminal of which is connected to the second terminal of the first transistor or the first terminal of the light-emitting device. The light-emitting control module includes a fourth transistor, the gate of which is connected to the light-emitting control line, the first terminal of which is connected to the second terminal of the first transistor, and the second terminal of which is connected to the first terminal of the light-emitting device.

6. A display panel, characterized in that, The display panel includes a plurality of pixel circuits as described in any one of claims 1 to 5.

7. The display panel according to claim 6, characterized in that, The display panel also includes multiple gating circuits, each of which includes a data voltage terminal, a first power supply voltage terminal, and an output terminal. The output terminal of the gating circuit is connected to at least one column of the pixel circuit, the data voltage terminal is connected to the data voltage, the first power supply voltage terminal is connected to the first power supply voltage, and the gating circuit is used to transmit the data voltage to the first power supply line in response to the effective level of the first control signal. And for responding to the effective level of the second control signal, the first power supply voltage is transmitted to the first power supply line, wherein, within a frame, the first control signal and the second control signal are at effective levels at different times.

8. The display panel according to claim 7, characterized in that, The gating circuit includes a first switching unit and a second switching unit. The first switching unit is connected between the first power line and the data voltage terminal and is used to transmit the data voltage to the first power line in response to the effective level of the first control signal. The second switching unit is connected between the first power line and the first power voltage terminal, and is used to transmit the first power voltage to the first power line in response to the effective level of the second control signal. Preferably, the first control signal and the second control signal are global signals; Preferably, the first switching unit includes a fifth transistor, and the second switching unit includes a sixth transistor; The gate of the fifth transistor is connected to the first control signal, the first terminal of the fifth transistor is connected to the data voltage terminal, and the second terminal of the fifth transistor is connected to the first power supply line; The gate of the sixth transistor is connected to the second control signal, the first terminal of the sixth transistor is connected to the first power supply voltage terminal, and the second terminal of the sixth transistor is connected to the first power supply line.

9. The display panel according to claim 7, characterized in that, Within one frame, the first control signal is at an active level during the threshold voltage compensation and data writing phase, and the second control signal is at an active level at least during the light emission phase; The working process of the pixel circuit in one frame includes a first reset stage, a threshold voltage characteristic adjustment stage, a threshold voltage compensation and data writing stage, a second reset stage, and a light emission stage, performed sequentially. The first reset phase of each pixel circuit is performed simultaneously, the threshold voltage characteristic adjustment phase of each pixel circuit is performed simultaneously, the threshold voltage compensation and data writing phase of each row of pixel circuits is performed row by row, the second reset phase of each row of pixel circuits is performed simultaneously, and the light emission phase of each pixel circuit is performed simultaneously. Preferably, the start time of the light emission control signal of each row of pixel circuits is the same.

10. The display panel according to claim 7, characterized in that, The display panel includes a display area and a non-display area, and multiple pixel circuits are located in the display area and arranged in multiple rows of pixel circuit groups; The display panel further includes: multiple shift registers and multiple second scan lines. The multiple shift registers are cascaded and located in the non-display area of ​​the display panel. The shift registers are connected to the control terminals of the compensation modules of multiple pixel circuits in a row of pixel circuit groups through corresponding second scan lines. The shift registers are configured to generate second scan signals. The second scan signal generated by the multiple shift registers simultaneously produces a first pulse and then a second pulse appears sequentially.

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