Bit-sparse-based ferroelectric in-memory computing chip uniform degradation and calibration method, system, device and medium

Abstract

A ferroelectric memory and computing chip uniform degradation and calibration method, system, device and medium based on bit sparsity, the memory and computing array includes a weight column and an error correction reference column, comprising: generating a sparse activation signal after bit sparsity processing of the input data stream; counting the number of each input of 1 in the error correction reference column to obtain the theoretical value of the error correction reference column; performing memory and computing processing on the memory and computing array by parallel inputting the sparse activation signal bit by bit to obtain the calculation value of the weight column and the calculation value of the error correction reference column; and monitoring the health state of the memory and computing array according to the calculation value of the error correction reference column and the theoretical value of the error correction reference column. The system, device and medium are used to realize the method, and the input data is bit-sparsed to ensure that the capacitance value of the ferroelectric capacitor can be globally uniformly degraded, so that the error correction reference column and the weight column have consistent polarization states, providing a feasible basis for the calibration circuit. The application ensures high-precision output while enhancing the stability of the ferroelectric memory and computing system.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and particularly relates to a method, system, device and medium for uniform degradation and calibration of ferroelectric memory chips based on bit sparsity. Background Technology

[0002] With the rapid development of artificial intelligence algorithms, the demand for high-efficiency computing architectures is becoming increasingly urgent. In-memory computing (CIM) architectures exhibit significant advantages by reducing data transfer between the processor and memory. Traditional resistive in-memory computing arrays suffer from high static power consumption and severe IR voltage drop. In contrast, CIM arrays based on ferroelectric capacitors (FeCAPs) are widely used in edge inference due to their high energy efficiency and non-volatility. However, ferroelectric materials are prone to polarization degradation under frequent polarization switching and read conditions, leading to capacitance drift and computational errors, severely impacting the long-term reliability of the system. Traditional ferroelectric in-memory computing architectures employ a fully active mode, causing some units to be under high electrothermal stress for extended periods, exacerbating non-uniform degradation. Especially in intensive computing tasks, unoptimized data mapping strategies significantly accelerate the degradation of critical units, resulting in non-linear performance degradation over time.

[0003] To address the device read degradation problem, the team led by Xueqing Li at Tsinghua University (Xu Z, Li T, Lee MY, et al. An NVM Non-Idealities Mitigation Solution Using Cell-Clustered Calibration for Analog High-Density Edge Multi-Level Cell Compute-in-Memory[J].IEEE Transactions on Circuits and Systems I: Regular Papers, 73[2026-04-14].) proposed a non-ideal mitigation scheme for NVM based on cell cluster calibration. By introducing a shared Local Recovery Unit (LRU) for local result calibration and employing dynamic boundary adaptive technology to compensate for state drift caused by read interference, the system's reliability and energy efficiency are significantly improved. However, the introduction of LRU in this scheme introduces additional circuit delays and overhead, and sensing errors may still occur when device states are severely overlapped, failing to fundamentally alleviate the device degradation problem. Summary of the Invention

[0004] To overcome the shortcomings of the prior art, the present invention aims to provide a method, system, device, and medium for uniform degradation and calibration of ferroelectric memory chips based on bit sparsity. By applying a uniform sparsity strategy to multiple rows of input data, the capacitance value of the ferroelectric capacitors is ensured to degrade globally and uniformly, enabling the error correction reference column units and weight column units to have consistent polarization states, thus providing a feasible basis for the normal operation of the calibration circuit. The method of the present invention, through a dual mechanism of uniform degradation followed by real-time correction, significantly enhances the stability of the ferroelectric memory system while ensuring high-precision output.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows: A method for uniform degradation and calibration of a ferroelectric memory chip based on bit sparsity, wherein the ferroelectric memory chip includes a memory array, the memory array including a weight column and an error correction reference column, and the method includes the following steps: Step 1: Perform bit sparsification processing on the input data stream to generate a sparse activation signal; Step 2: Count the number of times the input in the error correction reference column is 1 for each time to obtain the theoretical value of the error correction reference column; Step 3: Input the sparse activation signal into the in-memory array in parallel bit by bit, and perform in-memory processing based on the stored network weight data to obtain the calculated values ​​of the weight column and the error correction reference column. Step 4: Monitor the health status of the in-memory array based on the ratio of the calculated value to the theoretical value of the error correction reference column; if the ratio is less than... , To calibrate the threshold, proceed to step 5; if it is not less than, control the calculated values ​​of each weight column to perform shift and accumulation operations; Step 5: Based on the ratio, the calculated values ​​of the weight column are calibrated by uniform degradation to obtain the theoretical values ​​of the calibrated weight column; then, the theoretical values ​​of each calibrated weight column are controlled to perform shift and accumulation operations.

[0006] In step 1, the bit sparsification process is as follows: the input data stream is converted from its original code to suppress the redundancy of the complement code, then the converted data is decomposed into bit planes from the most significant bit to the least significant bit, and the significance is evaluated according to the weight contribution of each plane. The low-weight bit planes with smaller contributions are removed by dynamic pruning. Finally, the remaining bits are sampled based on the probability mask generated by random numbers to generate a sparse activation signal.

[0007] In step 3, the stored computation process is as follows: During the capacitor charging phase, the non-inverting input and output terminals of the operational amplifier are connected to the common-mode voltage, and the binary voltage is used to charge the capacitors of the memory array according to the sparse activation signal. During the charge transfer phase, the common-mode voltage is disconnected from the inverting input and output terminals of the operational amplifier. The charge generated on the bit lines of the memory array is transferred to the output terminal of the operational amplifier and output as a voltage. The output voltage is quantized by the corresponding analog-to-digital converter to obtain the calculated values ​​of the weight column and the error correction reference column, respectively.

[0008] In step 5, the calibration after uniform degradation is performed by multiplying the ratio of the calculated value of the error correction reference column to the theoretical value of the error correction reference column with the calculated value of the weight column to obtain the theoretical value of the weight column.

[0009] A system for uniform degradation and calibration of ferroelectric memory chips based on bit sparsity is used to implement the above-mentioned method for uniform degradation and calibration of ferroelectric memory chips; it includes a bit sparsity circuit, a memory array, an input calculator, a word line driver circuit, a bit line driver circuit, an integrator circuit, an analog-to-digital converter, and a circuit calibration module. Bit sparsity circuits are used to perform bit sparsification processing on the input data stream to generate sparse activation signals. Input calculator: Used to count the number of 1s entered in the error correction reference column to obtain the theoretical value of the error correction reference column; Word line driver circuit: used to input sparse activation signals in parallel bit by bit into the memory array to drive ferroelectric capacitors; Bit line drive circuit: used to provide drive voltage to the bit lines of the memory array and write network weight data into the ferroelectric capacitor cells of the memory array for storage; Integrating circuit: used to accumulate the charge released by all ferroelectric capacitor units on the weight column and error correction reference column of the memory array and convert it into a voltage signal output; Analog-to-digital converter: used to quantize the voltage signal output by the integrator circuit to obtain the calculated and theoretical values ​​of the weight column and the error correction reference column; Circuit calibration module: Used to calibrate the calculated value of the weight column based on the ratio of the calculated value of the error correction reference column to the theoretical value of the error correction reference column, so as to obtain the theoretical value of the weight column.

[0010] The bit sparse circuit integrates a sign-magnitude conversion module, a saliency evaluation module, a dynamic pruning module, and a probability sampling module. The sign-magnitude conversion module converts the input data to its original form to suppress complement redundancy. The saliency evaluation module then decomposes the converted data into bit planes from the most significant bit to the least significant bit, evaluating the saliency based on the weight contribution of each bit plane. Dynamic pruning is then performed based on the weight contribution of each bit plane using the dynamic pruning module, and sampling is performed using a probability mask generated by random numbers by the probability sampling module. This process controls the sparsity of the bit stream and generates a sparse activation signal.

[0011] The in-memory array includes multiple array bit lines, multiple array word lines, and several ferroelectric capacitor units for storing network weight data; the array word lines are arranged parallel to each other along the row direction as row control lines; the array bit lines are arranged parallel to each other along the column direction as column read / write lines; the ferroelectric capacitor units are located at the intersection of the array bit lines and the array word lines, with one end of the ferroelectric capacitor connected to the array word line and the other end connected to the array bit line.

[0012] The integrating circuit includes an operational amplifier, a feedback capacitor, a first switch, and a second switch. The first switch is connected between the output terminal and the non-inverting input terminal of the operational amplifier; the second switch is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier; one end of the feedback capacitor is connected to the output terminal of the operational amplifier, and the other end is connected to the second switch and the inverting input terminal of the operational amplifier; the inverting input terminal of the operational amplifier is connected to the bit lines of the weight column and the error correction reference column of the memory array.

[0013] The present invention also provides an electronic device, comprising: Memory: A computer program that stores the above-mentioned method for uniform degradation and calibration of ferroelectric memory chips, and is a computer-readable device; Processor: Used to implement the above-described method for uniform degradation and calibration of ferroelectric memory chips when executing the computer program.

[0014] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can implement the above-described method for uniform degradation and calibration of ferroelectric memory chips.

[0015] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. The uniform degradation control mechanism for ferroelectric capacitors in this invention applies a unified sparsity strategy to the multi-row input data processed in parallel, making the distribution frequency of the "1" signal in the entire chip highly consistent, thereby actively guiding all ferroelectric capacitor units to tend towards global uniform degradation, rather than the local over-degradation in traditional schemes.

[0016] 2. The present invention adds one or more dedicated error correction reference columns in the memory array, where all cells always store "1". This column is not used for data storage, but is dedicated to real-time monitoring and quantification of the signal attenuation caused by the polarization degradation of ferroelectric capacitance, providing the system with a real-time reference benchmark that is consistent with the degradation experienced by the array cells.

[0017] 3. This invention senses the health status of the memory array by comparing the theoretical and calculated values ​​of the error correction reference column. It achieves real-time and accurate detection of the ferroelectric capacitor status with minimal hardware overhead without requiring additional complex circuits or interrupting normal operation.

[0018] 4. This invention uses the ratio of the calculated value to the theoretical value of the error correction reference column to compensate for the actual simulated output of each weight column of the storage array, restoring the theoretical calculation result close to the ideal situation, thereby effectively correcting the calculation error introduced by the polarization degradation of ferroelectric capacitance.

[0019] In summary, compared with the prior art, the uniform degradation and calibration method of the present invention, through the dual mechanism of uniform degradation followed by real-time correction, jointly ensures the high reliability of the in-memory computing system throughout its life cycle, and realizes long-life, high-precision ferroelectric in-memory computing. Attached Figure Description

[0020] Figure 1 This is a flowchart of the method for uniform degradation and calibration of ferroelectric memory chips based on bit sparsity according to the present invention.

[0021] Figure 2 This is a schematic diagram of bit-level sparse data flow control preprocessing according to the present invention.

[0022] Figure 3 This is a schematic diagram of the working principle of the ferroelectric storage system of the present invention.

[0023] Figure 4 This is a schematic diagram of the ferroelectric memory system with calibration according to the present invention.

[0024] Figure 5 This is an optimized effect diagram of the method for uniform degradation and calibration of ferroelectric memory chips based on bit sparsity in this invention. Detailed Implementation

[0025] To make the objectives, technical solutions, and effects of this invention clearer and more explicit, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0026] like Figure 1 As shown, a method for uniform degradation and calibration of a ferroelectric memory chip based on bit sparsity is presented. The ferroelectric memory chip includes a memory array, which comprises a weight column and an error correction reference column. The specific method includes the following steps: Step 1: Write the network weight data into the ferroelectric capacitor cells of the memory array for storage; Step 2: Perform bit sparsification processing on the input data stream using a bit sparsity circuit to generate a sparse activation signal for activating the memory array; The bit sparsity processing flow is as follows: First, the input data stream is converted from its original code to eliminate the high-density bits "1" brought by the two's complement negative number. Then, the converted data is decomposed into a bit plane from the most significant bit (MSB) to the least significant bit (LSB), and the significance is evaluated based on the weight contribution of each plane. On this basis, the system forcibly removes the low-contribution bit planes through dynamic pruning. Finally, the remaining bits are finely sampled using a probability mask generated based on random numbers. This allows for precise control of the distribution ratio of "1" in the bit stream while preserving the original data characteristics to the maximum extent, providing an efficient sparse activation signal for the back-end storage array.

[0027] For input n-bit data, such as an 8-bit integer, the most significant bit (MSB) dominates the numerical range and core features of the data, while the least significant bit (LSB) carries detailed information. In computational tasks such as neural networks, algorithms are highly sensitive to changes in the MSB, but naturally robust to changes in the LSB. Based on this characteristic, bit sparsity technology selectively sets the LSB of the input data to zero, significantly reducing the actual operation frequency of memory units while maintaining computational accuracy. Bit sparsity circuits dynamically generate probability masks to mask a specified proportion of the LSB, generating sparse single bits of data. After sparsification, the memory units corresponding to bits with zero values ​​will avoid unnecessary read / write or polarization flip operations. Especially for ferroelectric capacitors, an input of "0" often only needs to maintain the current state, and the resulting electrothermal stress is much less than the polarization flip required to write "1", effectively mitigating the degradation damage accumulated by the device due to frequent access.

[0028] like Figure 2 As shown, the input data are "0111 1111" for the first row, "0010 0010" for the second row, and "0011 1101" for the third row. Adding 1 to the data in the first row converts it to "1000 0000", subtracting 2 from the data in the second row converts it to "0010 0000", and adding 3 to the data in the third row converts it to "0100 0000". The converted data is used to activate the corresponding row signal of the storage array. Since each row has only one bit set to 1, each row is activated only once. The first row is activated only in the first cycle, the second row is activated only in the third cycle, and the third row is activated only in the second cycle.

[0029] Step 3: Count the number of times the input in the error correction reference column is 1 for each time to obtain the theoretical value of the error correction reference column. ; For example, in a certain calculation... With one input, the input counter will sum and output the input data. The data is stored, and the input counter is a digital module whose output is used for subsequent error correction. Since the stored data is all 1s, the ideal quantization result of the analog-to-digital converter is also... However, the presence of polarization loss leads to some errors in its quantization results.

[0030] Step 4: Input the sparse activation signal bit by bit in parallel into the in-memory array, and perform in-memory processing based on the stored network weight data to obtain the calculated values ​​of the weight column. Calculated values ​​of the error correction reference column ; The in-memory processing flow specifically involves: accumulating the charges released by all ferroelectric capacitor units on the weight column and error correction reference column of the in-memory array, and converting them into voltage signal outputs; such as Figure 3 As shown, for each column, in the first stage, the non-inverting input and output of the operational amplifier are first connected to the common-mode voltage V. cm , converting sparse activation signals into binary voltages The input is multiplied by the stored network weight data to charge the ferroelectric capacitors, thus storing the calculation result of each ferroelectric capacitor unit as a charge on the ferroelectric capacitor. In the second stage, the common-mode voltage V is disconnected. cm With the inverting input and output terminals connected, the operational amplifier begins to function as an integrator, and the word line voltage starts from... Change to V cm The charge generated on the bit line is transferred to the output of the operational amplifier due to the integrator and is output as a voltage. The voltage output expression is as follows: in, Indicates the first The row of binary voltages represents the input binary data; Indicates the first Line 1 Column-stored binary network weight data has high capacitive states. and low capacitance state Two states; This represents the capacitance value of the capacitor between the output terminal and the negative input terminal of the operational amplifier in the integrator circuit.

[0031] The conversion of the calculated values ​​in the memory array to the output voltage The values ​​of the weight columns are obtained by quantization using the corresponding analog-to-digital converters. Calculated values ​​of the error correction reference column .

[0032] Step 5: Calculate the value using the error correction reference column. Theoretical values ​​of the error correction reference column ratio Perform health status monitoring of the storage array; if Less than , To calibrate the threshold, proceed to step 6; if it is not less than, then calculate the values ​​of each weight column. Perform a shift-accumulation operation and send the shift-accumulation result to the activation function for subsequent data processing; The shift-accumulation operation process is as follows: First, the externally input sparse activation signal enters the memory array in a bit-serial manner and performs a bit-by-bit multiplication operation with the network weight data stored in the ferroelectric capacitor unit; then, the memory array outputs a local part representing the effective bits with different weights and the calculation result, which are input into the shift accumulator according to the weight order of the bit plane; in the shift accumulator, the calculation result of the previous moment is left-shifted according to the bit weight relationship to achieve dimensional alignment, and then added and merged with the calculation result of the current bit plane. Through this cyclic "shift and sum" logic, the originally discrete bit operation is finally transformed into a complete multiplication and accumulation result at the hardware level.

[0033] Step 6: Set the ratio Calculated values ​​of each weight column Multiplying them together yields the theoretical values ​​for each weight column. To achieve calibration after uniform degradation; to obtain the theoretical values ​​of each weight column after calibration. Perform a shift-accumulation operation and send the shift-accumulation result to the activation function for subsequent data processing.

[0034] The invention mentioned Can be used to describe This is to maintain the changes caused by the loss and the health status of the storage array; similarly, there is a quantized calculation value for any column. and theoretical value , Essentially, it also describes Due to the changes caused by holding losses. Ignoring the effect of D2D variation (the characteristic differences between ferroelectric capacitor components and devices), we can obtain , ,because , and Given that the theoretical values ​​of each weight column can be calculated using this formula, we can obtain the theoretical values ​​of each column. The simulation results are as follows: Figure 5As shown in the diagram. The traditional scheme refers to the scheme without the inclusion of uniform degradation and calibration circuitry. Comparative analysis shows that as the degree of data loss increases, the performance of the traditional scheme significantly decreases, while the accuracy of the scheme of this invention remains at a high level. Experiments demonstrate that the uniform degradation and calibration method of this invention significantly enhances the stability of the ferroelectric memory system while ensuring high-precision output.

[0035] This invention employs a uniform bit sparsity strategy on multiple lines of input data, controlling the distribution frequency of "1"s in these sparse activation signals to a similar level, thereby promoting a more uniform degradation of the capacitance value of the entire ferroelectric capacitor unit. This consistent degradation behavior provides a feasible basis for system-level calibration and fault-tolerant compensation, significantly enhancing the system's reliability and lifespan.

[0036] like Figure 3 As shown, a system for uniform degradation and calibration of a ferroelectric memory chip based on bit sparsity includes a bit sparse circuit, a memory array, an input calculator, a word line driver circuit, a bit line driver circuit, an integrator circuit, an analog-to-digital converter, and a circuit calibration module. Figure 4 As shown; Bit sparsity circuit: This circuit is used to perform bit sparsification processing on the input data stream to generate a sparse activation signal. It integrates a sign-magnitude conversion module, a saliency evaluation module, a dynamic pruning module, and a probability sampling module. First, the circuit suppresses complement redundancy in the input data stream through the sign-magnitude conversion module. Then, the saliency evaluation module decomposes the converted data into bit planes from the most significant bit (MSB) to the least significant bit (LSB), and performs saliency evaluation based on the weight contribution of each bit plane. Next, the dynamic pruning module performs dynamic pruning based on the weight contribution of the bit planes, and the probability sampling module performs fine-grained sampling based on a probability mask generated by random numbers. This allows for precise control of bit stream sparsity while ensuring the integrity of data features, providing an efficient sparse activation signal for the backend in-memory array. In-memory array: includes multiple array bit lines (BL), multiple array word lines (WL), and several ferroelectric capacitor cells (C) for storing network weight data. FE The array word lines are arranged parallel to each other along the row direction, serving as row control lines; the array bit lines are arranged parallel to each other along the column direction, serving as column read / write lines; the ferroelectric capacitor unit is located at the intersection of the array bit lines and the array word lines, with one end of the ferroelectric capacitor connected to the array word line and the other end connected to the array bit line.

[0037] One or more error-correcting reference columns are added to the in-memory array, located on one side of the weight columns. All storage cells in these error-correcting reference columns always store "1". All weight columns and error-correcting reference columns in the in-memory array are connected to integration circuits, such as... Figure 2 As shown.

[0038] Bit sparse circuits ensure that the capacitance of ferroelectric capacitors degrades uniformly globally, enabling the error correction reference column cells and weight column cells to have consistent polarization states, thus providing conditions for the normal operation of the error correction circuit.

[0039] Input Calculator: Used to count the number of times the error correction reference column is set to 1, thus obtaining the theoretical value of the error correction reference column. And store it; Word line driver circuit: used to input sparse activation signals in parallel bit by bit into the memory array to achieve high load driving; the driver circuit can sample buffer chain; Bit line drive circuit: used to provide drive voltage to the bit lines of the memory array and write network weight data to ferroelectric capacitors for storage; Integrating circuit: Used to accumulate the charge released by all ferroelectric capacitor units on the weight column and error correction reference column of the memory array and convert it into a voltage signal output; the integrating circuit includes an operational amplifier, a feedback capacitor, a first switch and a second switch. The first switch is connected between the output terminal of the operational amplifier and the non-inverting input terminal (+ terminal) of the operational amplifier; the second switch is connected between the inverting input terminal (- terminal) of the operational amplifier and the non-inverting input terminal of the operational amplifier; one end of the feedback capacitor is connected to the output terminal of the operational amplifier, and the other end is connected to the second switch and the inverting input terminal of the operational amplifier; the inverting input terminal of the operational amplifier is connected to the bit lines of the weight column and error correction reference column of the memory array.

[0040] Analog-to-digital converter: Used to quantize the analog voltage signal output from the integrator circuit and convert it into a digital signal, wherein the digital signal includes the calculated values ​​of each weight column. Calculated values ​​of the error correction reference column Compared with theoretical value .

[0041] Circuit calibration module: used for calculating values ​​based on the error correction reference column. Theoretical values ​​of the error correction reference column ratio Calculated values ​​for each weight column Calibration is performed to obtain the theoretical values ​​of each weight column. .

Claims

1. A method for uniform degradation and calibration of a ferroelectric memory chip based on bit sparsity, wherein the ferroelectric memory chip includes a memory array, characterized in that, The in-memory array includes a weight column and an error correction reference column. The method includes the following steps: Step 1: Perform bit sparsification processing on the input data stream to generate a sparse activation signal; Step 2: Count the number of 1s entered in the error correction reference column to obtain the theoretical value of the error correction reference column; Step 3: Input the sparse activation signal bit by bit in parallel into the storage array for storage processing to obtain the calculated values ​​of each weight column and the calculated values ​​of the error correction reference column; Step 4: Monitor the health status of the in-memory array based on the ratio of the calculated value to the theoretical value of the error correction reference column; if the ratio is less than... , To calibrate the threshold, proceed to step 5; if it is not less than, perform a shift and summation operation on the calculated values ​​of each weight column. Step 5: Based on the ratio, calibrate the calculated values ​​of the weight column after uniform degradation to obtain the theoretical values ​​of the calibrated weight column; Subsequently, the theoretical values ​​of each weight column after calibration are shifted and accumulated.

2. The method for uniform degradation and calibration of ferroelectric memory chips according to claim 1, characterized in that: In step 1, the bit sparsification process is as follows: The input data stream is converted from its original code to suppress complement redundancy. Then, the converted data is decomposed into bit planes from the most significant bit to the least significant bit. The significance of each bit plane is evaluated based on its weight contribution. The low-contribution bit planes are removed by dynamic pruning. Finally, the remaining bits are sampled based on a probability mask generated by random numbers to generate a sparse activation signal.

3. The method for uniform degradation and calibration of ferroelectric memory chips according to claim 1, characterized in that: In step 3, the stored computation process is as follows: During the capacitor charging phase, the non-inverting input and output terminals of the operational amplifier are connected to the common-mode voltage, and the ferroelectric capacitors of the memory array are charged using binary voltage according to the sparse activation signal. During the charge transfer phase, the common-mode voltage is disconnected from the inverting input and output terminals of the operational amplifier. The charge generated on the bit lines of the memory array is transferred to the output terminal of the operational amplifier and output as a voltage. The output voltage is quantized by the corresponding analog-to-digital converter to obtain the calculated values ​​of the weight column and the error correction reference column, respectively.

4. The method for uniform degradation and calibration of ferroelectric memory chips according to claim 1, characterized in that: In step 5, the calibration after uniform degradation is performed by multiplying the ratio by the calculated value of the weight column to obtain the theoretical value of the weight column.

5. A system for uniform degradation and calibration of ferroelectric memory chips based on bit sparsity, used to implement the method for uniform degradation and calibration of ferroelectric memory chips according to any one of claims 1-4; characterized in that, This includes bit sparse circuits, memory arrays, input calculators, word line driver circuits, bit line driver circuits, integrating circuits, analog-to-digital converters, and circuit calibration modules. Bit sparsity circuits are used to perform bit sparsification processing on the input data stream to generate sparse activation signals. Input calculator: Used to count the number of 1s entered in the error correction reference column to obtain the theoretical value of the error correction reference column; Word line driver circuit: used to input sparse activation signals in parallel bit by bit into the memory array to drive ferroelectric capacitors; Bit line drive circuit: used to provide drive voltage to the bit lines of the memory array and write network weight data into the ferroelectric capacitor cells of the memory array for storage; Integrating circuit: used to accumulate the charge released by all ferroelectric capacitor units on the weight column and error correction reference column of the memory array and convert it into a voltage signal output; Analog-to-digital converter: used to quantize the voltage signal output by the integrator circuit to obtain the calculated and theoretical values ​​of the weight column and the error correction reference column; Circuit calibration module: Used to calibrate the calculated value of the weight column based on the ratio of the calculated value of the error correction reference column to the theoretical value of the error correction reference column, so as to obtain the theoretical value of the weight column.

6. The ferroelectric memory chip uniform degradation and calibration system according to claim 5, characterized in that: The bit sparse circuit integrates a sign-magnitude conversion module, a saliency evaluation module, a dynamic pruning module, and a probability sampling module. The sign-magnitude conversion module converts the input data to its original form to suppress complement redundancy. The saliency evaluation module then decomposes the converted data into bit planes from the most significant bit to the least significant bit, and evaluates the saliency based on the weight contribution of each bit plane. Based on the weight contribution of the bit planes, the dynamic pruning module performs dynamic pruning, and the probability sampling module performs sampling based on a probability mask generated by random numbers, thereby controlling the sparsity of the bit stream and generating a sparse activation signal.

7. The ferroelectric memory chip uniform degradation and calibration system according to claim 5, characterized in that: The in-memory array includes multiple array bit lines, multiple array word lines, and several ferroelectric capacitor units for storing network weight data; the array word lines are arranged parallel to each other along the row direction as row control lines; the array bit lines are arranged parallel to each other along the column direction as column read / write lines; the ferroelectric capacitor units are located at the intersection of the array bit lines and the array word lines, with one end of the ferroelectric capacitor connected to the array word line and the other end connected to the array bit line.

8. The ferroelectric memory chip uniform degradation and calibration system according to claim 5, characterized in that: The integrating circuit includes an operational amplifier, a feedback capacitor, a first switch, and a second switch. The first switch is connected between the output terminal and the non-inverting input terminal of the operational amplifier; the second switch is connected between the inverting input terminal and the non-inverting input terminal of the operational amplifier; one end of the feedback capacitor is connected to the output terminal of the operational amplifier, and the other end is connected to the second switch and the inverting input terminal of the operational amplifier; the inverting input terminal of the operational amplifier is connected to the bit lines of the weight column and the error correction reference column.

9. An electronic device, characterized in that, include: Memory: A computer program storing the ferroelectric memory chip uniform degradation and calibration method according to any one of claims 1-4, which is a computer-readable device; Processor: Used to implement the ferroelectric memory chip uniform degradation and calibration method according to any one of claims 1-4 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program that, when executed by a processor, enables the implementation of the ferroelectric memory chip uniform degradation and calibration method according to any one of claims 1-4.

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