A method for eliminating high-frequency common-mode noise of a parallel three-phase full-bridge inverter and an inverter system

Abstract

The application discloses a method for eliminating high-frequency common-mode noise of parallel three-phase full-bridge inverters and an inverter system, and belongs to the technical field of power electronic electromagnetic interference suppression. DM The application first acquires equivalent common-mode inductance L p and parasitic capacitance C r of each inverter, calculates LC resonance frequency f r according to the equivalent common-mode inductance L p and the parasitic capacitance C r , and determines half of the resonance period as a delay time T0; then, even-numbered inverters are paired two by two, and PWM waveforms of one inverter in each pair are controlled to be delayed relative to the other inverter by T0, so that resonance high-frequency common-mode currents generated by the two inverters are equal in size and opposite in direction, and are mutually canceled in a common-mode loop. The application can eliminate resonance high-frequency common-mode noise from the source by a control strategy without adding additional hardware filter devices, supports parallel expansion of any even-numbered inverters, cooperates with an existing common-mode filter circuit, can be directly upgraded and realized in an existing parallel inverter control program, and has low modification cost.

Description

Technical Field

[0001] This invention relates to the field of electromagnetic interference suppression technology for power electronic converters, specifically to a method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter and an inverter system thereof. Background Technology

[0002] High-power three-phase inverters are limited by the rated capacity of a single power device, so multiple three-phase full-bridge inverters are usually connected in parallel on the AC side to expand power capacity. When the inverter is working, the power devices switch at high frequency, and the DC side input voltage level is high, which will generate a common-mode voltage with significant amplitude, thereby causing serious electromagnetic interference and making it difficult for the equipment to meet the conducted emission and radiated emission limit standards.

[0003] The mainstream approach to suppressing common-mode conducted interference in existing parallel inverters is to add common-mode filter circuits on both the DC and AC sides. This is achieved by increasing the common-mode inductance and adding Y capacitors, among other hardware solutions, to improve the common-mode loop impedance and reduce external common-mode current. However, this approach has significant drawbacks:

[0004] 1. The common-mode filter is connected in series with the main power circuit. The large volume of the common-mode inductor and the large capacity of the Y capacitor will increase the hardware cost of the equipment and increase the size and weight of the whole machine, which is not conducive to the high power density and high efficiency design of the converter.

[0005] 2. To meet heat dissipation requirements, power devices have a large contact area with the heat sink, resulting in a non-negligible parasitic capacitance Cp between the device and the housing (PE). This parasitic capacitance adds a low-impedance common-mode discharge path, significantly weakening the filtering effect of traditional common-mode filters.

[0006] 3. The parasitic capacitance Cp and the AC-side filter equivalent common-mode inductance LDM form an LC resonant circuit. At the resonant frequency, the circuit impedance is extremely low. The common-mode voltage jump will excite a large-value high-frequency resonant common-mode current, forming high-frequency common-mode noise that is difficult to suppress by traditional common-mode filter circuits.

[0007] 4. Parasitic parameter modeling is complex, and common-mode filter parameters can only be determined through multiple prototype debugging iterations, which prolongs the product development cycle and increases R&D costs.

[0008] In summary, existing hardware filtering schemes cannot effectively solve the high-frequency common-mode noise problem caused by parasitic LC resonance. There is an urgent need for a technical solution that does not rely on additional hardware and achieves resonant high-frequency common-mode noise cancellation based on control strategies. Summary of the Invention

[0009] To address the shortcomings of existing technologies where high-frequency common-mode noise generated by parasitic LC resonance in parallel three-phase full-bridge inverters is difficult to effectively suppress using hardware common-mode filters, and where hardware filtering schemes are costly and bulky, this invention provides a method and inverter system for eliminating high-frequency common-mode noise in parallel three-phase full-bridge inverters. By applying a precise phase delay to the PWM waveform of the parallel inverter, the resonant high-frequency common-mode current is canceled out, eliminating the need to increase the specifications of the common-mode filter hardware, reducing the overall cost and size, and optimizing external common-mode conducted interference.

[0010] A method for eliminating high-frequency common-mode noise in parallel three-phase full-bridge inverters is applied to an inverter system consisting of an even number of three-phase full-bridge inverters connected in parallel on the AC side. This method aims to eliminate high-frequency common-mode noise, which is difficult for common-mode filter circuits to effectively suppress and is generated by the resonance between parasitic capacitance between power devices and the chassis and the AC-side filter inductor. The method includes the following steps:

[0011] Step 1: Obtain the equivalent common-mode inductance L of the three-phase filter inductors on the AC side of each inverter. DM And the parasitic capacitance C between the power device and the chassis PE. p ;

[0012] Step 2: According to the L DM and C p Calculate the LC resonant frequency f r :

[0013] ;

[0014] Step 3: Based on the resonant frequency f r The resonant period is obtained as T = 1 / f r We determine half a resonance period as the phase delay duration T0, that is:

[0015] ;

[0016] Step 4: Pair the even number of three-phase full-bridge inverters in pairs to form at least one inverter pairing group;

[0017] Step 5: For each inverter pairing group, control the three-phase output PWM waveform of one inverter to be delayed by the time T0 relative to the other inverter, so that the resonant high-frequency common-mode current excited by the common-mode voltage jump of the two inverters is equal in magnitude and opposite in direction, and cancels each other in the common-mode circuit, thereby suppressing high-frequency common-mode noise.

[0018] In a preferred embodiment of the present invention, in step one, the equivalent common-mode inductance LDM of the AC-side three-phase filter inductor is obtained by equivalent calculation of the single-phase inductance value of the three-phase filter inductor in three-phase parallel connection, and the calculation formula is as follows:

[0019] ;

[0020] Where L is the inductance value of the single-phase filter inductor on the AC side.

[0021] As a preferred embodiment of the present invention, in step one, the parasitic capacitance value C p The calculation formula is obtained through approximate calculation using a parallel-plate capacitor model:

[0022] ;

[0023] Where S is the contact area between the power device and the heat sink, d is the thickness of the insulating medium between the power device and the heat sink, and ε is the dielectric constant of the insulating medium.

[0024] As a preferred embodiment of the present invention, in step five, the delay of the three-phase output PWM waveform is achieved by delaying the entire PWM drive signal of the inverter's power transistor, or by carrier phase offset and modulation wave phase offset.

[0025] As a preferred embodiment of the present invention, the PWM control signal of the inverter pairing group is uniformly generated and configured with phase difference by the same master controller; or a master-slave control architecture is adopted, in which the master outputs a synchronization reference signal and the slave executes the phase offset of the delay T0 based on the synchronization reference signal.

[0026] As a preferred embodiment of the present invention, the inverter system is equipped with a common-mode filter circuit, and the elimination method works in conjunction with the common-mode filter circuit to jointly suppress the common-mode conducted interference of the inverter to the outside world.

[0027] A parallel three-phase full-bridge inverter system, comprising:

[0028] An even number of three-phase full-bridge inverters are connected in parallel on the AC side of each inverter.

[0029] A common-mode filter circuit is installed on the DC side and / or AC side of the inverter system to suppress common-mode conducted interference.

[0030] The control unit is connected to the drive circuit signal of each three-phase full-bridge inverter, and is used to pair the even-numbered three-phase full-bridge inverters in pairs, and according to the equivalent common-mode inductance L DM and parasitic capacitance C p Determine the delay time T0, and output a PWM drive signal with a phase difference of the delay time T0 to the two inverters in each pair.

[0031] By adopting the above technical solution, the present invention has the following beneficial effects:

[0032] 1. Existing common-mode filters can only suppress sub-common-mode interference at the switching frequency, and are ineffective against parasitic L-mode interference.DM C p The high-frequency noise generated by resonance has poor suppression effect. This invention uses precise half-resonant period phase shift to make the resonant common-mode current generated by the paired inverter cancel each other out in the opposite direction, thereby eliminating the high-frequency resonant component from the source of noise and solving the shortcomings of traditional hardware filtering.

[0033] 2. This invention relies entirely on software control strategies to achieve noise cancellation, without increasing the common-mode inductor, increasing the capacitor specifications, or adding additional filtering hardware. This can significantly reduce the cost of power circuit components, reduce the space occupied by the filter, and increase the overall power density of the inverter, making it suitable for the lightweight design requirements of high-power energy storage, photovoltaic, and drive inverters.

[0034] 3. The solution supports parallel operation of any even number of inverters, such as 2, 4, or 6. It only requires grouping the inverters into pairs and applying the T0 phase difference to each group independently. There are no additional hardware modifications required for topology expansion, which can adapt to different power level expansion needs.

[0035] 4. Phase delay can be achieved through various methods such as overall delay of the drive signal, carrier offset, and modulation wave offset; it is also compatible with the two mainstream parallel inverter control architectures of centralized control and master-slave synchronous control, and can be directly upgraded in the existing parallel inverter control program with low transformation cost.

[0036] 5. Hardware filters suppress common-mode interference at the basic switching frequency. This control strategy eliminates resonant high-frequency noise. Dual suppression further reduces the electromagnetic interference of the whole machine and makes it easier to meet EMC standard limits. Attached Figure Description

[0037] Figure 1 This is the basic circuit topology diagram of a single three-phase full-bridge inverter.

[0038] Figure 2 Simplified common-mode topology diagram of a single inverter after adding a DC-side common-mode filter;

[0039] Figure 3 This is a schematic diagram of the topology of the power devices in a single inverter and their parasitic capacitance to the PE.

[0040] Figure 4 The common-mode equivalent topology of a single inverter after introducing the parasitic capacitance of the components and the chassis;

[0041] Figure 5 A simplified common-mode topology diagram of a system with two inverters connected in parallel on the AC side and parasitic capacitance introduced;

[0042] Figure 6 The simulated common-mode voltage waveform of the parallel inverter without employing the phase shifting strategy of this invention;

[0043] Figure 7The simulation waveform of the common-mode voltage of the parallel inverter after adopting the half-resonant periodic phase shift strategy of the present invention.

[0044] Meaning of each number in the attached diagram:

[0045] V_CM, V_CM1, V_CM2: Equivalent common-mode noise sources for a single inverter, the first inverter, and the second inverter, respectively;

[0046] LDM, LDM1, LDM2: Equivalent common-mode inductance of AC side filter inductor of single unit, first unit, and second unit inverters;

[0047] LCM: DC-side common-mode filter inductor;

[0048] C: DC-side common-mode filter capacitor;

[0049] Cf: AC-side Y-type common-mode filter capacitor;

[0050] Cp, Cp1, Cp2: Parasitic capacitance between a single power device, the first power device, and the second power device and the PE (protective earth) housing;

[0051] ICM: Loop common-mode current;

[0052] N: DC bus negative terminal; O: inverter three-phase output neutral point; PE: equipment protective ground. Detailed Implementation

[0053] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments.

[0054] Example 1

[0055] like Figures 1 to 7 As shown, the present invention discloses a method for eliminating high-frequency common-mode noise in parallel three-phase full-bridge inverters. This method is applied to an inverter system consisting of an even number of three-phase full-bridge inverters connected in parallel on the AC side. It is used to eliminate high-frequency common-mode noise generated by the parasitic capacitance between the power devices and the chassis, and the resonance of the AC-side filter inductor. This embodiment uses two three-phase full-bridge inverters connected in parallel on the AC side as an example. However, those skilled in the art should understand that this method is also applicable to situations where four, six, or more even numbers of inverters are connected in parallel.

[0056] Specifically, the method of this embodiment includes the following steps:

[0057] Step 1: Obtain the equivalent common-mode inductance and parasitic capacitance values.

[0058] Obtain the equivalent common-mode inductance L of the three-phase filter inductors on the AC side of each inverter. DM And the parasitic capacitance C between the power device and the chassis PE.p .

[0059] Among them, the equivalent common-mode inductance L of the three-phase filter inductor on the AC side DM The inductance of a three-phase filter inductor is obtained through equivalent calculation of the single-phase inductance of the three-phase parallel circuit. The calculation formula is as follows:

[0060] ;

[0061] Where L is the inductance value of the single-phase filter inductor on the AC side. Since the three-phase inductors are connected in parallel in the common-mode circuit, the equivalent common-mode inductance is one-third of the single-phase inductance value.

[0062] Parasitic capacitance value C p The parasitic capacitance is approximated using a parallel-plate capacitor model. Specifically, the power device is mounted on a heat sink, with an insulating thermally conductive dielectric layer (such as a ceramic plate) between them. Assuming the contact area between the power device and the heat sink is S, the thickness of the insulating dielectric layer is d, and the dielectric constant of the insulating dielectric is ε, then the parasitic capacitance value satisfies:

[0063] ;

[0064] Those skilled in the art can obtain the specific values ​​of S, d, and ε based on the actual inverter's power module model, heat sink structure, and insulating medium material, and substitute them into the calculation.

[0065] Step 2: Calculate the LC resonant frequency.

[0066] Based on the equivalent common-mode inductance L obtained in step one DM and parasitic capacitance C p Calculate the resonant frequency f r The resonant frequency satisfies:

[0067] ;

[0068] In actual inverter operation, the high-frequency common-mode voltage V generated by the switching action of power devices... CM As an excitation source, when the frequency component of the common-mode voltage is close to or equal to the aforementioned resonant frequency f r At that time, by L DM With C p The resulting loop impedance is close to its minimum, thereby generating a large-amplitude high-frequency common-mode current at that frequency, which becomes the main source of conducted emission interference.

[0069] Step 3: Determine the phase delay duration.

[0070] Based on the resonant frequency f calculated in step two r Furthermore, the resonant period T = 1 / f is obtained. rAnd determine half a resonance period as the phase delay duration T0, that is:

[0071] ;

[0072] T0 is the delay time for applying phase shift to the parallel inverter in subsequent steps.

[0073] Step 4: Inverter pairing and grouping.

[0074] In an inverter system, an even number of three-phase full-bridge inverters are paired up to form at least one inverter pairing group. For a system with two inverters connected in parallel, the two inverters form one pairing group; for a system with four or more inverters connected in parallel, the system is divided into multiple pairing groups in any two-inverter configuration. Each pairing group operates independently and does not interfere with the others.

[0075] Step 5: Phase shift suppression control.

[0076] For each inverter pairing group, the three-phase output PWM waveform of one inverter is delayed relative to the other inverter by the duration T0 determined in step three.

[0077] Specifically, such as Figure 5 In the equivalent common-mode circuit of the two parallel inverters shown, the common-mode noise source V_CM1 of the first inverter and the common-mode noise source V_CM2 of the second inverter have the same switching frequency and harmonic components. When no phase shift is applied, the resonant high-frequency common-mode currents generated by the two inverters are in phase, and they are superimposed and amplified in the common-mode circuit, forming... Figure 6 The high-frequency oscillation waveform shown.

[0078] When the PWM drive signal of one inverter (such as the second one) is delayed by T0, its common-mode voltage transition time is delayed by half a resonant cycle relative to the first inverter. At this time, when the resonant current induced by the common-mode voltage transition of the first inverter is at the trough of the oscillation waveform, the common-mode voltage of the second inverter happens to transition, and the resonant current induced by it is out of phase with the former. The two resonant common-mode currents are equal in magnitude and opposite in direction in the common-mode circuit, thus canceling each other out.

[0079] like Figure 7 As shown, after adopting the above-mentioned half-resonant periodic phase shift strategy, the high-frequency oscillation component in the common-mode voltage is significantly suppressed. This control strategy directly acts on the source of resonant noise, fundamentally eliminating the high-frequency common-mode noise caused by the resonance of parasitic capacitance and AC-side filter inductor.

[0080] Preferably, the delay of the three-phase output PWM waveform in step five is achieved by delaying the overall PWM drive signal of the inverter's power transistors; or by shifting the carrier phase; or by shifting the modulation wave phase. All three methods are well-known PWM phase-shifting techniques to those skilled in the art, and all can achieve the same delay effect. The specific method used can be flexibly selected based on the actual controller's hardware and software resources.

[0081] Preferably, the PWM control signals of the parallel inverters are uniformly generated and configured with phase difference by the same master controller; or a master-slave control architecture is adopted, in which the master outputs a synchronization reference signal, and the slave executes the phase shift of the delay T0 based on the synchronization reference signal. Both of the above control architectures can achieve the phase difference control required by the present invention, and the specific architecture adopted depends on the actual control scheme of the inverter system.

[0082] Preferably, the inverter system of the present invention is configured with a common-mode filter circuit (including but not limited to a DC-side common-mode inductor and an AC-side Y capacitor). The method of the present invention works synergistically with the common-mode filter circuit: the common-mode filter circuit is used to suppress the basic common-mode conducted interference at the inverter switching frequency, and the method of the present invention is used to eliminate the high-frequency common-mode noise generated by the resonance of parasitic capacitance and AC-side filter inductor. The two work together to suppress the common-mode conducted interference of the inverter to the outside world, which can further reduce the electromagnetic interference level of the whole machine and make it easier to meet the conducted emission limit standards.

[0083] Example 2

[0084] This invention also provides a parallel three-phase full-bridge inverter system for performing the high-frequency common-mode noise cancellation method described in Embodiment 1 above. Figures 1 to 5 As shown, the system includes an even number of three-phase full-bridge inverters, a common-mode filter circuit, and a control unit.

[0085] The AC sides of each three-phase full-bridge inverter are connected in parallel, and their DC sides are respectively connected to a common DC bus. A common-mode filter circuit is installed on the DC side and / or AC side of the inverter system to suppress common-mode conducted interference at the fundamental frequency. The control unit is connected to the power switch drive circuit of each three-phase full-bridge inverter. It has a pre-set control algorithm based on steps one to five of Embodiment 1, used to pair even-numbered inverters in pairs and, based on the equivalent common-mode inductance L... DM and parasitic capacitance C p A delay time T0 is determined, and PWM drive signals with a phase difference of T0 are output to the two inverters in each pair. The specific working process of the control unit in this embodiment is the same as that in Embodiment 1, and will not be repeated here.

[0086] While the specific embodiments of the present invention have been described in detail above, the present invention is not limited to the above embodiments. Within the scope of knowledge possessed by those skilled in the art, various changes can be made without departing from the spirit of the present invention, and modifications or variations without creative effort are still within the protection scope of the present invention.

Claims

1. A method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter, characterized in that, This method, applied to an inverter system consisting of an even number of three-phase full-bridge inverters connected in parallel on the AC side, is used to eliminate high-frequency common-mode noise generated by the resonance of parasitic capacitance between power devices and the chassis and the AC-side filter inductor, which is difficult for common-mode filter circuits to suppress effectively. The method includes the following steps: Step 1: Obtain the equivalent common-mode inductance L of the three-phase filter inductors on the AC side of each inverter. DM And the parasitic capacitance C between the power device and the chassis PE. p ; Step 2: According to the L DM and C p Calculate the LC resonant frequency f r : ； Step 3: Based on the resonant frequency f r The resonant period is obtained as T = 1 / f r We determine half a resonance period as the phase delay duration T0, that is: ； Step 4: Pair the even number of three-phase full-bridge inverters in pairs to form at least one inverter pairing group; Step 5: For each inverter pairing group, control the three-phase output PWM waveform of one inverter to be delayed by the time T0 relative to the other inverter, so that the resonant high-frequency common-mode current excited by the common-mode voltage jump of the two inverters is equal in magnitude and opposite in direction, and cancels each other in the common-mode circuit, thereby suppressing high-frequency common-mode noise.

2. The method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter according to claim 1, characterized in that: In step one, the equivalent common-mode inductance LDM of the AC-side three-phase filter inductor is obtained by equivalent calculation of the single-phase inductance value of the three-phase filter inductor in parallel. The calculation formula is as follows: ； Where L is the inductance value of the single-phase filter inductor on the AC side.

3. The method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter according to claim 1, characterized in that: In step one, the parasitic capacitance value C p The calculation formula is obtained through approximate calculation using a parallel-plate capacitor model: ； Where S is the contact area between the power device and the heat sink, d is the thickness of the insulating medium between the power device and the heat sink, and ε is the dielectric constant of the insulating medium.

4. The method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter according to claim 1, characterized in that: In step five, the delay of the three-phase output PWM waveform is achieved by delaying the entire PWM drive signal of the inverter's power transistors, or by carrier phase shifting and modulation wave phase shifting.

5. The method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter according to claim 1, characterized in that: The PWM control signals of the inverter pairing group are uniformly generated and configured with phase difference by the same master controller; or a master-slave control architecture is adopted, in which the master outputs a synchronization reference signal and the slave executes the phase shift of the delay T0 based on the synchronization reference signal.

6. The method for eliminating high-frequency common-mode noise in a parallel three-phase full-bridge inverter according to claim 1, characterized in that: The inverter system is equipped with a common-mode filter circuit, and the elimination method works in conjunction with the common-mode filter circuit to jointly suppress the common-mode conducted interference from the inverter to the outside world.

7. A parallel three-phase full-bridge inverter system for performing the elimination method as described in any one of claims 1 to 6, characterized in that, include: An even number of three-phase full-bridge inverters are connected in parallel on the AC side of each inverter. A common-mode filter circuit is installed on the DC side and / or AC side of the inverter system to suppress common-mode conducted interference. The control unit is connected to the drive circuit signal of each three-phase full-bridge inverter, and is used to pair the even-numbered three-phase full-bridge inverters in pairs, and according to the equivalent common-mode inductance L DM and parasitic capacitance C p Determine the delay time T0, and output a PWM drive signal with a phase difference of the delay time T0 to the two inverters in each pair.

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