Multi-mode bucket control circuit

Abstract

The application belongs to the technical field of integrated circuits, and specifically discloses a multi-mode valley lock control circuit, which comprises a controller, a transformer, an output rectifier circuit, a sampling feedback circuit, a power tube, a power supply diode and a power tube current sampling circuit, and the controller comprises an error amplifier, a comparator, a valley bottom latch circuit, a selector, a flip-flop and a driving circuit. In the application, the PWM signal in the demagnetization time is combined with the QR valley bottom through an OR logic, and then input to the clock end of the D flip-flop, so as to generate an integrated valley bottom signal InValley to replace the valley bottom signal Valley of the QR for valley bottom counting and latching, thereby realizing valley bottom smooth latching under QR and CCM multi-mode operation, solving the problem that no effective resonance valley bottom is available for identification under the CCM mode, and eliminating the influence of resonance waveform distortion on valley bottom counting.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and specifically to a multi-mode valley lock control circuit. Background Technology

[0002] Flyback switching power supplies, with their advantages of simple structure, isolation safety, and low cost, are widely used in small and medium power applications such as fast charging adapters, standby power supplies for home appliances, and industrial auxiliary power supplies. As global energy efficiency standards continue to upgrade, Level 7 energy efficiency and ultra-low standby power consumption targets place stringent requirements on the power supply's conversion efficiency under light load and wide voltage conditions. Traditional fixed-frequency PWM hard-switching solutions suffer from high turn-on losses and significant efficiency degradation under light loads. While conventional latch-free quasi-resonant (QR) control can achieve valley-level soft turn-on, frequent transitions between adjacent resonant valleys occur when the load and input voltage fluctuate slightly, leading to audio noise, excessive low-frequency output ripple, and loop oscillations. Therefore, valley-locking control has become the core optimization technology for quasi-resonant flyback power supplies.

[0003] The core advantages of valley switching are reflected in three aspects. First, it fixes the turn-on at a single resonant valley, continuously maintaining a near-zero voltage turn-on state, significantly reducing the turn-on overlap loss of the MOSFET. Compared with hard switching, the loss is reduced by more than 60%, and the efficiency is significantly improved over a wide input and light load range, easily meeting high energy efficiency specifications. Second, it eliminates the random frequency jumps caused by valley switching, stabilizes the switching spectrum, reduces the dv / dt variation amplitude, reduces the difficulty of conducting and radiated EMI filtering design, and reduces the size and cost of external filtering components. Third, it suppresses transformer core vibration caused by resonant valley switching, eliminating power supply noise at its source, while compressing the output voltage envelope ripple, improving the dynamic response stability of the load, and adapting to noise- and ripple-sensitive equipment such as fast charging and precision instrument power supplies.

[0004] To improve power density, flyback control chips are required to support automatic switching between CCM continuous conduction and QR quasi-resonant multi-mode operation. Mode switching relies on load weight and input voltage amplitude. However, valley-locking logic is inherently mismatched with the resonant characteristics of the two operating modes, exhibiting multiple inherent defects in cross-mode operation, mode critical points, and steady-state ranges. When the load increases, the circuit transitions from QR mode to CCM continuous conduction mode. The inductor's stored energy cannot be fully released during the switch-off cycle, resulting in no freewheeling current at the primary side and no complete resonant waveform at Vds. No effective valley can be identified, and the valley-locking detection circuit continues to execute valley sampling logic, failing to capture the effective valley signal, thus rendering the locking mechanism ineffective. When the load decreases, the circuit transitions from CCM mode to QR conduction mode. The circuit is in a transitional state between intermittent and continuous conduction, leading to severe distortion of the resonant waveform. The number of valleys may fluctuate between single and double valleys, causing valley-locking failure. Summary of the Invention

[0005] The purpose of this invention is to provide a multi-mode valley latch control circuit to achieve smooth valley latching under multiple operating modes such as QR and CCM. By performing an OR logic combination between the PWM signal (CCM mode) and the QR valley during the demagnetization time, the signal is input to the clock terminal of a D flip-flop. The reset terminal of the D flip-flop is connected to the narrow pulse signal of the falling edge of the QR valley, and the data terminal of the D flip-flop is connected to a high level. The D flip-flop generates an integrated valley signal InValley to replace the valley signal Valley of QR for valley counting and latching. This technical solution can solve the problem of no effective resonant valley available for identification in CCM mode, and also eliminate the influence of system distortion on valley counting caused by resonant waveform distortion, thereby achieving smooth valley latching and switching when the system operates in multiple modes such as CCM and QR.

[0006] The objective of this invention can be achieved through the following technical solutions: A multi-mode valley lock control circuit is used in a flyback switching power supply. The control circuit includes a controller, a transformer, an output rectifier circuit, a sampling feedback circuit, a power transistor, a power supply diode, and a power transistor current sampling circuit. The controller includes an error amplifier, a comparator, a valley latch circuit, a selector, a flip-flop, and a drive circuit. The two input terminals of the error amplifier are respectively connected to the first reference voltage source and the output voltage feedback signal FB. The output signal COMP of the error amplifier is used to adjust the duty cycle, peak current and switching frequency of the system. The first comparator is used to compare the output signal COMP of the error amplifier and the sawtooth wave signal SAW. When the output PWM signal of the first comparator is high, the drive voltage DRV is high after passing through the selector set trigger, and the power transistor is turned on. The second comparator is used to compare the output current feedback signal CS and the second reference voltage source. When the output RESET signal of the second comparator is high, the trigger is reset, the drive voltage DRV is low, and the power transistor is turned off. The third comparator is used to compare the output voltage feedback signal FB with the third reference voltage source, and generates a clock signal that is input to the valley latch circuit for valley counting. The valley bottom latch circuit generates a latch signal LOCK and a valley bottom conduction signal VOK; When the valley is not latched, the LOCK signal is low, and the selector selects the PWM signal of channel 0; Once the valley floor is locked, the LOCK signal goes high, and the selector selects the VOK signal of channel 1. When the valley is not latched, the power transistor is turned on by the PWM signal; when the valley is latched, the power transistor is turned on by the VOK signal. The PWM signal is connected to the valley latch circuit to identify the system operating mode. During the demagnetization time, if the PWM signal changes from low to high, it indicates that the system needs to enter the CCM operating mode. If the PWM signal remains low, it indicates that the system maintains the QR operating mode.

[0007] The valley latch circuit includes a first counter, a second counter, a third counter, a first latch, a second latch, a delay circuit, a first digital comparator, a second digital comparator, an analog-to-digital converter (AD), a digital-to-analog converter (DA), a first analog comparator, a second analog comparator, and logic gate circuits. The demagnetization time TDEM signal is generated by a D flip-flop. When the drive signal DRV changes from high to low, the TDEM signal changes from low to high. When the valley signal Valley of QR changes from low to high, the TDEM signal changes from high to low. When the TDEM signal is high, it indicates the demagnetization time. If the PWM signal changes from low to high during the demagnetization time TDEM, it indicates that the system is preparing to enter the CCM continuous operation mode.

[0008] The CCM signal and the valley signal Valley are ORed. When the output of the OR logic changes from low to high, the integrated valley signal InValley changes from low to high. When the valley signal Valley changes from high to low, the integrated valley signal InValley changes from high to low. The resulting integrated valley signal InValley replaces the valley signal Valley for valley counting and latching. When the CCM signal rises from low to high before the Valley signal, the system enters continuous switching mode. When the CCM signal remains low, the system enters QR switch mode.

[0009] The first counter is used to count the number of times the switch is turned on and off, and outputs the first latch control signal ENLATCH1 and the second latch control signal ENLATCH2. The second counter is used to count the number of resonant valleys and outputs the average number of valleys (AVG) per cycle.

[0010] When the control signal ENLATCH1 changes from low to high, the average valley number AVG per cycle is stored by the first latch; When the control signal ENLATCH2 changes from low to high, the average valley number AVG per cycle is stored by the second latch; The signal ENLATCH2 is input to the first digital comparator after passing through the delay circuit. When the delay signal ENDLY changes from low to high, the first digital comparator compares the values ​​of the first latch and the second latch. If the values ​​of the first latch and the second latch are not equal, the output signal LOCK of the first digital comparator is low. When the values ​​of the first latch and the second latch are equal, the output signal LOCK of the first digital comparator is high.

[0011] When the output signal LOCK of the first digital comparator goes high, the analog-to-digital converter AD samples and saves the output signal COMP of the error amplifier. The digital-to-analog converter DA generates a voltage window [COMP_AD-, COMP_AD+] with a range of about ±100mV based on the sampled voltage COMP_AD. When the dynamically changing output signal COMP of the error amplifier exceeds this voltage window, the first digital comparator is cleared and the LOCK signal level changes from high to low.

[0012] When the LOCK signal is high, the third counter counts the number of resonances in the current cycle. When the count value of the third counter is equal to the value of the second latch, the output VOK signal of the second digital comparator changes from low to high, controlling the power transistor to turn on. The third counter is cleared to zero cycle by cycle through the drive signal DRV.

[0013] As a further aspect of the present invention: to simplify the circuit, the number of consecutive N switching cycles can be set to a power of 2, such as the count value of the first counter being N=2. x The count value of the second counter is CNT=2. x+y Where x and y are positive integers, therefore the average value AVG = 2. y , which corresponds to the high y bit of the counter.

[0014] The beneficial effects of this invention are as follows: This invention combines the PWM signal and the QR valley during the demagnetization time with an OR logic combination and inputs it to the clock terminal of the D flip-flop to generate an integrated valley signal InValley to replace the QR valley signal Valley for valley counting and latching. This achieves smooth valley latching under QR and CCM multi-mode operation, solves the problem of no effective resonant valley available for identification in CCM mode, and eliminates the influence of resonant waveform distortion on valley counting. Attached Figure Description

[0015] The invention will now be further described with reference to the accompanying drawings.

[0016] Figure 1 This is a typical application circuit of the switching power supply of the present invention; Figure 2 This is the schematic diagram of the control circuit of this invention; Figure 3This invention relates to a multi-mode valley lock control circuit.

[0017] In the diagram: U101, control circuit; U201, Error Amplifier; U202, First Comparator; U203, Second Comparator; U204, Master Control Flip-Flop; U205, Driver Circuit; U206, Third Comparator; U207, Valley Latch Circuit; U208, Selector; U502, First Counter; U503, Second Counter; U504, Third Counter; U505, First Latch; U506, Second Latch; U507, Delay Circuit; U508, First Digital Comparator; U509, Second Digital Comparator; U511, Analog-to-Digital Converter (AD); U512, Digital-to-Analog Converter (DA); U513, First Analog Comparator; U514, Second Analog Comparator; U515, NOR Gate; U521, AND Gate; U522, OR Gate; U523, First D Flip-Flop; U524, Falling Edge Pulse Generator I; U525, Second D Flip-Flop; U526, Falling Edge Pulse Generator II; U527, Rising Edge Pulse Generator. Detailed Implementation

[0018] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0019] Figure 1 This is a typical application circuit for a switching power supply, including: control circuit U101, transformer T1, output rectifier circuit R1, sampling feedback circuits R_FB1 and R_FB2, power transistor M1, and power transistor current sampling circuit R_CS, wherein the power transistor is connected to the primary winding, the output rectifier circuit is connected to the secondary winding, and the feedback circuit is connected to the auxiliary winding.

[0020] Figure 2 This is a schematic diagram of the control circuit of the present invention, including: error amplifier U201, first comparator U202, second comparator U203, third comparator U206, selector U208, master control trigger U204, valley latch circuit U207, and drive circuit U205. The positive terminal of the error amplifier U201 is connected to the first reference voltage source V1, and the negative terminal of the error amplifier U201 is connected to the feedback signal FB of the voltage divider resistors R_FB1 and R_FB2. The positive terminal of the first comparator U202 is connected to the output terminal of the error amplifier U201, and the negative terminal of the first comparator U202 is connected to the sawtooth wave signal. Channel 0 of selector U208 is connected to the output of first comparator U202, channel 1 of selector U208 is connected to the VOK terminal of valley latch circuit U207, and the control terminal of selector U208 is connected to the LOCK terminal of valley latch circuit U207. The set terminal S of the master control flip-flop U204 is connected to the output terminal of the selector U208, and the reset terminal R of the master control flip-flop U204 is connected to the output of the second comparator U203.

[0021] The positive and negative terminals of the second comparator U203 are connected to the aforementioned current sampling circuit R_CS and the second reference voltage source V2, respectively. The output terminal Q of the master control trigger U204 is connected to the drive circuit U205, and the output of the drive circuit U205 is connected to the gate of the power transistor M1 mentioned above. The input terminals of the valley latch circuit U207 are connected to the output of the error amplifier U201, the output of the driver circuit U205, and the output of the third comparator U206, respectively. The positive and negative terminals of the third comparator U206 are connected to the third reference voltage source V3 and the feedback signal FB, respectively.

[0022] Before the valley is locked, the LOCK signal is low voltage, the selector U208 selects channel 0, and the switching of the power transistor is controlled by the PWM signal. After the valley bottom is locked, the LOCK signal is high voltage, the selector U208 selects channel 1, and the switching of the power transistor is controlled by the VOK signal; When the system load changes and exits valley lockout, the LOCK signal changes from high to low, selector U208 selects channel 0, and the power transistor switch returns to PWM signal control until valley lockout is restored.

[0023] The PWM signal is connected to the valley latch circuit U207 to identify the system operating mode. During the demagnetization time, if the PWM signal changes from low to high, it indicates that the system needs to enter the CCM operating mode. If the PWM signal remains low, it indicates that the system maintains the QR operating mode. Figure 3 It is a multi-mode valley lock control circuit, including a first counter U502, a second counter U503, a third counter U504, a first latch U505, a second latch U506, a delay circuit U507, a first digital comparator U508, a second digital comparator U509, an analog-to-digital converter (AD) U511, a digital-to-analog converter (DA) U512, a first analog comparator U513, a second analog comparator U514, and logic gate circuits; The PWM signal and the demagnetizing signal TDEM are ANDed through AND gate U521 to generate the CCM signal, which is ORed through OR gate U522 and output to the clock terminal of the first D flip-flop U523. The reset terminal of the first D flip-flop U523 is connected to the output of the falling edge pulse generator U524 of the valley signal. The first D flip-flop U523 outputs an integrated valley signal InValley, which is connected to the second counter U503 and the third counter U504; The TDEM signal mentioned above is generated by the second D flip-flop U525. The clock terminal of the second D flip-flop U525 is connected to the output of the falling edge pulse generator U526 of the drive signal DRV, and the reset terminal of the second D flip-flop U525 is connected to the output of the rising edge pulse generator U527 of the valley signal. The clock signal for the first counter is DRV, and the clock signals for the second counter U503 and the third counter U504 are the valley signal Valley after valley shaping. After N switching cycles, the first counter U502 generates the first latch U505 enable signal ENLATCH1, which latches the average value AVG of the number of resonances per cycle obtained by the second counter U503 into the first latch U505. Similarly, after the next N switching cycles, the first counter U502 generates the second latch U506 enable signal ENLATCH2, which latches the second counter U503's average value AVG of the number of resonances per cycle into the second latch U506. The second digital comparator U509 compares the values ​​after the average value AVG is latched into the second latch U506. The first digital comparator U508's enable signal ENDLY is delayed by several nanoseconds compared to the second latch U506's enable signal ENLATCH2.

[0024] When the values ​​of the first latch U505 and the second latch U506 are not equal, the valley lock indicator signal LOCK is low, and the above operation is repeated until lock is achieved.

[0025] When the values ​​of the first latch U505 and the second latch U506 are equal, the valley lockout indicator signal LOCK is high. The analog-to-digital converter AD U511 samples and holds the output signal COMP of the error amplifier U201, and then transmits the signal through the digital-to-analog converter DA. U512 generates a voltage window [COMP_AD-, COMP_AD+] with a range of approximately ±100mV, which is connected to the positive terminal of the second analog comparator U514 and the negative terminal of the first analog comparator U513, respectively. The negative terminal of the second analog comparator U514 and the positive terminal of the first analog comparator U513 are both connected to the error amplifier U201 output signal COMP. When the dynamically changing COMP signal exceeds the above voltage window, if the COMP signal is greater than COMP_AD+, the first analog comparator U513 outputs a high level, or if the COMP signal is less than COMP_AD-, the second analog comparator U514 outputs a high level. When either the first analog comparator U513 or the second analog comparator U514 outputs a high level, and the NOR gate U515 outputs a low level, the first digital comparator U508 is cleared, the LOCK signal level changes from high to low, and the above locking operation continues.

[0026] When the dynamically changing COMP signal remains within the voltage window and the LOCK signal remains high, the third counter U504 counts the number of resonances in the current cycle. When the count value of the third counter U504 is equal to the value of the second latch U506, the output VOK signal of the second analog comparator U514 changes from low to high, controlling the power transistor to turn on. The third counter U504 is cleared to zero cycle by cycle through the drive signal DRV.

[0027] The foregoing has provided a detailed description of one embodiment of the present invention, but this description is merely a preferred embodiment and should not be construed as limiting the scope of the invention. All equivalent variations and modifications made within the scope of the claims of this invention should still fall within the patent coverage of this invention.

Claims

1. A multi-mode valley lock control circuit, characterized in that, In a flyback switching power supply, the control circuit includes a controller, a transformer, an output rectifier circuit, a sampling feedback circuit, a power transistor, a power supply diode, and a power transistor current sampling circuit. The controller includes an error amplifier, a comparator, a valley latch circuit, a selector, a flip-flop, and a drive circuit. The two input terminals of the error amplifier are respectively connected to the first reference voltage source and the output voltage feedback signal FB. The output signal COMP of the error amplifier is used to adjust the duty cycle, peak current and switching frequency of the system. The first comparator is used to compare the output signal COMP of the error amplifier and the sawtooth wave signal SAW. When the output PWM signal of the first comparator is high, the drive voltage DRV is high after passing through the selector set trigger, and the power transistor is turned on. The second comparator is used to compare the output current feedback signal CS and the second reference voltage source. When the output RESET signal of the second comparator is high, the trigger is reset, the drive voltage DRV is low, and the power transistor is turned off. The third comparator is used to compare the output voltage feedback signal FB with the third reference voltage source, and generates a clock signal that is input to the valley latch circuit for valley counting. The valley bottom latch circuit generates a latch signal LOCK and a valley bottom conduction signal VOK; When the valley is not latched, the LOCK signal is low, and the selector selects the PWM signal of channel 0; Once the valley floor is locked, the LOCK signal goes high, and the selector selects the VOK signal of channel 1. When the valley is not latched, the power transistor is turned on by the PWM signal; when the valley is latched, the power transistor is turned on by the VOK signal. The PWM signal is connected to the valley latch circuit to identify the system operating mode. During the demagnetization time, if the PWM signal changes from low to high, it indicates that the system needs to enter the CCM operating mode. If the PWM signal remains low, it indicates that the system maintains the QR operating mode. By combining the PWM signal and the QR valley during the demagnetization time using an OR logic combination, the signal is input to the clock terminal of the D flip-flop. The reset terminal of the D flip-flop is connected to the narrow pulse signal of the falling edge of the QR valley, and the data terminal of the D flip-flop is connected to a high level. The D flip-flop generates an integrated valley signal InValley to replace the QR valley signal Valley for valley counting and latching.

2. The multi-mode valley lock control circuit according to claim 1, characterized in that, The valley latch circuit includes a first counter, a second counter, a third counter, a first latch, a second latch, a delay circuit, a first digital comparator, a second digital comparator, an analog-to-digital converter (AD), a digital-to-analog converter (DA), a first analog comparator, a second analog comparator, and logic gate circuits.

3. The multi-mode valley lock control circuit according to claim 2, characterized in that, The demagnetization time TDEM signal is generated by a D flip-flop. When the drive signal DRV changes from high to low, the TDEM signal changes from low to high. When the valley signal of QR changes from low to high, the TDEM signal changes from high to low. When the TDEM signal is high, it indicates the demagnetization time. If a PWM signal changes from low to high during the demagnetization time TDEM, the system is ready to enter the CCM continuous operation mode.

4. The multi-mode valley lock control circuit according to claim 3, characterized in that, The CCM signal and the valley signal are ORed. When the output of the OR logic changes from low to high, the integrated valley signal InValley changes from low to high. When the valley signal Valley changes from high to low, the integrated valley signal InValley changes from high to low. The resulting integrated valley signal InValley replaces the valley signal Valley for valley counting and latching. When the CCM signal rises from low to high before the Valley signal, the system enters continuous switching mode. When the CCM signal remains low, the system enters QR switch mode.

5. The multi-mode valley lock control circuit according to claim 2, characterized in that, The first counter is used to count the number of times the switch is turned on and off, and outputs the first latch control signal ENLATCH1 and the second latch control signal ENLATCH2. The second counter is used to count the number of resonant valleys and outputs the average number of valleys (AVG) per cycle.

6. The multi-mode valley lock control circuit according to claim 5, characterized in that, When the control signal ENLATCH1 changes from low to high, the average valley number AVG per cycle is stored by the first latch; When the control signal ENLATCH2 changes from low to high, the average valley number AVG per cycle is stored by the second latch; After passing through a delay circuit, the signal ENLATCH2 is input to the first digital comparator. When the delay signal ENDLY changes from low to high, the first digital comparator compares the values ​​of the first latch and the second latch. If the values ​​of the first latch and the second latch are not equal, then the output signal LOCK of the first digital comparator will be low. If the values ​​of the first latch and the second latch are equal, the output signal LOCK of the first digital comparator is high.

7. The multi-mode valley lock control circuit according to claim 6, characterized in that, If the output signal LOCK of the first digital comparator goes high, the analog-to-digital converter AD samples and saves the output signal COMP of the error amplifier. The digital-to-analog converter DA generates a voltage window [COMP_AD-, COMP_AD+] with a range of about ±100mV based on the sampled voltage COMP_AD. If the dynamically changing error amplifier output signal COMP exceeds the voltage window, the first digital comparator is cleared, and the LOCK signal level changes from high to low.

8. The multi-mode valley lock control circuit according to claim 7, characterized in that, When the LOCK signal is high, the third counter counts the number of resonances in the current cycle. When the count value of the third counter is equal to the value of the second latch, the second digital comparator outputs the VOK signal from low to high, controlling the power transistor to turn on.

9. The multi-mode valley lock control circuit according to claim 8, characterized in that, The third counter is cleared to zero cycle by cycle using the drive signal DRV.

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