A processing method of a ring oscillator based analog front end

Abstract

The present application relates to the field of chip technology, in particular to a processing method of an analog front end based on a ring oscillator. The amplifier of the analog front end comprises a structure in which n inverters are connected in parallel, the ring oscillator comprises a structure in which p inverter units are connected end to end in series to form a ring, each inverter unit comprises a structure in which n inverters are connected in parallel, and the inverters used in the ring oscillator and the amplifier have the same structure and process corner; the method comprises: setting an initial value of a target variable k to n; acquiring an output frequency fk of the ring oscillator when k inverters are turned on in a single inverter unit during chip operation; if fk is greater than a target frequency f0, updating k to k-1, and proceeding to the previous step until fk ≤ f0; if fk is less than f0, controlling that k+1 inverters in the amplifier of the analog front end are in an on state and n-k-1 inverters are in an off state during chip operation. The present invention can reduce the power consumption of the analog front end.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a processing method for an analog front-end based on a ring oscillator. Background Technology

[0002] With Moore's Law gradually slowing down, chiplet technology has become a crucial path for continuously improving the integration and computing power of system-on-a-chip (SoC). Low power consumption is one of the core indicators of chiplet technology. Reducing power consumption can not only significantly improve the integration density of chipslets but also expand their applicability in various application scenarios. The typical chiplet interconnect protocol standard UCIe (Universal Chiplet Interconnect Express) sets clear requirements for power consumption. For example, when using advanced packaging, the target power consumption is 0.6pj / bit at a 0.7V supply voltage.

[0003] In traditional serializer / deserializer (SerDes) analog front-end (AFE) design, to account for process variations in integrated circuit manufacturing and ensure performance specifications are met across all process corners, circuit parameters (e.g., the control word of the amplifier in the analog front-end) are typically configured based on the lower performance limit of the slower process corners. However, in actual production, the process corner corresponding to the chip may not be a slow process corner. This approach leads to unnecessary power consumption in the receiver's analog front-end (i.e., the SerDes analog front-end) under actual operating conditions, resulting in wasted power. Summary of the Invention

[0004] The purpose of this invention is to provide a processing method for an analog front-end based on a ring oscillator, so as to solve the problem of power consumption waste in the analog front-end of the receiving end.

[0005] According to the present invention, a processing method for an analog front-end based on a ring oscillator is provided. The analog front-end is an analog front-end of a receiving end. The ring oscillator and the analog front-end are located in the same chip. The amplifier of the analog front-end includes a structure of n inverters connected in parallel. The ring oscillator includes a structure of p inverter units connected in series to form a ring. Each inverter unit includes a structure of n inverters connected in parallel. The ring oscillator and the amplifier use the same inverter structure and process angle. n is the number of inverters included in the amplifier, and p is the number of inverter units included in the ring oscillator. The processing method includes: S100, set the initial value of the target variable k to n.

[0006] S200, obtain the output frequency fk of the ring oscillator when k inverters are turned on in a single inverter unit during chip operation.

[0007] S300: if fk is greater than the target frequency f0, update k to k-1, and proceed to S200 until fk≤f0, then proceed to S400.

[0008] S400: if fk=f0, during operation of the control chip, k inverters in the amplifier of the analog front end are in an on state and n-k inverters are in an off state; if fk<f0, during operation of the control chip, k+1 inverters in the amplifier of the analog front end are in an on state and n-k-1 inverters are in an off state.

[0009] Compared with the prior art, the present invention has at least the following beneficial effects: In the present invention, a ring oscillator is additionally arranged in the chip where the analog front end of a receiving end is located, and the ring oscillator is additionally arranged specifically for solving the problem of power waste of the analog front end of the receiving end; the amplifier of the analog front end comprises a structure in which n inverters are connected in parallel, the ring oscillator comprises a structure in which p inverter units are connected end to end in series to form a ring, each inverter unit comprises a structure in which n inverters are connected in parallel, and the inverters adopted by the ring oscillator and the amplifier have the same structure and process corner; since the oscillation frequency of the ring oscillator is proportional to transconductance, and the high-frequency characteristic of the analog front end is proportional to transconductance, the oscillation frequency of the ring oscillator is positively correlated with the high-frequency characteristic of the analog front end. On this basis, the present invention uses the oscillation frequency of the ring oscillator to determine the number of turned-on inverters in the amplifier of the analog front end, so that the analog front end turns on the minimum number of inverters under the condition of meeting performance, thereby eliminating the redundant power consumption of the analog front end and solving the problem of power waste existing in the analog front end of the receiving end in the prior art.

[0010] Moreover, a chip usually comprises a large number (e.g., dozens) of analog front ends, and the present invention can realize the on / off control of inverters in amplifiers of all analog front ends by arranging one ring oscillator, which can reduce a large amount of power consumption under the condition of small chip area overhead. Description of Drawings

[0011] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings required for the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention, and those skilled in the art can also obtain other drawings based on these drawings without creative efforts.

[0012] Figure 1 is a schematic structural diagram of an analog front end provided by an embodiment of the present invention; Figure 2 is a schematic structural diagram of a ring oscillator provided by an embodiment of the present invention; Figure 3 A flowchart illustrating the processing method of the analog front-end based on a ring oscillator provided in an embodiment of the present invention; Figure 4 This is a schematic diagram illustrating the mapping relationship between the output frequency of a ring oscillator at a certain process angle and the number of inverters turned on in a single inverter unit of the ring oscillator, provided for an embodiment of the present invention. Detailed Implementation

[0013] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0014] According to this embodiment, a processing method for an analog front-end based on a ring oscillator is provided. The analog front-end is the analog front-end of the receiving end. The ring oscillator and the analog front-end are located in the same chip. The amplifier of the analog front-end includes a structure of n inverters connected in parallel. The ring oscillator includes a structure of p inverter units connected in series to form a ring. Each inverter unit includes a structure of n inverters connected in parallel. The ring oscillator and the amplifier use the same structure and process angle for the inverters. n is the number of inverters included in the amplifier, and p is the number of inverter units included in the ring oscillator.

[0015] It should be understood that the process corners of different chips produced from the same design may differ, but the process corners of components within the same chip (such as inverters) are the same. The performance of the same component produced at different process corners will differ, for example, in terms of speed and power consumption.

[0016] As a specific implementation method, such as Figure 1 As shown, the analog front-end includes an amplifier and an active inductor, where the amplifier comprises a structure formed by n inverters connected in parallel. The bandwidth of the analog front-end can be changed by controlling the number of inverters in the amplifier that are in the on state. It should be understood that if m of the n inverters in the amplifier are in the on state and nm inverters are in the off state during chip operation, then the amplifier has m parallel branches connected and nm parallel branches disconnected. The larger the value of m, the larger the bandwidth of the analog front-end, but the higher the power consumption of the analog front-end.

[0017] like Figure 2As shown, the ring oscillator comprises a structure in which p inverter units are connected end-to-end in series to form a ring, where p is an odd number greater than or equal to 3; the p inverter units are inverter unit 1, inverter unit 2, ..., inverter unit p respectively. Each inverter unit in the ring oscillator unit comprises a structure of n inverters connected in parallel. The output frequency of the ring oscillator can be controlled by controlling the number of enabled inverters in a single inverter unit of the ring oscillator. The more enabled inverters are in a single inverter unit of the ring oscillator, the higher the output frequency of the ring oscillator will be. In this embodiment, the number of enabled inverters in different inverter units of the ring oscillator is the same.

[0018] In this embodiment, as Figure 3 shown, the processing method comprises: S100, set the initial value of the target variable k to n.

[0019] S200, obtain the output frequency fk of the ring oscillator when k inverters are enabled in a single inverter unit during the operation of the chip.

[0020] S300, if fk is greater than the target frequency f0, update k to k-1, and proceed to S200, until fk ≤ f0, then proceed to S400.

[0021] S400, if fk=f0, control k inverters to be in an enabled state and n-k inverters to be in a disabled state in the amplifier of the analog front-end during the operation of the chip; if fk<f0, control k+1 inverters to be in an enabled state and n-k-1 inverters to be in a disabled state in the amplifier of the analog front-end during the operation of the chip.

[0022] In this embodiment, f0 satisfies: no matter at which process corner the inverters in the ring oscillator are manufactured, when the number of enabled inverters in a single inverter unit corresponding to the output frequency f0 of the ring oscillator in simulation is taken as the number of enabled inverters in the amplifier of the analog front-end in simulation, the bandwidth of the analog front-end can meet the requirement. As a specific implementation, the acquisition process of f0 comprises: S010, acquire qi, which is the number of enabled inverters in a single inverter unit corresponding to the i-th process corner when the output frequency of the ring oscillator is a candidate frequency in simulation; the value range of i is from 1 to a, and a is the preset number of process corners.

[0023] As a specific implementation, the a process corners are typical process corner (TT), slow-slow process corner (SS), fast-fast process corner (FF), slow-fast process corner (SF) and fast-slow process corner (FS).

[0024] S020, obtain the bandwidth of the analog front-end when qi inverters are turned on in the amplifier of the analog front-end during the simulation process.

[0025] In this embodiment, during the simulation process, when the inverter in the ring oscillator is manufactured using the i-th process angle, the inverter in the amplifier at the simulation front end is also manufactured using the i-th process angle.

[0026] S030, if the bandwidth of the analog front end corresponding to process angle a meets the requirements when the output frequency of the ring oscillator is the candidate frequency, then the candidate frequency is determined as f0.

[0027] In this embodiment, the requirement that the bandwidth of the simulated front end meets the requirement means that the bandwidth of the simulated front end is greater than or equal to a preset bandwidth threshold. This bandwidth threshold corresponds to the minimum bandwidth required for the simulated front end to drive its subsequent load to work normally.

[0028] As a specific implementation, if there are multiple candidate frequencies, and each of these candidate frequencies can be determined as f0 after passing through S010-S030, then the minimum frequency among these candidate frequencies can be determined as f0, thereby reducing the loss while ensuring that the bandwidth of the analog front end meets the requirements.

[0029] In this embodiment, n satisfies the following condition: when the number of inverters in a single inverter unit of the ring oscillator is n, if the inverters are manufactured using a slow-slow process angle, then when all n inverters in a single inverter unit of the ring oscillator are turned on, the output frequency of the ring oscillator is the target frequency. As a specific implementation, the process of obtaining n includes: S110; Obtain the mapping relationship between the output frequency of the ring oscillator and the number of inverters turned on in a single inverter unit of the ring oscillator under different process angles during the simulation.

[0030] like Figure 4 As shown, the vertical axis represents frequency, which gradually increases as the vertical axis extends; the horizontal axis represents the number of inverters in a single inverter unit, which gradually decreases as the horizontal axis extends. With a fixed process angle, the output frequency of the ring oscillator is positively correlated with the number of inverters in a single inverter unit within the ring oscillator. That is, as the number of inverters in a single inverter unit in the ring oscillator gradually decreases, the output frequency of the ring oscillator also gradually decreases.

[0031] S120, based on the mapping relationship, obtain the number of inverters turned on in a single inverter unit when the output frequency of the ring oscillator is the target frequency under different process angles.

[0032] S130, the maximum number of inverters turned on in a single inverter unit corresponding to all process corners is determined as n.

[0033] For example, there are 5 process corners in total. When the output frequency of the ring oscillator under the 1st, 2nd, 3rd, 4th and 5th process corners is the target frequency, the numbers of enabled inverters in a single inverter unit are 7, 9, 6, 8 and 5 respectively, thus n is 9.

[0034] As a specific embodiment, the analog front end further comprises an active inductor, the active inductor is configured to increase the bandwidth of the analog front end; the analog front end further comprises an active inductor, the inverters adopted by the ring oscillator and the active inductor have the same structure and the same process corner, and the number of inverters comprised in the active inductor is n. The structure of the active inductor is as follows: a resistor is connected between the input end and the output end of n parallel-connected inverters. If m inverters among the n inverters of the active inductor are in an enabled state and n-m inverters are in a disabled state during the operation of the chip, the active inductor during the operation of the chip has m parallel branches connected and n-m parallel branches disconnected, that is, the structure becomes that a resistor is connected between the input end and the output end of m parallel-connected inverters. In this specific embodiment, step S020 in the acquisition process of f0 is replaced with: acquiring the bandwidth of the analog front end when qi inverters are enabled in both the amplifier and the active inductor of the analog front end during simulation.

[0035] As a specific embodiment, S400 further comprises: if fk=f0, controlling k inverters to be in an enabled state and n-k inverters to be in a disabled state in the active inductor of the analog front end during the operation of the chip; if fk<f0, controlling k+1 inverters to be in an enabled state and n-k-1 inverters to be in a disabled state in the active inductor of the analog front end during the operation of the chip.

[0036] In this embodiment, a ring oscillator is additionally arranged in the chip where the analog front end of the receiving end is located, and the ring oscillator is additionally arranged specifically for solving the problem of power waste of the analog front end at the receiving end; the amplifier of the analog front end comprises a structure of n parallel-connected inverters, the ring oscillator comprises a structure where p inverter units are connected end to end in series to form a ring, each inverter unit comprises a structure of n parallel-connected inverters, and the inverters adopted by the ring oscillator and the amplifier have the same structure and the same process corner; since the oscillation frequency of the ring oscillator is proportional to the transconductance, and the high-frequency characteristic of the analog front end is proportional to the transconductance, the oscillation frequency of the ring oscillator is positively correlated with the high-frequency characteristic of the analog front end. On this basis, the present embodiment determines the number of enabled inverters in the amplifier of the analog front end by using the oscillation frequency of the ring oscillator, so that the analog front end enables the minimum number of inverters under the condition of meeting performance requirements, thereby eliminating the redundant power consumption of the analog front end and solving the problem of power waste existing in the analog front end of the receiving end in the prior art.

[0037] Moreover, chips typically include a large number (e.g., dozens) of analog front-ends. This invention can control the on / off state of the inverter units in the amplifiers of all analog front-ends by setting a ring oscillator, thereby reducing power consumption while minimizing chip area overhead.

[0038] While specific embodiments of the invention have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of the invention. It should also be understood that various modifications can be made to the embodiments without departing from the scope and spirit of the invention. The scope of the invention is defined by the appended claims.

Claims

1. A processing method for an analog front-end based on a ring oscillator, characterized in that, The analog front end is the analog front end of a receiving end, the ring oscillator and the analog front end are located in the same chip, the amplifier of the analog front end comprises a structure in which n inverters are connected in parallel, the ring oscillator comprises a structure in which p inverter units are connected end to end in series to form a ring, each inverter unit comprises a structure in which n inverters are connected in parallel, the inverters adopted by the ring oscillator and the amplifier have the same structure and process corner, n is the number of inverters included in the amplifier, and p is the number of inverter units included in the ring oscillator; the processing method comprises: S100, setting an initial value of a target variable k as n; S200, acquiring an output frequency fk of the ring oscillator when k inverters are turned on in a single inverter unit during chip operation; S300, if fk is greater than a target frequency f0, updating k to k-1, and proceeding to S200 until fk ≤ f0, and proceeding to S400; S400, if fk = f0, controlling k inverters in the amplifier of the analog front end to be in an on state and n-k inverters to be in an off state during chip operation; if fk < f0, controlling k+1 inverters in the amplifier of the analog front end to be in an on state and n-k-1 inverters to be in an off state during chip operation.

2. The processing method for the analog front-end based on a ring oscillator according to claim 1, characterized in that, The acquisition process of f0 comprises: S010, acquiring the number qi of inverters turned on in a single inverter unit corresponding to the i-th process corner when the output frequency of the ring oscillator is a candidate frequency during simulation; the value range of i is from 1 to a, and a is the preset number of process corners; S020, acquiring the bandwidth of the analog front end when qi inverters are turned on in the amplifier of the analog front end during simulation; S030, if the bandwidths of the analog front end corresponding to a types of process corners all meet requirements when the output frequency of the ring oscillator is the candidate frequency, determining the candidate frequency as f0.

3. The processing method for the analog front-end based on a ring oscillator according to claim 1, characterized in that, The acquisition process of n comprises: S110; acquiring the mapping relationship between the output frequency of the ring oscillator and the number of inverters turned on in a single inverter unit of the ring oscillator under different process corners during simulation; S120, acquiring, according to the mapping relationship, the number of inverters turned on in a single inverter unit corresponding to when the output frequency of the ring oscillator is the target frequency under different process corners; S130, determining the maximum value of the number of inverters turned on in a single inverter unit corresponding to all process corners as n.

4. The processing method for the analog front-end based on a ring oscillator according to claim 2, characterized in that, The a types of process corners are typical process corner, slow-slow process corner, fast-fast process corner, slow-fast process corner and fast-slow process corner.

5. The processing method for the analog front-end based on a ring oscillator according to claim 2, characterized in that, The analog front end further comprises an active inductor, the inverters adopted by the ring oscillator and the active inductor have the same structure and process corner, and the number of inverters included in the active inductor is n.

6. The processing method for the analog front-end based on a ring oscillator according to claim 5, characterized in that, Replacing S020 with: acquiring the bandwidth of the analog front end when qi inverters are turned on in both the amplifier and the active inductor of the analog front end during simulation.

7. The processing method for the analog front-end based on a ring oscillator according to claim 6, characterized in that, S400 further comprises: if fk=f0, controlling k inverters in the active inductor of the analog front end to be in an on state and n-k inverters to be in an off state during the operation of the chip; if fk<f0, controlling k+1 inverters in the active inductor of the analog front end to be in an on state and n-k-1 inverters to be in an off state during the operation of the chip.

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