A pulse generation and control method for high frequency driving of a neutron tube

Abstract

The present application belongs to the technical field of neutron tube driving, and particularly relates to a pulse generation and control method for high-frequency driving of a neutron tube, comprising: inputting a main control clock signal into an N-stage series RC compensation network after frequency division, so that time constants are distributed in a gradient manner; comparing the output voltage of the current stage with a floating threshold value, and generating an edge shaping signal when the voltage exceeds the threshold value; determining a demarcation parameter M, performing an exclusive OR operation on the edge shaping signals of the first M stages and the edge shaping signals of the last N-M stages respectively according to odd and even stages, and then performing an NAND operation to synthesize a high-frequency driving pulse; when the cathode current deviates from a preset interval, adjusting the charge and discharge current of a pulse width control capacitor in a trailing edge timing branch to change the pulse width; and when the absolute value sum of compensation currents exceeds a set threshold value, increasing the frequency division ratio of a frequency divider to reduce the reference frequency. The present application can improve the pulse edge quality, adapt to load fluctuations, prevent waveform distortion in extreme working conditions, and ensure stable operation of the neutron tube.

Description

Technical Field

[0001] This invention relates to the field of neutron tube driving technology. More specifically, this invention relates to a pulse generation and control method for high-frequency driving of neutron tubes. Background Technology

[0002] The stable operation of a neutron tube relies on a high-quality, high-frequency drive pulse provided by the driving circuit, which directly controls the neutron emission timing and yield. Under high-frequency operating conditions, the effects of circuit parasitic parameters and the dynamic changes in the neutron tube's equivalent capacitive load can cause distortion of the drive pulse, mainly manifested as a gradual leading edge and a trailing edge. An insufficiently steep leading edge reduces ion extraction efficiency and increases device heat dissipation, while a trailing edge can cause space charge accumulation within the tube, thus affecting the stability of the neutron yield. Furthermore, during neutron tube operation, the cathode current is susceptible to drift due to factors such as ambient temperature and internal pressure fluctuations. This load change can inversely interfere with the pulse generation circuit, causing abnormal deviations in the pulse width and operating frequency of the drive pulse.

[0003] Existing technologies typically employ RC timing compensation circuits combined with comparators to achieve high-frequency pulse generation and shaping control. For example, Chinese patent document CN206149162U discloses a high-voltage pulse power supply for driving a neutron tube ion source in uranium mine logging. This power supply uses a CPLD control chip in conjunction with upper and lower bridge arm isolation drive circuits to generate high-voltage pulses. By optimizing the switching parameters of the MOSFET, the pulse rise edge width is controlled to 0.8μs and the fall edge width to 20ns, which can meet the basic driving requirements of a neutron tube ion source in uranium mine logging. However, this scheme uses a fixed switching parameter configuration and cannot adaptively compensate for the dynamic changes in the capacitive load of the neutron tube, resulting in significant waveform distortion under high-frequency heavy-load conditions.

[0004] Existing multi-stage RC compensation networks often employ fixed RC parameter configurations and constant comparison thresholds, which cannot adapt to the compensation requirements for timing differences between the leading and trailing edges of high-frequency pulses. When signal amplitude attenuation occurs during transmission in a multi-stage RC network, the fixed threshold can easily lead to comparator mis-triggers and edge jitter, thus affecting the accuracy of pulse synthesis. In the pulse shaping stage, existing technologies often use a single path to uniformly process both the leading and trailing edges, failing to simultaneously address the steepening of the leading edge and the absorption of the trailing edge, making it difficult to achieve ideal pulse edge quality.

[0005] Regarding load fluctuation compensation, existing technologies typically utilize current feedback loops to fine-tune the pulse width to offset the effects of load changes. However, this compensation method suffers from limited adjustment range. When the cathode current deviates significantly from the preset range, causing conventional charging and discharging current compensation to reach its limit, existing control logic cannot perform global adjustment at the system level. This can easily lead to waveform distortion under high-frequency heavy-load conditions due to insufficient charging and discharging of the RC network. Furthermore, it lacks a self-protection mechanism for reference frequency degradation under extreme conditions, making it difficult to guarantee the long-term stable operation of the neutron tube under complex operating conditions.

[0006] To address the problems in the existing technologies, such as fixed RC compensation parameters, lack of adaptive comparison threshold, insufficient coordination of leading and trailing edge shaping, and limited pulse width and frequency protection adjustment capabilities under cathode current fluctuations, this solution proposes a pulse generation and control method for high-frequency driving of neutron tubes. Summary of the Invention

[0007] To address the technical problems of pulse waveform distortion and insufficient load adaptability in existing neutron tube high-frequency drive schemes, this invention provides a pulse generation and control method for neutron tube high-frequency drive.

[0008] This invention provides a pulse generation and control method for high-frequency driving of neutron tubes, comprising: S1, dividing the main control clock signal and inputting it into an N-stage series RC compensation network, and configuring the RC time constants of each stage to have a gradient distribution by decreasing resistance and increasing capacitance; comparing the output voltage of each stage of the RC compensation network with a floating threshold, and triggering the generation of an edge shaping signal when the threshold is exceeded, wherein the floating threshold is obtained based on the product of the corresponding reference peak voltage and the weighting coefficient; S2, determining the grouping boundary parameter M based on the resistance configuration parameters of the RC compensation network, and XORing the odd-numbered and even-numbered edge shaping signals of the first M stages and the last NM stages respectively, and then XORing them with each other to generate the corresponding front-end synthesized signal and the rear-end synthesized signal. The first and second segments of the synthesized signal are combined, and then AND and NOT operations are performed on the synthesized signals to synthesize a high-frequency driving pulse. The high-frequency driving pulse is dual-shaped, with the leading edge path steepened by a differential clamping circuit, and the trailing edge path connected to a controlled variable impedance loop. The gate control voltage is taken from the DC component of the neutron tube cathode current sampling signal after low-pass filtering, and the cutoff frequency of the low-pass filter is proportional to the reciprocal of the final stage RC time constant. S3. When the cathode current of the neutron tube deviates from the preset range, the pulse width of the output pulse is adjusted by adjusting the charging and discharging current of the pulse width control capacitor in the trailing edge timing branch. When the sum of the absolute values ​​of the compensation current used to adjust the pulse width exceeds the set threshold, the division ratio of the frequency divider is increased to reduce the reference frequency.

[0009] This invention feeds a frequency-divided clock into a multi-stage RC network with decreasing resistance and increasing capacitance, resulting in a gradient distribution of the time constant to compensate for the transmission delay of the capacitive load of the neutron tube. The output of each stage is compared with a floating threshold based on a reference peak value and adaptive weighting coefficients to generate an edge-shaping signal, reducing the risk of false triggering caused by signal attenuation. Subsequently, the boundary point is determined based on the resistance parameters, and the parity level signals of the preceding and following stages are XORed with the non-synthesized high-frequency pulse. The leading edge is steepened by differential clamping, and the trailing edge is controlled by a controlled variable impedance loop controlled by cathode current feedback to improve the pulse edge morphology. When the cathode current deviates, the pulse width is adjusted, and the frequency is reduced for protection when the compensation current exceeds the limit, preventing waveform distortion caused by insufficient charging and discharging of the RC network, and improving pulse quality and system stability.

[0010] Preferably, the step of configuring the RC time constants of each stage by decreasing resistance and increasing capacitance to achieve a gradient distribution includes: calibrating the initial resistance value of the first-stage RC network, and calculating and configuring the resistance values ​​of subsequent stages by decreasing in a fixed proportion; setting the initial capacitance value of the first-stage RC network, and configuring the capacitance values ​​of subsequent stages by increasing in arithmetic steps; so that the RC time constants of each stage decrease monotonically from the first stage to the last stage.

[0011] By calibrating the initial resistance and capacitance values ​​of the first-stage RC network, the resistance of subsequent stages decreases by a fixed ratio, while the capacitance increases by a fixed difference, ensuring that the RC time constant of each stage monotonically decreases from the first stage to the last. This configuration can progressively compress the phase lag of signal transmission, effectively compensating for signal leading-edge distortion and delay caused by the high-voltage structure of the neutron tube and parasitic capacitance, thus guaranteeing the response speed of the pulse edge.

[0012] Preferably, in the floating threshold generation process, the steps for determining the reference peak voltage and candidate weighting coefficients include: real-time acquisition and latching of the reference peak voltages corresponding to each stage, wherein the reference peak voltage of the first-stage RC network is the peak voltage of the frequency-divided square wave reference signal or a preset reference peak voltage, and the reference peak voltages of the second to Nth-stage RC networks are the positive peak voltages of the output signals of the previous-stage RC network; and the candidate weighting coefficients are calculated according to the current network stage, with the following relationship:

[0013] in, For the first The candidate weighting coefficients corresponding to the level, Based on the weight constant, To decay step size, This is the lower limit clamping value. This refers to the RC network level number. This is the function for finding the maximum value.

[0014] Candidate weighting coefficients are calculated by linearly attenuating with the network level, and a lower limit clamping value is set so that the comparison threshold at each level decreases reasonably as the signal transmission depth increases. This method can adapt to the signal amplitude attenuation characteristics of multi-level RC networks, avoid the problem of missed triggering after signal attenuation due to fixed thresholds, and ensure that the thresholds are not too low to cause noise-induced false triggering.

[0015] Preferably, in the floating threshold generation process, the steps for correcting the actual weighting coefficients and triggering edge shaping include: calculating the amplitude transfer coefficient based on the peak value of the current RC network output and the corresponding reference peak value, and limiting the amplitude of the candidate weighting coefficients to obtain the actual weighting coefficients.

[0016] in, For the first The actual weighting coefficients corresponding to the RC network are This is the amplitude transfer coefficient for this level. A safety factor less than 1 To obtain the minimum value function, the corresponding reference peak voltage latched by the digital-to-analog converter is multiplied by the actual weighting coefficient. The resulting floating threshold voltage is connected to the inverting input of the comparator and compared with the output voltage of this stage connected to the non-inverting input. The comparator flips and outputs a high level, triggering a Schmitt trigger to generate an edge-shaping signal with a standard rising edge.

[0017] By limiting the candidate weighting coefficients using the amplitude transfer coefficient, the amplitude can be dynamically adapted to the actual attenuation of the signal amplitude, preventing missed triggering due to excessively high thresholds or noise interference due to excessively low thresholds. Combined with the generation of edge-shaping signals with standard rising edges by Schmitt triggers, the jitter during comparator flip-flops is effectively eliminated, providing a high-precision synchronization reference and reliable signal quality for subsequent high-frequency pulse synthesis.

[0018] Preferably, the calculation step of determining the group boundary parameter M includes: reading a preset safety reference common ratio constant, calculating the absolute value of the difference between the actual network configuration resistor ratio as the resistor configuration parameter and the safety reference common ratio constant; multiplying the absolute value of the difference by the total number of stages N, rounding the result down, and then superimposing the initial boundary reference value to perform boundary limiting to obtain the group boundary parameter M.

[0019] Preferably, the step of synthesizing the high-frequency drive pulse includes: inputting the edge shaping signals of each stage into a synchronous latch unit to complete retiming, and filtering out narrow pulse signals shorter than a preset minimum pulse width threshold; inputting the odd-numbered edge shaping signals and even-numbered edge shaping signals of stages 1 to M into a multi-input XOR gate array for operation, and outputting the front-end synthesized signal; inputting the odd-numbered edge shaping signals and even-numbered edge shaping signals of stages M+1 to N into a multi-input XOR gate array for operation, and outputting the back-end synthesized signal; inputting the front-end synthesized signal and the back-end synthesized signal simultaneously into a two-input NAND gate module for logical NAND operation, and then latching them through an output register to synthesize the high-frequency drive pulse.

[0020] The timing of each edge-shaping signal is re-timed by a synchronous latch unit to filter out narrow pulse interference shorter than the minimum pulse width threshold. Then, the preceding and following signals are subjected to parity-level XOR and NAND operations to synthesize a high-frequency drive pulse. This process ensures the synchronization of signals participating in the logic operation and can generate a high-frequency pulse sequence with stable duty cycle and low distortion.

[0021] Preferably, the leading edge path is steepened by a differential clamping circuit, including: in the leading edge path, a high-frequency driving pulse is connected in series with a pF-level high-frequency differential capacitor, and a Schottky diode connected in parallel to ground on one side, which shortens the pulse rise time through the differential effect, and the negative peak voltage generated by the differential is clamped to ground potential by the Schottky diode.

[0022] Preferably, the trailing edge path is connected to a controlled variable impedance circuit, comprising: connecting the drain and source of the MOS transistor in series as a variable resistor in the discharge circuit; acquiring the transient current signal flowing through the cathode side of the neutron tube using a current sensor; converting the transient current signal into a voltage signal and sending it to a low-pass filter to extract the DC component voltage; calculating the product of the resistance and capacitance of the final-stage RC network to obtain the final-stage RC time constant; setting the cutoff frequency of the low-pass filter according to the product of the reciprocal of the final-stage RC time constant and a set proportional coefficient, wherein the set proportional coefficient is less than 1; amplifying the extracted DC component voltage in reverse proportional mode and connecting it to the gate of the MOS transistor; adjusting the on-resistance of the MOS transistor according to the fluctuation of the neutron tube cathode current to change the falling slope of the pulse trailing edge.

[0023] By using the drain and source of the MOSFET as a variable resistor connected in series in the trailing edge discharge circuit, the DC component of the cathode current sampling signal after low-pass filtering is used to adjust the gate voltage of the MOSFET, thereby changing the on-resistance. The low-pass filter cutoff frequency is proportional to the reciprocal of the final stage RC time constant, ensuring that the feedback response speed matches the dynamic characteristics of the system, and realizing the adaptive adjustment of the pulse trailing edge falling slope.

[0024] Preferably, the step of adjusting the pulse width of the output pulse by adjusting the charging and discharging current of the pulse width control capacitor in the trailing edge timing branch includes: comparing the DC component voltage reflecting the actual cathode current with the set upper and lower threshold values ​​of the target cathode current in real time; when the actual cathode current is lower than the lower threshold value, calculating the difference between the two and multiplying it by a first gain coefficient to generate a pulse width widening control word, driving the adjustable constant current source to reduce the discharge current of the pulse width control capacitor in the trailing edge timing branch or providing a holding current, so as to delay the trailing edge turn-off time to widen the pulse width; when the actual cathode current is higher than the upper threshold value, calculating the difference between the two and multiplying it by a second gain coefficient to generate a pulse width compression control word, driving the adjustable constant current source to increase the discharge current of the pulse width control capacitor in the trailing edge timing branch or extracting a holding current, so as to advance the trailing edge turn-off time to compress the pulse width.

[0025] By monitoring the cathode current in real time and comparing it with a preset threshold, a corresponding pulse width control word is generated based on the current deviation. This word drives an adjustable constant current source to change the charging and discharging current of the pulse width control capacitor, thereby adjusting the trailing edge turn-off time. This bidirectional pulse width adjustment mechanism can quickly respond to cathode current fluctuations, allowing the current to return to the preset operating range and stabilizing neutron yield.

[0026] Preferably, increasing the division ratio of the frequency divider to reduce the reference frequency includes: calculating the sum of the absolute values ​​of the pulse width broadening compensation current and the pulse width compression compensation current in real time within the current control cycle through an accumulation register set internally in the system; comparing the sum of the absolute values ​​with the safety upper limit threshold, which is the set threshold, in real time; when the sum of the absolute values ​​exceeds the safety upper limit threshold for three consecutive control cycles, determining that the current system is in a compensation saturation edge state; triggering the frequency reduction protection program, sending a frequency division ratio increase instruction to the digital frequency reduction module, increasing the frequency division coefficient by one step to reduce the frequency of the main control clock signal.

[0027] By continuously monitoring the total absolute value of the compensation current over multiple cycles and actively adjusting the frequency division ratio, the saturation edge state of the system's feedback regulation capability can be accurately identified. This frequency reduction protection mechanism extends the absolute time of a single control cycle, providing more sufficient charging and discharging margins for multi-stage RC compensation networks and capacitive loads such as neutron tubes. This fundamentally prevents severe waveform distortion and drive runaway risks caused by insufficient charging and discharging under high-frequency extreme conditions, significantly improving the system's survivability under extreme conditions.

[0028] The technical solution of the present invention has the following beneficial technical effects: By constructing a multi-stage series RC compensation network with decreasing resistance and increasing capacitance, and setting a floating threshold using weighting coefficients that vary with the stage number and are limited by amplitude transfer coefficients, edge-shaping signals are generated at the output of each stage. Furthermore, the odd-even stage signals are grouped according to boundary parameters and subjected to XOR and NAND operations to synthesize a high-frequency drive pulse. The leading edge is then steepened by differential clamping, and the trailing edge is adjusted using variable impedance based on cathode current sampling feedback. Simultaneously, the charging and discharging current of the trailing edge timing branch is adjusted according to the degree of cathode current deviation to correct the pulse width. When the total compensation current exceeds the limit, the frequency division ratio is actively increased to lower the reference frequency. This invention improves the steepness of the driving pulse's leading edge and the quality of its trailing edge descent, suppresses space charge accumulation and heat dissipation, and can adaptively adapt to cathode current fluctuations to stabilize the pulse width. It also prevents waveform distortion caused by insufficient charging and discharging of the RC network under extreme conditions, thereby improving the long-term operational stability of the neutron tube's high-frequency drive. Attached Figure Description

[0029] Figure 1 This is a flowchart of a pulse generation and control method for high-frequency driving of neutron tubes; Figure 2 This is a schematic diagram comparing the driving pulse waveforms. Detailed Implementation

[0030] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0031] The specific embodiments of the present invention will now be described in detail with reference to the accompanying drawings.

[0032] This invention discloses a pulse generation and control method for high-frequency driving of neutron tubes, referring to... Figure 1 This includes the following steps: S1. The reference signal is fed into the gradient RC network and generates an edge-shaping signal.

[0033] This step first feeds the digitally down-converted square wave reference signal into a multi-stage cascaded RC network as the excitation source, and establishes a comparison reference at the output of each stage that dynamically adjusts according to the network attenuation. The purpose is twofold: firstly, to compensate for the phase lag of the signal in long links by using gradient changes in the RC parameters, thus mitigating the leading-edge distortion caused by the capacitive load of the neutron tube; and secondly, to suppress edge jitter and false triggering caused by signal attenuation by using a floating threshold that dynamically adjusts with the number of stages and is limited by the amplitude transfer coefficient. The specific steps are as follows: 1. Configuration of master clock and gradient RC network In this embodiment, a high-frequency master control clock signal is generated by the phase-locked loop IP core integrated inside the FPGA or DSP. The frequency division coefficient is then set to an integer variable by the digital down-conversion module, and a square wave reference signal with a duty cycle locked at 50% is output as the excitation source and fed into an N-stage series RC compensation network.

[0034] To achieve a gradient distribution of the RC time constant, the resistors at each stage can be configured by writing to the digital potentiometer array via the I2C bus, and the capacitors at each stage can be configured by writing to the programmable capacitor array via the SPI bus. The hardware parameters must satisfy the product relationship between adjacent stages: ; In the formula, , The first The actual resistance and capacitance values ​​of the stage network. After calibrating the initial parameters of the first stage, the resistance of each subsequent stage decreases stepwise according to a geometric progression with a fixed common ratio, and the capacitance increases stepwise according to an arithmetic progression with a fixed step size. This makes the RC time constant of each stage exhibit a strictly monotonically decreasing gradient distribution from the first stage to the last stage, in order to match the parasitic delay characteristics of the neutron tube.

[0035] To facilitate further understanding, the following is a specific hardware configuration example: This example uses a 4-stage series structure with N stages, a 50MHz main control clock, a frequency divider of 10, and outputs a 5MHz square wave reference signal with a 50% duty cycle; the components used are surface-mount resistors with an accuracy of ±1% and C0G ceramic capacitors with an accuracy of ±5%. First-stage resistor The primary capacitor is rated at 2kΩ. The calibration is 10 pF, corresponding to the first stage time constant. It is 20ns. With a common resistance ratio of 0.5 and a capacitance step size of 2pF, the following can be derived sequentially: 1kΩ 500Ω For 250Ω and 12pF, 14pF, With a time constant of 16pF, the four-level network has time constants of 20ns, 12ns, 7ns, and 4ns respectively. The product constraints between adjacent levels are satisfied, exhibiting obvious gradient decreasing characteristics, which can effectively compress the phase lag of each level.

[0036] 2. Generation of floating threshold and triggering of edge shaping signal A high-speed comparator is cascaded after each RC network node. The generation of the comparison threshold depends on the real-time capture of the reference peak voltage, which is specifically accomplished by a peak detection and hold circuit in conjunction with a high-speed ADC module. Specifically, the first stage uses the peak value of the frequency-divided square wave reference signal or a preset reference signal as a reference, while the second and subsequent stages use the positive peak value of the output signal of the previous stage network as a reference.

[0037] The processor calculates the candidate weighting coefficients in real time based on the current level, using the following formula: ; In the formula, For the first Candidate weighting coefficients for each level; These are the basic weight constants used to set the initial threshold reference surface; The decay step size determines the slope at which the threshold decreases with the number of levels; This is a lower limit clamping value to prevent false triggering caused by an excessively low threshold. This is the RC network series number, counting from 1. This is the function for finding the maximum value.

[0038] To prevent the threshold from reaching the actual signal peak due to attenuation mismatch, the candidate weighting coefficients need to be further corrected based on the actual attenuation at this stage. Specifically, the amplitude transfer coefficient is calculated based on the ratio of the peak output of this stage's RC network to the corresponding reference peak. The actual weighting coefficients are obtained based on the following formula: ; In the formula, For the first The actual weighting coefficients corresponding to the RC network; A safety factor less than 1; To find the minimum value function, a digital-to-analog converter is used to compare the latched reference peak voltage with the actual weighting coefficients. The components are multiplied to output a floating comparison threshold, which is then connected to the inverting input of a high-speed comparator. When the output voltage at the non-inverting input of the comparator rises above this floating threshold, the comparator flips to output a high level, thereby driving the subsequent Schmitt trigger to output an edge-shaped signal with a standardized rising edge. The hysteresis characteristic of the Schmitt trigger itself can further suppress thermal noise and metastable glitches, improving edge consistency and jitter resistance.

[0039] Following the aforementioned hardware configuration example, when taking , , At that time, it can be deduced that the second level is... Level 4 ; combining the amplitude transfer coefficient and safety factor of this level After limiting, the resulting weighted coefficients are fed into a 12-bit high-frequency digital-to-analog converter, such as the AD5628, whose output floating threshold voltage is fed into the inverting input of an ultra-high-speed comparator with a response delay as low as 1.5ns. With this processing, the trigger reference for each stage can be adaptively adjusted according to signal attenuation.

[0040] S2, logic synthesis and dual-channel independent shaping of high-frequency drive pulses.

[0041] This step first uses a boundary parameter M, automatically determined by the network attenuation, to group and cross-recombine the multi-stage shaped signals. Then, it physically shapes the leading and trailing edges of the synthesized high-frequency drive pulse. The purpose is twofold: firstly, to eliminate competition hazards and narrow pulse glitches caused by direct synthesis of signals with different attenuation depths; and secondly, to ensure that the shaping of the leading and trailing edges is independent and can be controlled separately through leading-edge differential steepening and trailing-edge variable impedance feedback. The specific steps are as follows: 1. Determination and logical synthesis of grouping boundary parameters Each edge-shaping signal first enters the synchronous latch unit to complete retiming within a unified clock domain, and then passes through minimum pulse width discrimination logic to filter out narrow pulses shorter than a preset threshold. The microcontroller reads a preset safety reference ratio constant from its internal Flash memory and retrieves the resistance ratio of the current hardware configuration, calculating the absolute value of the difference between the two. This absolute value is multiplied by the total number of stages N, rounded down, and then superimposed with a pre-calibrated initial boundary reference value, and then within the interval... Boundary limiting is performed within the signal range to obtain the grouping boundary parameter M, thereby preventing the signal set in the front or back segment from being empty.

[0042] Based on the obtained M value, the logic routing matrix distributes the edge-shaped signals from level 1 to level M to the first multi-input XOR gate array. The odd and even levels are then subjected to tree-like XOR operations followed by mutual XOR to obtain the front-end synthesized signal. Simultaneously, the edge-shaped signals from level M+1 to level N are fed into a structurally equivalent second multi-input XOR gate array to obtain the rear-end synthesized signal in the same manner. The front-end and rear-end synthesized signals are synchronously fed into a two-input NAND gate module after passing through equal-length traces to complete Boolean merging, and then latched by the output register to form a high-frequency driving pulse. The grouping and recombination logic based on the boundary parameter can place signals with different attenuation gradients in independent synthesis paths, significantly reducing the risk of race conditions and stabilizing the duty cycle of the synthesized pulse within the range of 20% to 80%.

[0043] Taking a specific scenario as an example, the preset safety reference common ratio constant is 0.5, and the total number of levels N is 10. If the current actual common ratio deviates from this constant, resulting in a calculated difference of 0.1, then 0.1 multiplied by 10 equals 1. This is rounded down to obtain the initial boundary value. After correction by the initial boundary benchmark and boundary limiting, the value M is obtained. When N is 16 levels and the actual common ratio deviates to a difference of 0.25, M can be deduced to be 4. This grouping mechanism ensures that the boundary point is determined entirely in real time by the steepness of the network decay gradient, without the need for manual intervention.

[0044] 2. Dual-channel independent shaping of high-frequency drive pulses The synthesized high-frequency drive pulse is split into a leading edge shaping path and a trailing edge control path before being output to the neutron tube gate.

[0045] In the leading edge path, a pF-level high-frequency ceramic capacitor with extremely low equivalent series resistance is connected in series along the microstrip line, and a low forward voltage drop Schottky diode is connected in parallel at its output node. The anode of the diode is grounded, and the cathode is connected to the output terminal of the capacitor. When the rising edge of the pulse arrives, this capacitor and the subsequent load together form an ultrafast differentiating network, which significantly compresses the pulse rise time. The Schottky diode clamps the negative peak voltage generated by the differentiation to ground potential, while discharging the peak current, thus completing the steepening of the leading edge.

[0046] In the trailing edge path, the drain-source channel of the MOSFET is connected in series as a linear variable resistor in the gate charge discharge circuit. A P-channel MOSFET can be used. A closed-loop Hall current sensor continuously monitors the transient emission current on the cathode side of the neutron tube. The Hall current sensor features non-contact measurement and fast response, making it suitable for high-frequency transient current monitoring. The acquired current signal is converted to voltage by a sampling resistor and then fed into an active low-pass filter to extract the DC component representing the beam current intensity. To ensure that the shaping bandwidth matches the dynamic characteristics of the final stage RC circuit, the cutoff frequency of the low-pass filter is set by multiplying the reciprocal of the final stage RC time constant by a proportionality coefficient less than 1. This cutoff frequency is positioned above the low-frequency response bandwidth required for cathode current feedback control and below the high-frequency drive pulse reference frequency. The extracted DC component voltage is amplified by an inverse proportional amplifier and applied to the MOSFET gate, thereby changing the MOSFET's on-resistance according to the real-time fluctuations of the cathode current, and thus adjusting the falling slope of the pulse trailing edge.

[0047] Following the previous example, the rising edge path uses a combination of a 4.7pF high-voltage ceramic capacitor and a BAT54S Schottky diode, which can steepen the original rise time of approximately 5ns to below 1.5ns. The trailing edge path uses a closed-loop Hall current sensor with a response bandwidth of 200kHz. When the final stage time constant is 4ns and the scaling factor is 0.0001, the low-pass filter cutoff frequency can be derived to be approximately 25kHz according to the above setting principle. At this cutoff frequency, if the sensor detects a beam current of approximately 40mA, the filter outputs a DC component of approximately 2V. After being amplified by an inverting amplifier, it outputs approximately -5V and applies it to the gate of the P-channel MOSFET. Once the cathode current increases, causing the DC component to increase, the negative voltage amplitude of the inverting amplifier deepens accordingly, the MOSFET channel conduction deepens further, the impedance drops to the order of several ohms, accelerating the discharge of parasitic charges, thereby performing nanosecond-level closed-loop trimming of the pulse trailing edge.

[0048] S3. Pulse width adjustment and anti-saturation frequency division control under cathode current feedback.

[0049] In addition to the aforementioned pulse generation and shaping mechanisms, this step constructs a global feedback loop targeting the neutron tube's terminal load state. Its purpose is to: fine-tune the pulse width by adjusting the charging and discharging current of the pulse width control capacitor in the trailing edge timing branch when the cathode current deviates from the preset range due to environmental and load drift; and proactively reduce the reference frequency before the pulse width compensation approaches its physical limit, avoiding waveform distortion caused by insufficient charging and discharging of the RC network. The specific steps are as follows: 1. Bidirectional constant current pulse width adjustment The microcontroller's non-volatile memory stores the upper and lower thresholds of the target cathode current corresponding to the stable neutron yield of the neutron tube. The system periodically polls the DC component voltage output of the low-pass filter and sends the actual cathode current represented by it to a hardware window comparator for real-time comparison with the upper and lower thresholds.

[0050] When the actual cathode current is below the lower threshold, the processor calculates the difference and multiplies it by a first gain coefficient to generate a pulse width widening control word. This drives the adjustable constant current source to reduce the discharge current of the pulse width control capacitor in the trailing edge timing branch, or provides a holding current to the capacitor, delaying the arrival time of the trailing edge turn-off threshold, thereby widening the driving pulse pulse width and increasing the single excitation duration to enhance beam intensity. Conversely, when the actual cathode current is above the upper threshold, the processor calculates the overshoot difference and multiplies it by a second gain coefficient to generate a pulse width compression control word. This drives the adjustable constant current source to increase the discharge current, or extracts the holding current of the capacitor, advancing the arrival time of the trailing edge turn-off threshold, thereby compressing the pulse width and forcing the cathode current back to the preset range. This bidirectional adjustment is achieved through a Howland current pump built from an operational amplifier and a transistor, which can complete beam intensity correction within tens of microsecond response cycles. The working sequence of bidirectional constant current pulse width compensation is as follows: when the cathode current is lower than the preset lower threshold, the system outputs a positive compensation current to delay the discharge of the pulse width control capacitor in order to widen the pulse width; when the cathode current is higher than the preset upper threshold, the system outputs a negative compensation current to accelerate the discharge of the pulse width control capacitor in order to compress the pulse width; when the cathode current returns to the preset working range, the compensation current automatically returns to zero.

[0051] Taking a typical operating condition as an example, the target cathode current range is set to 35mA to 45mA, and the control period is 10μs. When the cathode current is detected to drop to 30mA, the processor calculates the difference of 5mA, and after weighting by the first gain coefficient, generates a pulse width widening control word with a digital value of 10, which drives the constant current source to delay the capacitor discharge process, thus widening the pulse width by about 5ns to 15ns. When the cathode current is detected to rise to 50mA, the processor calculates the overshoot of 5mA, and after weighting by the second gain coefficient, generates a pulse width compression control word with a digital value of 7, which drives the constant current source to accelerate the capacitor discharge process, thereby shortening the high-level duration accordingly.

[0052] 2. Compensation current monitoring and anti-saturation frequency division To prevent residual charge accumulation and distortion caused by frequent compensation of large currents under high-frequency heavy loads, a 32-bit high-speed accumulator register is set up inside the system. At the end of each control cycle, the absolute values ​​of the pulse width broadening and pulse width compression compensation currents issued in that cycle are taken and summed. The sum of the absolute values ​​is compared in real time with a preset safety upper limit threshold for compensation current, and a multi-cycle confirmation mechanism is used to prevent misjudgment caused by transient spikes: only when the sum of the absolute values ​​exceeds the upper limit threshold for three consecutive control cycles does the state machine determine that the compensation margin of the current hardware RC network has been pushed to the limit, and the entire drive system is on the high-risk edge of compensation saturation.

[0053] Once the compensation saturation state is confirmed, the microcontroller's highest-priority non-maskable interrupt triggers the frequency reduction protection subroutine. The interrupt service routine modifies the prescaler register of the digital frequency reduction module in the main frequency clock link through the hardware abstraction layer interface, increasing the division coefficient by one integer step, thus proportionally reducing the frequency of the main control square wave reference signal. After the reference frequency decreases, each pulse period is correspondingly widened. The additional time margin obtained allows the pulse width control capacitors in each stage of the RC compensation network nodes and the trailing edge timing branch to complete full charging and discharging and voltage reset before the next pulse arrives, avoiding voltage drift and envelope distortion caused by residual charge accumulation.

[0054] Taking the aforementioned operating condition as an example, the control cycle is set to 1ms, and the safety upper limit threshold is calibrated to 2.5mA. Under normal operating conditions, the sum of the absolute values ​​of the compensation current within a single cycle is usually within the safe range of approximately 0.9mA. If the sum exceeds 2.5mA within three consecutive 1ms cycles, a frequency reduction interruption is triggered, and the frequency division coefficient is adjusted up by one level. The frequency of the main control reference signal is reduced from 5MHz to approximately 4.16MHz, corresponding to a square wave period extended from 200ns to 240ns. The additional 40ns time window is sufficient to ensure that the voltage of the cascaded RC node completes relaxation and reset before the next pulse arrives, significantly reducing the risk of distortion under high-frequency heavy loads.

[0055] To verify the actual effect of the present invention, a neutron tube of a certain type of accelerator with an equivalent parasitic capacitance of 85pF was selected as the test load. The main control clock was set to 50MHz and the frequency division coefficient was set to 10. The test instruments used were a 2GHz bandwidth high-speed digital oscilloscope and a closed-loop Hall current sensor with a response frequency of 200kHz. The ambient temperature was maintained at 25℃ and the test was run continuously for four hours.

[0056] The experiment was set up with three control groups: the control group used a traditional fixed threshold four-level mean RC compensation network without leading and trailing edge shaping circuits; the ablation group introduced a four-level RC network with RC gradient distribution and floating threshold edge shaping on the basis of the control group, but retained a fixed trailing edge impedance; the complete experimental group further added a differential clamping leading edge steepening circuit, a MOS transistor variable impedance trailing edge trimming based on cathode current feedback, and a bidirectional constant current pulse width compensation and anti-saturation frequency reduction synergistic mechanism on the basis of the ablation group.

[0057] like Figure 2 As shown, the control group had the smoothest rising and falling edges of the pulse, with severe gradual changes at the leading edge and trailing at the trailing edge; the ablation group showed a significant improvement in the edge quality of the pulse compared to the control group, but the trailing at the trailing edge problem was not effectively resolved; the complete experimental group had the steepest rising and falling edges of the pulse, the least edge distortion, and a more stable pulse width.

[0058] Test data shows that the overall parasitic delay in the control group was approximately 28 ns, with a rise time of 8.5 ns and a fall time tail of 12 ns. The cathode current drifted between 32 mA and 51 mA, and the neutron yield fluctuation rate was as high as 14%. The ablation group, by using a gradient RC network and comparing with a floating threshold, compressed the parasitic delay to 9 ns, optimized the rise time to 4.2 ns, maintained the fall time at 11 ns, and narrowed the cathode current fluctuation to 34 mA–48 mA. The complete experimental group, through the synergy of leading-edge differential clamping and trailing-edge closed-loop trimming, stably controlled the overall parasitic delay to within 4 ns, compressed the rise time to a maximum of 1.2 ns, shortened the fall time to 1.8 ns, and firmly locked the cathode current within the target range of 35 mA–45 mA. During continuous operation, no frequency reduction protection was triggered, and the neutron yield fluctuation rate was suppressed to below 2.5%. These comparisons verify the synergistic advantages of the proposed scheme in terms of driving delay, edge quality, and long-period beam stability.

[0059] The above description represents the preferred embodiments of the present invention. It should be noted that those skilled in the art can make various improvements and modifications without departing from the principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.

Claims

1. A pulse generation and control method for high-frequency driving of neutron tubes, characterized in that, include: S1. The main control clock signal is divided and input into an N-stage series RC compensation network. By configuring the resistor to decrease and the capacitor to increase, the RC time constant of each stage is gradient distributed. The output voltage of each stage of the RC compensation network is compared with the floating threshold. When the threshold is exceeded, an edge shaping signal is generated. The floating threshold is obtained by multiplying the corresponding reference peak voltage and the weighting coefficient. S2. The grouping boundary parameter M is determined based on the resistor configuration parameters of the RC compensation network. The edge shaping signals of the odd and even stages in the first M stages and the last NM stages are XORed and then XORed with each other to generate the front-end synthesized signal and the back-end synthesized signal. Then, the front-end and back-end synthesized signals are ANDed and NOTed to synthesize a high-frequency driving pulse. The high-frequency drive pulse is shaped in two ways. The leading edge path is steepened by a differential clamping circuit, and the trailing edge path is connected to a controlled variable impedance loop. The gate control voltage is taken from the DC component of the neutron tube cathode current sampling signal after low-pass filtering, and the cutoff frequency of the low-pass filter is proportional to the reciprocal of the final stage RC time constant. S3. When the cathode current of the neutron tube deviates from the preset range, the pulse width of the output pulse is adjusted by adjusting the charging and discharging current of the pulse width control capacitor in the trailing edge timing branch. When the sum of the absolute values ​​of the compensation currents used to adjust the pulse width exceeds the set threshold, the division ratio of the frequency divider is increased to reduce the reference frequency.

2. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The method of configuring the RC time constants of each stage by decreasing resistance and increasing capacitance to achieve a gradient distribution includes: calibrating the initial resistance value of the first-stage RC network, and calculating and configuring the resistance values ​​of subsequent stages by decreasing in a fixed proportion. Set the initial capacitance value of the first-stage RC network, and then gradually increase the capacitance values ​​of each subsequent stage in an arithmetic progression, so that the RC time constant of each stage decreases monotonically from the first stage to the last stage.

3. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The steps for determining the reference peak voltage and candidate weighting coefficients during the floating threshold generation process include: real-time acquisition and latching of the reference peak voltages corresponding to each stage, wherein the reference peak voltage of the first-stage RC network is the peak voltage of the frequency-divided square wave reference signal or a preset reference peak voltage, and the reference peak voltages of the second to Nth-stage RC networks are the positive peak voltages of the output signals of the previous-stage RC network; and the candidate weighting coefficients are calculated based on the current network stage, with the following relationship: in, For the first The candidate weighting coefficients corresponding to the level, Based on the weight constant, To decay step size, This is the lower limit clamping value. This refers to the RC network level number. This is the function for finding the maximum value.

4. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 3, characterized in that, The floating threshold generation process includes the following steps: correcting the actual weighting coefficients and triggering edge shaping: calculating the amplitude transfer coefficient based on the peak value of the current RC network output and the corresponding reference peak value, and limiting the amplitude of the candidate weighting coefficients to obtain the actual weighting coefficients. in, For the first The actual weighting coefficients corresponding to the RC network are This is the amplitude transfer coefficient for this level. A safety factor less than 1 The function is for finding the minimum value; The corresponding reference peak voltage latched by the digital-to-analog converter is multiplied by the actual weighting coefficient, and the resulting floating threshold voltage is connected to the inverting input of the comparator. It is compared with the output voltage of this stage connected to the non-inverting input. The comparator flips to output a high level, triggering a Schmitt trigger to generate an edge-shaping signal with a standard rising edge.

5. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The calculation steps for determining the group boundary parameter M include: reading a preset safety reference common ratio constant, and calculating the absolute value of the difference between the actual network configuration resistor ratio, which is the resistor configuration parameter, and the safety reference common ratio constant; Multiply the absolute value of the difference by the total number of levels N, round the result down, and then superimpose the initial boundary benchmark value to perform boundary limiting to obtain the grouping boundary parameter M.

6. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The steps of synthesizing high-frequency drive pulses include: inputting edge shaping signals at each stage into the synchronous latch unit to complete retiming, and filtering out narrow pulse signals shorter than the preset minimum pulse width threshold; The odd-level edge-shaping signals and even-level edge-shaping signals of levels 1 to M are respectively fed into a multi-input XOR gate array for operation, and the front-end synthesized signal is output. The odd-numbered edge-shaping signals and even-numbered edge-shaping signals from level M+1 to level N are respectively fed into a multi-input XOR gate array for operation, and the resulting composite signal is output. The front-end synthesized signal and the back-end synthesized signal are simultaneously input into two input NAND gate modules for logical NAND operations, and then latched by the output register to synthesize the high-frequency drive pulse.

7. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The leading edge path is steepened by a differential clamping circuit, which includes: in the leading edge path, a high-frequency driving pulse is connected in series with a pF-level high-frequency differential capacitor, and a Schottky diode connected in parallel to ground on one side. The pulse rise time is shortened by the differential effect, and the negative peak voltage generated by the differential is clamped to ground potential by the Schottky diode.

8. The pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The trailing edge path is connected to a controlled variable impedance circuit, including: connecting the drain and source of the MOS transistor in series as a variable resistor in the discharge circuit; acquiring the transient current signal flowing through the cathode side of the neutron tube using a current sensor; converting the transient current signal into a voltage signal and sending it to a low-pass filter to extract the DC component voltage; calculating the product of the resistance and capacitance of the final-stage RC network to obtain the final-stage RC time constant; setting the cutoff frequency of the low-pass filter according to the product of the reciprocal of the final-stage RC time constant and a set proportional coefficient, wherein the set proportional coefficient is less than 1; and connecting the extracted DC component voltage to the gate of the MOS transistor after inverting proportional amplification; adjusting the on-resistance of the MOS transistor according to the fluctuation of the neutron tube cathode current to change the falling slope of the pulse trailing edge.

9. A pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The method of adjusting the charging and discharging current of the capacitor in the pulse width control branch of the trailing edge timing circuit to adjust the pulse width of the output pulse includes: comparing the DC component voltage reflecting the actual cathode current with the set upper and lower limit thresholds of the target cathode current in real time. When the actual cathode current is lower than the lower threshold, the difference between the two is calculated and multiplied by the first gain coefficient to generate the pulse width widening control word. This drives the adjustable constant current source to reduce the discharge current of the pulse width control capacitor in the trailing edge timing branch or to provide a holding current, thereby delaying the trailing edge turn-off time to widen the pulse width. When the actual cathode current is higher than the upper limit threshold, the difference between the two is calculated and multiplied by the second gain coefficient to generate a pulse width compression control word. This word drives the adjustable constant current source to increase the discharge current of the pulse width control capacitor in the trailing edge timing branch or to extract the holding current, thereby advancing the trailing edge turn-off time to compress the pulse width.

10. A pulse generation and control method for high-frequency driving of a neutron tube according to claim 1, characterized in that, The method of increasing the division ratio of the frequency divider to reduce the reference frequency includes: calculating the sum of the absolute values ​​of the pulse width widening compensation current and the pulse width compression compensation current in the current control cycle in real time through the accumulation register set inside the system. The sum of absolute values ​​is compared with the safety upper limit threshold, which is the set threshold, in real time. When the sum of absolute values ​​exceeds the safety upper limit threshold for three consecutive control cycles, the current system is determined to be in the state of compensation saturation edge. The frequency reduction protection program is triggered, and a frequency division ratio increase command is sent to the digital frequency reduction module to increase the frequency division coefficient by one step, thereby reducing the frequency of the main control clock signal.

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