Parallel power device differentiated gate driving system and chip

Abstract

The application provides a parallel power device differentiated gate drive system and chip, comprising: a power supply module providing a bus voltage for a direct current bus; a drive control module generating a drive control signal; a first drive branch generating a first positive drive voltage and a first negative off voltage based on the bus voltage and generating a first drive signal under the control of the drive control module; a second drive branch generating a second positive drive voltage and a second negative off voltage based on the bus voltage and generating a second drive signal under the control of the drive control module; and a first power tube and a second power tube in parallel, the first power tube being controlled by the first drive signal, and the second power tube being controlled by the second drive signal. In the application of IGBT and SiC in parallel, only a single isolation auxiliary power supply is used to realize the differentiated gate voltage required by the two types of devices, and at the same time, the misoperation, oscillation and dynamic shunt imbalance caused by power supply coupling are reduced.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor driving technology, and in particular to a differentiated gate driving system and chip for parallel power devices. Background Technology

[0002] As power electronics technology advances towards high voltage, high power, and high efficiency, IGBTs and SiC MOSFETs are often used in parallel in applications such as electric vehicle traction inverters, rail transit converters, grid-connected converters for new energy power generation, and high-power industrial drives. This hybrid parallel topology leverages the advantages of IGBTs—high voltage withstand capability, high current carrying capacity, and mature reliability—combined with the advantages of SiC MOSFETs—high-frequency switching characteristics, low on-resistance, and low switching losses—thus demonstrating significant engineering value in balancing system reliability, cost, and efficiency.

[0003] However, there are fundamental differences in gate drive requirements between IGBTs and SiC MOSFETs. SiC MOSFETs typically have a turn-on voltage of 18V, while IGBTs have 15V. Furthermore, due to the higher transconductance and faster switching speed of SiC devices, applying an excessively deep negative voltage during turn-off, while enhancing noise immunity, can also increase turn-off overvoltage and oscillation risks. Therefore, a shallower negative voltage turn-off (e.g., -2V to -5V) or zero-voltage turn-off is generally recommended. In contrast, IGBTs are typically recommended to turn on at +15V and turn off at -8V to -10V. A deeper negative turn-off voltage helps maintain a reliable dead zone and prevents false turn-on during bridge arm commutation. Additionally, SiC MOSFETs, due to their thinner gate oxide layer and smaller input capacitance, are more susceptible to parasitic Miller capacitance coupling in high dv / dt commutation environments, leading to false turn-on. While the Miller plateau effect also exists in IGBTs, its threshold is higher and its switching speed is relatively slower, making it less sensitive to Miller interference than SiC.

[0004] The main shortcomings of the parallel drive scheme for IGBT and SiC are as follows:

[0005] First, the dual auxiliary power supply scheme. That is, each IGBT and SiC is equipped with an independent isolated auxiliary power supply, which generates a suitable gate drive voltage. The advantage of this scheme is that it can supply power to the two types of devices completely independently, and there is no power supply coupling problem. However, its disadvantages are also very obvious: (1) It requires two sets of isolated DC / DC converters and corresponding isolation transformers and rectifier filter circuits, which leads to a significant increase in the area of ​​the driver board; (2) The increase in the number of isolation transformers brings higher insulation design complexity, especially in high-voltage applications where safety spacing requirements need to be met; (3) The potential difference between the two power supplies may introduce additional common-mode interference; (4) The system cost and volume increase significantly, which is not conducive to the improvement of power density.

[0006] Second, the single auxiliary power supply direct sharing scheme. This involves using only one isolated auxiliary power supply, directly connecting the same set of positive and negative power supply buses to the power supply terminals of both the IGBT and SiC driver chips. The advantages of this scheme are its simple structure and low cost. However, this scheme has serious defects: (1) When the recommended gate voltages of IGBT and SiC are different, the shared power supply can only choose a certain voltage value as a compromise, which will cause at least one type of device to work under a non-optimal drive voltage, increasing its conduction loss or switching loss. For example, for the safety of IGBT, the turn-on voltage is +15V. For SiC, which is the optimal drive voltage of +18V, it will limit the increase of the on-resistance Rdson, greatly increasing the loss of SiC and limiting its current output capability; (2) When the two drive chips share the same power supply bus, the transient large current charging and discharging (gate charging / discharging pulse) of one drive chip will generate voltage drop and ringing on the power supply bus, which will be directly coupled to the output of the other drive chip, affecting the stability of its gate voltage and waveform quality; (3) In the high-frequency switching process of IGBT and SiC in parallel, the power supply coupling between the two gate drive circuits will lead to increased gate crosstalk, increasing the risk of false turn-on; (4) The shared power supply circuit impedance makes it impossible to optimize the two gate drives independently, making it difficult to take into account the different requirements of different devices for drive impedance and switching speed.

[0007] Third, some solutions attempt to adjust the gate voltage by adding a simple resistor divider network on the basis of a common power supply. However, this solution is difficult to meet the transient high current requirements of the power stage gate drive. The voltage drop across the divider resistor will fluctuate with the load current, and cannot provide a stable and accurate gate drive voltage.

[0008] In summary, existing technologies struggle to simultaneously meet all of the following requirements using only a single-channel isolated auxiliary power supply: (1) providing differentiated gate turn-on and turn-off voltages for IGBTs and SiC respectively; (2) ensuring the stability and transient response capability of each gate drive voltage; (3) reducing power supply coupling between the two drives; (4) suppressing gate crosstalk and false turn-on during parallel switching; (5) improving the dynamic current distribution of parallel devices; and (6) reducing system cost, size, and design complexity. Therefore, how to achieve the differentiated gate voltages required by the two types of devices using only a single-channel isolated auxiliary power supply in parallel IGBT and SiC applications, while simultaneously reducing malfunctions, oscillations, and dynamic shunt imbalances caused by power supply coupling, has become one of the urgent problems to be solved by those skilled in the art.

[0009] It should be noted that the above description of the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of the present invention and facilitating understanding by those skilled in the art. It should not be assumed that the above technical solutions are known to those skilled in the art simply because they have been described in the background section of this invention. Summary of the Invention

[0010] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a differentiated gate drive system and chip for parallel power devices, which solves the problems of high cost, large size, low power density, large switching loss and poor stability when IGBT and SiC are used in parallel.

[0011] To achieve the above and other related objectives, the present invention provides a parallel power device differentiated gate drive system, the parallel power device differentiated gate drive system comprising at least:

[0012] The power supply module, drive control module, first drive branch, second drive branch, first power transistor, and second power transistor, wherein the first power transistor is a SiC transistor and the second power transistor is an IGBT transistor;

[0013] The power module provides bus voltage to the DC bus;

[0014] The drive control module generates a drive control signal to control the first power transistor to turn on earlier than the second power transistor and to control the first power transistor to turn off later than the second power transistor.

[0015] The first drive branch is connected to the DC bus, generates a first positive drive voltage and a first negative turn-off voltage based on the bus voltage, and generates a first drive signal under the control of the drive control module.

[0016] The second drive branch is connected to the DC bus, generates a second positive drive voltage and a second negative turn-off voltage based on the bus voltage, and generates a second drive signal under the control of the drive control module.

[0017] The first power transistor and the second power transistor are connected in parallel. The first power transistor is controlled by the first drive signal, and the second power transistor is controlled by the second drive signal.

[0018] Optionally, the power module is an isolated DC-DC converter.

[0019] Optionally, the power module includes a transformer, a first diode, a second diode, a third diode, and a fourth diode;

[0020] The primary winding of the transformer receives the input voltage; the first end of the first secondary winding of the transformer is connected to the anode of the first diode, the second end is connected to the anode of the second diode, and the middle tap is connected to the common ground of the DC bus; the cathodes of the first diode and the second diode are connected together and output a positive bus voltage; the first end of the second secondary winding of the transformer is connected to the anode of the third diode, the second end is connected to the anode of the fourth diode, and the middle tap outputs a negative bus voltage; the cathodes of the third diode and the fourth diode are connected together and connected to the common ground.

[0021] Optionally, the power module provides a positive bus voltage, a common ground, and a negative bus voltage; the positive bus voltage is greater than the positive drive voltage of the first power transistor and the second power transistor, the negative bus voltage is less than the negative turn-off voltage of the first power transistor and the second power transistor, and the common ground is between the positive bus voltage and the negative bus voltage.

[0022] Optionally, the drive control module includes a controller, an isolation unit, and a drive control signal generation unit;

[0023] The controller provides a PWM signal; the isolation unit is connected between the output of the controller and the input of the drive control signal generation unit; the drive control signal generation unit performs dead-time control and / or level conversion on the output signal of the isolation unit to generate the drive control signal.

[0024] Optionally, the first drive branch and / or the second drive branch include a voltage regulator unit, a positive energy storage network, a negative energy storage network, and a drive gate.

[0025] The voltage regulator unit is connected to the DC bus and is used to generate the positive drive voltage and negative turn-off voltage of the corresponding power transistor.

[0026] One end of the positive electrode energy storage network is connected to the positive drive voltage output by the voltage regulator unit, and the other end is connected to the common ground;

[0027] One end of the negative electrode energy storage network is connected to the negative turn-off voltage output by the voltage regulator unit, and the other end is connected to the common ground;

[0028] The drive gate is connected to the output terminal of the voltage regulator unit and is controlled by the drive control module to generate the corresponding drive signal for the power transistor.

[0029] Alternatively, the voltage stabilizing unit includes a positive voltage regulator and a negative voltage regulator;

[0030] The positive voltage regulator is connected to the positive bus voltage of the DC bus and the common ground, generating the positive drive voltage of the corresponding power transistor;

[0031] The negative voltage regulator is connected to the negative bus voltage of the DC bus and the common ground, generating the negative turn-off voltage of the corresponding power transistor.

[0032] Alternatively, both the positive electrode energy storage network and the negative electrode energy storage network include at least two capacitors connected in parallel.

[0033] Alternatively, the driving gate includes a pull-up unit, a pull-down unit, an on-resistor, and an off-resistor;

[0034] One end of the pull-up unit is connected to the corresponding positive drive voltage, and the other end is connected to one end of the pull-down unit via the turn-on resistor and the turn-off resistor in sequence; the other end of the pull-down unit is connected to the corresponding negative turn-off voltage; the control terminals of the pull-up unit and the pull-down unit are respectively controlled by the output signal of the drive control module; the connection node of the turn-on resistor and the turn-off resistor serves as the output terminal of the drive gate.

[0035] Optionally, the Kelvin pin of the first power transistor is connected to the common ground of the first drive branch through a first resistor.

[0036] Optionally, the Kelvin pin of the second power transistor is connected to the common ground of the second drive branch through a second resistor.

[0037] Optionally, the parallel power device differentiated gate drive system further includes a filter module connected between the DC bus and the second drive branch.

[0038] To achieve the above and other related objectives, the present invention also provides a chip, the chip comprising at least: the above-mentioned parallel power device differentiated gate drive system.

[0039] As described above, the parallel power device differentiated gate drive system and chip of the present invention have the following beneficial effects:

[0040] 1. This invention can simultaneously meet the differentiated gate drive requirements of IGBTs and SiC using only a single isolated auxiliary power supply. Compared to a dual auxiliary power supply solution, it reduces at least one isolation transformer, rectifier circuit, and filter circuit, thereby reducing the area of ​​the driver board by approximately 30% to 50% and the BOM cost by approximately 20% to 40%, significantly reducing system complexity and cost; it also reduces the difficulty of insulation design and the failure rate.

[0041] 2. This invention, through independent voltage regulation units for each drive branch, can precisely set the gate drive voltage of IGBTs and SiCs near their respective recommended values ​​(e.g., +15V / -9V for IGBTs, +18V / -3V for SiCs), ensuring that both types of devices operate under optimal drive conditions. Compared to the forced compromise of voltage values ​​in a single-supply shared solution, this invention can simultaneously optimize the conduction losses and switching performance of both types of devices, achieving precise differentiated gate voltage output.

[0042] 3. The multiple decoupling mechanism of the present invention (voltage level, energy storage level, loop level, and layout level decoupling) can significantly reduce the power supply coupling between the two drives. Experimental and simulation results show that the power supply coupling between the two drive branches of the present invention is reduced to less than 20% of the traditional single power supply sharing scheme.

[0043] 4. This invention improves the dynamic current distribution of parallel power devices through the synergistic effect of differentiated gate voltage, independent gate impedance network and differentiated drive timing, making the current distribution of IGBT and SiC more uniform during parallel turn-on and turn-off processes.

[0044] 5. In this invention, since both types of power devices operate at their respective recommended gate voltages and the parallel dynamic current sharing is improved, the switching losses are significantly reduced; among them, the total switching losses of the system are reduced by about 10% to 20% compared with the single power supply scheme, and the SiC conduction losses are reduced by about 10% to 15%.

[0045] 6. The stability of the gate waveform and the low coupling design of the gate circuit in this invention effectively reduce gate ringing and overshoot during the switching process; the gate voltage overshoot amplitude is reduced from 3V to 5V in the traditional scheme to 1V to 2V, and the ringing duration is shortened from 50ns to 100ns to 10ns to 30ns; the dv / dt change rate of the bridge arm midpoint voltage is also smoother, which is beneficial to reducing system-level electromagnetic interference (EMI) radiation. Attached Figure Description

[0046] Figure 1 The diagram shown is a schematic block diagram of the parallel power device differentiated gate drive system of the present invention.

[0047] Figure 2 The diagram shown is a structural schematic of the differentiated gate drive system for parallel power devices according to the present invention.

[0048] Figure 3 The diagram shown is a schematic of the differentiated driving timing of the present invention.

[0049] Figure 4 The diagram shows a test waveform of the parallel double pulse of the present invention.

[0050] Figure 5The diagram shown illustrates the parallel current distribution principle of this invention.

[0051] Figure 6 The diagram shows the layout of the first drive branch and the second drive branch of the present invention.

[0052] Figure 7 The diagram shows the gate voltage waveforms of IGBTs and SiC under a traditional single-supply shared scheme.

[0053] Figure 8 The diagram shown is a schematic representation of the gate voltage waveform of the present invention.

[0054] Component designation explanation

[0055] 1-Parallel power device differentiated gate drive system; 11-Power supply module; 12-Drive control module; 121-Controller; 122-Isolation unit; 123-Drive control signal generation unit; 13-First drive branch; 131-First voltage regulator unit; 13a-First positive voltage regulator; 13b-First negative voltage regulator; 13c-First pull-up unit; 13d-First pull-down unit; 132-First positive energy storage network; 133-First negative energy storage network; 134-First drive gate; 14-Second drive branch; 141-Second voltage regulator unit; 14a-Second positive voltage regulator; 14b-Second negative voltage regulator; 14c-Second pull-up unit; 14d-Second pull-down unit; 142-Second positive energy storage network; 143-Second negative energy storage network; 144-Second drive gate; 15-Filter module. Detailed Implementation

[0056] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0057] Please see Figures 1 to 8 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0058] like Figure 1 As shown, the present invention provides a parallel power device differentiated gate drive system 1, the parallel power device differentiated gate drive system 1 comprising:

[0059] The system includes a power supply module 11, a drive control module 12, a first drive branch 13, a second drive branch 14, a first power transistor, and a second power transistor. The first power transistor is designated as SiC and is implemented using a SiC transistor. The second power transistor is designated as IGBT and is implemented using an IGBT transistor.

[0060] like Figure 1 As shown, power module 11 provides bus voltage to the DC bus.

[0061] Specifically, in this embodiment, the power module 11 provides a positive bus voltage BUS+, a common ground GND, and a negative bus voltage BUS-. The positive bus voltage BUS+ is greater than the positive drive voltage of the first power transistor SiC and the second power transistor IGBT, while the negative bus voltage BUS- is less than the negative turn-off voltage of the first power transistor SiC and the second power transistor IGBT, thus reserving sufficient voltage margin for the subsequent voltage regulation unit. The common ground GND is located between the positive bus voltage BUS+ and the negative bus voltage BUS-. The DC bus includes three independent transmission lines, used to transmit the positive bus voltage BUS+, the negative bus voltage BUS-, and the common ground GND, respectively. In one example, when the first power transistor SiC requires +18V / -3V and the second power transistor IGBT requires +15V / -9V, the positive bus voltage BUS+ is set to +20V to +25V (+20V in this example), the negative bus voltage BUS- is set to -10V to -15V (-10V in this example), the input voltage Vin of power module 11 is +5V or +12V, and the common ground GND is set to 0V. In actual use, specific voltage values ​​can be configured as needed, and are not limited to this embodiment.

[0062] Specifically, power module 11 is an isolated DC-DC converter, including but not limited to isolated converters based on flyback or forward topologies. The isolation withstand voltage of the primary and secondary sides of the isolated DC / DC converter is not lower than the application voltage level of the power devices to ensure compliance with safety regulations. Details will not be elaborated here. Figure 2 As shown, as an example, the power module 11 includes a transformer T, a first diode D1, a second diode D2, a third diode D3, and a fourth diode D4. The primary winding of the transformer T receives the input voltage Vin; the first end of the first secondary winding is connected to the anode of the first diode D1, the second end is connected to the anode of the second diode D2, and the middle tap is connected to the common ground GND; the cathodes of the first diode D1 and the second diode D2 are connected together and output a positive bus voltage BUS+; the first end of the second secondary winding is connected to the anode of the third diode D3, the second end is connected to the anode of the fourth diode D4, and the middle tap outputs a negative bus voltage BUS-; the cathodes of the third diode D3 and the fourth diode D4 are connected together and connected to the common ground GND.

[0063] Specifically, in one example, the power module 11 has an output power capacity of not less than 2W, an output ripple of less than 100mVpp, and an isolation withstand voltage of not less than 5000Vrms (meeting the safety requirements for 1200V applications). In actual use, these parameters should be set as needed.

[0064] like Figure 1 As shown, the drive control module 12 generates a drive control signal to control the first power transistor SiC to turn on earlier than the second power transistor IGBT, and to control the first power transistor SiC to turn off later than the second power transistor IGBT.

[0065] Specifically, such as Figure 2 As shown, in this embodiment, the drive control module 12 includes a controller 121, an isolation unit 122, and a drive control signal generation unit 123. The controller 121 provides a PWM signal and can be implemented using modules capable of providing PWM signals, including but not limited to MCUs, DSPs, FPGAs, and dedicated drive controllers. The isolation unit 122 is connected between the output terminal of the controller 121 and the input terminal of the drive control signal generation unit 123 to achieve electrical isolation and suppress noise; it can be implemented using, but not limited to, isolation chips and optocouplers. The drive control signal generation unit 123 performs dead-time control and / or level conversion on the output signal of the isolation unit 122 to generate a drive control signal. The dead-time control is based on turn-on delay and turn-off delay registers, and the level conversion converts a low level to a high level. In this example, the output terminal of the drive control signal generation unit 123 is also equipped with four inverters, and the output terminals are respectively connected to the corresponding drive transistors.

[0066] Specifically, such as Figure 3As shown, in this embodiment, the drive control signal generation unit 123 generates a first drive control signal Ctl1 and a second drive control signal Ctl2. The first drive control signal Ctl1 controls the on / off state of the first power transistor SiC, and the second drive control signal Ctl2 controls the on / off state of the second power transistor IGBT. During the turn-on process, according to a predetermined turn-on timing difference Δton (for example, ranging from 10ns to 500ns, with a typical value of 100ns to 200ns), the first power transistor SiC is turned on before the second power transistor IGBT (i.e., the rising edge of the first drive control signal Ctl1 arrives earlier than the rising edge of the second drive control signal Ctl2). The SiC device has a shorter turn-on delay and a faster turn-on speed; turning on the SiC first allows it to bear a portion of the current, preventing the IGBT from bearing the entire inrush current alone. Simultaneously, the drain-source voltage of the SiC drops rapidly after it is turned on first, reducing the dv / dt stress during the IGBT turn-on process. During the turn-off process, the second power transistor, IGBT, is turned off before the first power transistor, SiC, according to a predetermined turn-off timing difference Δtoff (for example, ranging from 10ns to 500ns, with a typical value of 100ns to 200ns). IGBTs exhibit current tailing characteristics and have a slow turn-off speed; turning off the IGBT first allows it to enter the tailing stage earlier. The SiC transistor is turned off later to handle the final current commutation, utilizing its rapid turn-off capability to shorten the overall turn-off process. This timing difference can be precisely adjusted using the DSP's high-resolution PWM module (HRPWM, resolution approximately 150ps), or it can be achieved through hardware delay lines or RC delay networks.

[0067] It should be noted that the drive control module 12 can be configured with a specific structure as needed, as long as it can generate drive control signals, and is not limited to this embodiment. The drive control module 12 can also realize the linkage control of functions such as undervoltage lockout (UVLO), overcurrent protection (DESAT), short circuit protection and overheat protection, which will not be described in detail here.

[0068] like Figure 1 As shown, the first drive branch 13 is connected to the DC bus, generates a first positive drive voltage and a first negative turn-off voltage based on the bus voltage, and generates a first drive signal Drv1 under the control of the drive control module 12. In this embodiment, the first drive branch 13 includes a first voltage regulator unit 131, a first positive energy storage network 132, a first negative energy storage network 133, and a first drive gate 134.

[0069] Specifically, the first voltage regulator unit 131 is connected to the DC bus and is used to generate a first positive drive voltage (i.e., the positive drive voltage of the first power transistor SiC) and a first negative turn-off voltage (i.e., the negative drive voltage of the first power transistor SiC). In this example, the first positive drive voltage is set to +18V, and the first negative turn-off voltage is set to -3V. Figure 2As shown in the example, the first voltage regulator unit 131 includes a first positive voltage regulator 13a and a first negative voltage regulator 13b. The first positive voltage regulator 13a is connected to the positive bus voltage BUS+ and the common ground GND, and generates a first positive drive voltage (+18V) based on the positive bus voltage BUS+ (+20V). In this example, the margin is 2V. It can be implemented by means of, but is not limited to, a linear regulator (LDO), a TL431 precision reference combined with a power transistor series regulator, a low-noise switching regulator, etc., which will not be described in detail here. The first negative voltage regulator 13b is connected to the negative bus voltage BUS- and the common ground GND, and generates a first negative turn-off voltage (-3V). Since the negative turn-off voltage required by SiC is relatively shallow, it can be implemented by means of, but is not limited to, Zener diode clamping and low dropout regulation, which will not be described in detail here. In this embodiment, the first negative voltage regulator 13b includes a current-limiting resistor and a Zener diode (not shown in the figure). The current-limiting resistor (e.g., 10Ω / 0.5W) is connected in series between the negative bus voltage BUS- (-10V) and the negative power supply pin of the first driver gate 134 (i.e., the output terminal of the first negative voltage regulator 13b). The Zener diode is connected in parallel between the negative power supply pin of the first driver gate 134 and the common ground GND, so that the negative power supply pin of the first driver gate 134 is stabilized at around -3V. This scheme has a simple structure, and the 7V voltage difference between -3V and -10V is consumed by the current-limiting resistor, with a power loss of about 0.5W (determined by the static current and transient current of the driver chip). As another implementation of the present invention, the input terminal of the first positive voltage regulator 13a is further provided with a first capacitor C1, one end of the first capacitor C1 is connected to the input terminal of the first positive voltage regulator 13a, and the other end is connected to the common ground GND; the input terminal of the first negative voltage regulator 13b is further provided with a second capacitor C2, one end of the second capacitor C2 is connected to the input terminal of the first negative voltage regulator 13b, and the other end is connected to the common ground GND.

[0070] Specifically, one end of the first positive energy storage network 132 is connected to the first positive drive voltage output by the first voltage regulator unit 131, and the other end is connected to the common ground GND. As an example, the first positive energy storage network 132 includes at least two capacitors in parallel (as an example, the total capacitance ranges from 1µF to 100µF, with typical values ​​from 10µF to 22µF) to provide the transient large current required for gate charging and discharging, ensuring that the gate voltage does not collapse during switching transients. In one example, the first positive energy storage network 132 includes three decoupling capacitors in parallel, arranged close to the positive power supply pin of the first drive gate 134 (at a distance of less than 3mm) to ensure that the peak current (up to several amperes) of gate charging and discharging is provided by the local capacitors; the capacitance values ​​of each decoupling capacitor are 10µF / 25V, 100nF / 25V, and 10nF / 25V, respectively.

[0071] Specifically, one end of the first negative energy storage network 133 is connected to the first negative turn-off voltage output by the first voltage regulator unit 131, and the other end is connected to the common ground GND. As an example, the first negative energy storage network 133 includes at least two parallel capacitors (for example, the total capacitance ranges from 1µF to 100µF, with typical values ​​from 10µF to 22µF), also used to provide the transient large current required for gate charging and discharging, ensuring that the gate voltage does not collapse during switching transients. In one example, the first negative energy storage network 133 includes three parallel decoupling capacitors, arranged close to the negative power supply pin of the first drive gate 134 (at a distance of less than 3mm), with capacitance values ​​of 10µF / 16V, 100nF / 16V, and 10nF / 16V, respectively. It should be noted that the number and total capacitance of the parallel capacitors in the first positive energy storage network 132 and the first negative energy storage network 133 can be the same or different.

[0072] Specifically, the first driving gate 134 is connected to the output terminal of the first voltage regulator unit 131 and is controlled by the drive control module 12 to generate the first driving signal Drv1 (i.e., the driving signal of the first power transistor SiC). In one example, the first driving gate 134 includes a first pull-up unit 13c, a first pull-down unit 13d, a first turn-on resistor Ron_1, and a first turn-off resistor Roff_1. One end of the first pull-up unit 13c (serving as the positive power supply pin of the first driving gate 134) is connected to the first positive driving voltage (+18V) output by the first voltage regulator unit 131, and the other end is connected to one end of the first pull-down unit 13d via the first turn-on resistor Ron_1 and the first turn-off resistor Roff_1. The other end of the first pull-down unit 13d (serving as the negative power supply pin of the first driving gate 134) is connected to the first negative turn-off voltage (-3V) output by the first voltage regulator unit 131. The control terminals of the first pull-up unit 13c and the first pull-down unit 13d are respectively controlled by the output signal of the drive control module 12. The connection node of the first turn-on resistor Ron_1 and the first turn-off resistor Roff_1 serves as the output terminal of the first driving gate 134. The first pull-up unit 13c and the first pull-down unit 13d can be implemented using appropriate devices as needed, including but not limited to driver chips and MOSFETs. In this example, the first pull-up unit 13c includes a first NMOS transistor Q1 and a third resistor R3; the drain of the first NMOS transistor Q1 is connected to a positive drive voltage, the source is connected to a first turn-on resistor Ron_1, and the gate receives a drive control signal via the third resistor R3. In this example, the first pull-down unit 13d includes a second NMOS transistor Q2 and a fourth resistor R4; the drain of the second NMOS transistor Q2 is connected to a first turn-off resistor Roff_1, the source is connected to a negative turn-off voltage, and the gate receives a drive control signal; one end of the fourth resistor R4 is connected to the gate of the second NMOS transistor Q2, and the other end is connected to the first negative turn-off voltage. In this example, the first turn-on resistor Ron_1 and the first turn-off resistor Roff_1 are set to have small resistance values ​​to fully utilize the advantage of the fast switching speed of SiC devices. As an example, the typical value range of the first turn-on resistor Ron_1 is 1Ω to 5Ω (in one example, the resistance value of the first turn-on resistor Ron_1 is 2.2Ω (1W metal film resistor)), and the typical value range of the first turn-off resistor Roff_1 is 2Ω to 10Ω (in one example, the resistance value of the first turn-off resistor Roff_1 is 4.7Ω (1W metal film resistor)).As an example, the first driving gate 134 also includes a fifth diode D5 connected between the first turn-off resistor Roff_1 and the first pull-down unit 13d; wherein the anode of the fifth diode D5 is connected to the first turn-off resistor Roff_1, and the cathode is connected to the first pull-down unit 13d; the first turn-off resistor Roff_1 is selected by a reverse diode (the fifth diode D5): when turned on, current flows to the gate through the first turn-on resistor Ron_1, and when turned off, current is drawn from the gate through the first turn-off resistor Roff_1 and the reverse diode. This embodiment utilizes the active Miller clamp function integrated within the UCC21732. When the SiC device is turned off, the internal clamping transistor automatically turns on, forming a low-impedance path of approximately 1Ω to 5Ω between the gate and the source, guiding the Miller current to the source. The clamping action is automatically triggered by the internal logic of the driving chip, without the need for external control signals.

[0073] like Figure 1 As shown, the second drive branch 14 is connected to the DC bus, generates a second positive drive voltage and a second negative turn-off voltage based on the bus voltage, and generates a second drive signal Drv2 under the control of the drive control module 12. In this embodiment, the second drive branch 14 includes a second voltage regulator unit 141, a second positive energy storage network 142, a second negative energy storage network 143, and a second drive gate 144.

[0074] Specifically, the second voltage regulator unit 141 is connected to the DC bus and is used to generate a second positive drive voltage (i.e., the positive drive voltage of the second power transistor IGBT) and a second negative turn-off voltage (i.e., the negative drive voltage of the second power transistor IGBT). In this example, the second positive drive voltage is set to +15V, and the second negative turn-off voltage is set to -9V. Figure 2As shown in the example, the second voltage regulator unit 141 includes a second positive voltage regulator 14a and a second negative voltage regulator 14b. The second positive voltage regulator 14a is connected to the positive bus voltage BUS+ and the common ground GND, and generates a second positive drive voltage (+15V) based on the positive bus voltage BUS+ (+20V). In this example, the margin is 5V. It can be implemented using methods including but not limited to linear regulators (LDOs), TL431 precision references in series with power transistors, and low-noise switching regulators, which will not be described in detail here. The second negative voltage regulator 14b is connected to the negative bus voltage BUS- and the common ground GND, and generates a second negative turn-off voltage (-9V). It can be implemented using methods including but not limited to a reverse voltage regulator circuit composed of TL431 and PNP power transistors, and a dedicated negative voltage LDO, which will not be described in detail here. In this embodiment, the second negative voltage regulator 14b includes a TL431 chip and a PNP power transistor (not shown in the figure). The reference terminal of the TL431 samples the -9V output voltage through a voltage divider resistor network (Ra=10kΩ, Rb=11.5kΩ). The cathode of the TL431 drives the base of the PNP power transistor. The collector input terminal of the PNP power transistor is connected to the negative bus voltage BUS- (-10V), and the emitter outputs -9V. As another implementation of the present invention, the input terminal of the second positive voltage regulator 14a is also provided with a third capacitor C3. One end of the third capacitor C3 is connected to the input terminal of the second positive voltage regulator 14a, and the other end is connected to the common ground GND. The input terminal of the second negative voltage regulator 14b is also provided with a fourth capacitor C4. One end of the fourth capacitor C4 is connected to the input terminal of the second negative voltage regulator 14b, and the other end is connected to the common ground GND.

[0075] Specifically, one end of the second positive energy storage network 142 is connected to the positive drive voltage output by the second voltage regulator unit 141, and the other end is connected to the common ground GND. As an example, the second positive energy storage network 142 includes at least two capacitors in parallel (the total capacitance range and typical values ​​are described in the first positive energy storage network). In one example, the second positive energy storage network 142 includes three decoupling capacitors in parallel, arranged close to the positive power supply pin of the second drive gate 144 (at a distance of less than 3 mm), with capacitance values ​​of 10µF / 25V, 100nF / 25V, and 10nF / 25V, respectively.

[0076] Specifically, one end of the second negative energy storage network 143 is connected to the negative turn-off voltage output by the second voltage regulator unit 141, and the other end is connected to the common ground GND. As an example, the second negative energy storage network 143 includes at least two capacitors in parallel (the total capacitance range and typical values ​​are described in the first negative energy storage network). In one example, the second negative energy storage network 143 includes three decoupling capacitors in parallel, arranged close to the negative power supply pin of the second drive gate 144 (at a distance of less than 3 mm), with capacitance values ​​of 10µF / 16V, 100nF / 16V, and 10nF / 16V, respectively.

[0077] Specifically, the second driving gate 144 is connected to the output terminal of the second voltage regulator unit 141 and is controlled by the drive control module 12 to generate a drive signal for the second power transistor IGBT. In one example, the second driving gate 144 includes a second pull-up unit 14c, a second pull-down unit 14d, a second turn-on resistor Ron_2, and a second turn-off resistor Roff_2; the structure and connection relationship of each part are the same as those of the first driving gate 134. The structures of the first driving gate 134 and the second driving gate 144 can also be set differently, and are not limited to this embodiment. As an example, the typical value range of the second turn-on resistor Ron_2 is 2Ω to 10Ω (in one example, the resistance value of the second turn-on resistor Ron_2 is 4.7Ω (1W metal film resistor)), and the typical value range of the second turn-off resistor Roff_2 is 5Ω to 20Ω (in one example, the resistance value of the second turn-off resistor Roff_2 is 10Ω (1W metal film resistor)). As an example, the second driving gate 144 also includes a sixth diode D6, whose connection relationship and working principle are similar to those of the fifth diode D5, and will not be described in detail here.

[0078] like Figure 1 As shown, the first power transistor SiC and the second power transistor IGBT are connected in parallel. The first power transistor SiC is controlled by the first drive signal Drv1, and the second power transistor IGBT is controlled by the second drive signal Drv2.

[0079] Specifically, the drain of the first power transistor SiC and the collector of the second power transistor IGBT are connected together, and the source of the first power transistor SiC and the emitter of the second power transistor IGBT are connected together to achieve parallel connection. The gate of the first power transistor SiC is connected to the first drive signal Drv1, and the gate of the second power transistor IGBT is connected to the second drive signal Drv2.

[0080] Specifically, in this embodiment, a parallel application of a 1200V / 40A level first power transistor SiC and a second power transistor IGBT is used as an example. In actual use, it is not limited to this voltage and current level and can be extended to hybrid parallel power modules with higher voltage levels such as 1700V and 3300V. In this example, the typical switching frequency is taken as a reference value from 20kHz to 100kHz.

[0081] In another implementation of the present invention, the Kelvin pin (connected to the auxiliary source) of the first power transistor SiC is connected to the common ground of the first drive branch 13 through a first resistor R1, in order to eliminate the influence of parasitic resistance and inductance of the main source circuit on the drive signal. The Kelvin pin (connected to the auxiliary emitter) of the second power transistor IGBT is connected to the common ground of the second drive branch 14 through a second resistor R2, in order to eliminate the influence of parasitic resistance and inductance of the main emitter circuit on the drive signal.

[0082] As another implementation of the present invention, the parallel power device differentiated gate drive system 1 further includes a filter module 15, which is connected between the DC bus and the second drive branch 14 to suppress EMI. In one example, the filter module 15 is implemented using three inductors, each inductor transmitting the voltage on a DC bus; in practical use, any circuit structure that can suppress EMI is applicable to the present invention.

[0083] like Figure 4 and Figure 5 As shown, the working process of the parallel power device differentiated gate drive system 1 of the present invention is illustrated by taking the turn-on of the half-bridge diode as an example:

[0084] S1) When the PWM command requests turn-on, the controller first outputs the turn-on signal for the first power transistor SiC (150ns in advance). The first drive branch pulls the gate voltage of the first power transistor SiC from -3V to +18V. Since the local energy storage capacitor provides the charging current nearby, the +18V bus is not affected by the second drive branch, and the gate charging waveform is smooth without collapse. The turn-on delay of the first power transistor SiC is about 30ns to 50ns, during which time the drain-source voltage drops rapidly.

[0085] S2) After 150ns, the controller outputs the turn-on signal for the second power transistor IGBT, and the second drive branch pulls the gate voltage of the second power transistor IGBT from -9V to +15V. At this time, the first power transistor SiC has partially turned on and is carrying part of the current, reducing the voltage change rate during the turn-on process of the second power transistor IGBT and decreasing the turn-on loss. The turn-on delay of the second power transistor IGBT is approximately 100ns to 200ns (due to the large gate charge), and the turn-on speed is controlled by the resistance value of the second turn-on resistor Ron_2.

[0086] (S3) After both power transistors are turned on, the steady-state current is naturally distributed according to the ratio of their on-resistance. Since the second power transistor IGBT is fully saturated and conducting at +15V, the on-resistance of the first power transistor SiC is further reduced at +18V, and both transistors are operating at their optimal drive points.

[0087] S4) The turn-off process is similar, but the timing is reversed: the second power transistor IGBT turns off first (150ns earlier), followed by the first power transistor SiC. The second power transistor IGBT turns off and enters the current tailing stage, after which the first power transistor SiC quickly turns off to complete the commutation.

[0088] The present invention also provides a chip, including the parallel power device differentiated gate drive system 1 of the present invention. For example... Figure 6 As shown in this embodiment, in the chip, the first driving branch 13 and the second driving branch 14 are independent of each other in layout, and the distance between the two branches is not less than 5mm.

[0089] Specifically, 1) The power supply traces for the two drive branches are routed independently from the DC bus branch point, each leading to the decoupling capacitor and driver chip of its corresponding branch. 2) The ground planes of the SiC drive branches converge at the Kelvin reference point and are connected to the system common ground GND through a single point. The IGBT_GND is connected to the system common ground GND through a filter to avoid ground loops. 3) The loop area of ​​the drive loop (from gate to power transistor gate, and then back to the driver chip via the Kelvin reference point) is minimized, typically not exceeding 50 mm². 4) Local decoupling capacitors are placed within 3 mm of the power supply pins of the driver chip. 5) A minimum spacing of 5 mm is maintained between the two drive branches to avoid magnetic and electric field coupling.

[0090] The parallel power device differentiated gate drive system 1 of the present invention achieves low coupling between the two drive branches through the following multiple decoupling measures:

[0091] 1) Voltage level decoupling: The voltage regulator unit of each drive branch has independent input and output characteristics, which can suppress the transmission of transient voltage fluctuations on the common bus downstream. The power supply rejection ratio (PSRR) and transient response capability of the voltage regulator unit are key parameters.

[0092] 2) Energy storage level decoupling: The local energy storage capacitor network of each drive branch provides gate charging and discharging current nearby, so that the voltage regulator unit only needs to compensate for the average current instead of the peak current, which greatly reduces the risk of the two branches competing for transient current through the common bus.

[0093] 3) Loop-level decoupling: The gate circuits of each drive branch (from the output of the drive chip through the gate resistor to the gate of the power transistor, and then back to the reference of the drive chip through the Kelvin reference) are completely independent, and there is no shared gate circuit impedance.

[0094] 4) Layout-level decoupling: On the PCB layout, the power supply traces, decoupling capacitors and gate circuits of the two drive branches are arranged in independent areas to avoid trace coupling and parasitic parameter crosstalk.

[0095] Simulations were performed on the differentiated gate drive system 1 of the single-supply parallel power devices of the present invention and the conventional single-supply gate drive system, such as... Figure 7 As shown, in the traditional single-supply shared-power scheme, the gate voltage waveforms of IGBTs and SiC exhibit obvious ringing and voltage sag; for example... Figure 8 As shown, in the gate voltage waveform of the present invention, the gate voltage of each branch is stable, clean, and without offset.

[0096] In summary, this invention provides a differentiated gate drive system and chip for parallel power devices, comprising: a power module, a drive control module, a first drive branch, a second drive branch, a first power transistor, and a second power transistor, wherein the first power transistor is a SiC transistor and the second power transistor is an IGBT transistor; the power module provides a bus voltage to the DC bus; the drive control module generates a drive control signal to control the first power transistor to turn on earlier than the second power transistor and to control the first power transistor to turn off later than the second power transistor; the first drive branch is connected to the DC bus, generates a first positive drive voltage and a first negative turn-off voltage based on the bus voltage, and generates a first drive signal under the control of the drive control module; the second drive branch is connected to the DC bus, generates a second positive drive voltage and a second negative turn-off voltage based on the bus voltage, and generates a second drive signal under the control of the drive control module; the first power transistor and the second power transistor are connected in parallel, the first power transistor is controlled by the first drive signal, and the second power transistor is controlled by the second drive signal. In parallel applications of IGBTs and SiC, this invention utilizes only a single isolated auxiliary power supply to achieve the differentiated gate voltages required by the two types of devices, while simultaneously reducing malfunctions, oscillations, and dynamic shunt imbalances caused by power supply coupling. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and possesses high industrial applicability.

[0097] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A differentiated gate drive system for parallel power devices, characterized in that, The parallel power device differentiated gate drive system includes at least: The power supply module, drive control module, first drive branch, second drive branch, first power transistor, and second power transistor, wherein the first power transistor is a SiC transistor and the second power transistor is an IGBT transistor; The power module provides bus voltage to the DC bus; The drive control module generates a drive control signal to control the first power transistor to turn on earlier than the second power transistor and to control the first power transistor to turn off later than the second power transistor. The first drive branch is connected to the DC bus, generates a first positive drive voltage and a first negative turn-off voltage based on the bus voltage, and generates a first drive signal under the control of the drive control module. The second drive branch is connected to the DC bus, generates a second positive drive voltage and a second negative turn-off voltage based on the bus voltage, and generates a second drive signal under the control of the drive control module. The first power transistor and the second power transistor are connected in parallel. The first power transistor is controlled by the first drive signal, and the second power transistor is controlled by the second drive signal.

2. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The power module is an isolated DC-DC converter.

3. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The power module includes a transformer, a first diode, a second diode, a third diode, and a fourth diode; The primary winding of the transformer receives the input voltage; the first end of the first secondary winding of the transformer is connected to the anode of the first diode, the second end is connected to the anode of the second diode, and the middle tap is connected to the common ground of the DC bus; the cathodes of the first diode and the second diode are connected together and output a positive bus voltage; the first end of the second secondary winding of the transformer is connected to the anode of the third diode, the second end is connected to the anode of the fourth diode, and the middle tap outputs a negative bus voltage; the cathodes of the third diode and the fourth diode are connected together and connected to the common ground.

4. The differentiated gate drive system for parallel power devices according to any one of claims 1-3, characterized in that: The power module provides a positive bus voltage, a common ground, and a negative bus voltage; the positive bus voltage is greater than the positive drive voltage of the first power transistor and the second power transistor, the negative bus voltage is less than the negative turn-off voltage of the first power transistor and the second power transistor, and the common ground is between the positive bus voltage and the negative bus voltage.

5. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The drive control module includes a controller, an isolation unit, and a drive control signal generation unit; The controller provides a PWM signal; the isolation unit is connected between the output of the controller and the input of the drive control signal generation unit. The drive control signal generation unit performs dead-time control and / or level conversion on the output signal of the isolation unit to generate the drive control signal.

6. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The first drive branch and / or the second drive branch include a voltage regulator unit, a positive energy storage network, a negative energy storage network, and a drive gate; The voltage regulator unit is connected to the DC bus and is used to generate the positive drive voltage and negative turn-off voltage of the corresponding power transistor. One end of the positive electrode energy storage network is connected to the positive drive voltage output by the voltage regulator unit, and the other end is connected to the common ground; One end of the negative electrode energy storage network is connected to the negative turn-off voltage output by the voltage regulator unit, and the other end is connected to the common ground; The drive gate is connected to the output terminal of the voltage regulator unit and is controlled by the drive control module to generate the corresponding drive signal for the power transistor.

7. The parallel power device differentiated gate drive system according to claim 6, characterized in that: The voltage stabilizing unit includes a positive voltage regulator and a negative voltage regulator; The positive voltage regulator is connected to the positive bus voltage of the DC bus and the common ground, generating the positive drive voltage of the corresponding power transistor; The negative voltage regulator is connected to the negative bus voltage of the DC bus and the common ground, generating the negative turn-off voltage of the corresponding power transistor.

8. The parallel power device differentiated gate drive system according to claim 6, characterized in that: Both the positive electrode energy storage network and the negative electrode energy storage network include at least two capacitors connected in parallel.

9. The parallel power device differentiated gate drive system according to claim 6, characterized in that: The driving gate includes a pull-up unit, a pull-down unit, an on-resistor, and an off-resistor; One end of the pull-up unit is connected to the corresponding positive drive voltage, and the other end is connected to one end of the pull-down unit via the turn-on resistor and the turn-off resistor in sequence; the other end of the pull-down unit is connected to the corresponding negative turn-off voltage; the control terminals of the pull-up unit and the pull-down unit are respectively controlled by the output signal of the drive control module; the connection node of the turn-on resistor and the turn-off resistor serves as the output terminal of the drive gate.

10. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The Kelvin pin of the first power transistor is connected to the common ground of the first drive branch through a first resistor.

11. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The Kelvin pin of the second power transistor is connected to the common ground of the second drive branch through a second resistor.

12. The parallel power device differentiated gate drive system according to claim 1, characterized in that: The parallel power device differentiated gate drive system also includes a filter module connected between the DC bus and the second drive branch.

13. A chip, characterized in that, The chip includes at least: a parallel power device differentiated gate drive system as described in any one of claims 1-12.

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