Semiconductor device

Abstract

Provided is a semiconductor device capable of reducing loss. The semiconductor device includes a control signal input terminal, a switching element, and a control section. The switching element includes a first control terminal and a second control terminal. The control section includes a control terminal, an input terminal (S), an output terminal (D), a control switching element, and a delay section. The control switching element includes a control terminal (Gs), an input terminal (Ss), and an output terminal (Ds). The delay section includes an input terminal (Din) and an output terminal (Dout). The delay section outputs a control voltage to the output terminal after a delay time elapses from a time when a voltage input to the input terminal is switched. The input terminal (Ss) is connected to the input terminal (S). The output terminal (Ds) is connected to the output terminal (D). The input terminal (Din) is connected to the control terminal. The output terminal (Dout) is connected to the control terminal (Ds). The first control terminal is connected to the input terminal (S). The second control terminal is connected to the output terminal (D).

Description

[0001] This application is based on Japanese Patent Application 2025-034809 (filed on March 5, 2025), and enjoys priority benefits from this application. This application incorporates the entire contents of that application by reference. Technical Field

[0002] Embodiments of the present invention relate to semiconductor devices. Background Technology

[0003] For example, in semiconductor devices such as transistors, it is desirable to reduce losses. Summary of the Invention

[0004] Embodiments of the present invention provide a semiconductor device capable of reducing losses.

[0005] Methods used to solve problems: According to an embodiment, a semiconductor device includes a control signal input terminal, a switching element, and a control unit. The switching element includes a first control terminal G1 and a second control terminal G2. The control unit includes a control terminal G, an input terminal S, and an output terminal D. The control unit includes a control switching element and a delay unit. The control switching element includes a control terminal Gs, an input terminal Ss, and an output terminal Ds. The delay unit includes an input terminal Din and an output terminal Dout. After a delay time td elapses from the moment the voltage input to the input terminal Din switches from a first voltage V1 to a second voltage V2, the delay unit outputs a control voltage Vd to the output terminal Dout. The input terminal Ss of the control switching element is electrically connected to the input terminal S of the control unit. The output terminal Ds of the control switching element is electrically connected to the output terminal D of the control unit. The input terminal Din of the delay unit is electrically connected to the control terminal G of the control unit. The output terminal Dout of the delay unit is electrically connected to the control terminal Gs of the control switching element. The first control terminal G1 of the switching element is electrically connected to the input terminal S of the control unit. The second control terminal G2 of the switching element is electrically connected to the output terminal D of the control unit.

[0006] The semiconductor device configured as described above can provide a semiconductor device that can reduce losses. Attached Figure Description

[0007] Figure 1 This is an equivalent circuit diagram illustrating the semiconductor device of the first embodiment.

[0008] Figure 2 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0009] Figure 3This is an equivalent circuit diagram illustrating the semiconductor device of the first embodiment.

[0010] Figure 4 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0011] Figure 5 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0012] Figure 6 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0013] Figure 7 This is an equivalent circuit diagram illustrating the semiconductor device of the first embodiment.

[0014] Figure 8 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0015] Figure 9 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0016] Figure 10 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0017] Figure 11 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0018] Figure 12 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0019] Figure 13 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0020] Figure 14 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0021] Figure 15 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0022] Figure 16 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0023] Figure 17 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0024] Figure 18 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0025] Explanation of reference numerals in the attached figures: 10: Switching element; 11-13: Semiconductor element; 20: Control unit; 20a: Turn-off delay circuit; 20b: Turn-on delay circuit; 20c: Turn-on insulation circuit; 20d: Pulse generation circuit; 21: Control switching element; 22: Delay unit; 30: Gate driver; 40M: Semiconductor component; 41-48: First to eighth semiconductor regions; 51, 52: First and second electrodes; 61-63: First and third insulation regions; 110-113: Semiconductor device; C delay : Capacitor, D: Output terminal, Din: Input terminal of delay section 22, Dout: Output terminal of delay section 22, Ds: Output terminal of control switching element 21, E1~E3: First~Third control electrodes, G: Control terminal, G1~G3: First~Third control terminals, GD: Control signal input terminal, Gs: Control terminal, R delay : Resistor, S: Input terminal, Ss: Input terminal, V1, V2: First voltage, Second voltage, Vd: Control voltage, td1~td3: First~Third delay time. Detailed Implementation

[0026] Hereinafter, various embodiments of the present invention will be described with reference to the accompanying drawings.

[0027] The accompanying drawings are schematic or conceptual, and the relationship between the thickness and width of each part, the ratio of the size between parts, etc., may not be the same as in reality. Even when representing the same part, sometimes the accompanying drawings show different dimensions and ratios.

[0028] In this application specification and various figures, elements that are the same as those mentioned above in the figures are labeled with the same reference numerals and detailed descriptions are omitted where appropriate.

[0029] (First Implementation) Figure 1 This is an equivalent circuit diagram illustrating the semiconductor device of the first embodiment.

[0030] like Figure 1 As shown, the semiconductor device 110 of the embodiment includes a control signal input terminal GD, a switching element 10, and a control unit 20.

[0031] The switching element 10 includes a first control terminal G1 and a second control terminal G2, which are at least two independent control terminals.

[0032] The control unit 20 includes a control terminal G, an input terminal S, an output terminal D, a control switching element 21, and a delay unit 22. The control switching element 21 includes a control terminal Gs, an input terminal Ss, and an output terminal Ds. The delay unit 22 includes an input terminal Din and an output terminal Dout.

[0033] After a delay time td elapses from the moment when the voltage input to the input terminal Din is switched from a first voltage V1 to a second voltage V2, the delay section 22 outputs a control voltage Vd to the output terminal Dout.

[0034] The input terminal Ss of the control switching element 21 is electrically connected to the input terminal S of the control section 20. The output terminal Ds of the control switching element 21 is electrically connected to the output terminal D of the control section 20. The input terminal Din of the delay section 22 is electrically connected to the control terminal G of the control section 20. The output terminal Dout of the delay section 22 is electrically connected to the control terminal Gs of the control switching element 21.

[0035] The first control terminal G1 of the switching element 10 is electrically connected to the input terminal S of the control section 20. The second control terminal G2 of the switching element 10 is electrically connected to the output terminal D of the control section 20.

[0036] In the embodiment, by providing the control switching element 21, one control signal input terminal GD can be used to control the first control terminal G1 and the second control terminal G2 of the switching element 10 at different timings. By controlling the two control terminals at different timings, for example, loss (such as switching loss and conduction loss) can be reduced. According to the embodiment, it is not necessary to provide a control circuit for each control terminal. According to the embodiment, a semiconductor device capable of reducing loss with a simple circuit configuration can be provided.

[0037] The switching element 10 may be, for example, a vertical MOSFET, a vertical IGBT, or the like. In these transistors, a plurality of types of gates (for example, dual gates) are provided. Different control signals are supplied to the plurality of types of gates via the first control terminal G1 and the second control terminal G2.

[0038] The switching element 10 may, for example, include a control electrode provided on the back surface. The switching element 10 may, for example, include an N cathode region and a P cathode region provided on the back surface.

[0039] In one example, the first voltage V1 < the second voltage V2. In this case, when the voltage applied to the control terminal G of the control section 20 changes from the first voltage V1 to the second voltage V2, the control switching element 21 may be turned on or off after delaying the delay time td determined by the time constant of the delay section 22.

[0040] In one example, the first voltage V1 > the second voltage V2. In this case, when the voltage applied to the control terminal G of the control section 20 changes from the first voltage V1 to the second voltage V2, the control switching element 21 may be turned on or off after a delay time td' (<td).

[0041] In one example, the first voltage V1 is greater than the second voltage V2. In this case, when the voltage applied to the control terminal G of the control unit 20 changes from the first voltage V1 to the second voltage V2, the control switching element 21 can be turned on or off after a first delay time td1 that depends on the time constant of the delay unit 22.

[0042] In one example, the first voltage V1 is less than the second voltage V2. In this case, when the voltage applied to the control terminal G of the control unit 20 changes from the first voltage V1 to the second voltage V2, the control switching element 21 can be turned on or off after a second delay time td2 (td2 < td1).

[0043] Figure 2 is a schematic diagram illustrating the semiconductor device according to the first embodiment.

[0044] Figure 2 A semiconductor device 110 is illustrated. A drive signal is input from the gate driver 30 to the delay unit 22. After a delay time td elapses from when the drive signal is output from the gate driver 30, the delay unit 22 supplies a control voltage Vd to the control switching element 21. Accordingly, the control switching element 21 is turned into an on state or an off state. As a result, the drive signal is output from the output terminal D of the control unit 20 with a delay of the delay time td.

[0045] An example of the delay unit 22 according to the embodiment will be described.

[0046] Figure 3 is an equivalent circuit diagram illustrating the semiconductor device 110 according to the first embodiment.

[0047] As Figure 3 illustrated, for example, the delay unit 22 includes a resistor R delay and a capacitor C delay . One end of the resistor R delay is electrically connected to the input terminal Din of the delay unit 22. One end of the capacitor C delay is electrically connected to ground. The other end of the resistor R delay is electrically connected to the other end of the capacitor C delay and the output terminal Dout of the delay unit 22. The output terminal Dout of the delay unit 22 is electrically connected to the control terminal Gs of the control switching element 21. A signal input to the input terminal Din of the delay unit 22 is output from the output terminal Dout of the delay unit 22 after a delay time corresponding to the time constant of the resistor R delay and the capacitor C delay .

[0048] For example, the delay unit 22 may include at least one of a resistor, a coil, a capacitor, an operational amplifier, and a logic circuit.

[0049] exist Figure 1 In the semiconductor device 110 shown, the connection from the control signal input terminal GD to the input terminal Ss of the control switching element 21, and the connection from the control terminal G of the control unit 20 to the control terminal Gs of the control switching element 21, may, for example, include a connection via a capacitor. These connections may, for example, include connections for receiving and transmitting light signals via an optocoupler or the like.

[0050] For example, one or more components such as diodes, switches, operational amplifiers, and optocouplers can be installed between the input terminal Din of the delay section 22 and the control terminal Gs of the control switching element 21.

[0051] The semiconductor device 110 may also include other control units. One or more components from the following control units are mounted between the control signal input terminal GD and the input terminal S of the control unit 20, between the control signal input terminal GD and the first control terminal G1 of the switching element 10, between the input terminal S of the control unit 20 and the first control terminal G1 of the switching element 10, and between the output terminal D of the control unit 20 and the second control terminal G2 of the switching element 10.

[0052] The control switching element 21 may include, for example, a transistor. The control switching element 21 may be, for example, any one of a metal-oxide-semiconductor transistor (MOSFET), a bipolar transistor (BPT), an insulated-gate bipolar transistor (IGBT), a gallium nitride high electron mobility transistor (GaN-HEMT), and a GaN-HEMT connected to a MOSFET via a common source and common gate.

[0053] For example, the control switch element 21 may not perform body diode operation between its input terminal Ss and its output terminal Ds.

[0054] The voltage withstand capability of the control switch element 21 can be, for example, above 20V and below 200V.

[0055] In one example, the channel polarity of the control switching element 21 may be, for example, an N-channel. The control switching element 21 can be turned off, for example, by a gate voltage exceeding a first threshold voltage. In another example, the channel polarity of the control switching element 21 may be, for example, a P-channel. The control switching element 21 can be turned off, for example, by a gate voltage below a second threshold voltage.

[0056] In one example, control switch element 21 may be normally off. Control switch element 21 may be in an open state when the voltage at its control terminal Gs is zero volts. In another example, control switch element 21 may be normally on. Control switch element 21 may be in an on state when the voltage at its control terminal Gs is zero volts.

[0057] Four functions can be obtained by controlling the channel polarity of the switching element 21 and the combination of normally on / normally off.

[0058] For example, when the control switch element 21 is normally on and P-channel, a turn-off delay circuit is configured. For example, when the control switch element 21 is normally on and N-channel, a turn-on delay circuit is configured. For example, when the control switch element 21 is normally off and P-channel, a turn-on isolation circuit is configured. For example, when the control switch element 21 is normally off and N-channel, a turn-off isolation circuit is configured. Through these combinations, various gate control methods can be realized. Through these combinations, control signals with different voltage rise or fall timings can be generated based on a single gate signal. Multiple control signals with delays of either voltage rise or fall timings can be generated based on a single gate signal.

[0059] For example, a portion of the control unit 20 may be integrated into the switching element 10.

[0060] Figure 4 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0061] like Figure 4 As shown, the semiconductor device 111 of this embodiment includes a turn-off delay circuit 20a and a semiconductor element 11. The turn-off delay circuit 20a is included in the control unit 20. In the turn-off delay circuit 20a, the control switching element 21 is normally on and has a P-channel. The semiconductor element 11 is a dual-gate IGBT. A dual-gate IGBT is an example of a switching element 10.

[0062] Semiconductor device 11 includes a first control electrode E1, a second control electrode E2, a first control terminal G1, and a second control terminal G2. The first control terminal G1 is electrically connected to the first control electrode E1. The second control terminal G2 is electrically connected to the second control electrode E2. The second control electrode E2 corresponds to the main gate (MG) of semiconductor device 11. The first control electrode E1 corresponds to the control gate (CG) of semiconductor device 11.

[0063] The output terminal of the gate driver 30 is electrically connected to the control signal input terminal GD of the turn-off delay circuit 20a. The control signal input terminal GD of the turn-off delay circuit 20a is electrically connected to the first control terminal G1 of the semiconductor element 11 and the input terminal S of the turn-off delay circuit 20a. The output terminal D of the turn-off delay circuit 20a is electrically connected to the second control terminal G2 of the semiconductor element 11.

[0064] like Figure 4 As shown, the semiconductor element 11 includes a first electrode 51, a second electrode 52, a first insulating region 61, a second insulating region 62, and a semiconductor component 40M. The semiconductor component 40M is disposed between the first electrode 51 and the second electrode 52. The semiconductor component 40M includes a first semiconductor region 41 of a first conductivity type, a second semiconductor region 42 of a second conductivity type, a third semiconductor region 43 of a first conductivity type, and a fourth semiconductor region 44 of a second conductivity type. The second semiconductor region 42 is located between the first electrode 51 and the second electrode 52. The third semiconductor region 43 is located between the second semiconductor region 42 and the second electrode 52. The second electrode 52 and the third semiconductor region 43 are electrically connected. The fourth semiconductor region 44 is located between the first electrode 51 and the first semiconductor region 41. The fourth semiconductor region 44 is electrically connected to the first electrode 51. The first insulating region 61 is disposed between the first control electrode E1 and the first semiconductor region 41, the second semiconductor region 42, the third semiconductor region 43, and the second electrode 52. The second insulating region 62 is disposed between the second control electrode E2 and the first semiconductor region 41, the second semiconductor region 42, the third semiconductor region 43, and the second electrode 52. The first insulating region 61 and the second insulating region 62 are in contact with the first semiconductor region 41, the second semiconductor region 42, and the third semiconductor region 43. The first semiconductor region 41, the second semiconductor region 42, and the third semiconductor region 43 are opposite to the first control electrode E1 and the second control electrode E2. In the second direction X, the first insulating region 61 and the second insulating region 62 are located between and in contact with two adjacent third semiconductor regions 43. The first electrode 51 is, for example, a collector electrode. The second electrode 52 is an emitter electrode. The direction from the first electrode 51 toward the second electrode 52 is defined as the first direction Z. One of the directions intersecting the first direction Z is defined as the second direction X. The second direction X is, for example, orthogonal to the first direction Z. In the second direction X, the first control electrode E1 and the second control electrode E2 face the second semiconductor region 42. The first control electrode E1 and the second control electrode E2 are electrically independent, connected to different control terminals, and are input with different signals. The first control electrode E1 and the second control electrode E2 can be of the same shape or have different structures.

[0065] Figure 5This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0066] Figure 5 This indicates the signal input to the first control terminal G1 and the second control terminal G2 of the semiconductor element 11.

[0067] The signal that turns off semiconductor element 11 is called the turn-off signal. The turn-off signal is a signal that drops from a first voltage V1 (higher than the threshold voltage of semiconductor element 11) to a second voltage V2 (lower than the threshold voltage). The signal that turns on semiconductor element 11 is called the turn-on signal. The turn-on signal is a signal that rises from a second voltage V2 (lower than the threshold voltage of semiconductor element 11) to a first voltage V1 (higher than the threshold voltage). For example... Figure 5 As shown, the turn-off signal input to the second control terminal G2 of the semiconductor element 11 (dual-gate IGBT) is delayed by a first delay time td1 compared to the turn-off signal input to the first control terminal G1.

[0068] Figure 6 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0069] Figure 6 This represents the signal input from the gate driver 30, and the signals input to the first control terminal G1 and the second control terminal G2 of the semiconductor element 11. As an example, an example is shown where the threshold voltage of the semiconductor element 11 is 10V, the first voltage is 15V, and the second voltage is -15V.

[0070] like Figure 6 As shown, the turn-on signal from the gate driver 30 is input to the first control terminal G1 and the second control terminal G2 of the semiconductor device 11. The turn-off signal from the gate driver 30 is input to the first control terminal G1. The turn-off signal from the gate driver 30 is input to the second control terminal G2 with a delay.

[0071] Figure 7 This is an equivalent circuit diagram illustrating the semiconductor device of the first embodiment.

[0072] like Figure 7 As shown, the pulse generation circuit 20d includes a post-conduction insulation circuit 20c, a delay section 22, an N-channel control switching element 21, an input terminal S, and an output terminal D. The post-conduction insulation circuit 20c is a control section 20 where the control switching element 21 is normally off and has a P-channel.

[0073] The output terminal of the gate driver 30 is electrically connected to the control signal input terminal GD. The control signal input terminal GD is electrically connected to the input terminal S of the turn-on isolation circuit 20c and the input terminal Din of the delay section 22. The output terminal Dout of the delay section 22 is electrically connected to the control terminal Gs of the control switching element 21. The input terminal Ss of the control switching element 21 is grounded or electrically connected to a constant voltage source. The output terminal Ds of the control switching element 21 is electrically connected to the output terminal D of the turn-on isolation circuit 20c and the output terminal D of the pulse generation circuit 20d.

[0074] Figure 8 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0075] Figure 8 This indicates the voltage at the control signal input terminal GD and the output terminal D of the pulse generation circuit 20d.

[0076] like Figure 8 As shown, the input conduction signal is output from the output terminal. After a second delay time td2 from the conduction signal output from the output terminal, the voltage of the constant voltage source is output from the output terminal. The pulse generation circuit 20d generates pulses for a certain period of time from the start of conduction.

[0077] Figure 9 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0078] like Figure 9 As shown, the semiconductor device 112 of the embodiment includes a turn-off delay circuit 20a, a turn-on delay circuit 20b, a pulse generation circuit 20d, and a semiconductor element 12. The semiconductor element 12 is a tri-gate IGBT. A tri-gate IGBT is an example of a switching element 10. The semiconductor element 12 has three independent control electrodes and control terminals.

[0079] Semiconductor element 12 includes a first control electrode E1, a second control electrode E2, a third control electrode E3, a first control terminal G1, a second control terminal G2, and a third control terminal G3. The first control terminal G1 is electrically connected to the first control electrode E1. The second control terminal G2 is electrically connected to the second control electrode E2. The third control terminal G3 is electrically connected to the third control electrode E3. The second control electrode E2 corresponds to the main gate (MG) of semiconductor element 12. The first control electrode E1 corresponds to the control gate (CGp) of semiconductor element 12. The third control electrode E3 corresponds to the control gate (CGs) of semiconductor element 12. A third insulating region 63 is disposed between the third control electrode E3 and the first semiconductor region 41, the second semiconductor region 42, the third semiconductor region 43, and the second electrode 52. The first semiconductor region 41, the second semiconductor region 42, and the third semiconductor region 43 are opposite to the third control electrode E3. The third control electrode E3 may have the same structure as the first control electrode E1, or it may have a different structure.

[0080] The output terminal of the gate driver 30 is electrically connected to the control signal input terminal GD. The control signal input terminal GD is electrically connected to the input terminal S of the turn-on delay circuit 20b. The output terminal D of the turn-on delay circuit 20b is electrically connected to the input terminal S of the turn-off delay circuit 20a, the input terminal S of the pulse generation circuit 20d, and the first control terminal G1 of the semiconductor element 12. The output terminal D of the turn-off delay circuit 20a is electrically connected to the second control terminal G2 of the semiconductor element 12. The output terminal D of the pulse generation circuit 20d is electrically connected to the third control terminal G3 of the semiconductor element 12.

[0081] Figure 10 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0082] Figure 10 These represent the signals input to the first control terminal G1, the second control terminal G2, and the third control terminal G3 of the semiconductor element 12 (trigate IGBT).

[0083] like Figure 10 As shown, a pulse with a width of the second delay time td2 is input to the third control terminal G3 of the semiconductor element 12. The turn-off signal input to the second control terminal G2 is delayed by the first delay time td1 compared to the turn-off signal input to the first control terminal G1.

[0084] Figure 11 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0085] Figure 11This displays the signals input from the gate driver 30, and the signals input to the first control terminal G1, the second control terminal G2, and the third control terminal G3 of the semiconductor element 12.

[0086] like Figure 11 As shown, the turn-on signal of the gate driver 30 is input to the first control terminal G1, the second control terminal G2, and the third control terminal G3 of the semiconductor element 12 with a delay. A constant voltage source voltage is input to the third control terminal G3 with a delay from the turn-on signal input to the third control terminal G3. A turn-off signal from the gate driver 30 is input to the first control terminal G1. A turn-off signal from the gate driver 30 is input to the second control terminal G2 with a delay.

[0087] like Figure 9 As shown, in semiconductor element 12, the first semiconductor region 41 may also include a fifth semiconductor region 45 of a first conductivity type. The fifth semiconductor region 45 is connected to the fourth semiconductor region 44. The fifth semiconductor region 45 is, for example, a buffer layer.

[0088] Figure 12 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0089] like Figure 12 As shown, the semiconductor device 113 of the embodiment includes a turn-off delay circuit 20a, a turn-on delay circuit 20b, and a semiconductor element 13. The semiconductor element 13 is a split-gate IGBT. A split-gate IGBT is an example of a switching element 10.

[0090] Semiconductor element 13 is a trench-type device. In semiconductor element 13, a first control electrode E1 and a second control electrode E2 are disposed within a trench. A first control terminal G1 is electrically connected to the first control electrode E1. A second control terminal G2 is electrically connected to the second control electrode E2. In the first direction Z, the first control electrode E1 is located between a portion of the first semiconductor region 41 and the second electrode 52. In the first direction Z, the second control electrode E2 is located between the first control electrode E1 and the second electrode 52. In the second direction X, the first control electrode E1 faces the first semiconductor region 41. In the second direction X, the second control electrode E2 faces the second semiconductor region 42 and the third semiconductor region 43.

[0091] The output terminal of the gate driver 30 is electrically connected to the control signal input terminal GD. The control signal input terminal GD is electrically connected to the input terminal S of the turn-off delay circuit 20a and the input terminal S of the turn-on delay circuit 20b. The output terminal D of the turn-off delay circuit 20a is electrically connected to the second control terminal G2 of the semiconductor element 13. The output terminal D of the turn-on delay circuit 20b is electrically connected to the first control terminal G1 of the semiconductor element 13. A single delay section 22 may be shared in both the turn-off delay circuit 20a and the turn-on delay circuit 20b.

[0092] Figure 13 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0093] Figure 13 The signals input to the first control terminal G1 and the second control terminal G2 of the semiconductor element 13 are shown.

[0094] like Figure 13 As shown, the turn-on signal input to the first control terminal G1 of the semiconductor element 13 is delayed by a third delay time td3 compared to the turn-on signal input to the second control terminal G2. The turn-off signal input to the second control terminal G2 of the semiconductor element 13 is delayed by a first delay time td1 compared to the turn-off signal input to the first control terminal G1.

[0095] Figure 14 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0096] Figure 14 This indicates the signal input from the gate driver 30, and the signal input to the first control terminal G1 and the second control terminal G2 of the semiconductor element 13.

[0097] like Figure 14 As shown, the turn-on signal from the gate driver 30 is input to the second control terminal G2 of the semiconductor device 13. The turn-on signal from the gate driver 30 is input to the first control terminal G1 of the semiconductor device 13 after a third delay time td3. The turn-off signal from the gate driver 30 is input to the first control terminal G1. The turn-off signal from the gate driver 30 is input to the second control terminal G2 after a first delay time td1.

[0098] like Figure 12As shown, semiconductor element 13 may include a sixth semiconductor region 46. The sixth semiconductor region 46 is located between the first semiconductor region 41 and the second semiconductor region 42. The sixth semiconductor region 46 is, for example, of a first conductivity type. The first semiconductor region 41 may also include the sixth semiconductor region 46. The impurity concentration of the first conductivity type in the sixth semiconductor region 46 is higher than that in other parts of the first semiconductor region 41. The sixth semiconductor region 46 is located between the first semiconductor region 41 and the second semiconductor region 42 in a first direction Z. In a second direction X, a first control electrode E1 faces the sixth semiconductor region 46. In the second direction X, a second control electrode E2 faces the sixth semiconductor region 46.

[0099] Figure 15 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0100] like Figure 15 As shown, the semiconductor device 114 of this embodiment includes a turn-off delay circuit 20a, a turn-on delay circuit 20b, another turn-on delay circuit 20b, a turn-on isolation circuit 20c, a control switching element 21, and a semiconductor element 12. The semiconductor element 12 is a tri-gate IGBT. A tri-gate IGBT is an example of the switching element 10. The tri-gate IGBT has independent three-system control electrodes.

[0101] The output terminal of the gate driver 30 is electrically connected to the control signal input terminal GD. The control signal input terminal GD is electrically connected to the input terminal S of one turn-on delay circuit 20b and the control terminal G of one turn-on delay circuit 20b. The output terminal D of one turn-on delay circuit 20b is electrically connected to the input terminal S of the turn-off delay circuit 20a, the control terminal G of the turn-off delay circuit 20a, the input terminal S of another turn-on delay circuit 20b, the control terminal G of another turn-on delay circuit 20b, the control terminal Gs of the control switching element 21, and the first control terminal G1 of the semiconductor element 12. The output terminal D of the turn-off delay circuit 20a is electrically connected to the second control terminal G2 of the semiconductor element 12. The input terminal Ss of the control switching element 21 is electrically connected to a constant voltage source. The output terminal Ds of the control switching element 21 is electrically connected to the input terminal S of the turn-on isolation circuit 20c and the control terminal G of the turn-on isolation circuit 20c. After conduction, the output terminal D of the insulation circuit 20c is electrically connected to the output terminal D of other conduction delay circuits 20b and the third control terminal G3 of semiconductor element 12.

[0102] Figure 16 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0103] Figure 16These represent signals input from the gate driver 30 to the first control terminal G1, the second control terminal G2, and the third control terminal G3 of the semiconductor element 12 in the semiconductor device 114.

[0104] like Figure 16 As shown, after a turn-on signal is input from the gate driver 30, a third delay time td3 is delayed before the turn-on signal is input to the first control terminal G1, the second control terminal G2, and the third control terminal G3 of the semiconductor element 12. The voltage of the signal input to the first control terminal G1 of the semiconductor element 12 is the same as the voltage of the constant voltage source. After a second delay time td2 from the input of the constant voltage source voltage to the first control terminal G1, the turn-on signal from the gate driver 30 is input to the first control terminal G1. A turn-off signal from the gate driver 30 is input to the first control terminal G1 and the third control terminal G3. A turn-off signal from the gate driver 30 is input to the second control terminal G2 after a first delay time td1. According to the embodiment, three control signals with different voltages can be input to the first control terminal G1.

[0105] Figure 17 This is a schematic diagram illustrating a semiconductor device according to the first embodiment.

[0106] like Figure 17 As shown, the semiconductor device 115 of this embodiment includes a turn-off delay circuit 20a, another turn-off delay circuit 20a, a resistor, an optocoupler, a DC / DC converter, and a semiconductor element 14. The semiconductor element 14 is a double-gate IGBT. The double-gate IGBT has at least two independent control electrodes on each side of the semiconductor element 40M. Figure 17 In this design, a fourth electrode 54 of planar gate type is provided on the back side of the vertical trench gate IGBT, which is controlled to be turned on by the second control electrode E2 provided on the front side of the semiconductor component 40M. The gate structure can be either a trench gate structure or a planar gate structure. A double-gate IGBT is an example of the switching element 10.

[0107] like Figure 17 As shown, the semiconductor element 14 includes a first electrode 51, a second electrode 52, a third electrode 53, a fourth electrode 54, a first insulating region 61, a third insulating region 63, a first control electrode E1, a second control electrode E2, a third control electrode E3, and a semiconductor component 40M.

[0108] Semiconductor component 40M is disposed between first electrode 51 and second electrode 52. Semiconductor component 40M includes a first semiconductor region 41 of first conductivity type, a second semiconductor region 42 of second conductivity type, a third semiconductor region 43 of first conductivity type, a fourth semiconductor region 44 of second conductivity type, a sixth semiconductor region 46 of first conductivity type, a seventh semiconductor region 47 of first conductivity type, and an eighth semiconductor region 48 of second conductivity type.

[0109] The second semiconductor region 42 is located between the first semiconductor region 41 and the second electrode 52. The third semiconductor region 43 is located between at least a portion of the second semiconductor region 42 and the second electrode 52. The second electrode 52 and the third semiconductor region 43 are electrically connected.

[0110] The third insulating region 63 is located between the third electrode 53 and the first semiconductor region 41, between the third electrode 53 and a portion of the second semiconductor region 42, and between the third electrode 53 and the third semiconductor region 43. The third electrode 53 is opposite to a portion of the first semiconductor region 41, a portion of the second semiconductor region 42, and a portion of the third semiconductor region 43. The fourth semiconductor region 44 is located between the first electrode 51 and the first semiconductor region 41. The sixth semiconductor region 46 is located between the first electrode 51 and a portion of the fourth semiconductor region 44.

[0111] The fourth semiconductor region 44 is located between the first electrode 51 and the first semiconductor region 44. The sixth semiconductor region 46 is located between the first electrode 51 and a portion of the fourth semiconductor region 44. The seventh semiconductor region 47 is located between the fourth electrode 54 and the first semiconductor region 41. The seventh semiconductor region 47 is located between one fourth semiconductor region 44 and another fourth semiconductor region 44 in the second direction X. A portion of the fourth semiconductor region 44 is located between the seventh semiconductor region 47 and the sixth semiconductor region 46 in the second direction X. The eighth semiconductor region 48 is located between the first electrode 51 and the fourth semiconductor region 44 in the first direction Z. The direction from the seventh semiconductor region 47 to the eighth semiconductor region 48 is along the second direction X. The sixth semiconductor region 46 is located between a portion of the fourth semiconductor region 44 and the eighth semiconductor region 48 in the second direction X. The first insulating region 61 is located between the first electrode 51 and the fourth electrode 54, between the fourth electrode 54 and a portion of the fourth semiconductor region 44, between the fourth electrode 54 and a portion of the sixth semiconductor region 46, and between the fourth electrode 54 and the seventh semiconductor region 47. The fourth electrode 54 is opposed to a portion of the fourth semiconductor region 44, a portion of the sixth semiconductor region 46, and the seventh semiconductor region 47. The fourth electrode 54 is opposed to a portion of the fourth semiconductor region 44, a portion of the sixth semiconductor region 46, and the seventh semiconductor region 47 through a third insulating region 63. The first electrode 51 is connected to the sixth semiconductor region 46 and the eighth semiconductor region 48.

[0112] Alternatively, a fifth semiconductor region 45 of the first conductivity type can be provided. The fifth semiconductor region 45 is located between the fourth semiconductor region 44 and the first semiconductor region 41. The first conductivity type impurity concentration in the fifth semiconductor region 45 is higher than that in the first semiconductor region 41.

[0113] The first electrode 51 is, for example, a collector electrode. The second electrode 52 is, for example, an emitter electrode. The first control electrode E1 includes two third electrodes 53 opposite to a second semiconductor region 42. The second control electrode E2 includes two third electrodes 53 opposite to other second semiconductor regions 42. The third control electrode E3 is electrically connected to the fourth electrode 54.

[0114] The output terminal of the gate driver 30 is electrically connected to the control signal input terminal GD. The control signal input terminal GD is electrically connected to the input terminal S of one turn-off delay circuit 20a, the control terminal G of one turn-off delay circuit 20a, the input terminal S of another turn-off delay circuit 20a, the control terminal G of another turn-off delay circuit 20a, and one end of a resistor. The other end of the resistor is electrically connected to the input terminal of the optocoupler. The output terminal of the optocoupler is electrically connected to the third control terminal G3. The resistor is electrically insulated from the third control terminal G3. The optocoupler can also be replaced with other isolators.

[0115] The output terminal D of one turn-off delay circuit 20a is electrically connected to the first control terminal G1. The output terminal D of another turn-off delay circuit 20a is electrically connected to the second control terminal G2. The first control terminal G1 is electrically connected to the first control electrode E1 of the semiconductor element 14. The second control terminal G2 is electrically connected to the second control electrode E2 of the semiconductor element 14. The third control terminal G3 is electrically connected to the third control electrode E3.

[0116] Figure 18 This is a graph illustrating the characteristics of the control circuit in the first embodiment.

[0117] Figure 18 These represent signals input to the first control terminal G1, the second control terminal G2, and the third control terminal G3 of the semiconductor device 115 to the semiconductor element 14.

[0118] like Figure 18 As shown, the turn-off signal input from the gate driver 30 is inverted by the optocoupler and input as a turn-on signal to the third control terminal G3. The turn-off signal is input to the first control terminal G1 after a first delay time td1 from the turn-on signal input to the third control terminal G3. The turn-off signal is input to the second control terminal G2 after a fourth delay time td4 from the turn-on signal input to the third control terminal G3. The first delay time td1 corresponds to the time constant of one turn-off delay circuit 20a. The fourth delay time td4 corresponds to the time constant of other turn-off delay circuits 20a.

[0119] According to the embodiments, a semiconductor device and its control circuit that can reduce switching losses and conduction losses can be provided.

[0120] The implementation methods may include the following technical solutions.

[0121] (Technical Solution 1) A semiconductor device, comprising: Control signal input terminals; The switching element includes a first control terminal G1 and a second control terminal G2; and The control unit includes control terminal G, input terminal S, and output terminal D. The control unit includes: The control switching element includes a control terminal Gs, an input terminal Ss, and an output terminal Ds; and Delay section, The delay section includes an input terminal Din and an output terminal Dout. The delay unit outputs the control voltage Vd to the output terminal Dout after a delay time td elapsed from the moment the voltage input to the input terminal Din switches from the first voltage V1 to the second voltage V2. The input terminal Ss of the control switch element is electrically connected to the input terminal S of the control unit. The output terminal Ds of the control switching element is electrically connected to the output terminal D of the control unit. The input terminal Din of the delay section is electrically connected to the control terminal G of the control section, and the output terminal Dout of the delay section is electrically connected to the control terminal Gs of the control switching element. The first control terminal G1 of the switching element is electrically connected to the input terminal S of the control unit. The second control terminal G2 of the switching element is electrically connected to the output terminal D of the control unit.

[0122] (Technical Solution 2) According to the semiconductor device described in technical solution 1, the control switching element is a transistor.

[0123] (Technical Solution 3) According to any one of technical solutions 1 to 2, the control switching element of the semiconductor device is any one of MOSFET, bipolar transistor, IGBT, Gan-HEMT, and Gan-HEMT connected to MOSFET via common source and common gate.

[0124] (Technical Solution 4) According to any one of technical solutions 1 to 3, in the semiconductor device, the control switching element does not perform body diode operation between the input terminal Ss and the output terminal Ds.

[0125] (Technical Solution 5) According to any one of technical solutions 1 to 4, in the semiconductor device, the voltage withstand capability of the control switching element is 20V or higher and 200V or lower.

[0126] (Technical Solution 6) According to any one of technical solutions 1 to 5, the control switching element is disconnected when the gate voltage exceeds a first threshold voltage and is in an off state when the gate voltage is zero volts.

[0127] (Technical Solution 7) According to any one of technical solutions 1 to 5, the control switching element is disconnected when the gate voltage is below the second threshold voltage and is in an off state when the gate voltage is zero volts.

[0128] (Technical Solution 8) According to any one of technical solutions 1 to 5, the semiconductor device is in a state where the control switching element is disconnected when the gate voltage exceeds a first threshold voltage and connected when the gate voltage is zero volts.

[0129] (Technical Solution 9) According to any one of technical solutions 1 to 5, the control switching element is disconnected when the gate voltage is below the second threshold voltage and is in the on state when the gate voltage is zero volts.

[0130] (Technical Solution 10) According to any one of technical solutions 1 to 9, the connection from the control signal input terminal to the input terminal Ss of the control switch element, and the connection from the control terminal G of the control unit to the control terminal Gs of the control switch element, include the case of a connection considered to be via a capacitor, or include a connection based on an optocoupler or the like for receiving and emitting signals.

[0131] (Technical Solution 11) According to any one of technical solutions 1 to 10, in the semiconductor device, one or more of the following components are sandwiched between the output terminal Dout of the delay section and the control terminal Gs of the control switching element: a resistor, a coil, a capacitor, a diode, a switch, an operational amplifier, and an optocoupler.

[0132] (Technical Solution 12) According to any one of technical solutions 1 to 11, in the semiconductor device, a diode, a switch, an operational amplifier, and any one or more optocouplers are sandwiched between the input terminal Din of the delay section and the control terminal Gs of the control switching element.

[0133] (Technical Solution 13) According to any one of technical solutions 1 to 12, the delay section of the semiconductor device includes at least one of a resistor, a coil, a capacitor, an operational amplifier, and a logic circuit.

[0134] (Technical Solution 14) The semiconductor device according to any one of technical solutions 1 to 13 further includes other control units. A resistor, coil, capacitor, diode, switch, operational amplifier, optocoupler, and one or more other components from the control unit are sandwiched between the control signal input terminal and the input terminal S of the control unit, between the control signal input terminal and the first control terminal G1 of the switching element, between the input terminal S of the control unit and the first control terminal G1 of the switching element, and between the output terminal D of the control unit and the second control terminal G2 of the switching element.

[0135] (Technical Solution 15) According to the semiconductor device of technical solution 14, the control terminal G of the control unit is electrically connected to one of the input terminal S, the input terminal S' of the other control unit, and the output terminal D' of the other control unit.

[0136] (Technical Solution 16) In any one of technical solutions 1 to 15, the switching element of the semiconductor device is a vertical MOSFET or a vertical IGBT.

[0137] (Technical Solution 17) According to any one of technical solutions 1 to 16, the semiconductor device includes a first control electrode E1, a second control electrode E2, and a third control electrode E3.

[0138] (Technical Solution 18) According to any one of technical solutions 1 to 17, the semiconductor device has a control electrode on the back side.

[0139] (Technical Solution 19) According to any one of technical solutions 1 to 18, the semiconductor device has an N-cathode region and a P-cathode region on the back side.

[0140] (Technical Solution 20) According to any one of technical solutions 1 to 16, the semiconductor device, the switching element is a trench-type device, which includes a first control electrode E1 and a second control electrode E2 in a trench, and the first control terminal G1 and the second control terminal G2 are respectively connected to one of the first control electrode E1 and the second control electrode E2.

[0141] (Technical Solution 21) The semiconductor device according to any one of claims 1 to 20, wherein a part of said control unit is built in said switching element.

[0142] (Claim 22) The semiconductor device according to any one of claims 1 to 21, wherein when the voltage applied to said control terminal G of said control unit changes from a first voltage V1 to a second voltage V2, in a case where the first voltage V1 < the second voltage V2, said control switching element is turned on or off after delaying a delay time td dependent on the time constant of said delay unit, and in a case where the first voltage V1 > the second voltage V2, said control switching element is turned on or off with a delay time td' (< td).

[0143] (Claim 23) The semiconductor device according to any one of claims 1 to 22, wherein when the voltage applied to said control terminal G of said control unit changes from a first voltage V1 to a second voltage V2, in a case where the first voltage V1 > the second voltage V2, said control switching element is turned on or off after delaying a delay time td1 dependent on the time constant of said delay unit, and in a case where the first voltage V1 < the second voltage V2, said control switching element is turned on or off with a delay time td2 (< td1).

[0144] (Claim 24) The semiconductor device according to any one of claims 1 to 23, wherein a voltage change applied to the second control terminal G2 of said switching element is delayed by a time dependent on the time constant of said delay unit relative to a voltage change of the first control terminal G1.

[0145] In the above, embodiments of the present invention have been described with reference to specific examples. However, the present invention is not limited to these specific examples. For example, the specific configurations of respective elements such as electrodes, wiring members, semiconductor members, semiconductor regions, conductive members and insulating regions included in a semiconductor device are included in the scope of the present invention as long as those skilled in the art can properly select them from well-known ranges to implement the present invention in the same manner and obtain the same effects.

[0146] In addition, any solution obtained by combining any two or more elements of the respective specific examples within the technically feasible range is included in the scope of the present invention as long as it contains the gist of the present invention.

[0147] Furthermore, as embodiments of the present invention, based on the above-described semiconductor device and semiconductor module, all semiconductor devices and semiconductor modules that can be implemented by those skilled in the art through appropriate design modifications are also within the scope of the present invention as long as they contain the gist of the present invention.

[0148] Furthermore, within the scope of the present invention, those skilled in the art will be able to conceive of various modifications and alterations, which also fall within the scope of the present invention.

[0149] Several embodiments of the present invention have been described, but these embodiments are provided by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments or variations thereof are included in the scope or spirit of the invention, and are included within the scope of the invention as described in the claims and its equivalents.

Claims

1. A semiconductor device, wherein, include: Control signal input terminals; The switching element includes a first control terminal (G1) and a second control terminal (G2); as well as The control unit includes control terminals (G), input terminals (S), and output terminals (D). The control unit includes: The control switching element includes a control terminal (Gs), an input terminal (Ss), and an output terminal (Ds). as well as Delay section, The delay section includes an input terminal (Din) and an output terminal (Dout). The delay unit outputs the control voltage (Vd) to the output terminal (Dout) after a delay time (td) elapses from the moment the voltage input to the input terminal (Din) switches from the first voltage (V1) to the second voltage (V2). The input terminal (Ss) of the control switch element is electrically connected to the input terminal (S) of the control unit. The output terminal (Ds) of the control switching element is electrically connected to the output terminal (D) of the control unit. The input terminal (Din) of the delay section is electrically connected to the control terminal (G) of the control section, and the output terminal (Dout) of the delay section is electrically connected to the control terminal (Gs) of the control switching element. The first control terminal (G1) of the switching element is electrically connected to the input terminal (S) of the control unit. The second control terminal (G2) of the switching element is electrically connected to the output terminal (D) of the control unit.

2. The semiconductor device according to claim 1, wherein, The control switching element is a transistor.

3. The semiconductor device according to claim 1, wherein, The control switching element is one of the following: metal oxide semiconductor transistor (MOSFET), bipolar transistor, insulated gate bipolar transistor (IGBT), gallium nitride high electron mobility transistor (GaN-HEMT), and GaN-HEMT connected to the MOSFET via a common source and common gate.

4. The semiconductor device according to claim 2, wherein, The control switching element does not perform body diode operation between the input terminal (Ss) and the output terminal (Ds).

5. The semiconductor device according to claim 2, wherein, The voltage withstand capability of the control switch element is above 20V and below 200V.

6. The semiconductor device according to claim 2, wherein, The control switch element is disconnected when the gate voltage exceeds the first threshold voltage, and is in the off state when the gate voltage is zero volts.

7. The semiconductor device according to claim 2, wherein, The control switch element is disconnected when the gate voltage is below the second threshold voltage, and is in the off state when the gate voltage is zero volts.

8. The semiconductor device according to claim 2, wherein, The control switch element is disconnected when the gate voltage exceeds the first threshold voltage and is turned on when the gate voltage is zero volts.

9. The semiconductor device according to claim 2, wherein, The control switch element is disconnected when the gate voltage is below the second threshold voltage and is turned on when the gate voltage is zero volts.

10. The semiconductor device according to claim 2, wherein, The connection from the control signal input terminal to the input terminal (Ss) of the control switch element, and the connection from the control terminal (G) of the control unit to the control terminal (Gs) of the control switch element, include connections considered to be via capacitors, or connections based on photoelectric couplers or the like for receiving and transmitting light signals.

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