Calibration method, device, equipment and medium of time-interleaved analog-to-digital converter

Abstract

The application provides a calibration method, device, equipment and medium for a time-interleaved analog-to-digital converter, which comprises the following steps: a pseudo-random sequence generator sends a pseudo-random noise sequence to all sub-analog-to-digital converters and all digital calibration engines; based on any sub-analog-to-digital converter, the sub-analog-to-digital converter acquires an analog input signal, a gain modulator performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain an original digital output signal; based on any digital calibration engine, the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine is acquired, offset calibration and reverse demodulation are performed on the original digital output signal based on the pseudo-random noise sequence to obtain a sub-digital output signal; and all the acquired sub-digital output signals are spliced to obtain a total digital output signal. According to the technical scheme of the embodiment of the application, noise caused by inter-channel offset mismatch is suppressed, and the spurious-free dynamic range and the signal-to-noise distortion ratio of the time-interleaved analog-to-digital converter are improved.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a calibration method, apparatus, device, and medium for a time-interleaved analog-to-digital converter. Background Technology

[0002] With the rapid development of modern communication technology, radar detection, broadband oscilloscopes, and high-energy physics experiments, the performance requirements for the core component of the signal processing front-end—the analog-to-digital converter (ADC)—are becoming increasingly stringent. In 5G / 6G base station communication, optical communication networks, and phased array radar systems, the sampling rate and bandwidth of ADCs typically need to reach gigabits per second (GS / s) or even higher, while maintaining high resolution and dynamic range.

[0003] Limited by the physical limitations of semiconductor process nodes, single-core ADCs face technical bottlenecks in pursuing ultra-high sampling rates, including exponentially increasing power consumption, dramatically increased design complexity, and a sharp decline in conversion accuracy. Currently, this technical problem is addressed through the Time-Interleaved Analog-to-Digital Converter (TI ADC) architecture. TI ADC interleaves the sampling of M parallel sub-ADCs. The system's master clock frequency is fs, and each sub-ADC only needs to operate at a lower frequency of fs / M. Through precise clock phase control, each sub-ADC samples the input signal sequentially, and the digital outputs of each channel are finally concatenated, thus achieving a high sampling rate at the overall system master clock frequency. TI ADC breaks through the speed limitations of single-core ADCs, achieving ultra-high-speed sampling with lower hardware cost and power consumption.

[0004] However, the performance of TI ADCs is severely limited by non-ideal mismatches between channels, i.e., channel offset mismatches. Due to random deviations in the manufacturing process, offset mismatches inevitably exist between the channels of each sub-analog-to-digital converter. To eliminate offset mismatches, existing technologies mainly employ front-end calibration, statistically based back-end calibration, and calibration based on chopping or randomization.

[0005] In front-end calibration, the process typically occurs during system power-on initialization or idle periods. The system cuts off input signals, shorts the inputs of each sub-ADC to common-mode level, measures the static output value of each channel as offset error, and stores it in a register. During normal operation, this error value is subtracted from the output data using digital logic. Its working principle utilizes the system's sleep period for static measurement. It is widely used in consumer electronics devices where continuous operation is not critical and interrupted sampling is permissible. However, front-end calibration cannot handle dynamic changes (poor PVT sensitivity); it is only performed once at startup and cannot track offset drift caused by temperature rise and voltage fluctuations during chip operation. In high-speed systems operating for extended periods, offset errors caused by temperature drift reappear, leading to performance degradation over time. Furthermore, this method requires system interruption, which is unacceptable for communication base stations or real-time monitoring systems requiring 24-hour continuous operation. Statistical digital back-end calibration is currently the most widely used technique.

[0006] In statistical background calibration, the core idea is to assume that the statistical mean of the input signal is zero over a long period (or that the statistical characteristics of the input signals of each channel are consistent). By averaging the output data of each sub-ADC over a long period, the DC offset of each channel is estimated, and subtraction calibration is performed in the digital domain. Its working principle is to extract the error using the statistical property that E[x(n) + OS_i] ≈ OS_i (assuming E[x(n)] ≈ 0). This is commonly used in communication receivers because communication signals are usually modulated, exhibiting good randomness and zero-mean characteristics. However, statistical background calibration heavily relies on the characteristics of the input signal (correlation issues); traditional statistical calibration algorithms are based on the assumption that "the DC component of the input signal is zero" or "the signal is uncorrelated with channel selection." However, in practical applications, this assumption often fails: when the input signal itself contains a DC component, or when the input signal frequency is exactly an integer multiple of fs / M, the statistical averaging method will misjudge the input signal itself as an offset error and filter it out, destroying the useful signal. If the input signal has specific periodic characteristics, traditional adaptive filtering algorithms (such as the LMS algorithm) may get stuck in local minima or even diverge, leading to calibration failure.

[0007] In chopper-based or randomized calibration techniques, a chopper switch is introduced at the analog front end to reverse the polarity of the input signal using a pseudo-random sequence. Its working principle is to decouple the input signal from the inter-channel offset mismatch error through random polarity reversal, thereby eliminating the impact of inter-channel offset mismatch on performance without relying on the input signal frequency or statistical characteristics. However, in chopper and randomized techniques, analog chopper switches are difficult to design in high-speed circuits and introduce additional clock feedthrough and charge injection errors, limiting input linearity.

[0008] In summary, existing calibration methods for offset mismatch in time-interleaved analog-to-digital converters (ADCs) fail in applications where the content of the input signal is unknown. This results in the input signal acquired by the time-interleaved ADC being overwhelmed by noise, leading to a small spurious-free dynamic range (SFDR) and signal-to-noise distortion rate (SNDR) for the time-interleaved ADC. Summary of the Invention

[0009] This invention aims to at least solve one of the technical problems existing in the prior art. To this end, this invention proposes a calibration method, apparatus, device, and medium for a time-interleaved analog-to-digital converter (ADC). By utilizing the uncorrelation between pseudo-random noise sequences and analog input signals, the calibration process is decoupled from the analog input signals, thereby significantly suppressing spurious emissions caused by inter-channel offset mismatch and improving the spurious-free dynamic range and signal-to-noise ratio of the time-interleaved ADC.

[0010] In a first aspect, embodiments of the present invention provide a calibration method for a time-interleaved analog-to-digital converter (ADC). The time-interleaved ADC includes a pseudo-random sequence generator, multiple paired, cascaded sub-ADCs, and a digital calibration engine. All the sub-ADCs are connected in parallel to the pseudo-random sequence generator, and all the digital calibration engines are connected in parallel to the pseudo-random sequence generator. A gain modulator is integrated at the front end of each sub-ADC. The method includes: The pseudo-random sequence generator sends the generated pseudo-random noise sequence to all the sub-analog-to-digital converters and all the digital calibration engines, wherein the pseudo-random noise sequence is used to drive the overall gain of the sub-channels corresponding to the sub-analog-to-digital converters to change randomly; Based on any of the sub-analog-to-digital converters, the sub-analog-to-digital converter acquires an analog input signal, and the gain modulator integrated in the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain the original digital output signal; Based on any of the digital calibration engines, the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine is obtained, and the original digital output signal is offset-calibrated and inversely demodulated based on the pseudo-random noise sequence to obtain the sub-digital output signal. All the sub-digital output signals are acquired, and all the sub-digital output signals are concatenated to obtain the total digital output signal.

[0011] According to some embodiments of the present invention, the gain modulator includes a series-connected variable gain buffer and a quantizer, wherein the gain of the variable gain buffer is variable and the variable gain buffer is driven by the pseudo-random noise sequence; The gain modulator integrated into the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain the original digital output signal, including: The gain modulator acquires the pseudo-random noise sequence, randomly assigns a pseudo-random noise value based on the pseudo-random noise sequence, and causes the overall gain of the sub-channel corresponding to the sub-analog-to-digital converter to change randomly according to the pseudo-random noise value. The variable gain buffer randomly modulates the analog input signal and outputs an analog modulated signal. The pseudo-random noise sequence includes two pseudo-random noise values, and the pseudo-random noise value is equal to zero or one. The quantizer performs quantization processing on the acquired analog modulation signal to obtain the original digital output signal.

[0012] According to some embodiments of the present invention, the gain modulator randomly changes the overall gain of the sub-channel corresponding to the sub-analog-to-digital converter based on the pseudo-random noise value, and the variable gain buffer randomly modulates the analog input signal to output an analog modulated signal, including: When the pseudo-random noise value is zero, the gain of the variable gain buffer is one, and the variable gain buffer multiplies the acquired analog input signal by one to obtain the analog modulation signal. Alternatively, when the pseudo-random noise value is one, the gain of the variable gain buffer is a preset gain coefficient, and the variable gain buffer multiplies the acquired analog input signal by the preset gain coefficient to obtain the analog modulation signal.

[0013] According to some embodiments of the present invention, the digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset calibration module includes a first subtractor. The output terminal of the sub-analog-to-digital converter is connected to the input terminal of the offset detection module and the input terminal of the first subtractor, respectively. The output terminal of the offset detection module is connected to the input terminal of the first subtractor, and the output terminal of the first subtractor is connected to the gain demodulation module. Acquire the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine, and perform offset calibration and inverse demodulation on the original digital output signal based on the pseudo-random noise sequence to obtain the sub-digital output signal, including: The offset detection module extracts the offset error value of the sub-analog-to-digital converter based on the acquired original digital output signal and the pseudo-random noise sequence. The first subtractor subtracts the offset error value from the original digital output signal to obtain a preliminary offset calibration signal; The gain demodulation module performs inverse demodulation on the acquired preliminary offset calibration signal based on the pseudo-random noise value to obtain the sub-digital output signal.

[0014] According to some embodiments of the present invention, the offset detection module includes a first shunt component and a second shunt component. Both the first shunt component and the second shunt component include a first multiplier, an accumulator and an averager connected in series. The output terminal of the first shunt component is connected to a second subtractor. The output terminal of the second shunt component is connected in series with the second multiplier and the second subtractor. The output terminal of the second subtractor is connected to a third multiplier. The offset detection module extracts the offset error value of the sub-analog-to-digital converter based on the acquired original digital output signal and the pseudo-random noise sequence, including: In the first splitter component, the first multiplier acquires the original digital output signal and the pseudo-random noise value. The first multiplier outputs the original digital output signal corresponding to the pseudo-random noise value of one to the accumulator. The accumulator accumulates all the acquired original digital output signals and sends them to the averager. The averager outputs a first accumulated average value based on all the accumulated original digital output signals. In the second splitter component, the first multiplier acquires the original digital output signal and the inverse signal of the pseudo-random noise value. The first multiplier outputs the original digital output signal corresponding to the pseudo-random noise value that is zero to the accumulator. The accumulator accumulates all the acquired original digital output signals and sends them to the averager. The averager outputs a second accumulated average value based on all the accumulated original digital output signals. Wherein, when the pseudo-random noise value is equal to one, the inverse signal of the pseudo-random noise value is equal to zero, or when the pseudo-random noise value is equal to zero, the inverse signal of the pseudo-random noise value is equal to one. The second multiplier multiplies the second accumulated average value and the preset gain coefficient to obtain a multiplication result, and sends the multiplication result to the second subtractor. The second subtractor performs a difference operation based on the obtained first accumulated average value and the multiplication result to obtain a difference result. The third multiplier multiplies the obtained difference result by a scaling factor to obtain the offset error value, wherein the scaling factor is equal to 1 / (1-α), α is the preset gain coefficient, and the difference result is equal to the difference between the first accumulated average value and the multiplication result.

[0015] According to some embodiments of the present invention, the gain demodulation module includes a fourth multiplier and a multiplexer, wherein the input of the fourth multiplier is connected to the first subtractor and the multiplexer, respectively; The gain demodulation module performs inverse demodulation on the acquired preliminary offset calibration signal based on the pseudo-random noise value to obtain the sub-digital output signal, including: The multiplexer acquires the pseudo-random noise value and determines the gain recovery coefficient based on the pseudo-random noise value. When the pseudo-random noise value is equal to zero, the gain recovery coefficient is equal to one, or when the pseudo-random noise value is equal to one, the gain recovery coefficient is equal to 1 / α, where α is the preset gain coefficient. The fourth multiplier acquires the preliminary offset calibration signal and the gain recovery coefficient, multiplies the preliminary offset calibration signal and the gain recovery coefficient, and performs inverse demodulation to obtain the sub-digital output signal.

[0016] In a second aspect, embodiments of the present invention provide a calibration apparatus for a time-interleaved analog-to-digital converter, including at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor, which, when executed by the at least one control processor, enables the at least one control processor to perform the calibration method for the time-interleaved analog-to-digital converter as described in the first aspect above.

[0017] Thirdly, embodiments of the present invention provide an electronic device including a calibration device for a time-interleaved analog-to-digital converter as described in the second aspect above.

[0018] Fourthly, embodiments of the present invention provide a computer-readable storage medium storing computer-executable instructions for performing the calibration method of the time-interleaved analog-to-digital converter as described in the first aspect above.

[0019] The calibration method for a time-interleaved analog-to-digital converter according to an embodiment of the present invention has at least the following beneficial effects: the pseudo-random sequence generator sends a generated pseudo-random noise sequence to all the sub-analog-to-digital converters and all the digital calibration engines, wherein the pseudo-random noise sequence is used to drive the overall gain of the sub-channels corresponding to the sub-analog-to-digital converters to undergo random changes; based on any one of the sub-analog-to-digital converters, the sub-analog-to-digital converter acquires an analog input signal, and the gain modulator integrated in the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain an original digital output signal; based on any one of the digital calibration engines, the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine is acquired, and a sub-digital output signal is obtained based on the acquired original digital output signal and the pseudo-random noise sequence; all the sub-digital output signals are acquired, and all the sub-digital output signals are concatenated to obtain a total digital output signal. According to the technical solution of the present invention, the uncorrelation between pseudo-random noise sequence and analog input signal is used to realize random modulation of analog input signal. Combined with digital calibration engine, the offset error of each sub-analog-to-digital converter is eliminated, and the modulation noise is eliminated by reverse demodulation, thereby significantly suppressing spurious caused by channel mismatch and greatly improving the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) of the system. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the overall architecture of a time-interleaved analog-to-digital converter provided in one embodiment of the present invention; Figure 2 This is a detailed schematic diagram of the internal logic structure and signal processing flow of a digital calibration engine provided in another embodiment of the present invention; Figure 3 This is a flowchart of a calibration method for a time-interleaved analog-to-digital converter provided in another embodiment of the present invention; Figure 4 This is a detailed schematic diagram illustrating the working state and principle of a gain modulator provided in another embodiment of the present invention; Figure 5 This is a structural diagram of a calibration device for a time-interleaved analog-to-digital converter provided in another embodiment of the present invention. Detailed Implementation

[0021] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0022] In the description of this invention, it should be understood that the orientation descriptions, such as up, down, front, back, left, right, etc., are based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention.

[0023] In the description of this invention, "several" means one or more, "more than" means two or more, "greater than," "less than," and "exceeding" are understood to exclude the stated number, while "above," "below," and "within" are understood to include the stated number. The use of "first" and "second" in the description is merely for distinguishing technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0024] In the description of this invention, unless otherwise explicitly defined, terms such as "setting," "installing," and "connecting" should be interpreted broadly, and those skilled in the art can reasonably determine the specific meaning of the above terms in this invention in conjunction with the specific content of the technical solution.

[0025] According to the technical solution of the embodiments of the present invention, the present invention provides a calibration method, apparatus, device and medium for a time-interleaved analog-to-digital converter (ADC). The calibration method for the time-interleaved ADC includes: a pseudo-random sequence generator sending a generated pseudo-random noise sequence to all the sub-ADCs and all the digital calibration engines, wherein the pseudo-random noise sequence is used to drive a random change in the overall gain of the sub-channels corresponding to the sub-ADCs; based on any one of the sub-ADCs, the sub-ADC acquires an analog input signal, and the gain modulator integrated in the sub-ADC performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain an original digital output signal; based on any one of the digital calibration engines, the original digital output signal output by the sub-ADC connected in series with the digital calibration engine is acquired, and a sub-digital output signal is obtained based on the acquired original digital output signal and the pseudo-random noise sequence; all the sub-digital output signals are acquired, and all the sub-digital output signals are concatenated to obtain a total digital output signal. According to the technical solution of the present invention, the uncorrelation between pseudo-random noise sequence and analog input signal is used to realize random modulation of analog input signal. Combined with digital calibration engine, the offset error of each sub-analog-to-digital converter is eliminated, and the modulation noise is eliminated by reverse demodulation, thereby significantly suppressing spurious caused by channel mismatch and greatly improving the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) of the system.

[0026] First, refer to Figure 1 , Figure 1 This is a schematic diagram of the overall architecture of a time-interleaved analog-to-digital converter.

[0027] like Figure 1 As shown, the time-interleaved analog-to-digital converter in this embodiment includes a pseudo-random sequence generator, multiple paired cascaded sub-analog-to-digital converters, and a digital calibration engine. All sub-analog-to-digital converters are connected in parallel to the pseudo-random sequence generator, and all digital calibration engines are connected in parallel to the pseudo-random sequence generator. The front end of the sub-analog-to-digital converters integrates a gain modulator.

[0028] It should be noted that, in Figure 1 In this context, Vin is the analog input signal, sub-ADC is the sub-analog-to-digital converter, sub-ADC_M is the Mth sub-analog-to-digital converter, Dout1_raw is the raw digital output signal of the first sub-analog-to-digital converter, OS is the offset error value, Dout1_cal is the sub-digital output signal of the first sub-analog-to-digital converter and the digital calibration engine connected in series with it; PN is a pseudo-random noise sequence.

[0029] It should be noted that the time-interleaved analog-to-digital converter of this application includes a pseudo-random sequence generator, multiple parallel sub-analog-to-digital converters (time-interleaved sub-channels), and a digital calibration engine connected to each sub-channel respectively.

[0030] It should be noted that the pseudo-random sequence generator is used to generate pseudo-random noise (PN) sequences.

[0031] It should be noted that each sub-channel has an integrated gain modulator at its front end, which is used to modulate the acquired analog input signal.

[0032] Additionally, refer to Figure 1 The gain modulator includes a variable gain buffer and a quantizer connected in series. The gain of the variable gain buffer is variable and is driven by a pseudo-random noise sequence.

[0033] It should be noted that the gain modulator includes a variable gain buffer, which receives the analog input signal and drives the quantizer connected in series with it.

[0034] It should be noted that the gain of the gain modulator is variable, and the gain of the gain modulator is controlled by a pseudo-random noise sequence (PN sequence).

[0035] Additionally, refer to Figure 2 , Figure 2 This is a detailed schematic diagram of the internal logic structure and signal processing flow of a digital calibration engine provided in another embodiment of the present invention. The digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset calibration module includes a first subtractor. The output terminal of the sub-analog-to-digital converter is connected to the input terminal of the offset detection module and the input terminal of the first subtractor, respectively. The output terminal of the offset detection module is connected to the input terminal of the first subtractor, and the output terminal of the first subtractor is connected to the gain demodulation module.

[0036] It should be noted that, in Figure 2 In this context, Dout_raw is the raw digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine, α is the preset gain coefficient, PN is the pseudo-random noise sequence, OS is the offset error value, and Dout_cal is the sub-digital output signal output by the digital calibration engine.

[0037] It should be noted that the digital calibration engine internally includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset calibration module is the first subtractor, which is used to eliminate the offset mismatch of this sub-channel.

[0038] It should be noted that the digital calibration engine can quickly and accurately extract and eliminate the offset error values ​​of each sub-channel, and in conjunction with the gain demodulation logic, eliminate modulation noise, thereby significantly suppressing spurious noise caused by channel mismatch and greatly improving the system's spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR).

[0039] Additionally, refer to Figure 2 The offset detection module includes a first shunt component and a second shunt component. Both the first shunt component and the second shunt component include a first multiplier, an accumulator and an averager connected in series. The output of the first shunt component is connected to the second subtractor. The output of the second shunt component is connected in series with the second multiplier and the second subtractor. The output of the second subtractor is connected to the third multiplier.

[0040] It should be noted that the offset detection module can calculate the precise offset error (OS) value of the corresponding sub-channel. The first and second shunt components are used to shunt the original digital output signals corresponding to different pseudo-random noise values, respectively, splitting all the original digital output signals into original digital output signals with a pseudo-random noise value of one and original digital output signals with a pseudo-random noise value of zero.

[0041] Additionally, refer to Figure 2 The gain demodulation module includes a fourth multiplier and a multiplexer. The input of the fourth multiplier is connected to the first subtractor and the multiplexer, respectively.

[0042] It should be noted that the gain demodulation module multiplies the signal with the offset error eliminated by the corresponding gain recovery coefficient to complete the inverse gain demodulation, and finally outputs a sub-digital output signal that has removed the effects of offset and gain modulation.

[0043] The following is based on Figure 1 The time-interleaved analog-to-digital converter shown further illustrates the technical solution of this embodiment of the invention.

[0044] Reference Figure 3 , Figure 3 The flowchart illustrates a calibration method for a time-interleaved analog-to-digital converter (ADC) according to an embodiment of the present invention. This calibration method includes, but is not limited to, the following steps: S10, the pseudo-random sequence generator sends the generated pseudo-random noise sequence to all sub-analog-to-digital converters and all digital calibration engines, wherein the pseudo-random noise sequence is used to drive the overall gain of the sub-channels corresponding to the sub-analog-to-digital converters to change randomly.

[0045] It should be noted that the pseudo-random sequence generator is used to generate pseudo-random noise sequences and can send these sequences to all sub-analog-to-digital converters and all digital calibration engines connected to it. The pseudo-random sequence drives random changes in the overall gain of the sub-channels, thereby enabling correlation detection in the digital calibration logic to completely decouple the offset error from the input signal.

[0046] S20: Based on any sub-analog-to-digital converter, the sub-analog-to-digital converter acquires the analog input signal, and the gain modulator integrated in the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on a pseudo-random noise sequence to obtain the original digital output signal.

[0047] It should be noted that the random gain modulation of this application is implemented in the gain modulator; after the analog input signal enters the sub-channel corresponding to each sub-analog-to-digital converter, it first passes through the gain modulator driven by a pseudo-random noise sequence. The gain modulator randomly changes the overall gain of the sub-channel according to the current pseudo-random noise value, thereby realizing random modulation of the input signal.

[0048] It should be noted that the randomly modulated analog signal is quantized by the quantizer in the sub-ADC to generate the original digital output signal, which is then transmitted to the digital calibration engine.

[0049] S30: Based on any digital calibration engine, acquire the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine, and perform offset calibration and inverse demodulation on the original digital output signal based on the pseudo-random noise sequence to obtain the sub-digital output signal.

[0050] It should be noted that the offset detection and calibration in this application are achieved through a digital calibration engine. In the digital calibration engine, the offset error value of the sub-channel is obtained by calculating the original digital output signal and the corresponding pseudo-random noise sequence. The offset error value is then subtracted from the original digital output signal to complete the initial calibration after offset mismatch. The pre-calibrated signal is then inversely demodulated to eliminate the influence of previously introduced random gain variations on signal linearity and modulation noise, resulting in a calibrated and high-precision sub-digital output signal.

[0051] It should be noted that after the analog input signal passes through the sub-analog-to-digital converter and the digital calibration engine, the offset error component of the analog input signal is eliminated, effectively suppressing the fixed-mode noise caused by offset mismatch and significantly improving the spurious-free dynamic range of the system.

[0052] S40: Obtain all sub-digital output signals and concatenate them to obtain the total digital output signal.

[0053] It should be noted that in existing time-interleaved analog-to-digital converters, multiple digital output signals are obtained by interleaving sampling in time through multiple parallel sub-analog-to-digital converters, and then all digital output signals are spliced ​​together to achieve a high sampling rate as a whole. The method of splicing sub-digital output signals to obtain a total digital output signal in this application is prior art and has not been improved in any way, so it will not be elaborated further.

[0054] It should be noted that in existing technologies, time-interleaved analog-to-digital converters (TI ADCs) meet the requirements of high sampling rates, high bandwidth, and high resolution and dynamic range for existing ADCs. However, three main mismatch errors inevitably exist between the sub-ADC channels of TI ADCs: offset mismatch, gain mismatch, and timing skew mismatch. Among these, offset mismatch is the most fundamental and must be addressed first. Offset mismatch refers to the inconsistency in the output DC levels of different sub-ADCs at zero input. In the frequency domain, this periodic offset error manifests as fixed spurs at frequencies of k*fs / M (k=1, 2, …,M-1). These spurs are called "fixed pattern noise," and they severely degrade the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) of the ADC, causing weak signals to be overwhelmed by noise, failing to meet the requirements of high-performance systems. To eliminate offset mismatch, existing technologies mainly employ front-end calibration, statistically based back-end calibration, and calibration based on chopping or randomization. Front-end calibration typically occurs during system power-on initialization or idle periods. The system cuts off the input signal, shorts the inputs of each sub-ADC to common-mode level, measures the static output value of each channel as the offset error, and stores it in a register. During normal operation, this error value is subtracted from the output data via digital logic. Its working principle utilizes the system's sleep period for static measurement. It is widely used in consumer electronics devices where continuous operation requirements are not high and interrupted sampling is permissible. However, front-end calibration cannot handle dynamic changes (poor PVT sensitivity); it is only performed once at startup and cannot track offset drift caused by temperature rise and voltage fluctuations during chip operation. In high-speed systems operating for extended periods, offset errors caused by temperature drift reappear, leading to performance degradation over time. Furthermore, this method requires system interruption, which is unacceptable for communication base stations or real-time monitoring systems requiring 24-hour continuous operation. Statistical digital back-end calibration is currently the most widely used technique. The core idea of ​​this method is to assume that the statistical mean of the input signal is zero over a long period (or that the statistical characteristics of the input signals in each channel are consistent). By accumulating and averaging the output data of each sub-ADC over a long period, the DC offset of each channel is estimated, and subtraction calibration is performed in the digital domain. Its working principle is to extract the error using the statistical property of E[x(n) + OS_i] ≈ OS_i (assuming E[x(n)] ≈ 0).Commonly found in communication receivers, statistical calibration relies heavily on the characteristics of the input signal (correlation issues). Traditional statistical calibration algorithms are based on the assumptions that "the DC component of the input signal is zero" or "the signal is uncorrelated with channel selection." However, in practical applications, this assumption often fails: when the input signal itself contains a DC component, or when the input signal frequency is an integer multiple of fs / M, the statistical averaging method may misjudge the input signal itself as offset error and filter it out, destroying the useful signal. If the input signal has specific periodic characteristics, traditional adaptive filtering algorithms (such as the LMS algorithm) may get stuck in local minima or even diverge, leading to calibration failure. In chopper-based or randomized calibration techniques, a chopper switch is introduced at the analog front end to perform polarity reversal on the input signal using a pseudo-random sequence. Its working principle is to decouple the input signal from the inter-channel offset mismatch error through random polarity reversal, thereby eliminating the impact of inter-channel offset mismatch on performance without relying on the input signal frequency or statistical characteristics. However, in chopper and randomization techniques, analog chopper switches are difficult to design in high-speed circuits, introducing additional clock feedthrough and charge injection errors, which limit input linearity. In summary, existing TIADC offset calibration techniques fall short when facing applications with unknown input signal content (such as those containing DC, low-frequency, or specific periodic signals) and real-time changing environments. In particular, the "input signal correlation" problem has always been a core bottleneck limiting the versatility of statistically based background calibration techniques.

[0055] It should be noted that this invention aims to provide a background calibration method for inter-channel offset mismatch in a time-interleaved analog-to-digital converter (ADC) independent of the input signal. By introducing an innovative channel gain modulation technique, the extraction of offset error is completely decoupled from the input signal, and real-time compensation is performed. This achieves true full background calibration, with calibration accuracy unaffected by the frequency, amplitude, and distribution of the input signal. It converges quickly even with DC input or in silent mode, significantly improving the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) of the ADC.

[0056] In another embodiment, in step S20, the gain modulator integrated into the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on a pseudo-random noise sequence to obtain the original digital output signal, including but not limited to the following steps: S21, the gain modulator acquires a pseudo-random noise sequence, randomly assigns a pseudo-random noise value based on the pseudo-random noise sequence, and the gain modulator causes the overall gain of the sub-channel corresponding to the sub-analog-to-digital converter to change randomly according to the pseudo-random noise value. The variable gain buffer randomly modulates the analog input signal and outputs an analog modulated signal. The pseudo-random noise sequence includes two pseudo-random noise values, which are equal to zero or one. S22, the quantizer quantizes the acquired analog modulated signal to obtain the original digital output signal.

[0057] It should be noted that after the analog input signal enters each sub-channel of the sub-analog-to-digital converter, it first passes through a gain modulator driven by a pseudo-random noise sequence. The gain modulator randomly changes the overall gain of the sub-channel according to the current pseudo-random noise value, thereby achieving random modulation of the analog input signal.

[0058] It should be noted that the modulated analog input signal is quantized by the quantizer in the sub-analog-to-digital converter to generate the original digital output signal, which is then transmitted to the digital calibration engine.

[0059] In another embodiment, in step S21, the gain modulator randomly changes the overall gain of the sub-channel corresponding to the sub-analog-to-digital converter according to the pseudo-random noise value, and the variable gain buffer randomly modulates the analog input signal to output an analog modulated signal, including but not limited to the following steps: S211, when the pseudo-random noise value is zero, the gain of the variable gain buffer is one, and the variable gain buffer multiplies the acquired analog input signal by one to obtain the analog modulated signal. S212, or, when the pseudo-random noise value is one, the gain of the variable gain buffer is a preset gain coefficient, and the variable gain buffer multiplies the acquired analog input signal by the preset gain coefficient to obtain the analog modulated signal.

[0060] It should be noted that, referring to Figure 4 , Figure 4 This is a detailed schematic diagram illustrating the working state and principle of a gain modulator provided in another embodiment of the present invention. When the pseudo-random noise value is 0, the gain of the input gain buffer is set to 1, at which point the output voltage equals the input voltage, that is, the analog modulated signal equals the analog input signal. When the pseudo-random noise value is 1, the gain of the input gain buffer is set to a preset gain coefficient, at which point the output voltage equals the input voltage multiplied by the preset gain coefficient, that is, the analog modulated signal equals the analog input signal multiplied by the preset gain coefficient.

[0061] In another embodiment, step S30 includes, but is not limited to, the following steps: S31, the offset detection module extracts the offset error value of the sub-analog-to-digital converter based on the acquired original digital output signal and pseudo-random noise sequence; S32, the first subtractor subtracts the offset error value from the original digital output signal to obtain the preliminary offset calibration signal; S33, the gain demodulation module performs inverse demodulation on the acquired preliminary offset calibration signal based on the pseudo-random noise value to obtain the sub-digital output signal.

[0062] It should be noted that the offset detection module determines the offset error value of the sub-channel corresponding to the sub-analog-to-digital converter based on the original digital output signal and the pseudo-random noise sequence, and sends the offset error value to the offset calibration module. In the offset calibration module, the calculated offset error value is subtracted from the original signal, thereby eliminating the offset mismatch of the sub-channel. The gain demodulation module performs inverse demodulation of the initial offset calibration signal, thus removing the effects of offset and gain modulation from the initial offset calibration signal.

[0063] In another embodiment, step S31 includes, but is not limited to, the following steps: S311, in the first shunt component, the first multiplier acquires the original digital output signal and the pseudo-random noise value. The first multiplier outputs the original digital output signal corresponding to the pseudo-random noise value of one to the accumulator. The accumulator accumulates all the acquired original digital output signals and sends them to the averager. The averager outputs the first accumulated average value based on all the accumulated original digital output signals. S312, in the second shunt component, the first multiplier acquires the original digital output signal and the inverse signal of the pseudo-random noise value. The first multiplier outputs the original digital output signal corresponding to the pseudo-random noise value that is zero to the accumulator. The accumulator accumulates all the acquired original digital output signals and sends them to the averager. The averager outputs a second accumulated average value based on all the accumulated original digital output signals. Wherein, when the pseudo-random noise value is equal to one, the inverse signal of the pseudo-random noise value is equal to zero, or when the pseudo-random noise value is equal to zero, the inverse signal of the pseudo-random noise value is equal to one. S313, the second multiplier multiplies the second accumulated average value and the preset gain coefficient to obtain the multiplication result, and sends the multiplication result to the second subtractor. The second subtractor performs a difference operation based on the obtained first accumulated average value and the multiplication result to obtain the difference result. The third multiplier multiplies the obtained difference result by the scaling factor to obtain the offset error value, where the scaling factor is equal to 1 / (1-α), α is the preset gain coefficient, and the difference result is equal to the difference between the first accumulated average value and the multiplication result.

[0064] It should be noted that in the offset detection module, the first and second splitting components perform splitting processing based on the original digital output signal and its corresponding pseudo-random noise value (positive or negative phase), thereby separating the data stream Dout_raw(PN=0) of the original digital output signal with zero pseudo-random noise value and the data stream Dout_raw(PN=1) of the original digital output signal with one pseudo-random noise value. These two data streams are then accumulated in accumulators and their averages are calculated by averagers. During this process, the statistically uncorrelated nature of the pseudo-random sequence (PN) and the analog input signal (Vin) is utilized to eliminate the influence of the analog input signal on the averages calculated by the two averagers.

[0065] It should be noted that the accumulated average value of the original digital output signal data stream Dout_raw(PN=1) with a pseudo-random noise value of 1 is the first accumulated average value, and the accumulated average value of the original digital output signal data stream Dout_raw(PN=0) with a pseudo-random noise value of zero is the second accumulated average value.

[0066] It should be noted that the second accumulated average value is multiplied by the preset gain coefficient α, and then the difference is calculated (i.e., subtraction) with the first accumulated average value to obtain the difference result; the difference result is further multiplied by the scaling factor 1 / (1-α) to calculate the precise offset error (OS) value of the sub-channel, thereby realizing the operation of the first accumulated average value and the second accumulated average value to extract the offset error.

[0067] In another embodiment, step S33 includes, but is not limited to, the following steps: S331, the multiplexer acquires the pseudo-random noise value and determines the gain recovery coefficient based on the pseudo-random noise value. When the pseudo-random noise value is equal to zero, the gain recovery coefficient is equal to one, or when the pseudo-random noise value is equal to one, the gain recovery coefficient is equal to 1 / α, where α is a preset gain coefficient. S332, the fourth multiplier obtains the preliminary offset calibration signal and the gain recovery coefficient, multiplies the preliminary offset calibration signal and the gain recovery coefficient and performs inverse demodulation to obtain the sub-digital output signal.

[0068] It should be noted that the data inputs of the multiplexer (MUX) are the constants 1 and 1 / α (where α is the preset gain coefficient), and the selection input is a pseudo-random noise sequence. In the gain demodulation module, the pseudo-random noise value enters a multiplexer (MUX) controlled by the pseudo-random noise sequence. The multiplexer selects the gain restoration coefficient based on the current pseudo-random noise value: when the pseudo-random noise value is zero, indicating a specific state, a gain restoration coefficient of 1 is selected; while in another state, when the pseudo-random noise value is one, a gain restoration coefficient of 1 / α (where α is the preset gain coefficient) is selected. The initial offset calibration signal (the signal that has eliminated the offset error) is multiplied by the corresponding gain restoration coefficient to complete the inverse gain demodulation, and finally outputs a high-precision sub-digital output signal (Dout_cal) that has removed the effects of offset and gain modulation.

[0069] It should be noted that the calibration method of the time-interleaved analog-to-digital converter of the present invention is independent of the content of the analog input signal of the time-interleaved analog-to-digital converter and can realize background calibration of inter-channel offset mismatch.

[0070] It should be noted that by introducing a gain modulator controlled by a pseudo-random noise sequence (PN) at the analog front end, the calibration process is successfully decoupled from the statistical characteristics of the input signal, effectively solving the problem of traditional statistical-based background calibration techniques failing under certain input conditions. Utilizing the uncorrelation between the pseudo-random noise sequence and the analog input signal, the digital calibration engine can quickly and accurately extract and eliminate the offset errors of each sub-channel. Combined with gain demodulation logic to eliminate modulation noise, this significantly suppresses spurious noise caused by channel mismatch, greatly improving the system's spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR). Furthermore, the calibration method of this application operates in the background, converges rapidly, and can track and compensate for dynamic errors caused by temperature, voltage, or aging in real time. It also has low analog overhead and is easy to integrate, ensuring the high performance and robustness of the analog-to-digital converter throughout its entire lifecycle and under any input scenario.

[0071] It should be noted that the calibration method of this application does not require interruption of the normal signal acquisition process, thus enabling full background operation. Furthermore, the calibration accuracy and convergence of the method should not depend on the spectral characteristics, amplitude, or statistical distribution of the analog input signal. Regardless of whether the input is DC, a sine wave, or in a silent state, the calibration can accurately extract and eliminate offset errors; that is, the calibration method of this application is input-signal-independent. The calibration method of this application avoids complex modifications to analog circuits, relying primarily on digital logic for implementation, to adapt to the digitalization trend of advanced processes, resulting in low hardware overhead and high robustness.

[0072] It should be noted that the main objective of this invention is to detect and correct the offset mismatch of each channel in real time, quickly, and accurately without affecting the normal conversion function of the analog-to-digital converter (ADC). Even when the input signal has a strong DC component or specific frequency interference, the accuracy of the calibration can be guaranteed, thereby significantly improving the SFDR and SNDR of the time-interleaved ADC and meeting the needs of high-performance communication and measurement systems. This invention addresses the problem that existing statistical background calibration techniques for time-interleaved ADCs heavily rely on the statistical characteristics of the input signal and fail when processing DC or periodic signals. It provides a calibration method for inter-channel offset mismatch that is independent of the input signal.

[0073] It should be noted that this invention introduces a random gain modulation mechanism into the sub-channels, using a pseudo-random sequence to drive random changes in the overall gain of the sub-channels. This allows for the complete decoupling of offset errors from the input signal in the digital calibration logic using correlation detection, and enables real-time compensation. This achieves true full-background calibration, where calibration accuracy is unaffected by the frequency, amplitude, and distribution of the input signal. It also converges quickly even with DC input or in silent mode, significantly improving the spurious-free dynamic range (SFDR) and signal-to-noise ratio (SNDR) of time-interleaved analog-to-digital converters.

[0074] like Figure 5 As shown, Figure 5 This is a structural diagram of a calibration apparatus for a time-interleaved analog-to-digital converter (ADC) according to an embodiment of the present invention. The present invention also provides a calibration apparatus for a time-interleaved ADC, comprising: The processor 501 can be implemented using a general-purpose central processing unit (CPU), microprocessor, application specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 502 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 502 can store the operating system and other applications. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called by the processor 501 to execute the calibration method of the time-interleaved analog-to-digital converter of the embodiments of this application. The input / output interface 503 is used to implement information input and output; The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, network cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504); The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.

[0075] This application also provides an electronic device, including a calibration device for a time-interleaved analog-to-digital converter as described above.

[0076] This application also provides a storage medium, which is a computer-readable storage medium, storing a computer program that, when executed by a processor, implements the above-described calibration method for a time-interleaved analog-to-digital converter.

[0077] Memory, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs and non-transitory computer-executable programs. Furthermore, memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, memory may optionally include memory remotely located relative to the processor, and these remote memories can be connected to the processor via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof. The device embodiments described above are merely illustrative, and the units described as separate components may or may not be physically separate, and may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] It will be understood by those skilled in the art that all or some of the steps and systems in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. Furthermore, as is known to those skilled in the art, communication media typically include computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0079] The above provides a detailed description of the preferred embodiments of the present invention. However, the present invention is not limited to the above embodiments. Those skilled in the art can make various equivalent modifications or substitutions without departing from the spirit of the present invention. All such equivalent modifications or substitutions are included within the scope defined by the claims of the present invention.

Claims

1. A calibration method for a time-interleaved analog-to-digital converter, characterized in that, The time-interleaved analog-to-digital converter (ADC) includes a pseudo-random sequence generator, multiple paired cascaded sub-ADCs, and a digital calibration engine. All the sub-ADCs are connected in parallel to the pseudo-random sequence generator, and all the digital calibration engines are connected in parallel to the pseudo-random sequence generator. A gain modulator is integrated at the front end of each sub-ADC. The method includes: The pseudo-random sequence generator sends the generated pseudo-random noise sequence to all the sub-analog-to-digital converters and all the digital calibration engines, wherein the pseudo-random noise sequence is used to drive the overall gain of the sub-channels corresponding to the sub-analog-to-digital converters to change randomly; Based on any of the sub-analog-to-digital converters, the sub-analog-to-digital converter acquires an analog input signal, and the gain modulator integrated in the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain the original digital output signal; Based on any of the digital calibration engines, the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine is obtained, and the original digital output signal is offset-calibrated and inversely demodulated based on the pseudo-random noise sequence to obtain the sub-digital output signal. All the sub-digital output signals are acquired, and all the sub-digital output signals are concatenated to obtain the total digital output signal.

2. The calibration method for a time-interleaved analog-to-digital converter according to claim 1, characterized in that, The gain modulator includes a variable gain buffer and a quantizer connected in series, wherein the gain of the variable gain buffer is variable and the variable gain buffer is driven by the pseudo-random noise sequence; The gain modulator integrated into the sub-analog-to-digital converter performs random modulation and quantization processing on the analog input signal based on the pseudo-random noise sequence to obtain the original digital output signal, including: The gain modulator acquires the pseudo-random noise sequence, randomly assigns a pseudo-random noise value based on the pseudo-random noise sequence, and causes the overall gain of the sub-channel corresponding to the sub-analog-to-digital converter to change randomly according to the pseudo-random noise value. The variable gain buffer randomly modulates the analog input signal and outputs an analog modulated signal. The pseudo-random noise sequence includes two pseudo-random noise values, and the pseudo-random noise value is equal to zero or one. The quantizer performs quantization processing on the acquired analog modulation signal to obtain the original digital output signal.

3. The calibration method for a time-interleaved analog-to-digital converter according to claim 2, characterized in that, The gain modulator randomly changes the overall gain of the sub-channel corresponding to the sub-analog-to-digital converter based on the pseudo-random noise value, and the variable gain buffer randomly modulates the analog input signal to output an analog modulated signal, including: When the pseudo-random noise value is zero, the gain of the variable gain buffer is one, and the variable gain buffer multiplies the acquired analog input signal by one to obtain the analog modulation signal. Alternatively, when the pseudo-random noise value is one, the gain of the variable gain buffer is a preset gain coefficient, and the variable gain buffer multiplies the acquired analog input signal by the preset gain coefficient to obtain the analog modulation signal.

4. The calibration method for a time-interleaved analog-to-digital converter according to claim 3, characterized in that, The digital calibration engine includes an offset detection module, an offset calibration module, and a gain demodulation module. The offset calibration module includes a first subtractor. The output of the sub-analog-to-digital converter is connected to the input of the offset detection module and the input of the first subtractor, respectively. The output of the offset detection module is connected to the input of the first subtractor, and the output of the first subtractor is connected to the gain demodulation module. Acquire the original digital output signal output by the sub-analog-to-digital converter connected in series with the digital calibration engine, and perform offset calibration and inverse demodulation on the original digital output signal based on the pseudo-random noise sequence to obtain the sub-digital output signal, including: The offset detection module extracts the offset error value of the sub-analog-to-digital converter based on the acquired original digital output signal and the pseudo-random noise sequence. The first subtractor subtracts the offset error value from the original digital output signal to obtain a preliminary offset calibration signal; The gain demodulation module performs inverse demodulation on the acquired preliminary offset calibration signal based on the pseudo-random noise value to obtain the sub-digital output signal.

5. The calibration method for a time-interleaved analog-to-digital converter according to claim 4, characterized in that, The offset detection module includes a first shunt component and a second shunt component. Both the first shunt component and the second shunt component include a first multiplier, an accumulator and an averager connected in series. The output of the first shunt component is connected to a second subtractor. The output of the second shunt component is connected in series with the second multiplier and the second subtractor. The output of the second subtractor is connected to a third multiplier. The offset detection module extracts the offset error value of the sub-analog-to-digital converter based on the acquired original digital output signal and the pseudo-random noise sequence, including: In the first splitter component, the first multiplier acquires the original digital output signal and the pseudo-random noise value. The first multiplier outputs the original digital output signal corresponding to the pseudo-random noise value of one to the accumulator. The accumulator accumulates all the acquired original digital output signals and sends them to the averager. The averager outputs a first accumulated average value based on all the accumulated original digital output signals. In the second splitter component, the first multiplier acquires the original digital output signal and the inverse signal of the pseudo-random noise value. The first multiplier outputs the original digital output signal corresponding to the pseudo-random noise value that is zero to the accumulator. The accumulator accumulates all the acquired original digital output signals and sends them to the averager. The averager outputs a second accumulated average value based on all the accumulated original digital output signals. Wherein, when the pseudo-random noise value is equal to one, the inverse signal of the pseudo-random noise value is equal to zero, or when the pseudo-random noise value is equal to zero, the inverse signal of the pseudo-random noise value is equal to one. The second multiplier multiplies the second accumulated average value and the preset gain coefficient to obtain a multiplication result, and sends the multiplication result to the second subtractor. The second subtractor performs a difference operation based on the obtained first accumulated average value and the multiplication result to obtain a difference result. The third multiplier multiplies the obtained difference result by a scaling factor to obtain the offset error value, wherein the scaling factor is equal to 1 / (1-α), α is the preset gain coefficient, and the difference result is equal to the difference between the first accumulated average value and the multiplication result.

6. The calibration method for a time-interleaved analog-to-digital converter according to claim 4, characterized in that, The gain demodulation module includes a fourth multiplier and a multiplexer, with the input of the fourth multiplier connected to the first subtractor and the multiplexer, respectively. The gain demodulation module performs inverse demodulation on the acquired preliminary offset calibration signal based on the pseudo-random noise value to obtain the sub-digital output signal, including: The multiplexer acquires the pseudo-random noise value and determines the gain recovery coefficient based on the pseudo-random noise value. When the pseudo-random noise value is equal to zero, the gain recovery coefficient is equal to one, or when the pseudo-random noise value is equal to one, the gain recovery coefficient is equal to 1 / α, where α is the preset gain coefficient. The fourth multiplier acquires the preliminary offset calibration signal and the gain recovery coefficient, multiplies the preliminary offset calibration signal and the gain recovery coefficient, and performs inverse demodulation to obtain the sub-digital output signal.

7. A calibration device for a time-interleaved analog-to-digital converter, characterized in that, It includes at least one control processor and a memory for communicatively connecting to the at least one control processor; the memory stores instructions executable by the at least one control processor to enable the at least one control processor to perform the calibration method of the time-interleaved analog-to-digital converter as described in any one of claims 1 to 6.

8. An electronic device, characterized in that, The calibration device includes the time-interleaved analog-to-digital converter as described in claim 7.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer-executable instructions for causing a computer to perform the calibration method for a time-interleaved analog-to-digital converter as described in any one of claims 1 to 6.

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