Dual-band parallel underwater acoustic image high-speed transmission system and method

Abstract

The application discloses a kind of double frequency band parallel underwater acoustic image high-speed transmission system and transmission method, belong to underwater acoustic communication technical field.This system takes OMPAL138ARM+DSP dual-core heterogeneous processor as core, and divides function partition: ARM kernel completes image pre-processing, communication parameter configuration and system task scheduling, and DSP kernel realizes double-path signal parallel modulation and demodulation, synchronous detection and real-time signal operation.This method selects 20kHz, 28kHz two independent carriers to construct double frequency band parallel transmission link, and completes signal framing and emission by fusing QPSK modulation, root raised cosine filtering, linear frequency modulation synchronization head technology;Image is reconstructed by designing row-by-row accurate pixel mapping strategy at receiving end, and the problem of vertical stripe and pixel misregistration existing in traditional scheme is eliminated from the source.The application breaks through the bottleneck of traditional underwater acoustic communication bandwidth, improves image transmission rate and channel anti-interference ability, and image restoration quality is significantly optimized, and can be widely applied to underwater robot, underwater vehicle and other underwater operation platform image data real-time return scene.

Description

Technical Field

[0001] This invention relates to a dual-band parallel high-speed underwater acoustic image transmission system and method, belonging to the field of underwater acoustic communication technology. It is particularly suitable for real-time grayscale image transmission scenarios of platforms such as underwater robots and autonomous underwater vehicles. Background Technology

[0002] Underwater acoustic communication is the only effective means of underwater information transmission. However, due to the narrow bandwidth of underwater acoustic channels, severe multipath interference, and significant Doppler effect, traditional single-band underwater acoustic communication systems cannot meet the rate requirements of real-time image transmission. Existing technologies for underwater image transmission mainly suffer from the following problems:

[0003] Low transmission rate: Single-band communication is limited by channel bandwidth, making it impossible to transmit large amounts of image data in a short time, resulting in poor real-time performance; Poor image restoration quality: Traditional image bitstream mapping methods are prone to row and column misalignment, producing obvious vertical stripe interference; Weak noise resistance: Without the use of noise reduction techniques such as matched filtering, the bit error rate is high in low signal-to-noise ratio environments, leading to image blurring or distortion. To address these issues, there is an urgent need for an underwater acoustic image transmission system that can improve transmission rate, enhance image restoration quality, and strengthen noise resistance. Summary of the Invention

[0004] This invention provides a dual-band parallel underwater acoustic image high-speed transmission system and method. It employs a dual-core heterogeneous processor architecture, combining dual-band parallel transmission, QPSK modulation, root-raised cosine filtering, and precise line-by-line mapping technology to achieve the following functions: Dual-band parallel transmission: Data is transmitted simultaneously using two independent carrier bands, 20kHz and 28kHz, doubling the transmission rate; High noise immunity demodulation: Matched filtering technology effectively suppresses channel noise and reduces the bit error rate; Stripe-free image restoration: Through rigorous line-by-line pixel mapping, the vertical stripe problem caused by traditional mapping methods is completely solved.

[0005] The specific technical solution is as follows:

[0006] A dual-band parallel underwater acoustic image high-speed transmission system includes a main control module, an acquisition module, and a transmission module;

[0007] The main control module uses a dual-core heterogeneous processor OMAPL138, consisting of an ARM core processor and a DSP core processor; the ARM core processor and the DSP core processor communicate with each other through shared memory and interrupts.

[0008] The ARM core processor runs a Linux system and is responsible for loading the image to be transmitted and converting it into a binary bit stream, configuring dual-band communication parameters, scheduling the DSP core to perform modulation and demodulation tasks, receiving the demodulated bit stream returned by the DSP and mapping it back to a grayscale image, calculating the transmission error rate and displaying the comparison results between the original image and the restored image.

[0009] The DSP core processor runs the SYS / BIOS real-time system, which is responsible for splitting the bit stream sent by the ARM into two paths. These paths are QPSK modulated and root-raised cosine filtered in the 20kHz and 28kHz carrier frequency bands, respectively. The processor generates a linear frequency modulation synchronization header and completes signal framing, driving the transmitting module to transmit underwater acoustic signals. During reception, the processor performs linear frequency modulation synchronization detection, performs dual-band downconversion, matched filtering, and sampling decision on the acquired signal, and splices the two demodulated bit streams together before sending them back to the ARM core processor.

[0010] The acquisition module uses ADS8568, which supports eight-channel synchronous sampling up to 510kbps, with a fixed sampling rate of 96kHz. It amplifies and filters weak underwater acoustic signals through preamplifiers and postamplifiers.

[0011] The transmitting module uses the DA5724, which is configured as a 16-bit digital-to-analog converter. It drives the underwater acoustic transducer through a power amplifier to convert electrical signals into acoustic signals and radiate them into the water.

[0012] Furthermore, the DSP core processor has a built-in dual-band parallel modulation module with a baseband bandwidth of 7kHz, a symbol rate of 4kHz, a raised cosine roll-off factor of 0.2, and 24 upsampling points per symbol for each carrier band.

[0013] Furthermore, the DSP core processor has a built-in linear frequency modulation synchronization header generation module. The synchronization header uses an up-modulated signal of 16kHz to 32kHz with a length of 8192 sampling points. A guard interval of 8192 sampling points is set between the frame header and the data segment.

[0014] Furthermore, the ARM core processor has a built-in image progressive mapping module that maps the demodulated continuous bitstream into grayscale image pixel values ​​row by row and column by column, with each pixel unit consisting of 8 bits, in strict accordance with the order of 115 rows × 127 columns.

[0015] Furthermore, the DSP core processor has a built-in matched filter demodulation module that uses the same root-raised cosine filter as the transmitter to perform matched filtering on the down-converted baseband signal, effectively suppressing channel noise.

[0016] A high-speed underwater acoustic image transmission method with dual-band parallel operation, employing the aforementioned high-speed underwater acoustic image transmission system with dual-band parallel operation, includes the following steps:

[0017] Step 1: The host computer loads the grayscale image to be transmitted, converts it into a binary bit stream, and sends it to the ARM core processor;

[0018] Step 2: Configure the ARM core processor with dual-band communication parameters to divide the bit stream into two equal-length data segments, which are then forwarded to the DSP core processor via shared memory.

[0019] Step 3: The DSP core processor performs QPSK constellation mapping, root raised cosine filtering, and upconversion on the two data streams respectively to generate two carrier signals and superimpose them.

[0020] Step 4: The DSP core processor generates a linear frequency modulation synchronization head, adds a guard interval, and frames it with the superimposed baseband signal to drive the transmitting module to transmit underwater acoustic signals.

[0021] Step 5: The receiving end acquisition module continuously acquires underwater acoustic signals at a sampling rate of 96kHz, and the DSP core processor performs linear frequency modulation synchronization detection to locate the start position of the data frame.

[0022] Step 6: The DSP core processor performs downconversion, matched filtering, and sampling decision on the synchronized signal at 20kHz and 28kHz respectively to obtain two demodulated bit streams, which are then spliced ​​together.

[0023] Step 7: The DSP core processor sends the spliced ​​complete bitstream back to the ARM core processor via shared memory;

[0024] Step 8: The ARM core processor maps the bit stream into a 115×127 grayscale image, with each bit as an 8-bit pixel unit, row by row and column by column. It then calculates the transmission error rate and displays the comparison results between the original image and the restored image.

[0025] This invention doubles the underwater acoustic image transmission rate through dual-band parallel transmission technology, meeting the requirements of real-time image transmission. Matched filtering significantly improves the system's noise immunity and reduces the bit error rate. Through rigorous row-by-row and column-by-column pixel mapping, it completely solves the common vertical stripe misalignment problem in traditional image transmission, greatly improving image restoration quality. This invention can be widely applied in underwater environment monitoring, underwater operation monitoring, and submersible image transmission. Attached Figure Description

[0026] Figure 1 is a block diagram of the overall system architecture of the present invention, showing the dual-core processor, dual-band modulation and demodulation module and external interface connection relationship.

[0027] Figure 2 This is a flowchart of the dual-band parallel image transmission process of the present invention, which describes in detail the complete workflow of the transmitter and receiver.

[0028] Figure 3 This is a schematic diagram of the transmission frame structure of the present invention, illustrating the composition relationship between the synchronization header, guard interval, and dual-band data segment.

[0029] Figure 4 This is a comparison image of the original image and the restored image of the present invention, which visually demonstrates the image restoration effect of the system. Detailed Implementation

[0030] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments:

[0031] A dual-band parallel high-speed underwater acoustic image transmission system and method addresses the key problems of low transmission rate, poor restoration quality, and weak noise resistance in traditional underwater acoustic image transmission. It provides a system integration approach integrating dual-band parallel transmission, matched filtering demodulation, and line-by-line precise pixel mapping. As shown in Figure 1, the system adopts a modular design, mainly including a main control module, an acquisition module, and a transmission module.

[0032] The main control module uses the dual-core heterogeneous processor OMAPL138 as the core board. The OMAPL138 includes an ARM core processor and a DSP core processor. The programs in this embodiment all run on this core board. The ARM core processor runs the Linux system, and the DSP core processor runs the SYS / BIOS real-time system.

[0033] The acquisition module uses ADS8568, which supports eight-channel synchronous sampling up to 510kbps, with a fixed sampling rate of 96kHz; the preamplifier amplifies the weak underwater acoustic signal and reduces noise interference; the postamplifier amplifies the filtered signal a second time to improve the output gain.

[0034] The transmitting module uses the DA5724, configured as a 16-bit digital-to-analog converter; the power amplifier amplifies the power of the electrical signal processed at the front end, enabling it to drive the underwater acoustic transducer, converting the electrical signal into an acoustic signal and radiating it into the water.

[0035] The system's workflow follows Figure 2 conduct.

[0036] Step 1: The host computer loads the grayscale image to be transmitted, converts it into a binary bit stream, and sends it to the ARM core processor;

[0037] Step 2: Configure the ARM core processor with dual-band communication parameters to divide the bit stream into two equal-length data segments, which are then forwarded to the DSP core processor via shared memory.

[0038] Step 3: The DSP core processor completes dual-band parallel modulation and signal framing, driving the transmitting module to transmit underwater acoustic signals;

[0039] Step 4: The receiving end acquisition module continuously acquires underwater acoustic signals, and the DSP core processor performs synchronous detection and dual-band demodulation to obtain a complete image bitstream;

[0040] Step 5: The DSP core processor sends the bit stream and channel parameters back to the ARM core processor, and the ARM completes image restoration, bit error rate calculation and comparison display.

[0041] Completing the above steps requires the cooperation of running threads in both the ARM core processor and the DSP core processor. The specific thread logic is as follows:

[0042] 1. ARM core processor operating status

[0043] In this embodiment, the Linux system of the ARM core processor is mainly responsible for functions such as host computer interaction, image preprocessing, dual-band parameter configuration, image restoration and display, and log storage. Specifically, the working state of the ARM core processor is as follows:

[0044] (1) After power-on, the Linux system provided by the core board is run, and the boot script written in this embodiment is run. The specific execution content of the boot script includes setting the static IP of the system and running the dual-core project script. The content of the dual-core project script includes: mounting the DSP core program, mounting the Syslink driver, and running the executable file of the ARM core processor. The Syslink driver provides inter-core interaction capability for ARM and DSP. In this embodiment, the shared memory provided by Syslink is mainly used for data interaction between ARM and DSP core processors.

[0045] (2) Specifically, after the ARM core processor runs, it performs the following steps:

[0046] 1) Perform Syslink module initialization, initialize the serial port and configure the serial port parameters baud rate to 115200, and add the serial port read event to the epoll process;

[0047] 2) Use Syslink's IPC module to implement core authentication with the DSP core processor. Use Syslink to establish a shared memory area for the dual-core ARM and DSP processors;

[0048] 3) Create ARM core processor threads, including a thread for waiting for data from the DSP core processor, a network port data processing thread, an image restoration and display thread, and a timed task thread. Specifically, the four threads respectively implement the following:

[0049] ① The DSP core processor data waiting thread is mainly used to detect data in the shared memory area and store logs, reconstruct images, and calculate the bit error rate, etc. The shared memory information exchange data packet construction in this embodiment follows... Figure 3 The process proceeds as shown. The data preparation flag is checked once per second. After the thread detects data, it determines the message type, which includes three types: demodulation completion message, channel status message, and error alarm message. Specifically: upon receiving a demodulation completion message, the thread reads the RTC time and writes it to the log, extracting the complete image bitstream; upon receiving a channel status message, it records parameters such as the received signal-to-noise ratio and Doppler factor; upon receiving an error alarm message, it sends an alarm message to the host computer. Once the complete bitstream is extracted, the image restoration module is called to complete the grayscale image mapping.

[0050] ② The network port data processing thread communicates with the host computer based on the UDP protocol. After starting, the thread binds to port 9600 to listen on all network interfaces and continuously receives data packets from the specified IP address. The protocol of the network port data processing thread follows... Figure 4 The process involves performing differentiated processing based on the message header type: image transmission instructions extract the image bitstream and forward it to the DSP shared memory area; parameter configuration instructions update the system's global communication parameters; time synchronization instructions calibrate the system clock; and image comparison instructions trigger the comparison display of the original image and the restored image.

[0051] ③ The image restoration and display thread implements precise mapping and visualization of the image bitstream. The thread waits for the demodulation completion event to trigger and first verifies whether the bitstream length meets the 115×127×8-bit requirement. For valid bitstreams, it performs row-by-row, column-by-column pixel mapping: starting from the beginning of the bitstream, every 8 bits are converted to a grayscale value and sequentially filled into a 115-row × 127-column two-dimensional array. After mapping, the transmission error rate is calculated and written to the log. Finally, the original image and the restored image are displayed side-by-side in the same window, with image size and error rate information labeled.

[0052] ④ A scheduled task thread implements automated image transfer triggered by file timestamps. The thread continuously monitors grayscale image files in a specified directory and executes task scheduling based on the timestamps in the filenames. It organizes the file list in chronological order using bubble sort and automatically cleans up expired files. When a file with a matching timestamp is detected, the image is read and converted into a bitstream, a message packet is constructed and written to shared memory, an operation log is generated, and the processed file is removed. This thread ensures real-time response of the scheduled task through periodic polling.

[0053] 2. DSP Core Processor Operating Status

[0054] In this embodiment, the DSP core processor is mainly responsible for functions such as dual-band parallel modulation and demodulation, linear frequency modulation synchronization detection, matched filtering, and real-time signal processing. Specifically, the DSP core processor operates as follows:

[0055] (1) The DSP core processor is mounted and started after the Linux boot script runs, waiting for inter-core confirmation from the ARM core processor. After the inter-core communication is established, the DSP core processor performs peripheral initialization, thread initialization, etc. The DSP has powerful floating-point arithmetic capabilities and is responsible for executing most of the signal processing algorithms in this invention. After the device is running, the DSP continuously calculates the data monitoring communication signals of the acquisition module, completes tasks such as synchronous detection, dual-band demodulation, parameter calculation and data transmission, and listens for ARM control instructions to execute corresponding modulation and transmission operations.

[0056] (2) Specifically, after the DSP core processor runs, it performs the following steps: peripheral initialization, including GPIO, ADC and DAC drivers. After peripheral initialization is completed, it calls the SYSBIOS built-in thread to create the DSP core processor main thread, and finally starts the BIOS.

[0057] (3) After the DSP core processor system starts running, it establishes inter-core communication with the ARM core in the main thread, creating four core threads: a signal sending thread, a signal receiving thread, a thread waiting for data from the ARM core processor, and a thread sending data to the ARM core processor. Through the cooperation of these four threads, functions such as dual-band modulation transmission, image data processing, information feedback, and system control are realized. Specifically, the contents of the four threads include:

[0058] ① The ARM core processor data thread waits for real-time responses to ARM data based on shared memory. After the thread starts, it initializes the data buffer and continuously polls the flag bits in the shared memory area to detect data update events. When a flag bit is detected, it extracts core configuration information such as data payload length, power level, and dual-band identifier, and triggers the signal transmission thread through a semaphore mechanism to modulate and frame the bit stream to be modulated according to specified parameters. After the operation is completed, the shared memory flag bits are reset, releasing ARM data update permissions.

[0059] ② A thread that sends data to the ARM core processor implements the transmission of image bitstream and channel parameters from the DSP to the ARM. After the thread starts, it continuously waits for the receive signal from the acquisition module to detect whether a communication frame has arrived. When synchronization is successful, demodulation and decoding are performed using the corresponding algorithm. The thread triggers three event types through semaphores: synchronization success event, demodulation completion event (containing the complete image bitstream), and channel status event (containing Doppler factor and signal-to-noise ratio). After the operation is completed, the read flag value is modified to prompt the ARM to perform data extraction.

[0060] ③ The signal transmission thread implements real-time generation and transmission control of dual-band parallel underwater acoustic signals. The thread is triggered by a semaphore and first converts the signal to the corresponding DAC output amplitude value based on the power level. Then, it executes the dual-band modulation process: the image bitstream is divided into two equal paths, each undergoing QPSK constellation mapping and root-raised cosine filtering to suppress inter-symbol interference; the two baseband signals are up-converted to 20kHz and 28kHz carrier frequencies respectively and linearly superimposed. A 16kHz to 32kHz linear frequency modulation synchronization header is generated, and a guard interval and frame end are added to form a complete transmission frame. The floating-point data is converted to a 16-bit integer format to drive the transducer to transmit the signal. After the process is completed, resources are released and the system state is reset.

[0061] ④ The signal receiving thread implements real-time reception and processing of dual-band parallel underwater acoustic signals. The system defaults to receive mode, with the ADC continuously acquiring signals at a 96kHz sampling rate, using ping-pong buffering technology to achieve uninterrupted continuous sampling. After thread startup, the signal processing environment is initialized, generating a local linear frequency modulated signal and allocating a buffer. A semaphore is used to wait for the ADC acquisition completion event; upon triggering, data preprocessing is performed. A matched filtering algorithm is used for synchronization detection to locate the start position of the data frame. After successful synchronization, the dual-band demodulation process is executed: the two carriers are down-converted to obtain the baseband signal; a root-raised cosine filter, identical to that used at the transmitter, is used for matched filtering to suppress channel noise; sampling and decision are performed at 24 sampling points per symbol to obtain two bitstreams, which are then concatenated into a complete image bitstream. Finally, the bitstream and channel parameters are encapsulated into a data packet and submitted to the ARM core processor. After completion, the system state is reset.

[0062] Throughout the process, the dual-core processors have a clear division of labor: the ARM core processor is responsible for image preprocessing, dual-band parameter configuration, task scheduling, and image restoration and display, while the DSP core processor focuses on dual-channel parallel modulation and demodulation, synchronous detection, and real-time signal processing. It features high transmission rate, strong noise resistance, and good image restoration quality, effectively improving the performance of the underwater acoustic image transmission system and is suitable for the real-time image data backhaul requirements of platforms such as underwater robots and autonomous underwater vehicles.

Claims

1. A dual-band parallel underwater acoustic image high-speed transmission system, characterized in that, The system includes a main control module, an acquisition module, and a transmission module. The main control module uses a dual-core heterogeneous processor, the OMAPL138, consisting of an ARM core processor and a DSP core processor. Communication between the ARM and DSP core processors is achieved through shared memory and interrupts. The ARM core processor runs a Linux system and is responsible for loading the image to be transmitted and converting it into a binary bitstream, configuring dual-band communication parameters, scheduling the DSP core to perform modulation and demodulation tasks, receiving the demodulated bitstream returned by the DSP and mapping it back to a grayscale image, calculating the transmission error rate, and displaying a comparison between the original and restored images. The DSP core processor runs a SYS / BIOS real-time system, responsible for splitting the bitstream from the ARM into two paths, performing QPS on the 20kHz and 28kHz carrier bands respectively. K-modulation and root-raised cosine filtering generate a linear frequency modulation (LFM) synchronization header and complete signal framing, driving the transmitting module to transmit underwater acoustic signals. During reception, LFM synchronization detection is performed, and the acquired signal undergoes dual-band downconversion, matched filtering, and sampling decision. The two demodulated bitstreams are then spliced ​​together and sent back to the ARM core processor. The acquisition module uses an ADS8568, which supports eight-channel synchronous sampling up to 510kbps, with a fixed sampling rate of 96kHz. It amplifies and filters weak underwater acoustic signals through preamplifiers and postamplifiers. The transmitting module uses a DA5724, configured as a 16-bit digital-to-analog converter, which drives the underwater acoustic transducer through a power amplifier to convert electrical signals into acoustic signals that are radiated into the water.

2. The dual-band parallel underwater acoustic image high-speed transmission system according to claim 1, characterized in that, The DSP core processor has a built-in dual-band parallel modulation module with a baseband bandwidth of 7kHz, a symbol rate of 4kHz, a raised cosine roll-off factor of 0.2, and 24 upsampling points per symbol.

3. The dual-band parallel underwater acoustic image high-speed transmission system according to claim 1, characterized in that, The DSP core processor has a built-in linear frequency modulation synchronization header generation module. The synchronization header uses an up-modulated signal of 16kHz to 32kHz with a length of 8192 sampling points. A guard interval of 8192 sampling points is set between the frame header and the data segment.

4. The dual-band parallel underwater acoustic image high-speed transmission system according to claim 1, characterized in that, The ARM core processor has a built-in image progressive mapping module that maps the demodulated continuous bitstream into grayscale image pixel values, with each pixel unit consisting of 8 bits, strictly following the order of 115 rows × 127 columns.

5. The dual-band parallel underwater acoustic image high-speed transmission system according to claim 1, characterized in that, The DSP core processor has a built-in matched filter demodulation module, which uses the same root-raised cosine filter as the transmitter to perform matched filtering on the down-converted baseband signal, effectively suppressing channel noise.

6. A high-speed underwater acoustic image transmission method with dual-band parallel transmission, characterized in that, The dual-band parallel underwater acoustic image high-speed transmission system according to any one of claims 1 to 5 includes the following steps: Step 1: The host computer loads the grayscale image to be transmitted, converts it into a binary bitstream, and sends it to the ARM core processor; Step 2: Configure the ARM core processor with dual-band communication parameters to divide the bit stream into two equal-length data segments, which are then forwarded to the DSP core processor via shared memory. Step 3: The DSP core processor performs QPSK constellation mapping, root raised cosine filtering, and upconversion on the two data streams respectively to generate two carrier signals and superimpose them. Step 4: The DSP core processor generates a linear frequency modulation synchronization head, adds a guard interval, and frames it with the superimposed baseband signal to drive the transmitting module to transmit underwater acoustic signals. Step 5: The receiving end acquisition module continuously acquires underwater acoustic signals at a sampling rate of 96kHz, and the DSP core processor performs linear frequency modulation synchronization detection to locate the start position of the data frame. Step 6: The DSP core processor performs downconversion, matched filtering, and sampling decision on the synchronized signal at 20kHz and 28kHz respectively to obtain two demodulated bit streams, which are then spliced ​​together. Step 7: The DSP core processor sends the spliced ​​complete bitstream back to the ARM core processor via shared memory; Step 8: The ARM core processor maps the bit stream into a 115×127 grayscale image, with each bit as an 8-bit pixel unit, row by row and column by column. It then calculates the transmission error rate and displays the comparison results between the original image and the restored image.

Images