Adaptive anti-interference efficient frame synchronization method based on FPGA

Abstract

The application discloses an adaptive anti-interference high-efficiency frame synchronization method based on FPGA and relates to the technical field of wireless communication.The method carries out multi-stage delay on telemetry code streams through a length-configurable delay module, carries out parallel correlation operation through a segmented parallel correlation module to obtain a correlation value, carries out real-time statistics on a bit error rate through a bit error rate statistics module, dynamically calculates the number of allowed errors as a decision threshold according to the bit error rate and the length of a frame header through a dynamic threshold updating module, and adaptively adjusts the frame header detection threshold.Finally, the method carries out parallel logical operation on the multi-path detection results through a synchronous multi-stage confirmation control module to determine a synchronous or out-of-lock state.The application solves the problems of low-signal-to-noise ratio synchronization leakage, burst error invalidation and poor adaptability of a fixed threshold, has the advantages of high throughput, low time delay and low resource consumption, and is suitable for frame synchronization processing of high-speed telemetry code streams.

Description

Technical Field

[0001] This invention belongs to the field of wireless communication technology, and in particular relates to an FPGA-based adaptive anti-interference high-efficiency frame synchronization method. Background Technology

[0002] In the field of range telemetry, the IRIG-106 standard is widely used to standardize the telemetry data frame structure, modulation scheme, and coding type to ensure interoperability of telemetry equipment from different manufacturers. Frame synchronization is a core component of baseband processing in digital communication receivers, responsible for locating the start synchronization word of each frame in the received data stream, providing a frame alignment reference for subsequent demultiplexing, channel decoding, and data parsing. The accuracy of synchronization word detection directly determines the overall performance of the receiver; a single synchronization error can lead to single-frame decoding failure, resulting in continuous data packet loss; if frame synchronization fails in a real-time telemetry system, it can further cause carrier tracking loop instability.

[0003] The telemetry channel at the target range exhibits typical time-varying and non-stationary characteristics. In long-distance transmission scenarios, the signal-to-noise ratio of the received signal is extremely low, making it highly susceptible to multi-bit errors in the synchronization word. Furthermore, when the target is flying at low altitude or in urban environments, multipath propagation occurs in the telemetry link, and channel delay spread can reach several microseconds. Multipath effects cause deep amplitude fading of the received signal, triggering consecutive burst errors in the synchronization word. For example, a 32-bit synchronization word may experience 10 to 15 consecutive bit errors. The length and location of these burst errors are random, placing extremely high demands on the error correction and fault tolerance capabilities of the frame synchronization algorithm.

[0004] Existing frame synchronization detection generally adopts a fixed threshold decision mechanism based on sliding correlation. This mechanism has the following obvious drawbacks in real-world complex channel environments: First, a fixed threshold cannot adaptively adjust with channel conditions, making it difficult to achieve an optimal trade-off between acquisition probability and false alarm probability. When the detection threshold is set too high, under low signal-to-noise ratio conditions, even if the frame is at the true frame header position, its correlation peak will be lower than the decision threshold, thus causing missed synchronization. When the detection threshold is set too low, under high signal-to-noise ratio conditions, when strong noise or random data is locally correlated with the synchronization word, it is very easy to identify a false frame header, resulting in a false alarm.

[0005] Secondly, traditional detection schemes have weak adaptability to continuous burst errors. When multipath fading causes the length of consecutive errors in the synchronization word to reach one-third of the total frame header length, the correlation coefficient calculated by traditional correlation algorithms is often lower than the fixed detection threshold, resulting in the inability to identify the valid frame header position and synchronization failure.

[0006] Finally, traditional synchronization confirmation mechanisms are inefficient and resource-intensive. Existing solutions determine synchronization upon detecting a suspected synchronization word, lacking a multi-level verification mechanism and resulting in poor reliability. If a traditional serial multi-level confirmation mechanism is used, it introduces significant processing latency, easily leading to high-speed data loss and failing to meet the synchronization requirements of high-speed telemetry streams (e.g., 200Mbps and above). Furthermore, existing solutions typically lack synchronization maintenance and fast recapture logic, resulting in lengthy recapture times after synchronization loss.

[0007] In summary, existing frame synchronization techniques have shortcomings in areas such as low signal-to-noise ratio missing synchronization suppression, burst error tolerance, adaptive adjustment of detection threshold, and high-speed bitstream processing efficiency. There is an urgent need for an efficient frame synchronization method that can adapt to complex channel environments, has high throughput, and low resource overhead. Summary of the Invention

[0008] In view of this, the present invention aims to propose an adaptive anti-interference and high-efficiency frame synchronization method based on FPGA to solve the problems existing in the current frame synchronization technology, such as poor adaptability of fixed threshold, low signal-to-noise ratio missed synchronization, failure of burst error detection, false synchronization cascading failure, and low processing efficiency at high bit rates. The main technical problems solved by the present invention are as follows: (1) Solve the problem of missing synchronization word detection under low signal-to-noise ratio conditions: overcome the defect of high probability of missing synchronization when the signal-to-noise ratio is less than 5dB in traditional FPGA fixed threshold correlation detection, and improve the synchronization acquisition capability in long-distance weak signal reception environment.

[0009] (2) Solve the problem of synchronization failure caused by burst errors caused by multipath fading: overcome the defect of traditional correlation algorithms that cannot identify the effective frame header position when the length of consecutive errors in the synchronization word reaches a large proportion of the total length of the frame header, and improve the system's fault tolerance to consecutive burst errors.

[0010] (3) Solve the problem of poor adaptability of fixed threshold leading to difficulty in balancing false alarms and missed synchronization: overcome the defects of fixed internal parameters of FPGA and lack of support for online dynamic configuration, realize the adaptive adjustment of detection strategy according to channel quality in a wide signal-to-noise ratio range, and achieve the optimal balance between maximizing the capture probability and minimizing the false alarm probability.

[0011] (4) Solve the problems of low data throughput and large processing delay in traditional synchronization methods: overcome the defects of large processing delay and easy data loss introduced by traditional serial multi-level confirmation mechanism, and meet the real-time synchronization processing requirements of high-speed (such as 200Mbps and above) telemetry code streams.

[0012] To achieve the above objectives, the technical solution of the present invention is implemented as follows: This invention provides an FPGA-based adaptive anti-interference high-efficiency frame synchronization method, comprising the following steps: Step S1: Obtain frame length configuration information, frame header parameter information, baseline threshold information, and synchronization strategy configuration information through the configuration module; Step S2: The input telemetry PCM bitstream is delayed in multiple stages according to the frame length configuration information by the length-configurable delay module to obtain multiple delayed data streams; Step S3: Perform segmented parallel correlation operations on the multi-channel delayed data stream and telemetry PCM code stream using the segmented parallel correlation module to obtain the correlation value; Step S4: The frame header detection module compares the relevant values ​​with the dynamic threshold and outputs the frame header detection identifier based on the comparison result; Step S5: The multi-level confirmation control module performs logical operations on the multi-frame header detection flags according to the synchronization strategy configuration information to determine the synchronization lock status or unlock status. Step S6: The serial code stream is converted into word synchronization signal and frame synchronization signal output by the synchronization data conversion module according to the synchronization lock state, and the bit error rate is calculated by the bit error rate statistics module. Step S7: The dynamic threshold update module calculates the number of allowed errors based on the bit error rate, baseline threshold information and frame header length, and uses it as the new dynamic threshold, which is then fed back to step S4.

[0013] Furthermore, in step S2, the delay is achieved through a dual-port random access memory and a loop counter; the loop counter counts according to the delay length parameter, and the count value is synchronously used as the read address and write address of the dual-port random access memory, and the bit-level delay is achieved by the read address lagging behind the write address.

[0014] Furthermore, step S3 specifically includes: Input telemetry PCM code stream expression After a delay, the result is obtained. The frame header content is output in segments. ; calculate ,in This represents the XOR operation. Indicates the first Bit error indication; The calculation results are then subjected to bitwise AND operations through a window function, and then accumulated through a pipelined adder to obtain the relevant values.

[0015] Furthermore, the expression for the window function is: ; in, Indicates the index of the bit position currently being processed. This is the set actual frame header length.

[0016] Furthermore, the comparison logic expression in step S4 is as follows: ; in, For relevant values, For dynamic thresholds, This is a frame header detection identifier.

[0017] Furthermore, step S5 specifically includes: When the system is in a unlocked state, select the first M1 frame header detection flags and perform a logical AND operation, where M1 is less than the total number of AN. When the operation result is 1, output the synchronization lock flag. When the system is in a synchronized locked state, select the first M2 frame header detection flags and perform a logical OR operation, where M2 is less than the total number of channels AN. When the operation result is all 0, output the unlock flag.

[0018] Furthermore, the mathematical expression for calculating the dynamic threshold in step S7 is: ; in, For the configured baseline threshold coefficient, For bit error rate, It is the frame header length. This represents the number of errors allowed during frame header detection.

[0019] Furthermore, in step S1, the frame length configuration information, frame header parameter information, reference threshold information, and synchronization strategy configuration information are all stored through an EEPROM storage chip, supporting data retention after power failure and online updates.

[0020] Furthermore, in step S2, the maximum number AN of the length-configurable delay module is set to 5, and in step S3, the number of channels BD for segmented parallel correlation operations is set to 64.

[0021] Compared with existing technologies, the FPGA-based adaptive anti-interference high-efficiency frame synchronization method of the present invention has the following advantages: 1. Adaptive Dynamic Adjustment of Decision Threshold, Balancing Missed Synchronization and False Alarm Suppression: This invention dynamically adjusts the decision threshold in real-time by statistically analyzing the channel bit error rate, updating relevant detection thresholds according to channel quality. Under low signal-to-noise ratio (SNR) conditions, the threshold is automatically widened to suppress missed synchronization, while under high SNR conditions, the threshold is automatically tightened to suppress false alarms. This achieves an optimal trade-off between maximizing acquisition probability and minimizing false alarm probability, significantly improving synchronization reliability in complex channel environments.

[0022] 2. Full-process parameterized configuration with support for online dynamic updates: This invention enables full-process parameterized configuration of key parameters such as frame length, frame header length, frame header content, baseline threshold, and synchronization verification strategy. All parameters can be updated online via external commands without recompiling the FPGA logic code, greatly improving the system's flexibility and engineering applicability.

[0023] 3. Parallel multi-level verification architecture, high processing efficiency and strong reliability: This invention adopts a pipelined architecture to complete multi-level verification of synchronization locking and lock loss determination, and the verification strategy supports user customization. This architecture abandons the traditional serial state machine processing method, significantly reducing processing latency while ensuring the reliability of the decision, and the processing efficiency is significantly better than traditional serial algorithms.

[0024] 4. High throughput, low latency, and low resource overhead, adaptable to high-speed bitstreams: All modules of this invention adopt a pipelined, parallel composite architecture, effectively adapting to the timing constraints of FPGAs. This architecture combines the advantages of high throughput, low latency, and low resource overhead, utilizing dual-port RAM to replace traditional flip-flop chains to achieve long delays, effectively saving logic resources, and enabling real-time synchronous processing of high-speed telemetry bitstreams of 200Mbps and above.

[0025] 5. Strong platform versatility and wide range of application scenarios: This invention is highly versatile and can be seamlessly adapted to Xilinx, Altera, and the entire range of domestic FPGA chips. Its excellent anti-interference capability and efficient synchronization performance can widely support various range telemetry application scenarios such as ground base stations, vehicle-mounted, and missile-borne systems. Attached Figure Description

[0026] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an undue limitation of the invention. In the drawings: Figure 1 This is a schematic diagram of the system block diagram of the FPGA-based adaptive anti-interference high-efficiency frame synchronization method of the present invention; Figure 2 This is a schematic diagram of the principle block of the configurable delay unit of the present invention; Figure 3 This is a schematic diagram of the block diagram of the segmented parallel correlator of the present invention. Detailed Implementation

[0027] It should be noted that, unless otherwise specified, the embodiments and features described in the present invention can be combined with each other.

[0028] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicating orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art will understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0031] I. System Overall Architecture and Signal Link This invention provides an FPGA-based adaptive anti-interference high-efficiency frame synchronization method, particularly suitable for frame synchronization processing of PCM-FM, SOQPSK-TG, and ARTM CPM modulated signals under the IRIG-106 standard framework in low signal-to-noise ratio and high bit error rate channel environments. This method can be widely applied in scenarios such as range flight testing, UAV data links, reentry telemetry, and multi-target telemetry.

[0032] like Figure 1The diagram shown is a system block diagram of the adaptive anti-interference high-efficiency frame synchronization method based on FPGA of the present invention. The overall hardware architecture of this method is implemented inside the FPGA, and mainly includes a frame length configuration module A1, length-configurable delay modules A2 to A1, segmented parallel correlation modules A1 to A2, segmented parallel correlation modules A2 to A3, frame header detection modules A1 to A3, frame header parameter configuration module A3, synchronization multi-level confirmation control module A3, synchronization data conversion module A3, bit error rate statistics module A3, synchronization strategy configuration module A3, dynamic threshold update module A3, and baseline threshold configuration module A3, which are all part of the present invention.

[0033] The input signal for this method is a telemetry PCM baseband code stream. The signal link process is as follows: the telemetry transmitter outputs a microwave signal, which is converted into an electrical signal by the antenna, amplified by a low-noise amplifier, and then subjected to telemetry demodulation, bit synchronization, and baseband code conversion. Finally, the output PCM code stream is sent to the input port of this synchronization module.

[0034] The system's workflow is mainly divided into parameter configuration stage, synchronous search stage, synchronous locking stage, and adaptive adjustment stage.

[0035] During the parameter configuration phase, external control commands are transmitted through the FPGA's external interface. The frame length configuration module A1 parses the commands to obtain frame length information, the frame header parameter configuration module 3AN+1 obtains the frame header length and content information, the baseline threshold configuration module 3AN+7 obtains the baseline threshold coefficient, and the synchronization strategy configuration module 3AN+5 obtains the acknowledgment count strategy. These parameters are all stored in an external EEPROM or on-chip block memory after power loss and distributed to each functional module for runtime configuration.

[0036] During the synchronization search phase, the system is in a unlocked state. The input PCM bitstream undergoes multi-level delays through configurable delay modules A2 to AN, forming a time-staggered data stream. These data streams are fed in parallel into segmented parallel correlation modules AN+1 to 2AN for correlation calculation. The calculation results are sent to frame header detection modules 2AN+1 to 3AN and compared with the real-time threshold output by the dynamic threshold update module 3AN+6. If a suspected frame header is detected, the signal is sent to the synchronization multi-level confirmation control module 3AN+2. This module performs logical operations on the multi-channel detection results according to the parameters set by the synchronization strategy configuration module 3AN+5. If the confirmation count requirement is met, synchronization is considered successful, and the system enters the synchronization locked state.

[0037] During the synchronization locking phase, the synchronization data conversion module 3AN+3 converts the serial code stream into word synchronization signals and frame synchronization signals based on the synchronization position, and simultaneously outputs the deframed telemetry data. At the same time, the bit error rate statistics module 3AN+4 begins to analyze the bit error rate of the known data and calculates the current bit error rate.

[0038] During the adaptive adjustment phase, the bit error rate (BER) statistics module 3AN+4 sends the BER to the dynamic threshold update module 3AN+6. The dynamic threshold update module 3AN+6, in conjunction with the parameters from the baseline threshold configuration module 3AN+7, dynamically calculates a new permissible error count threshold using a mathematical model and feeds it back to the frame header detection modules 2AN+1 to 3AN. This allows the system to automatically adjust its detection sensitivity based on channel quality.

[0039] II. Detailed Module Structure and FPGA Implementation Principles 1. Frame length configuration module A1 The frame length configuration module A1 is the core unit that obtains frame length configuration information through external command interaction and parsing. The frame length unit is bits. The module stores parameters through parameter storage chips such as EEPROM and supports data retention even when power is off. This module outputs frame length information to the length-configurable delay module A2 and then to the length-configurable delay module AN.

[0040] Internally within the FPGA, this module contains an instruction decoding state machine. When an external write enable signal is detected, the state machine transitions from the idle state to the receive state, reading the address and data on the bus. If the address matches the frame length register address, the data is latched. The frame length information output by this module serves as the counter modulus value for subsequent delay modules or as a random access memory depth configuration parameter.

[0041] 2. Length-configurable delay modules A2 to AN The length-configurable delay modules A2 to AN have identical internal structures, enabling the delay of the input data stream by a specific data length. The configuration length information comes from the output of the frame length configuration module A1.

[0042] like Figure 2 The diagram shows the principle block diagram of a configurable delay unit. Internally, this unit consists of a dual-port random access memory (DRAM) and a loop counter. The DRAM contains three write signals: write clock, write data, and write address; and three read signals: read clock, read data, and read address. The loop counter is an incremental counter whose maximum count value is the delay length. The count value is synchronously used as the read and write addresses of the DRAM, ensuring consistency between read and write addresses.

[0043] In practice, the raw bitstream is input to the write data port of the dual-port random access memory (DRAM), and the system clock synchronously drives the DRAM and the loop counter. The loop counter counts based on the input delay length parameter. To achieve precise bit-level delay, a fixed difference is maintained between the read address and the write address. In FPGA block RRAMs, reading and writing to the same address are typically supported. In this design, the output of the loop counter is connected to both the write address port and the read address port.

[0044] If a delay of K clock cycles is required, the read address logic needs to be designed so that the read address equals the write address minus K, modulo the depth. However... Figure 2 In the structure shown, during actual operation, the loop counter generates a write address, and the count value minus the set delay length is used as the read address. The difference between the read and write addresses achieves precise bit-level delay.

[0045] In this way, data is read out only after a set clock cycle after entering the random access memory, thus achieving precise bit-level delay. Compared with traditional flip-flop chains, this delay structure based on dual-port random access memory can greatly save FPGA flip-flop resources in the case of long delays, and achieve efficient delay by utilizing block random access memory resources.

[0046] 3. Segmented parallel related modules AN+1 to 2AN The segmented parallel correlation modules AN+1 to 2AN have the same internal structure and principle. The method comprises a total of AN segmented parallel correlation modules. The inputs are the outputs of AN-1 configurable delay units and the method input telemetry PCM data stream. Frame header parameters are derived from frame header parameter configuration module 3AN+1. This module fully utilizes the parallel structure characteristics of the FPGA to achieve segmented parallel correlation operations, enabling fast and efficient frame header correlation calculation.

[0047] Traditional sliding correlation methods typically use shift registers to slide bit by bit. At high speeds, the combinational logic paths become too long, making timing convergence difficult. This invention employs a segmented parallel architecture. AN modules process data in different time windows. For example, module AN+1 processes the original bitstream, module AN+2 processes the bitstream delayed by one frame, and so on. This is equivalent to searching for AN possible frame header start positions in parallel on the time axis, or it can be used to combat multipath effects, where signals from different paths arrive at different times and are aligned using different delay modules.

[0048] Each segmented parallel module internally employs, for example... Figure 3 The segmented parallel structure shown further breaks down the matching operation of the long frame header, ensuring stable operation at extremely high clock frequencies.

[0049] 4. Frame header detection module 2AN+1 to 3AN The internal structure and principle of frame header detection modules 2AN+1 to 3AN are the same. They detect and output frame header information based on the correlation values ​​output by the corresponding segmented parallel correlation modules and the real-time detection thresholds output by the dynamic threshold update module 3AN+6.

[0050] The mathematical expression for the detection logic is: (1); in, The output of the segmented parallel correlation module is the calculated number of bit errors or Hamming distance; The result output by the dynamic threshold update module 3AN+6 is the threshold for the maximum number of errors allowed. This indicates the output result of the frame header detection module.

[0051] The physical meaning of this formula lies in the difference between the received data and the local frame header template, i.e., the number of bit errors. The difference is less than the upper limit allowed by the system, i.e., the threshold. If a match is found, a high-level 1 is output; otherwise, a low-level 0 is output. This fault-tolerant decision mechanism based on Hamming distance is more efficient than traditional hard-decision, i.e., a perfect match. It is better able to adapt to sudden error environments. In FPGA, this module is implemented as a simple numerical comparator. and All values ​​are unsigned integers, and the comparison result is output directly.

[0052] 5. Frame header parameter configuration module 3AN+1 The frame header parameter configuration module 3AN+1 works similarly to the frame length configuration module A1, also interacting with and parsing frame header parameter information, including the frame header length, through external commands. And the frame header content sequence. This information is synchronously transmitted to length-configurable delay modules A2 to AN to control the delay length to match the frame header position, and to segmented parallel related modules to provide a local frame header template. .

[0053] Inside the FPGA, frame header content is typically stored in distributed random access memory or a register file for rapid parallel reading on the rising edge of the clock, making it available to relevant modules. Parameter storage and power-down retention are achieved through hardware interaction with parameter memories such as EEPROM.

[0054] 6. Synchronous multi-level confirmation control module 3AN+2 The multi-level confirmation control module 3AN+2 determines the number of confirmations required for synchronization and lock loss based on the parameters output by the synchronization strategy configuration module 3AN+5. This module abandons the traditional state machine and serial processing architecture, improving the module's real-time processing efficiency.

[0055] Traditional methods typically employ a serial state machine, detecting a suspected frame header and then waiting for the next frame to detect it again, which is time-consuming, requiring at least one frame cycle. This invention employs parallel multi-level confirmation.

[0056] When the system is in an unlocked state, if the frame header detection module 3AN outputs a detection flag of 1, then according to the synchronization strategy, the first M1 frame header detection outputs are selected for a logical AND operation, where M1 is less than AN. This means that among the AN parallel channels or AN different delay positions, at least M1 channels must simultaneously detect the frame header, and the logical AND result must be 1 for synchronization to be considered reliable. When the operation result is 1, a synchronization lock flag is output.

[0057] When the system is in a synchronized locked state, if the frame header detection module 3AN outputs an indicator of 0, meaning no frame header has been detected, then the first M2 detection outputs are selected for a logical OR operation, where M2 is less than AN. This means that only when no frame header is detected for M2 consecutive channels or M2 detection points, and the logical OR result is 0, is it considered a true loss of lock. When the operation result is all 0s, a loss of lock indicator is output. This mechanism effectively prevents false loss of lock caused by a single sudden interference, improving the robustness of the system.

[0058] 7. Synchronization Strategy Configuration Module 3AN+5 The synchronization strategy configuration module 3AN+5 works similarly to the frame length configuration module A1. It also interacts with and parses relevant parameters of the synchronization strategy configuration through external commands. These parameters include the number of synchronization acknowledgments (M1) and the number of lockout acknowledgments (M2). This parameter information is synchronized to the multi-level acknowledgment control module 3AN+2, and the parameters are stored and retained even after power loss through hardware interaction with parameter memory such as EEPROM.

[0059] 8. Synchronous Data Conversion Module 3AN+3 The synchronization data conversion module 3AN+3 converts the serial code stream output by the length-configurable delay module AN into words based on the synchronization or unlock status and synchronization position output by the synchronization multi-level confirmation control module 3AN+2, and outputs word synchronization signals and frame synchronization signals.

[0060] This module is essentially a serial-to-parallel converter and frame aligner. Once synchronization is confirmed, the internal counter divides the bit stream into frames according to the length set by the frame length configuration module A1. For every set number of bits received, a frame synchronization pulse is output, and a parallel data word is output when the pulse is valid.

[0061] 9. Bit Error Rate Statistics Module 3AN+4 The bit error rate (BER) statistics module 3AN+4 estimates the current BER by performing statistical analysis on specific data based on the output data from the synchronization data conversion module 3AN+3. Special data mainly includes known data information such as frame headers and frame counts.

[0062] Because the frame header content is known, configured by module 3AN+1, and the frame count typically follows an increasing pattern, it is also known. The module counts the number of error bits by comparing the received known data with the theoretical value.

[0063] In its implementation, the module contains an error counter and a total bit counter. After a period of time, for example, counting 100 frames, the bit error rate of the current data frame is calculated. This bit error rate information is typically quantized into a fixed-point number and sent to the dynamic threshold update module 3AN+6.

[0064] 10. Dynamic threshold update module 3AN+6 The dynamic threshold update module 3AN+6 dynamically adjusts the threshold information related to frame header decisions based on the baseline threshold output by the baseline threshold configuration module 3AN+7 and the current bit error rate information output by the bit error rate statistics module 3AN+4. The mathematical expression for this threshold is: (2); in, This represents the configured baseline threshold coefficient, used to adjust sensitivity, and is typically a constant. The bit error rate is the output of the bit error rate statistics module 3AN+4. It is the frame header length; This is the number of errors allowed during frame header detection, i.e., the value output by the dynamic threshold update module 3AN+6.

[0065] This formula embodies the core adaptive concept of this invention. When the channel environment is poor and the bit error rate is low... When it rises, The value increases. This means the system allows for more bit errors in the frame header, thus lowering the detection threshold, as shown in Equation 1. Increase the size to prevent synchronization loss due to excessive bit errors at low signal-to-noise ratios. Easier to satisfy.

[0066] When the channel environment is good, the bit error rate is... When it decreases, The value decreases. This means that the system requires a high degree of matching between frame headers, raising the detection threshold and preventing false alarms caused by random correlation of noise at high signal-to-noise ratios.

[0067] As the frame header length, the impact of the normalized bit error rate is mitigated, making the threshold... It is directly proportional to the frame header length, which conforms to statistical laws.

[0068] In an FPGA, this formula is implemented using a multiplier. The result is usually a decimal and needs to be converted to a fixed-point number for calculation. Output the integer part.

[0069] 11. Baseline Threshold Configuration Module 3AN+7 The baseline threshold configuration module 3AN+7 works similarly to the frame length configuration module A1, interacting with and parsing baseline threshold information via external commands. This information is transmitted to the dynamic threshold update module 3AN+6, which dynamically adjusts a baseline value, i.e., the value in formula 2. The parameter storage and power-off retention functions are achieved through hardware interaction with parameter memory such as EEPROM.

[0070] III. Detailed Explanation of the Internal Principles of Segmented Parallel Correlators The entire process of this method is now complete. The following section will elaborate on the internal structure and principles of the segmented parallelism modules AN+1 to 2AN.

[0071] like Figure 3 The diagram shown is a block diagram of a segmented parallel correlator. The specific implementation of the segmented parallel correlator consists of a delay correlation module B1, delay correlation modules B2 through B2 BD, a frame header content segmentation module BD+1, a frame header length window selection module BD+2, and BD-1 adders. Here, BD represents the configurable longest frame header length.

[0072] The original design of this structure was to address the timing convergence difficulties in long frame header related operations within FPGAs. Directly performing parallel comparisons on 64-bit or longer data results in excessively long combinational logic paths, leading to a decrease in the maximum operating frequency. This invention divides the long frame header into BD segments, each 1 bit, and processes them through a pipelined structure.

[0073] The delay-related modules B1 to BD have the same internal structure, and their specific mathematical expressions are as follows: (3); The expression for the telemetry PCM bitstream input to the delay correlation module is as follows: .exist Figure 3 In the pipeline structure, data flows from left to right. The first module receives the current input. Output after register delay To the next level. Or, to understand it as, the... Each module processes the delay relative to the input. Data from one period.

[0074] Another input to the delay-related module is This means that the frame header content is output in segments. The frame header content segmentation module BD+1 sends the complete frame header sequence to each delay-related module in parallel.

[0075] This represents the XOR operation.

[0076] The delay-related module calculation results are as follows If the received bit With frame header If they are the same, the XOR result is 0; if they are different, it is 1. Therefore Indicates the first Bit error indication. This value is input to the frame header length window selection module BD+2.

[0077] The frame header content segmentation module BD+1 divides the frame header content into BD bits of data, which are then input into each delay correlator module for correlation calculations. This is equivalent to establishing a parallel frame header template register group inside the FPGA.

[0078] The frame header length window selection module generates a window function of the corresponding length based on the frame header length setting value, which comes from the output of the frame header parameter configuration module 3AN+1. This window function is then used in a bitwise AND operation with the calculation result of the delay correlator. This is to support variable-length frame headers. If the actual frame header length... Less than the maximum configuration length If it exceeds The portion should be ignored and considered as 0 errors. That is, the pipeline structure of the segmented parallel correlation module does not need dynamic adjustment; only the window function size needs to be adjusted to L. When the delay correlator result of the portion greater than L and less than or equal to the length BD portion is ANDed with "0", the result is 0. By adjusting the window function size in this way, the bit error rate result for different frame lengths L, i.e., the y1 value, can be calculated. The expression for this window function is: (4); in, Indicates the current module's index, from 1 to BD. This is the set actual frame header length.

[0079] when At that time, the window function value is 1, and the bitwise AND operation retains the value of 1. That is, the error value of that bit is retained.

[0080] when When the window function value is 0, the result of the bitwise AND operation is 0, meaning that the bit is forced to have no error and is not included in the total bit error count. In the specific hardware implementation of the FPGA, the bitwise AND operation is implemented by setting AND gates before each input of the pipeline adder, and by configuring the window function... The value controls the on / off state of the gate, thereby achieving dynamic adjustment without changing the physical structure of the pipeline adder.

[0081] The output results of the frame header length window selection module BD+2 are respectively subjected to pipelined addition operations. Figure 3 A series of adders are displayed at the bottom. and Add them together, then multiply the result by the sum. The process continues, adding the results and so on. To optimize timing, practical FPGA implementations typically employ a cascaded pipeline of tree-structured adders or carry-and-save adders. The advantage of pipelined addition is that it ensures good timing characteristics for the FPGA and provides high computational efficiency. The final accumulated result is the frame header correlation value, i.e., the total number of bit errors, which is then sent to the subsequent frame header detection module.

[0082] IV. Examples Example 1 Based on the current engineering requirement of a maximum frame length of 32768 bits, a dual-port random access memory with a 1-bit width and a depth of 32768 bits is selected for the configurable delay module. This approach meets the maximum 32768-bit frame length configuration requirement while minimizing FPGA logic resources. This achieves the goal of meeting generalization requirements while minimizing FPGA resource overhead.

[0083] The maximum number of confirmations for synchronization and lock loss is configured with a value of 5 (AN), which balances hardware resource overhead with the reliability requirements of engineering testing. Figure 1 The value of AN in the equation is 5.

[0084] At this time, the system includes frame length configuration module A1.

[0085] There are four configurable delay modules: A2, A3, A4, and A5, numbered A2 to AN respectively.

[0086] The segmented parallel related modules are A6, A7, A8, A9, and A10, with corresponding numbers AN+1 to 2AN, totaling 5 modules.

[0087] The frame header detection modules are A11, A12, A13, A14, and A15, with corresponding numbers 2AN+1 to 3AN, totaling 5 modules.

[0088] Frame header parameter configuration module A16, i.e., 3AN+1.

[0089] Synchronous multi-level confirmation control module A17, i.e., 3AN+2.

[0090] Synchronous data conversion module A18, i.e. 3AN+3.

[0091] The bit error rate statistics module is A19, which is 3AN+4.

[0092] Synchronization strategy configuration module A20, i.e. 3AN+5.

[0093] The dynamic threshold update module A21 is 3AN+6.

[0094] The baseline threshold configuration module is A22, which is 3AN+7.

[0095] The segmented parallel correlation module has 64 internal delay correlation channels (BD=64), corresponding to a maximum supported 64-bit frame header configuration. This means... Figure 3 The production line depth is 64 levels.

[0096] External parameter storage uses I 2 The AT24C128 chip with a C interface is small in size and has a simple interface, which can meet the storage requirements of all configuration parameters.

[0097] Example 2: Dynamic Threshold Adjustment Process In this embodiment, the dynamic threshold update module A21, i.e., 3AN+6, operates as follows: Assuming frame header length 32 bits. Baseline threshold coefficient. Set to 1.

[0098] The formula is .

[0099] Scenario 1: Long-distance weak signal reception, with a signal-to-noise ratio of less than 5dB.

[0100] At this time, the bit error rate The statistical module measured a relatively high level. That is, 10%.

[0101] Dynamic threshold Rounded down to 3.

[0102] This means that 3 bits of error are allowed.

[0103] A traditional fixed threshold might be set to 1. In this case, the probability of more than one error in the 32-bit frame header is extremely high, leading to missed synchronization using traditional methods. This invention allows for three errors, significantly reducing the probability of missed synchronization.

[0104] Scenario 2: Strong signal at close range, high signal-to-noise ratio.

[0105] At this time, the bit error rate Extremely low, as measured by the statistical module. .

[0106] Dynamic threshold Rounded down to 0.

[0107] This means that zero errors are allowed.

[0108] If a traditional fixed threshold is set to 1, under strong signal conditions, random noise has a very small probability of locally correlating with the frame header, generating one bit error and causing a false alarm. This invention lowers the threshold to 0, requiring a perfect match, thus eliminating false alarms.

[0109] Example 3: Synchronous Multi-Level Confirmation Process This embodiment demonstrates the specific logic of the synchronous multi-level confirmation control module A17, namely 3AN+2.

[0110] If AN=5, then there are 5 frame header detection outputs from 5 parallel channels.

[0111] Synchronization strategy configuration module A20, i.e. 3AN+5 setting: synchronization confirmation requires M1=3 times, and lock loss confirmation requires M2=2 times.

[0112] The system is initially in an unlocked state.

[0113] At time T1: the output of the 5-channel detection is 1, 0, 1, 0, 1.

[0114] Select the following three paths for M1: 1, 0, 1.

[0115] Logical AND operation: 1 AND 0 AND 1 equals 0.

[0116] If the result is not 1, synchronization is not confirmed. The system continues searching.

[0117] At time T2: the output of the 5-channel detection is 1,1,1,0,0.

[0118] Select the following path M1=3: 1,1,1.

[0119] Logical AND operation: 1 AND 1 AND 1 equals 1.

[0120] The result is 1, and the synchronization lock flag is output. The system enters the locked state.

[0121] Once the system is locked, tracking begins.

[0122] At time T3: A sudden interference occurs in the channel, and the outputs of the 5-channel detection are 0,0,1,1,1. Note that in the locked state, the output is 0, meaning no interference was detected.

[0123] Before selecting M2=2 channels: 0,0.

[0124] Logical OR operation: 0 or 0 equals 0.

[0125] The result is all 0s, and a lock loss flag is output. The system determines that the lock has been lost and re-enters the search state.

[0126] The logic here is to output a lost-lock flag when the operation result is all 0s. If M2=2, the first two paths are selected as 0, 0, or the operation result is 0, satisfying the all-zero condition, and a lost-lock is determined. This means that a lost-lock is determined when no detection is detected for two consecutive times, resulting in a fast response speed.

[0127] If the output at time T3 is 0, 1, 0, 0, 0.

[0128] Select the first M2=2 channels: 0,1.

[0129] Logical OR operation: 0 or 1 equals 1.

[0130] If the result is not all zeros, the system is not considered to have lost the lock. The system remains locked. This demonstrates its anti-interference capability; a single missed detection will not lead to a loss of lock.

[0131] V. Summary of the beneficial effects of the invention First, the adaptive dynamic threshold mechanism based on bit error rate feedback effectively solves the contradiction between low signal-to-noise ratio missed synchronization and high signal-to-noise ratio false alarm.

[0132] Traditional fixed-threshold methods often fall short in complex channels. This invention uses a bit error rate (BER) statistics module to sense channel quality in real time and a dynamic threshold update module to execute the formula. As shown in Example 2, in a scenario of long-distance weak signal reception (signal-to-noise ratio below 5dB), the system detects a high bit error rate and automatically increases the number of allowable errors. This effectively relaxes the detection threshold, enabling the successful capture of frame headers that would otherwise suffer from continuous burst errors due to multipath fading, significantly reducing the probability of missed synchronization. In close-range, strong signal scenarios, the system detects extremely low bit error rates and automatically tightens the threshold to 0, requiring perfect matching and effectively eliminating false alarms caused by local correlations in random noise. This mechanism of adaptively adjusting the detection strategy according to channel conditions truly achieves the optimal trade-off between maximizing the capture probability and minimizing the false alarm probability.

[0133] Second, the segmented parallel correlation and dual-port RAM delay architecture breaks through the high-speed timing bottleneck and significantly reduces hardware resource overhead.

[0134] To address the timing convergence difficulties in FPGAs caused by high-speed telemetry bitstreams (e.g., 200 Mbps and above), this invention abandons the traditional long shift register sliding correlation structure. On one hand, a configurable delay module is constructed using a dual-port random access memory and a loop counter, minimizing trigger resource consumption while meeting the maximum 32768-bit long frame delay requirement. On the other hand, in the segmented parallel correlation module, the formula... Perform bitwise XOR operations and combine them with window functions. Invalid bits are masked, and the data is finally accumulated using a pipelined adder. This design, which breaks down long frame header matching operations into short bit parallel processing and is supplemented by pipelined cascading, greatly shortens the combinational logic path, ensures the timing stability of the FPGA at extremely high clock frequencies, and achieves a balance between high throughput and low latency.

[0135] Third, the parallel multi-level confirmation mechanism significantly improves the system's ability to resist sudden interference and maintain synchronous stability.

[0136] Traditional serial state machine confirmation mechanisms suffer from slow response and susceptibility to single-instance interference leading to lock loss. This invention introduces a parallel logic operation strategy into the synchronous multi-level confirmation control module. As shown in Example 3, during the synchronization search phase, a logical AND operation is performed on the first M1 detection results, ensuring high reliability of synchronization locking and eliminating false synchronization. During the synchronization lock tracking phase, a logical OR operation is performed on the first M2 detection results, ensuring that the system only determines lock loss when frame headers are not detected consecutively multiple times. This design endows the system with strong fault tolerance; missed detections caused by single or occasional channel burst interference will not lead to false lock loss, effectively avoiding carrier tracking loop instability and continuous data packet loss, thus ensuring the continuity of the telemetry data link.

[0137] Fourth, the full-process parameterization and highly versatile design greatly improve the efficiency of engineering deployment and adaptability to multiple scenarios.

[0138] This invention abstracts all core parameters, such as frame length, frame header content, reference threshold, and synchronization strategy, into configurable items and achieves power-loss retention through storage chips such as EEPROM. This means that when facing different models of telemetry equipment or different mission requirements, engineers do not need to modify the underlying hardware code or recompile the FPGA logic; they can simply update the configuration parameters online through external command interaction. Furthermore, this architecture does not rely on specific vendors' IP cores and can seamlessly adapt to Xilinx, Altera, and the entire range of domestic FPGA chips. It is widely applicable to various range telemetry application scenarios, including ground base stations, vehicle-mounted, missile-borne, and UAV data links, demonstrating extremely high engineering promotion value and platform versatility.

[0139] In summary, this invention represents a comprehensive innovation from theoretical algorithms to underlying hardware architecture, achieving substantial breakthroughs in anti-interference capabilities, processing speed, resource utilization, and engineering flexibility, providing an efficient and reliable solution for telemetry frame synchronization in complex electromagnetic environments.

[0140] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. An FPGA-based adaptive anti-interference high-efficiency frame synchronization method, characterized in that, Includes the following steps: Step S1: Obtain frame length configuration information, frame header parameter information, baseline threshold information, and synchronization strategy configuration information through the configuration module; the frame header parameter information includes frame header length and frame header content sequence, the baseline threshold information is the baseline threshold coefficient, and the synchronization strategy configuration information includes the value of synchronization confirmation count M1 and the value of lock loss confirmation count M2. Step S2: The input telemetry PCM code stream is delayed in multiple stages according to the frame length configuration information by the length-configurable delay module to obtain multiple delayed data streams; the maximum number of the length-configurable delay module is AN, and there are a total of AN minus 1 length-configurable delay modules; Step S3: Perform segmented parallel correlation operations on the multiple delayed data streams and telemetry PCM bitstreams using segmented parallel correlation modules to obtain correlation values. The number of segmented parallel correlation modules is AN, and their inputs are the outputs of AN minus 1 configurable delay modules and the input telemetry PCM bitstreams. Each AN segmented parallel correlation module processes data from different time windows, searching in parallel for AN possible frame header start positions on the time axis. Each segmented parallel correlation module internally consists of delay correlation modules B1 to BD, a frame header content segmentation module, a frame header length window selection module, and BD minus 1 adders, where BD is the configurable longest frame header length. After delaying the input telemetry PCM bitstream, a delayed sequence is obtained. The frame header content segmentation module divides the complete frame header content sequence into BD bits of data, which are then fed in parallel. Each delay-related module performs an XOR operation on the segmented data of the delay sequence and the frame header content. The XOR result indicates the bit error rate of that bit. The XOR results of each delay-related module are then subjected to a bitwise AND operation through a window function generated by the frame header length window selection module based on the frame header length setting value. This bitwise AND operation is then accumulated by a pipeline adder to obtain a correlation value. The correlation value is the number of bit errors between the received data and the local frame header template, i.e., the Hamming distance. The bitwise AND operation is implemented by setting AND gates before each input of the pipeline adder. The on / off state of the AND gates is controlled by configuring the window function value. When the window function value is 1, the bit error rate of that bit is retained after the bitwise AND operation. When the window function value is 0, the result of the bitwise AND operation is 0, and that bit is forcibly considered to have no error and is not included in the total bit error count. This allows for dynamic adjustment of the frame header length without changing the physical structure of the pipeline adder. Step S4: The relevant value is compared with the dynamic threshold by the frame header detection module, and a frame header detection flag is output according to the comparison result. The number of frame header detection modules is AN, which correspond one-to-one with AN segmented parallel relevant modules. The comparison logic is that when the relevant value is less than the dynamic threshold, it is determined that the match is successful and the frame header detection flag outputs a high level 1; otherwise, it is determined that the match is not successful and the frame header detection flag outputs a low level 0. The relevant value and the dynamic threshold are both unsigned integers. Step S5: The multi-level synchronization confirmation control module performs logical operations on the multi-frame header detection flags according to the synchronization strategy configuration information to determine the synchronization lock state or the unlock state. The multi-level synchronization confirmation control module abandons the traditional state machine and serial processing architecture. Specifically, when the system is in the unlock state, the first M1 frame header detection flags are selected for a logical AND operation, where M1 is less than the total number of flags AN. When the operation result is 1, the synchronization lock flag is output. When the system is in the synchronization lock state, the first M2 frame header detection flags are selected for a logical OR operation, where M2 is less than the total number of flags AN. When the operation result is all 0, the unlock flag is output. Step S6: The synchronous data conversion module converts the serial code stream into word synchronization signals and frame synchronization signals according to the synchronization lock state, and the bit error rate statistics module calculates the bit error rate of the known data. The synchronous data conversion module converts the serial code stream output by the length configurable delay module AN into words according to the synchronization lock state and synchronization position output by the synchronization multi-level confirmation control module. The bit error rate statistics module uses the data output by the synchronous data conversion module as the statistical object. The known data to be counted includes the frame header and frame count. The number of error bits is counted by comparing the difference between the received known data and the theoretical value. The error counter and total bit counter contained in the module are used to calculate the current data frame bit error rate after a set number of frames. The bit error rate is quantized into a fixed number and sent to the dynamic threshold update module. Step S7: The dynamic threshold update module calculates the number of allowable errors based on the bit error rate, baseline threshold information, and frame header length, using this as the new dynamic threshold, and feeds it back to step S4. The calculation involves multiplying the configured baseline threshold coefficient by the bit error rate output by the bit error rate statistics module and the frame header length, rounding the product, and outputting the result as the number of allowable errors during frame header detection, i.e., the new dynamic threshold. The frame header length, as a product factor, normalizes the impact of the bit error rate, making the new dynamic threshold proportional to the frame header length. When the channel environment is poor and the bit error rate increases, the allowable number of errors increases. As the number of errors increases, the system allows for more bit errors in the frame header, thereby lowering the detection threshold and preventing missed synchronization due to excessive bit errors at low signal-to-noise ratios. When the channel environment is good and the bit error rate decreases, the number of errors allowed decreases, and the system requires a high degree of matching in the frame header, thereby raising the detection threshold and preventing false alarms caused by random correlation of noise at high signal-to-noise ratios. The new dynamic threshold is fed back to AN frame header detection modules, enabling the system to automatically adjust the detection sensitivity according to the channel quality, forming a closed loop from synchronization locking, bit error rate statistics, threshold update to frame header detection.

2. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 1, characterized in that, In step S2, a delay is achieved using a dual-port random access memory and a loop counter. The loop counter counts according to the delay length parameter, and the count value is synchronously used as the read address and write address of the dual-port random access memory. Bit-level delay is achieved by the read address lagging behind the write address.

3. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 1, characterized in that, Step S3 specifically includes: Input telemetry PCM code stream expression After a delay, the result is obtained. The frame header content is output in segments. ; calculate ,in This represents the XOR operation. Indicates the first Bit error indication; The calculation results are then subjected to bitwise AND operations through a window function, and finally accumulated through a pipelined adder to obtain the relevant values.

4. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 3, characterized in that, The expression for the window function is: ； in, Indicates the index of the bit position currently being processed. This is the set actual frame header length.

5. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 1, characterized in that, The comparison logic expression in step S4 is: ； in, For relevant values, For dynamic thresholds, This is a frame header detection identifier.

6. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 1, characterized in that, The mathematical expression for calculating the dynamic threshold in step S7 is: ； in, For the configured baseline threshold coefficient, For bit error rate, It is the frame header length. This represents the number of errors allowed during frame header detection.

7. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 1, characterized in that, In step S1, the frame length configuration information, frame header parameter information, reference threshold information, and synchronization strategy configuration information are all stored through an EEPROM storage chip, which supports data saving and online updates after power failure.

8. The FPGA-based adaptive anti-interference high-efficiency frame synchronization method according to claim 1, characterized in that, In step S2, the maximum number AN of the length-configurable delay module is 5, and in step S3, the number of channels BD for the segmented parallel correlation operation is 64.

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