A method and system for lighting based on a CPU direct XGE network port of a module platform

Abstract

The application discloses a method and system for CPU direct XGE network port lightening based on a Kingfisher module platform, and belongs to the technical field of computer hardware. The method adopts the following steps: after the server mainboard is powered on, the CPU module detects the working state of each XGE network port in real time, and continuously transmits a standard SGPIO signal to the CPLD of the mainboard; the CPLD decodes the SGPIO signal, outputs corresponding Link and Active control signals according to the link state and rate type of each network port; and the network port indicator light presents lightening, extinguishing or flickering according to the control signal, so as to indicate the connection state and data transmission activity. The application multiplexes the inherent SGPIO signal of the CPU module and the CPLD of the mainboard for hardware decoding, does not need to increase a PHY chip or an independent network card controller, and does not depend on an operating system. The network port state can be indicated in real time and accurately from the power-on, the hysteresis of software polling is avoided, the cost is low, and the reliability is high.

Description

Technical Field

[0001] This invention belongs to the field of computer hardware technology and relates to a method and system for lighting LEDs via the XGE network port directly output from the CPU of the Kunpeng module platform. Background Technology

[0002] With the rapid development of cloud computing, big data, and artificial intelligence technologies, servers and communication equipment are placing higher demands on the performance and density of network interfaces. The Kunpeng 920 processor, as a high-performance ARM architecture server chip, typically provides multiple physical Ethernet interfaces directly in its integrated CPU module, such as supporting eight XGE (10 Gigabit Ethernet) interfaces. These XGE interfaces can be configured to connect to an external PHY chip to output electrical signals; alternatively, they can be used directly as 10G, 25G, 40G, 50G, or 100G optical ports without the need for an additional PHY chip.

[0003] In existing network interface indicator light control schemes, for Ethernet ports with PHY chips, the connection status, speed, and activity indicators of the network port are typically handled by the PHY chip: the PHY chip detects the link status and negotiates the speed, then directly outputs the corresponding LED control signals to drive the network port indicator lights on the panel. This solution is mature and reliable, and is widely used in various network card and motherboard designs.

[0004] However, when the XGE interface is configured as a high-speed optical port (10G and above) and directly output from the CPU, the Kunpeng 920 CPU module itself does not provide dedicated indicator light control pins or signals for each XGE network port. This means the directly output optical port cannot directly obtain indication signals reflecting link status, speed, and activity like a traditional network card. Specifically, although the MAC controller integrated within the CPU module can obtain the link status and operating speed of the network port through internal registers, it does not output this status information to external pins in the form of physical level signals. Therefore, in terms of hardware design, the directly output optical port lacks the direct control signals required to drive indicator lights, causing the corresponding optical port on the device panel to fail to display its operating status correctly, greatly inconveniencing user maintenance and troubleshooting.

[0005] In existing technologies, the common approach to addressing the lack of indicator light signals on CPU-based direct-output Ethernet ports is to rely on external network card chips or indirectly achieve this through complex software polling methods. However, the former increases hardware costs and design complexity, while the latter suffers from poor real-time performance, excessive CPU resource consumption, and cannot function properly during system startup or before the operating system is fully loaded. Therefore, there is an urgent need for a low-cost, high-real-time solution that does not require modification of the CPU's internal logic to solve the indicator light control problem for the Kunpeng 920 CPU module's direct-output XGE optical port. Summary of the Invention

[0006] The purpose of this invention is to solve the problem of indicator light control for the XGE optical port directly output by the Kunpeng 920 CPU module in the prior art, and to provide a method and system for lighting up the XGE network port directly output by the CPU based on the Kunpeng module platform.

[0007] To achieve the above objectives, the present invention employs the following technical solution:

[0008] A method for lighting LEDs via the direct XGE Ethernet port output from the CPU of the Kunpeng module platform includes the following steps:

[0009] Step 1: Power on the server motherboard and boot up normally;

[0010] Step 2: The CPU module monitors the working status of each XGE network port in real time and continuously transmits the working status to the CPLD of the motherboard through the SGPIO signal;

[0011] Step 3: The CPLD continuously decodes the SGPIO signals. Based on the link status and rate type of each XGE port, the CPLD outputs the corresponding Link control signal and Active control signal through its pins.

[0012] Step four: The network port indicator light will turn on, off, or flash depending on the high or low levels of the Link control signal and the Active control signal, in order to indicate the connection status and data transmission activity of the corresponding network port.

[0013] The SGPIO signals include the SCK clock signal, the SLOAD boundary flag signal, the SDI data receive signal, and the SDO data transmit signal; among them, data transmitted is valid only when the SLOAD signal is low.

[0014] Each XGE network port corresponds to 3 bits of data, which are packaged and transmitted by the CPU module through SGPIO signals. During CPLD decoding, the 3 bits of data for each network port are parsed into link status bits and rate type bits respectively.

[0015] In the aforementioned 3-digit data:

[0016] bit0 indicates the link status: 0 represents no link, 1 represents a link with no data transmission or reception, and a 1Hz pulse represents a link with both data transmission and reception.

[0017] The combination of bit1 and bit2 indicates the data rate type: 00 represents gigabit, 01 represents 10G, 10 represents 25G, 0 / 1Hz represents 40G, 0 / 4Hz represents 50G, and 1 / 1Hz represents 100G.

[0018] The CPLD controls the Active indicator light according to the decoded bit0 state: when bit0 is a 1Hz pulse, the Active indicator light flashes at a frequency of 1Hz; when bit0 is 1 and there is no pulse, the Active indicator light is off; when bit0 is 0, the Active indicator light is off. The CPLD controls the Link indicator light according to whether bit0 is zero: when bit0 is 0, the Link indicator light is off; otherwise, the Link indicator light is always on.

[0019] The CPU module summarizes the working status of the 8 XGE network ports into 24 bits of data, and transmits 24 bits of data each time an SGPIO signal is transmitted; after receiving the 24 bits of data, the CPLD divides it into 8 parts, with each part consisting of 3 bits corresponding to one XGE network port.

[0020] A system for lighting LEDs via a direct XGE Ethernet port output from the Kunpeng module platform CPU includes:

[0021] The Kunpeng CPU module is used to detect the working status of its multiple XGE network ports and encode the working status as SGPIO signal output.

[0022] The CPLD's input terminal is connected to the SGPIO signal output terminal of the CPU module. It is used to decode the SGPIO signal and output the Link indicator control signal and Active indicator control signal through its general-purpose input / output pins according to the decoding result.

[0023] The indicator circuit includes a Link indicator and an Active indicator for each XGE network port. The control terminals of the indicator lights are connected to the corresponding pins of the CPLD to display the network port status according to the control signals.

[0024] The CPLD is internally configured with SGPIO decoding logic. The decoding logic divides the continuously received 24-bit data into 8 groups of 3-bit data. Each group of data corresponds to an XGE network port, and generates the corresponding Link and Active drive levels based on bit0, bit1, and bit2 in each group of data.

[0025] The Link indicator light is green, and the Active indicator light is yellow. The Link indicator light is solid green when there is a link to the corresponding network port and off when there is no link. The Active indicator light flashes yellow when there is data transmission to the corresponding network port and off when there is no data transmission.

[0026] When the CPLD decodes bit0 of any XGE network port as 0, the Link indicator and Active indicator corresponding to that network port are both turned off; when bit0 is 1 and there is no pulse, only the Link indicator is constantly lit, and the Active indicator is off; when bit0 is a 1Hz pulse, the Link indicator is constantly lit and the Active indicator flashes at a frequency of 1Hz.

[0027] Compared with the prior art, the present invention has the following beneficial effects:

[0028] This invention effectively solves the technical problem of the Kunpeng 920 CPU module's direct-output XGE high-speed optical port failing to illuminate due to the lack of dedicated indicator light control pins. By reusing the CPU module's inherent standard SGPIO signal and combining it with the existing CPLD on the motherboard for hardware decoding, this invention achieves real-time indication of network port link status and data transmission / reception activity without requiring additional PHY chips, independent network card controllers, or GPIO expansion chips. This method does not rely on an operating system or driver and can function normally from server power-on, avoiding the lag and resource consumption issues of software polling schemes, while maintaining consistent user visual habits with general-purpose network cards.

[0029] This invention boasts excellent scalability and reliability. The SGPIO protocol can transmit status data from multiple network ports simultaneously, which are then decoded by the CPLD to drive corresponding indicator lights, facilitating centralized control and future expansion. The entire solution is compatible with the standard SGPIO protocol, requiring no modification to the CPU's internal logic or firmware, and can be easily extended to other server platforms with similar architectures. As a pure hardware logic device, the CPLD can operate stably even in harsh environments, and the built-in clock and frame synchronization mechanism of the SGPIO signal ensures anti-interference capabilities. Thus, it achieves high real-time performance and high reliability for network port indicator lights at extremely low cost, significantly improving device maintainability. Attached Figure Description

[0030] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present invention and should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0031] Figure 1 This is a flowchart of the method for lighting LEDs using the CPU direct output XGE network port based on the Kunpeng module platform according to the present invention;

[0032] Figure 2 This is a system block diagram of the present invention for lighting LEDs via the CPU direct output XGE network port of the Kunpeng module platform. Detailed Implementation

[0033] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0034] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0035] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0036] A method for lighting LEDs via the XGE network port directly output from the CPU of the Kunpeng module platform, as described in this invention, includes the following steps:

[0037] Step 1: Power on the server motherboard and boot up normally;

[0038] Step two: The CPU module continuously monitors the operating status of each XGE port in real time and transmits this status to the CPLD on the motherboard via SGPIO signals. The SGPIO signals include the SCK clock signal, SLOAD boundary flag signal, SDI data receive signal, and SDO data transmit signal; data transmitted is only valid when the SLOAD signal is low. The CPU module summarizes the operating status of the eight XGE ports into 24 bits of data, transmitting 24 bits of data each time an SGPIO signal is transmitted. The CPLD receives the 24 bits of data and divides it into eight parts, each with three bits corresponding to one XGE port.

[0039] Step 3: The CPLD continuously decodes the SGPIO signals. Based on the decoded link status and rate type of each XGE port, the CPLD outputs corresponding Link control signals and Active control signals through its pins. Each XGE port corresponds to 3 bits of data, which are packaged and transmitted by the CPU module via SGPIO signals. During decoding, the CPLD parses the 3 bits of data for each port into link status bits and rate type bits. The 3 bits of data include:

[0040] bit0 indicates the link status: 0 represents no link, 1 represents a link with no data transmission or reception, and a 1Hz pulse represents a link with both data transmission and reception.

[0041] The combination of bit1 and bit2 indicates the data rate type: 00 represents gigabit, 01 represents 10G, 10 represents 25G, 0 / 1Hz represents 40G, 0 / 4Hz represents 50G, and 1 / 1Hz represents 100G.

[0042] The CPLD controls the Active indicator light based on the decoded bit0 state: when bit0 is a 1Hz pulse, the Active indicator light flashes at a frequency of 1Hz; when bit0 is 1 and there is no pulse, the Active indicator light is off; when bit0 is 0, the Active indicator light is off. The CPLD controls the Link indicator light based on whether bit0 is zero: when bit0 is 0, the Link indicator light is off; otherwise, the Link indicator light is always on.

[0043] Step four: The network port indicator light will turn on, off, or flash depending on the high or low levels of the Link control signal and the Active control signal, in order to indicate the connection status and data transmission activity of the corresponding network port.

[0044] A system for lighting LEDs based on the direct XGE network port output from the CPU of the Kunpeng module platform, as described in this invention, includes:

[0045] The Kunpeng CPU module is used to detect the working status of its multiple XGE network ports and encode the working status as SGPIO signal output.

[0046] The CPLD, whose input terminal is connected to the SGPIO signal output terminal of the CPU module, is used to decode the SGPIO signal and output the Link indicator control signal and Active indicator control signal through its general-purpose input / output pins according to the decoding result. The CPLD is internally configured with SGPIO decoding logic, which divides the continuously received 24-bit data into 8 groups of 3-bit data, each group of data corresponding to an XGE network port, and generates the corresponding Link and Active drive levels according to bit0, bit1, and bit2 in each group of data.

[0047] When the CPLD decodes bit0 of any XGE network port as 0, the Link indicator and Active indicator corresponding to that network port are both turned off; when bit0 is 1 and there is no pulse, only the Link indicator is constantly lit, and the Active indicator is off; when bit0 is a 1Hz pulse, the Link indicator is constantly lit and the Active indicator flashes at a frequency of 1Hz.

[0048] The indicator circuit includes a Link indicator and an Active indicator for each XGE network port. The control terminals of the indicator lights are connected to the corresponding pins of the CPLD to display the network port status according to the control signals.

[0049] The Link indicator light is green, and the Active indicator light is yellow. The Link indicator light is solid green when there is a link to the corresponding network port and off when there is no link. The Active indicator light flashes yellow when there is data transmission to the corresponding network port and off when there is no data transmission.

[0050] The present invention will now be described in further detail with reference to the accompanying drawings:

[0051] The specific implementation process of this invention is as follows: Figure 1 As shown, it includes the following steps:

[0052] Step 1: Power on the server motherboard to ensure it can boot normally and provide a stable power supply for the CPU module and CPLD.

[0053] Step two: The CPU module continuously monitors the operating status of each XGE port it outputs in real time, including link connection status, data transmission and reception activity, and the current negotiation rate, and transmits this status information to the motherboard's CPLD via SGPIO signals. SGPIO is a standard protocol containing four signals: SCK (clock signal), SLOAD (boundary marker signal), SDI (data receive), and SDO (data transmit). Data transmitted is only valid when the SLOAD signal is low. Each XGE port corresponds to 3 bits of data, specifically defined as follows:

[0054] bit0: Indicates the link and activity status of the network interface.

[0055] 0 — No link (Link down);

[0056] 1 — Link up, no data transmission or reception (Link up, no activity);

[0057] A 1Hz pulse indicates that there is a link and data transmission / reception.

[0058] The combination of bit1 and bit2 indicates the network interface speed type.

[0059] 00 — Gigabit (1 Gbps);

[0060] 01 — 10 Gbps;

[0061] 10-25 Gbps;

[0062] 0 / 1Hz — 40 Gbps;

[0063] 0 / 4Hz — 50 Gbps;

[0064] 1 / 1Hz — 100 Gbps.

[0065] For the eight XGE ports, the CPU module aggregates the 3-bit data from each port, for a total of 24 bits of data. Each time an SGPIO signal is transmitted, this 24-bit data is packaged and sent to the CPLD.

[0066] Step three: The motherboard's CPLD continuously decodes the received SGPIO signals. The CPLD has internal decoding logic; upon receiving 24 bits of data, it divides it into eight parts, each with three bits corresponding to an XGE network port. Based on the three bits of data for each network port, the CPLD outputs the corresponding Link control signal and Active control signal through its general-purpose input / output pins.

[0067] Examples of decoding and control are as follows:

[0068] If the 3-bit data of a network port is parsed as "1Hz / 1 / 0" (i.e., bit0 is a 1Hz pulse, bit1=1, bit2=0), then it corresponds to a 10G XGE network port and there is data transmission and reception activity. The CPLD drives the Active indicator light of this network port to flash at 1Hz and drives the Link indicator light to be constantly on.

[0069] If the parsed data is "1 / 1 / 0" (bit0=1, bit1=1, bit2=0), it corresponds to the 10G XGE network port but there is no data transmission or reception activity. The CPLD will turn off the Active indicator light, while the Link indicator light will remain constantly on.

[0070] If the parsed data is "0 / 1 / 0" (bit0=0, bit1=1, bit2=0), then the corresponding 10G XGE network port has neither a link nor data activity. The CPLD will turn off both the Active and Link indicator lights.

[0071] Step four: The network port indicator lights illuminate, turn off, or flash according to the high and low levels of the Link and Active signals output from the CPLD pins, allowing users to intuitively identify the working status of the network port. In this embodiment, the Link indicator light is green, and the Active indicator light is yellow. Their specific status indications are shown in the table below:

[0072] Table 1. Status Description of Network Port Indicator Lights

[0073] Link status indicator (green) Solid green: Link status is normal; Green off: No Link. Active status indicator (yellow) Flashing yellow indicates network data transmission; yellow off indicates no data activity.

[0074] Through the above steps, this invention successfully implemented indicator light control for direct-output XGE network ports (including 10G, 25G, 40G, 50G, and 100G optical ports) by utilizing the existing SGPIO signals of the Kunpeng CPU module and the CPLD resources on the motherboard. This method requires no additional PHY chip or dedicated network card controller, and does not rely on operating system drivers. It can reflect the network port status in real time and accurately after power-on, effectively compensating for the deficiency of the Kunpeng module CPU platform's inability to illuminate direct-output XGE network ports, reducing design costs and improving server maintainability.

[0075] like Figure 2 As shown, this invention provides a system that uses a CPLD to decode SGPIO signals transmitted from a CPU module to implement XGE network port indicator light functions. The system includes: a Kunpeng 920 CPU module, a CPLD on the motherboard, and indicator light circuits corresponding to each XGE network port. The CPU module outputs the operating status of its multiple XGE network ports via a standard SGPIO bus; the input of the CPLD is connected to the SGPIO bus for decoding SGPIO signals; the output pins of the CPLD are connected to the Link and Active indicator lights of each network port, respectively.

[0076] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for lighting LEDs via a direct XGE Ethernet port output from a Kunpeng module platform CPU, characterized in that, Includes the following steps: Step 1: Power on the server motherboard and boot up normally; Step 2: The CPU module monitors the working status of each XGE network port in real time and continuously transmits the working status to the CPLD of the motherboard through the SGPIO signal; Step 3: The CPLD continuously decodes the SGPIO signals. Based on the link status and rate type of each XGE port, the CPLD outputs the corresponding Link control signal and Active control signal through its pins. Step four: The network port indicator light will turn on, off, or flash depending on the high or low levels of the Link control signal and the Active control signal, in order to indicate the connection status and data transmission activity of the corresponding network port.

2. The method for lighting LEDs via a direct XGE network port output from a Kunpeng module platform CPU as described in claim 1, characterized in that, The SGPIO signals include the SCK clock signal, the SLOAD boundary flag signal, the SDI data receive signal, and the SDO data transmit signal; among them, data transmitted is valid only when the SLOAD signal is low.

3. The method for lighting LEDs via a direct XGE network port output from a Kunpeng module platform CPU as described in claim 1, characterized in that... Each XGE network port corresponds to 3 bits of data, which are packaged and transmitted by the CPU module through SGPIO signals. During CPLD decoding, the 3 bits of data for each network port are parsed into link status bits and rate type bits respectively.

4. The method for lighting LEDs via a direct XGE network port output from a Kunpeng module platform CPU as described in claim 3, characterized in that, In the aforementioned 3-digit data: bit0 indicates the link status: 0 represents no link, 1 represents a link with no data transmission or reception, and a 1Hz pulse represents a link with both data transmission and reception. The combination of bit1 and bit2 indicates the data rate type: 00 represents gigabit, 01 represents 10G, 10 represents 25G, 0 / 1Hz represents 40G, 0 / 4Hz represents 50G, and 1 / 1Hz represents 100G.

5. The method for lighting LEDs via a direct XGE network port output from a Kunpeng module platform CPU as described in claim 5, characterized in that... The CPLD controls the Active indicator light according to the decoded bit0 state: when bit0 is a 1Hz pulse, the Active indicator light flashes at a frequency of 1Hz; when bit0 is 1 and there is no pulse, the Active indicator light is off; when bit0 is 0, the Active indicator light is off. The CPLD controls the Link indicator light according to whether bit0 is zero: when bit0 is 0, the Link indicator light is off; otherwise, the Link indicator light is always on.

6. The method for lighting LEDs via a direct XGE network port output from a Kunpeng module platform CPU as described in claim 1, characterized in that, The CPU module summarizes the working status of the 8 XGE network ports into 24 bits of data, and transmits 24 bits of data each time an SGPIO signal is transmitted; after receiving the 24 bits of data, the CPLD divides it into 8 parts, with each part consisting of 3 bits corresponding to one XGE network port.

7. A system for lighting LEDs via a direct XGE network port output from a Kunpeng module platform CPU, characterized in that: include: The Kunpeng CPU module is used to detect the working status of its multiple XGE network ports and encode the working status as SGPIO signal output. The CPLD's input terminal is connected to the SGPIO signal output terminal of the CPU module. It is used to decode the SGPIO signal and output the Link indicator control signal and Active indicator control signal through its general-purpose input / output pins according to the decoding result. The indicator circuit includes a Link indicator and an Active indicator for each XGE network port. The control terminals of the indicator lights are connected to the corresponding pins of the CPLD to display the network port status according to the control signals.

8. The system for lighting LEDs based on the direct XGE network port output from the CPU of the Kunpeng module platform as described in claim 7, characterized in that, The CPLD is internally configured with SGPIO decoding logic. The decoding logic divides the continuously received 24-bit data into 8 groups of 3-bit data. Each group of data corresponds to an XGE network port, and generates the corresponding Link and Active drive levels based on bit0, bit1, and bit2 in each group of data.

9. A system for lighting LEDs based on the direct XGE network port output from the CPU of the Kunpeng module platform as described in claim 7, characterized in that, The Link indicator light is green, and the Active indicator light is yellow. The Link indicator light is solid green when there is a link to the corresponding network port and off when there is no link. The Active indicator light flashes yellow when there is data transmission to the corresponding network port and off when there is no data transmission.

10. The system for lighting LEDs based on the direct XGE network port output from the CPU of the Kunpeng module platform as described in claim 7, characterized in that, When the CPLD decodes bit0 of any XGE network port as 0, the Link indicator and Active indicator corresponding to that network port are both turned off; when bit0 is 1 and there is no pulse, only the Link indicator is constantly lit, and the Active indicator is off; when bit0 is a 1Hz pulse, the Link indicator is constantly lit and the Active indicator flashes at a frequency of 1Hz.

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