Flash memory structure and method of making the same

Abstract

The application provides a flash memory structure and a preparation method thereof. A grinding sacrificial layer is formed on an oxide layer covering a polysilicon layer, and the grinding sacrificial layer is subjected to a planarization treatment to expose the oxide layer and a hard mask layer in a gate stack. Subsequently, the polysilicon layer on both sides of the gate stack is subjected to a first etching treatment to form a word line polysilicon layer and an erase gate polysilicon layer. Then, the oxide layer is removed, and the polysilicon layer is subjected to a second etching treatment to reduce the height difference of the surface steps. In this way, the process steps such as photolithography, oxide layer dry etching and glue removal in the process of forming the word line polysilicon layer and the erase gate polysilicon layer can be reduced, the preparation process of the word line and the erase gate polysilicon structure in the flash memory is simplified, the process complexity and the manufacturing cost are reduced, the height difference between the word line polysilicon layer, the erase gate polysilicon layer and the adjacent polysilicon layer is improved, and the stability of the subsequent process and the consistency of the device structure are improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a flash memory structure and its fabrication method. Background Technology

[0002] Flash memory is a type of non-volatile memory that retains stored data even after power is lost, making it widely used in embedded memory and related integrated circuit products. The basic memory cell of flash memory typically includes a floating gate, a control gate, word lines, and an erase gate. The floating gate stores charge, the control gate regulates the potential of the floating gate, and the word lines and erase gate jointly participate in the selection, reading, and erasing operations of the memory cell. In embedded flash memory process nodes such as 40SST, the fabrication quality of the word line polysilicon layer and the erase gate polysilicon layer has a significant impact on the device's electrical performance, erase efficiency, and process stability. Existing word line and erase gate polysilicon fabrication processes typically require multiple steps after depositing polysilicon and oxide layers, including photolithography, word line cap dry etching, resist removal, dummy upper polysilicon deposition, chemical mechanical planarization, polysilicon etch-back, and oxide layer removal. This process is lengthy and complex. In particular, photolithography, dry etching, and resist removal steps not only increase mask and equipment costs and extend the process cycle, but may also introduce problems such as photoresist residue, etching damage, particle defects, and difficulty in controlling step height differences, thereby affecting subsequent film deposition, planarization, and the consistency of device structure. Summary of the Invention

[0003] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a flash memory structure and its fabrication method, which solves the problems of complex fabrication process, numerous process steps, and high manufacturing cost of word lines and erase gate polysilicon layers in the prior art, and the fact that process steps such as photolithography, word line cap oxygen dry etching, and resist removal are prone to introducing defects and affecting process stability.

[0004] To achieve the above and other related objectives, the present invention provides a method for fabricating a flash memory structure, the method comprising:

[0005] An intermediate structure is provided, the intermediate structure including a semiconductor substrate, a gate stack located on the semiconductor substrate, a polysilicon layer conformally covering the semiconductor substrate and the gate stack, and an oxide layer conformally covering the polysilicon layer; wherein, the gate stack includes, from bottom to top, a floating gate, an inter-gate insulating layer, a control gate, and a hard mask layer.

[0006] A polishing sacrificial layer covering the intermediate structure is formed on the oxide layer;

[0007] The surface of the polishing sacrificial layer away from the intermediate structure is planarized until the oxide layer located above the semiconductor substrate and the hard mask layer in the gate stack are exposed;

[0008] The exposed polysilicon layers located on both sides of the gate stack are subjected to a first etch process to remove part of the thickness of the polysilicon layers, forming word line polysilicon layers and erase gate polysilicon layers located on both sides of the gate stack, and forming a step height difference between the word line polysilicon layers and adjacent polysilicon layers, and between the erase gate polysilicon layers and adjacent polysilicon layers.

[0009] Remove the oxide layer; and

[0010] The polycrystalline silicon layer is subjected to a second etch process to reduce the step height difference.

[0011] Optionally, the sidewalls of the gate stack are formed with sidewalls.

[0012] Optionally, a silicon oxide layer is formed on one surface of the semiconductor substrate on which the polysilicon layer and the gate stack are formed.

[0013] Optionally, before the first etch-back process, the thickness of the polysilicon layer covering the semiconductor substrate is greater than the thickness of the word line polysilicon layer formed after the first etch-back process, and before the first etch-back process, the thickness of the polysilicon layer covering the semiconductor substrate is greater than the thickness of the erase gate polysilicon layer formed after the first etch-back process.

[0014] Optionally, the hard mask layer includes a silicon nitride layer.

[0015] Optionally, the upper surface of the hard mask layer in the gate stack is higher than the upper surface of the oxide layer located on the semiconductor substrate, and the lower surface of the hard mask layer is lower than the upper surface of the oxide layer located on the semiconductor substrate.

[0016] Optionally, the material of the polishing sacrificial layer includes polycrystalline silicon.

[0017] Optionally, a chemical mechanical polishing process is used to planarize the surface of the polishing sacrificial layer away from the intermediate structure until the oxide layer located above the semiconductor substrate and the hard mask layer in the gate stack are exposed.

[0018] Optionally, a shallow trench isolation structure is formed within the semiconductor substrate.

[0019] The present invention also provides a flash memory structure, which is prepared by the flash memory structure preparation method described in any one of the above claims.

[0020] As described above, the flash memory structure and its fabrication method of the present invention have the following beneficial effects: by forming a polishing sacrificial layer on the oxide layer covering the polysilicon layer, and planarizing the polishing sacrificial layer to expose the oxide layer and the hard mask layer in the gate stack, and then performing a first etch process on the polysilicon layers located on both sides of the gate stack to form the word line polysilicon layer and the erase gate polysilicon layer, and then removing the oxide layer and performing a second etch process on the polysilicon layer to reduce the surface step height difference, the process steps such as photolithography, dry etching of oxide layer and resist removal can be reduced during the formation of word line polysilicon layer and erase gate polysilicon layer, simplifying the fabrication process of word line and erase gate polysilicon structure in flash memory, reducing process complexity and manufacturing cost, and improving the height difference between word line polysilicon layer, erase gate polysilicon layer and adjacent polysilicon layer, which is beneficial to improving the stability of subsequent processes and the consistency of device structure. Attached Figure Description

[0021] Figure 1 The diagram shows a flow chart of the method for fabricating the flash memory structure of the present invention.

[0022] Figures 2 to 7 The diagram shows a cross-sectional view of each step in the fabrication method of the flash memory structure of the present invention.

[0023] Component labeling explanation: 1 Intermediate structure, 10 Semiconductor substrate, 101 Silicon oxide layer, 11 Gate stack, 111 Floating gate, 112 Gate insulating layer, 113 Control gate, 114 Hard mask layer, 12 Polysilicon layer, 121 Word line polysilicon layer, 122 Erase gate polysilicon layer, 13 Oxide layer, 14 Sidewall, 141 First sidewall, 142 Second sidewall, 2 Polishing sacrificial layer, Steps S1~S6. Detailed Implementation

[0024] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0025] Please see Figures 1 to 7 It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the illustrations only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0026] This embodiment provides a method for fabricating a flash memory structure, such as... Figure 1 As shown, the preparation method includes:

[0027] An intermediate structure is provided, the intermediate structure including a semiconductor substrate, a gate stack located on the semiconductor substrate, a polysilicon layer conformally covering the semiconductor substrate and the gate stack, and an oxide layer conformally covering the polysilicon layer; wherein, the gate stack includes, from bottom to top, a floating gate, an inter-gate insulating layer, a control gate, and a hard mask layer.

[0028] A polishing sacrificial layer covering the intermediate structure is formed on the oxide layer;

[0029] The surface of the polishing sacrificial layer away from the intermediate structure is planarized until the oxide layer located above the semiconductor substrate and the hard mask layer in the gate stack are exposed;

[0030] The exposed polysilicon layers located on both sides of the gate stack are subjected to a first etch process to remove part of the thickness of the polysilicon layers, forming word line polysilicon layers and erase gate polysilicon layers located on both sides of the gate stack, and forming a step height difference between the word line polysilicon layers and adjacent polysilicon layers, and between the erase gate polysilicon layers and adjacent polysilicon layers.

[0031] Remove the oxide layer; and

[0032] The polycrystalline silicon layer is subjected to a second etch process to reduce the step height difference.

[0033] The method for fabricating the flash memory structure in this embodiment involves forming a polishing sacrificial layer on the oxide layer covering the polysilicon layer, and planarizing the polishing sacrificial layer to expose the oxide layer and the hard mask layer in the gate stack. Subsequently, a first etch is performed on the polysilicon layers located on both sides of the gate stack to form word line polysilicon layers and erase gate polysilicon layers. Then, the oxide layer is removed and a second etch is performed on the polysilicon layers to reduce the surface step height difference. This reduces the number of process steps such as photolithography, dry etching of oxide layers, and resist removal during the formation of word line polysilicon layers and erase gate polysilicon layers, simplifying the fabrication process of word line and erase gate polysilicon structures in flash memory, reducing process complexity and manufacturing costs. At the same time, it improves the height difference between word line polysilicon layers, erase gate polysilicon layers and adjacent polysilicon layers, which is beneficial to improving the stability of subsequent processes and the consistency of device structure.

[0034] The fabrication method of the flash memory structure in this embodiment will be described in detail below with reference to the specific accompanying drawings.

[0035] like Figure 2As shown, step S1 is performed first, providing an intermediate structure 1. The intermediate structure 1 includes a semiconductor substrate 10, a gate stack 11 located on the semiconductor substrate 10, a polysilicon layer 12 conformally covering the semiconductor substrate 10 and the gate stack 11, and an oxide layer 13 conformally covering the polysilicon layer. The gate stack 11 includes, from bottom to top, a floating gate 111, an inter-gate insulating layer 112, a control gate 113, and a hard mask layer 114.

[0036] Specifically, as an example, a shallow trench isolation structure (not shown) is formed within the semiconductor substrate 10 to isolate different active regions within the semiconductor substrate 10. A silicon oxide layer 101 is formed on one surface of the semiconductor substrate 10 where the polysilicon layer 12 and the gate stack 11 are formed. The silicon oxide layer 101 can be used, for example, as a stop layer in subsequent etching processes. The semiconductor substrate 10 can also form corresponding device structures according to device design and process requirements, such as well regions, doped regions, source / drain regions, threshold adjustment regions, or other functional areas for forming flash memory cells and peripheral circuit devices. It should be noted that the specific type, location, quantity, size, doping type, and formation method of the shallow trench isolation structure, the silicon oxide layer 101, and the device structures within the semiconductor substrate 10 are not limited to this embodiment. Those skilled in the art can select or adjust these elements according to the actual device structure, process node, and process requirements.

[0037] Specifically, as an example, the sidewalls of the gate stack 11 are formed with sidewalls 14, which cover the sidewalls of the gate stack 11 to provide lateral protection for the gate stack 11 and define the spacing between the gate stack 11 and the subsequently formed word line polysilicon layer and erase gate polysilicon layer. The sidewalls 14 may include a first sidewall 141 and a second sidewall 142 stacked together, with the first sidewall 141 located on the sidewall surface of the gate stack 11 and the second sidewall 142 located on the side of the first sidewall 141 away from the gate stack 11. The first sidewall 141 and the second sidewall 142 may be formed of the same material or different materials; for example, the first sidewall 141 and the second sidewall 142 may each include at least one of silicon oxide, silicon nitride, and silicon oxynitride. It should be noted that the number of layers, materials, thickness and formation method of the sidewall 14 are not limited to this embodiment. Those skilled in the art can select or adjust them according to the structure of the gate stack 11, the formation requirements of subsequent film layers and the etching process requirements.

[0038] As an example, the hard mask layer 114 includes a silicon nitride layer. The hard mask layer 114 can be used as an etching mask during the formation of the gate stack 11 to protect the control gate 113 and the underlying inter-gate insulating layer 112 and the floating gate 111. Furthermore, during subsequent planarization of the polishing sacrificial layer, the hard mask layer 114 can also serve as a stop layer or auxiliary stop layer for planarization, thereby improving the control accuracy of the top morphology of the gate stack 11. It should be noted that the material of the hard mask layer 114 is not limited to silicon nitride. In other embodiments, the hard mask layer 114 can also be selected as a silicon oxide layer, a silicon oxynitride layer, or a stacked structure composed of multiple dielectric layers, depending on the etching selectivity, planarization process requirements, and device structure requirements.

[0039] As an example, the upper surface of the hard mask layer 114 in the gate stack 11 is higher than the upper surface of the oxide layer 13 located on the semiconductor substrate 10, and the lower surface of the hard mask layer 114 is lower than the upper surface of the oxide layer 13 located on the semiconductor substrate 10. That is, in the direction perpendicular to the semiconductor substrate 10, the upper surface of the oxide layer 13 is located between the upper and lower surfaces of the hard mask layer 114, such that the hard mask layer 114 at least partially protrudes from the upper surface of the oxide layer 13. Through the above height relationship, when performing planarization processing on the polishing sacrificial layer, the oxide layer 13 located above the semiconductor substrate 10 and the hard mask layer 114 located at the top of the gate stack 11 can serve as the stop position or auxiliary stop position for the planarization process, thereby facilitating the control of the surface morphology after planarization and ensuring a more stable process starting morphology when performing the first etch on the polysilicon layer 12. It should be noted that the specific height difference between the hard mask layer 114 and the oxide layer 13 is not limited to this embodiment. Those skilled in the art can select or adjust it according to the height of the gate stack 11, the thickness of the oxide layer 13, the thickness of the polishing sacrificial layer, and the planarization process window.

[0040] like Figure 3 As shown, step S2 is then performed to form a polishing sacrificial layer 2 covering the intermediate structure 1 on the oxide layer 13.

[0041] As an example, the material of the polishing sacrificial layer 2 includes polysilicon. The polishing sacrificial layer 2 is formed on the side of the oxide layer 13 away from the polysilicon layer 12 and covers the intermediate structure 1 to fill the recessed area formed by the protrusion of the gate stack 11, thereby providing sacrificial material to be removed for subsequent planarization processing. Since the polishing sacrificial layer 2 includes polysilicon, there can be good planarization selectivity between the polishing sacrificial layer 2, the oxide layer 13, and the hard mask layer 114. This allows the oxide layer 13 located above the semiconductor substrate 10 and the hard mask layer 114 located on top of the gate stack 11 to be used as the stop position or auxiliary stop position during subsequent planarization processing of the polishing sacrificial layer 2, thereby facilitating control of the removal endpoint of the polishing sacrificial layer 2 and the surface morphology after planarization. It should be noted that the material of the polishing sacrificial layer 2 is not limited to polysilicon. In other embodiments, the polishing sacrificial layer 2 can also be selected as other materials suitable as sacrificial fillers, depending on the planarization process requirements, material removal rate, etching selectivity, and subsequent etch-back process window.

[0042] like Figure 4 As shown, step S3 is then performed to planarize the surface of the polishing sacrificial layer 2 away from the intermediate structure 1 until the oxide layer 13 located above the semiconductor substrate 10 and the hard mask layer 114 in the gate stack 11 are exposed.

[0043] As an example, a planarization process, including but not limited to chemical mechanical polishing (CMP), can be used to planarize the surface of the polishing sacrificial layer 2 away from the intermediate structure 1. During the planarization process, the polishing sacrificial layer 2 is gradually removed until the oxide layer 13 located above the semiconductor substrate 10 and the hard mask layer 114 in the gate stack 11 are exposed. That is, the oxide layer 13 and the hard mask layer 114 can jointly serve as the stop position or auxiliary stop position of the planarization process to control the removal endpoint of the polishing sacrificial layer 2 and to obtain a relatively flat surface morphology for the structure after the planarization process. Through the above planarization process, excess polishing sacrificial layer 2 located above the oxide layer 13 and the hard mask layer 114 can be removed, so that a stable process starting morphology can be obtained when the polysilicon layer 12 is subsequently etched for the first time. It should be noted that the specific process of the planarization treatment is not limited to chemical mechanical polishing. In other embodiments, other suitable processes for achieving planarization can be selected according to the materials of the grinding sacrificial layer 2, the oxide layer 13 and the hard mask layer 114, the removal rate, the selectivity, and the surface flatness requirements.

[0044] like Figure 5As shown, step S4 is then performed to perform a first etch process on the exposed polysilicon layers located on both sides of the gate stack to remove part of the thickness of the polysilicon layers, forming word line polysilicon layers and erase gate polysilicon layers located on both sides of the gate stack, and forming a step height difference between the word line polysilicon layers and the adjacent polysilicon layers, and between the erase gate polysilicon layers and the adjacent polysilicon layers.

[0045] Specifically, the step height difference includes a first step height difference H1 and a second step height difference H2, wherein the first step height difference H1 is formed between the word line polysilicon layer 121 and the adjacent polysilicon layer 12, and the second step height difference H2 is formed between the erase gate polysilicon layer 122 and the adjacent polysilicon layer 12.

[0046] Specifically, the first etch pass is preferably a selective etching process. This involves controlling process parameters such as etching gas, etching power, etching pressure, or etching time to ensure that the polysilicon layer 12 has a higher etching rate relative to the oxide layer 13 and the hard mask layer 114. This reduces etching losses on the oxide layer 13 and the hard mask layer 114 while etching the polysilicon layer 12. Consequently, the oxide layer 13 and the hard mask layer 114 can act as a shield or protector during the first etch pass, allowing the portion of the polysilicon layer 12 below the oxide layer 13 to be retained, while the exposed polysilicon layers 12 located on both sides of the gate stack 11 have a portion of their thickness etched away.

[0047] As a preferred example, before the first etch-back process, the thickness of the polysilicon layer 12 covering the semiconductor substrate 10 is greater than the thickness of the word line polysilicon layer 121 formed after the first etch-back process, and before the first etch-back process, the thickness of the polysilicon layer 12 covering the semiconductor substrate 10 is greater than the thickness of the erase gate polysilicon layer 122 formed after the first etch-back process. This allows for a process margin to be reserved for the first etch-back process of the polysilicon layer 12.

[0048] As a preferred example, after the first etch-back process, the upper surfaces of the word line polysilicon layer 121 and the erase gate polysilicon layer 122 are lower than the upper surfaces of the adjacent polysilicon layers 12, resulting in a step height difference between the word line polysilicon layer 121 and the adjacent polysilicon layers 12, and between the erase gate polysilicon layer 122 and the adjacent polysilicon layers 12. It should be noted that the specific etching method, etching depth, and final thickness of the word line polysilicon layer 121 and the erase gate polysilicon layer 122 in the first etch-back process are not limited to this embodiment. Those skilled in the art can select the appropriate method based on the target device structure, the initial thickness of the polysilicon layers 12, and the subsequent step height difference adjustment requirements.

[0049] like Figure 6 As shown, step S5 is then performed to remove the oxide layer 13.

[0050] Specifically, the oxide layer 13 can be used as a stop layer, a masking layer, or a protective layer during the aforementioned planarization process and the first etch pass. After the formation of the word line polysilicon layer 121 and the erase gate polysilicon layer 122 is completed, the oxide layer 13 is removed to facilitate the subsequent second etch pass of the exposed polysilicon layer 12. As an example, the oxide layer 13 can be removed using a wet etching process, a dry etching process, or a combination of dry and wet etching. It should be noted that the specific removal method of the oxide layer 13 is not limited to this embodiment. Those skilled in the art can select the appropriate method based on the material and thickness of the oxide layer 13, the etching selectivity of the polysilicon layer 12, and the structural protection requirements of the gate stack 11.

[0051] like Figure 7 As shown, step S6 is then performed to etch the polysilicon layer 12 a second time to reduce the step height difference.

[0052] Specifically, the first step height difference H1 and the second step height difference H2 are reduced through a second etch process. For example, the second etch process removes at least the portion of the polysilicon layer 12 adjacent to the word line polysilicon layer 121 and the erase gate polysilicon layer 122 that is higher than the word line polysilicon layer 121 and the erase gate polysilicon layer 122, thereby reducing the first step height difference H1 and the second step height difference H2. This improves the process window for subsequent film deposition, photolithography, or etching processes and enhances the morphological consistency of the formed flash memory structure. It should be noted that the specific etching method, etching time, etching depth, and etching selectivity of the second etch process are not limited to this embodiment. Those skilled in the art can select or adjust these parameters based on the magnitude of the step height difference, the target thickness of the word line polysilicon layer 121 and the erase gate polysilicon layer 122, and subsequent process requirements, as long as the step height difference can be reduced.

[0053] This embodiment also provides a flash memory structure, which can be prepared using the above-described flash memory structure preparation method, but is not limited to this method. Other suitable preparation methods are also possible, and the beneficial effects they can achieve can be found in the specific description of the preparation method, which will not be repeated here.

[0054] In summary, the flash memory structure and its fabrication method of the present invention, by forming a polishing sacrificial layer on the oxide layer covering the polysilicon layer, and planarizing the polishing sacrificial layer to expose the oxide layer and the hard mask layer in the gate stack, and then performing a first etch on the polysilicon layers located on both sides of the gate stack to form the word line polysilicon layer and the erase gate polysilicon layer, and then removing the oxide layer and performing a second etch on the polysilicon layer to reduce the surface step height difference, can reduce the photolithography, dry etching of oxide layer and resist removal processes in the formation of word line polysilicon layer and erase gate polysilicon layer, simplify the fabrication process of word line and erase gate polysilicon structure in flash memory, reduce process complexity and manufacturing cost, and improve the height difference between word line polysilicon layer, erase gate polysilicon layer and adjacent polysilicon layers, which is beneficial to improving the stability of subsequent processes and the consistency of device structure. Therefore, the present invention effectively overcomes the various shortcomings of the prior art and has high industrial application value.

[0055] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A method of fabricating a flash memory structure, comprising: The preparation method includes: An intermediate structure is provided, the intermediate structure including a semiconductor substrate, a gate stack located on the semiconductor substrate, a polysilicon layer conformally covering the semiconductor substrate and the gate stack, and an oxide layer conformally covering the polysilicon layer; wherein, the gate stack includes, from bottom to top, a floating gate, an inter-gate insulating layer, a control gate, and a hard mask layer. A polishing sacrificial layer covering the intermediate structure is formed on the oxide layer; The surface of the polishing sacrificial layer away from the intermediate structure is planarized until the oxide layer above the semiconductor substrate and the hard mask layer in the gate stack are exposed; The exposed polysilicon layers located on both sides of the gate stack are subjected to a first etch process to remove part of the thickness of the polysilicon layers, forming word line polysilicon layers and erase gate polysilicon layers located on both sides of the gate stack, and forming a step height difference between the word line polysilicon layers and adjacent polysilicon layers, and between the erase gate polysilicon layers and adjacent polysilicon layers. Remove the oxide layer; and The polycrystalline silicon layer is subjected to a second etch process to reduce the step height difference.

2. The method for fabricating a flash memory structure according to claim 1, characterized in that: The sidewalls of the gate stack are formed with sidewalls.

3. The method for fabricating a flash memory structure according to claim 1, characterized in that: A silicon oxide layer is formed on one side surface of the semiconductor substrate on which the polysilicon layer and the gate stack are formed.

4. The method for fabricating a flash memory structure according to claim 1, characterized in that: Before the first etch-back process, the thickness of the polysilicon layer covering the semiconductor substrate is greater than the thickness of the word line polysilicon layer formed after the first etch-back process, and before the first etch-back process, the thickness of the polysilicon layer covering the semiconductor substrate is greater than the thickness of the erase gate polysilicon layer formed after the first etch-back process.

5. The method for fabricating a flash memory structure according to claim 1, characterized in that: The hard mask layer includes a silicon nitride layer.

6. The method for fabricating a flash memory structure according to claim 1, characterized in that: The upper surface of the hard mask layer in the gate stack is higher than the upper surface of the oxide layer located on the semiconductor substrate, and the lower surface of the hard mask layer is lower than the upper surface of the oxide layer located on the semiconductor substrate.

7. The method for fabricating a flash memory structure according to claim 1, characterized in that: The material of the polishing sacrificial layer includes polycrystalline silicon.

8. The method for fabricating a flash memory structure according to claim 1, characterized in that: The surface of the polishing sacrificial layer away from the intermediate structure is planarized using a chemical mechanical polishing process until the oxide layer located above the semiconductor substrate and the hard mask layer in the gate stack are exposed.

9. The method for fabricating a flash memory structure according to claim 1, characterized in that: A shallow trench isolation structure is formed within the semiconductor substrate.

10. A flash memory structure, characterized in that: It is prepared using the method for preparing the flash memory structure as described in any one of claims 1 to 9.

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