Semiconductor device, template, and method for manufacturing template

Abstract

According to one embodiment, a semiconductor device includes a substrate, a first stacked film, and a second stacked film, the first and second stacked films including a plurality of insulating layers and a plurality of electrode layers alternately arranged on the substrate. The device further includes a plurality of columnar portions arranged within the insulating layers and the electrode layers of the first stacked film, including a charge storage layer and a semiconductor layer. The second stacked film further includes an insulating film having a first lower surface and a second lower surface, the first lower surface being inclined at a first angle with respect to an upper surface of one of the electrode layers within the first stacked film, and the second lower surface being inclined at a second angle smaller than the first angle with respect to the upper surface of the one of the electrode layers within the first stacked film. The insulating layers and the electrode layers within the second stacked film are arranged below the first and second lower surfaces of the insulating film.

Description

[0001] Divisional application statement

[0002] This application is a divisional application of Chinese patent application No. 2021108743500, filed on July 30, 2021, entitled "Semiconductor device, template and method of manufacturing template".

[0003] Related applications

[0004] This application is based on and seeks the benefit of priority of the prior Japanese Patent Application No. 2021-045058, filed on March 18, 2021, the entire contents of which are incorporated herein by reference. Technical Field

[0005] Embodiments of this disclosure relate to a semiconductor device, a template, and a method of manufacturing the template. Background Technology

[0006] In semiconductor devices, when a multilayer film consisting of alternating insulating and electrode layers is provided, these insulating and electrode layers are sometimes disposed on an inclined surface. In this case, it is preferable to provide the insulating and electrode layers on an inclined surface of suitable shape. Summary of the Invention

[0007] One embodiment of the present invention provides a semiconductor device in which an insulating layer and an electrode layer of a laminated film can be disposed on an inclined surface of a suitable shape.

[0008] According to one embodiment, a semiconductor device includes a substrate, a first laminated film, and a second laminated film. The first laminated film and the second laminated film include a plurality of insulating layers and a plurality of electrode layers alternately disposed on the substrate. The device further includes a plurality of columnar portions disposed within the insulating layers and the electrode layers of the first laminated film, and including a charge storage layer and a semiconductor layer. The second laminated film further includes an insulating film having a first lower surface and a second lower surface. The first lower surface is inclined at a first angle relative to the upper surface of one of the electrode layers in the first laminated film, and the second lower surface is inclined at a second angle smaller than the first angle relative to the upper surface of one of the electrode layers in the first laminated film. The insulating layers and the electrode layers in the second laminated film are disposed below the first lower surface and the second lower surface of the insulating film.

[0009] Based on the above configuration, a semiconductor device can be provided in which an insulating layer and an electrode layer of a laminated film can be disposed on an inclined surface of a suitable shape. Attached Figure Description

[0010] Figure 1This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0011] Figure 2 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0012] Figure 3 This is a cross-sectional view showing the structure of the columnar portion 25 in the first embodiment.

[0013] Figure 4 This is a cross-sectional view showing the structure of the storage cell array section 14 and the hoop-up section 15 of the first embodiment.

[0014] Figures 5A-5D This is a top view showing the structure of the semiconductor device according to the first embodiment.

[0015] Figure 6 This is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the first embodiment.

[0016] Figure 7 and Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0017] Figures 9-14 This is a cross-sectional view showing a method for manufacturing the array wafer W2 according to the first embodiment.

[0018] Figures 15A-15E These are top and cross-sectional views showing the method of forming the insulating film 23 according to the first embodiment.

[0019] Figures 16A-16C This is another top view and cross-sectional view showing the method of forming the insulating film 23 according to the first embodiment.

[0020] Figure 17 This is another top view showing the method of forming the insulating film 23 according to the first embodiment.

[0021] Figures 18A-18C and Figures 19A-19C This is another cross-sectional view showing the method of forming the insulating film 23 according to the first embodiment.

[0022] Figures 20A-20D This is a cross-sectional view showing a method for forming the insulating film 23 according to a modified example of the first embodiment.

[0023] Figures 21A-21E These are top and cross-sectional views showing a method for forming the insulating film 23, which is another variation of the first embodiment.

[0024] Figure 22 This is a cross-sectional view showing an example of the shape of template 3 in the second embodiment.

[0025] Figures 23A-25B It is shown Figure 22 A cross-sectional view of the manufacturing method of template 3.

[0026] Figure 26 This is a cross-sectional view showing another example of the shape of template 3 in the second embodiment.

[0027] Figures 27A to 29B It is shown Figure 26 A cross-sectional view of the manufacturing method of template 3.

[0028] Figure 30 This is a cross-sectional view showing another example of the shape of template 3 in the second embodiment. Detailed Implementation

[0029] The following describes several embodiments of the present invention, but these embodiments are given as examples and are not intended to limit the scope of the invention. Figures 1 to 30 In the accompanying drawings, the same components are labeled with the same reference numerals, and repeated descriptions are omitted.

[0030] (First Implementation)

[0031] Figure 1 This is a cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0032] The semiconductor device in this embodiment is, for example, a three-dimensional semiconductor memory, comprising a circuit region 1 and an array region 2. Figure 1 In this embodiment, an array region 2 is disposed on a circuit region 1. The array region 2 has a memory cell array, and the circuit region 1 has a CMOS circuit for controlling the memory cell array. The semiconductor device of this embodiment is manufactured, for example, by bonding a circuit wafer containing the circuit region 1 and an array wafer containing the array region 2. Figure 1 The mating surface S of circuit region 1 (circuit wafer) and array region 2 (array wafer) is shown.

[0033] Figure 1 The X, Y, and Z directions, which are perpendicular to each other, are shown. In this specification, the +Z direction is referred to as the up direction, and the -Z direction as the down direction. The -Z direction may or may not be aligned with the direction of gravity.

[0034] The semiconductor device of this embodiment includes a substrate 11, an interlayer insulating film 12, an interlayer insulating film 13, a memory cell array 14, a connection portion 15, a plurality of transistors 16, and a plurality of transistors 17. The substrate 11, the interlayer insulating film 12, the transistors 16 and 17 are disposed in the circuit region 1, and the interlayer insulating film 13, the memory cell array 14 and the connection portion 15 are disposed in the array region 2.

[0035] Substrate 11 is, for example, a semiconductor substrate such as a silicon substrate. Figure 1 In this design, the upper and lower surfaces of the substrate 11 are parallel to the X and Y directions and perpendicular to the Z direction. An interlayer insulating film 12 is disposed on the substrate 11, and an interlayer insulating film 13 is disposed on the interlayer insulating film 12. The interface between the interlayer insulating film 12 and the interlayer insulating film 13 forms part of the bonding surface S. A memory cell array section 14 and a connection section 15 are disposed on the interlayer insulating film 13. Transistors 16 and 17 are disposed on the substrate 11 within the interlayer insulating film 12.

[0036] The memory cell array section 14 includes a laminated film 14a and a laminated film 14b disposed on the laminated film 14a. The memory cell array section 14 (laminated films 14a and 14b) is an example of a first laminated film. Similarly, the connection section 15 includes a laminated film 15a and a laminated film 15b disposed on the laminated film 15a. The connection section 15 (laminated films 15a and 15b) is an example of a second laminated film. Furthermore, the laminated film 15a is an example of a first part, and the laminated film 15b is an example of a second part.

[0037] The laminate 14a includes a plurality of insulating layers 21 and a plurality of electrode layers 22 alternately laminated on an interlayer insulating film 13. The laminate 15a includes a plurality of insulating layers 21 and a plurality of electrode layers 22 alternately laminated on an interlayer insulating film 13, and an insulating film 23 disposed on these insulating layers 21 and electrode layers 22. Laminates 14a and 15a share the same insulating layers 21 and electrode layers 22. The insulating layers 21, electrode layers 22, and insulating films 23 in laminates 14a and 15a are, for example, silicon oxide films, metal layers containing tungsten layers, and silicon oxide films, respectively. These electrode layers 22 include, for example, word lines and source-side select lines.

[0038] The laminate 14b includes an insulating film 24 disposed on the laminate 14a, a plurality of insulating layers 21 alternately laminated on the insulating film 24, and a plurality of electrode layers 22. The laminate 15b includes an insulating film 24 disposed on the laminate 15a, a plurality of insulating layers 21 and a plurality of electrode layers 22 alternately laminated on the insulating film 24, and an insulating film 23 disposed on these insulating films 24, insulating layers 21, and electrode layers 22. The laminates 14b and 15b share the same insulating film 24, insulating layers 21, and electrode layers 22. The insulating layers 21, electrode layers 22, insulating films 23, and insulating films 24 in the laminates 14b and 15b are, for example, silicon oxide films, metal layers containing tungsten layers, silicon oxide films, and silicon oxide films, respectively. These electrode layers 22 include, for example, word lines and drain-side select lines.

[0039] The insulating film 23 within the laminated film 15b has a surface S1 inclined at one angle relative to the upper surface of the substrate 11 and a surface S2 inclined at another angle relative to the upper surface of the substrate 11. These surfaces S1 and S2 are the lower surfaces of the insulating film 23. Since the upper surface of the substrate 11 is parallel to the XY plane, surfaces S1 and S2 are inclined relative to the XY plane. The angle of surface S2 relative to the upper surface of the substrate 11 (e.g., 0.1 to 4 degrees) is set to be smaller than the angle of surface S1 relative to the upper surface of the substrate 11 (e.g., 4.5 to 10 degrees). Therefore, surface S1 is steeply inclined, while surface S2 is gently inclined. The upper end of surface S2 is connected to the lower end of surface S1, and the tangent point (tangent line) between the lower end of surface S1 and the upper end of surface S2 is called the inflection point (inflection line). In this embodiment, the upper and lower surfaces of each electrode layer 22 in the laminated films 14a and 14b are also parallel to the XY plane, and surfaces S1 and S2 are inclined relative to the upper and lower surfaces of each electrode layer 22 in the laminated films 14a and 14b.

[0040] Furthermore, the insulating film 23 within the laminate 15a has a surface S3 that is inclined at a certain angle relative to the upper surface of the substrate 11. This surface S3 is the lower surface of the insulating film 23. Since the upper surface of the substrate 11 is parallel to the XY plane, surface S3 is inclined relative to the XY plane. The angle of surface S3 relative to the upper surface of the substrate 11 is set to be approximately the same as the angle of surface S2 relative to the upper surface of the substrate 11. Therefore, surface S1 is steeply inclined, while surfaces S2 and S3 are gently inclined. Figure 1 The surface S3 shown is approximately located on the extension surface of surface S2. In this embodiment, the upper and lower surfaces of each electrode layer 22 in the laminated films 14a and 14b are also parallel to the XY plane, and surface S3 is inclined relative to the upper and lower surfaces of each electrode layer 22 in the laminated films 14a and 14b.

[0041] In this embodiment, the insulating layer 21 and electrode layer 22 within the connecting portion 15 are disposed beneath these surfaces S1, S2, and S3. Therefore, within the laminated film 15b, the insulating layer 21 and electrode layer 22 beneath surfaces S1 and S2 extend non-parallel to the XY plane. Similarly, within the laminated film 15a, the insulating layer 21 and electrode layer 22 beneath surface S3 extend non-parallel to the XY plane. Surface S1 is an example of a first lower surface, and surfaces S2 and S3 are examples of second lower surfaces. Furthermore, the angle of surface S1 relative to the upper surface of the substrate 11 is an example of a first angle, and the angles of surfaces S2 and S3 relative to the upper surface of the substrate 11 are examples of second angles.

[0042] Within the memory cell array section 14, a plurality of columnar portions 25 are disposed within the insulating layer 21, electrode layer 22, and insulating film 24 of the laminated films 14a and 14b, penetrating the laminated films 14a and 14b. Each columnar portion 25 in this embodiment includes a charge storage layer and a channel semiconductor layer constituting a plurality of memory cells. Each columnar portion 25 in this embodiment includes a portion disposed within the laminated film 14a and a portion disposed within the laminated film 14b.

[0043] Within the connecting portion 15, a plurality of beam portions 26 are disposed within the insulating layer 21, electrode layer 22, insulating film 23, and insulating film 24 of the laminated films 15a and 15b, penetrating the laminated films 15a and 15b. The beam portions 26 are formed, for example, from a silicon oxide film. Each beam portion 26 in this embodiment functions as a beam reinforcing the laminated films 14a, 14b, 15a, and 15b. Each beam portion 26 in this embodiment includes a portion disposed within the laminated film 15a and a portion disposed within the laminated film 15b.

[0044] Each transistor 16 has a gate insulating film 16a and a gate 16b sequentially disposed on a substrate 11, and a source region and a drain region (not shown) disposed within the substrate 11. The transistor 16 is disposed under the memory cell array section 14 and is electrically connected to the columnar section 25 within the memory cell array section 14. The transistor 16 is an example of a first transistor.

[0045] Each transistor 17 includes a gate insulating film 17a and a gate 17b sequentially disposed on a substrate 11, and a source region and a drain region (not shown) disposed within the substrate 11. The transistor 17 is disposed below the memory cell array section 14 and below the connection section 15, and is electrically connected to the electrode layer 22 within the connection section 15. The transistor 17 is an example of a second transistor. In this embodiment, the gate length of the transistor 17 is set to be longer than the gate length of the transistor 16.

[0046] Contact plugs 31, 32, wiring layer 33, via plug 34, wiring layer 35, via plug 36, wiring layer 37, via plug 38, and metal pads 39 are disposed under the memory cell array section 14 within the circuit region 1. Each contact plug 31 and 32 is disposed on the gate 16b, source region, or drain region of the corresponding transistor 16. Wiring layer 33, via plug 34, wiring layer 35, via plug 36, wiring layer 37, via plug 38, and metal pads 39 are sequentially disposed on contact plugs 31 and 32.

[0047] Contact plugs 41, wiring layers 42, via plugs 43, wiring layers 44, via plugs 45, and metal pads 46 are disposed within the circuit region 1, below the memory cell array section 14 and below the connection section 15. Each contact plug 41 is disposed on the gate 17b, source region, or drain region of the corresponding transistor 17. Wiring layers 42, via plugs 43, wiring layers 44, via plugs 45, and metal pads 46 are sequentially disposed on the contact plugs 41.

[0048] Metal pads 51, wiring layers 52, via plugs 53, wiring layers 54, via plugs 55, and wiring layers 56 are disposed under the memory cell array section 14 within the array region 2. Metal pads 51 are disposed on and bonded to metal pads 39. The bonding surfaces of metal pads 39 and 51 form part of the mating surface S. Wiring layers 52, 53, 54, 55, and 56 are sequentially disposed on the metal pads 51. Each wiring within wiring layer 54 functions as a bit line. Each wiring within wiring layer 56 is connected to and electrically connected to a corresponding plurality of columnar portions 25. Thus, the columnar portions 25 are electrically connected to the transistor 16 via the wiring structure shown by reference numerals 31-39 and 51-56. The wiring within wiring layer 56 is an example of the first wiring.

[0049] Metal pad 61, wiring layer 62, via plug 63, wiring layer 64, via plug 65, and wiring layer 66 are disposed below the connection portion 15 within the array region 2. Metal pad 61 is disposed on and bonded to metal pad 46. The bonding surface between metal pad 46 and metal pad 61 forms part of the mating surface S. Wiring layer 62, via plug 63, wiring layer 64, via plug 65, and wiring layer 66 are sequentially disposed on metal pad 61. Each wiring within wiring layer 66 is connected to and electrically connected to a corresponding electrode layer 22. Thus, electrode layer 22 is electrically connected to transistor 17 via the wiring structure shown by reference numerals 41-46 and 61-66. The wiring within wiring layer 66 is an example of a second wiring configuration.

[0050] Figure 1 Routers 66a, 66b, and 66c within routing layer 66 are shown. Router 66a is positioned below surface S1, as shown... Figure 1 As shown, it is electrically connected to transistor 17 disposed under memory cell array section 14. Wiring 66b is disposed under surface S2, as shown... Figure 1 As shown, it is electrically connected to transistor 17 disposed under connection portion 15. Wiring 66c is disposed under surface S3, as shown... Figure 1 As shown, it is electrically connected to the transistor 17 disposed under the connection part 15.

[0051] As will be described later, wiring 66a electrically connects the electrode layer 22 within the laminated film 15b to the transistor 17 under the memory cell array section 14. Figure 4 Additionally, wiring 66b electrically connects the electrode layer 22 within the laminated film 15b to the transistor 17 under the connection portion 15. Figure 4 Additionally, wiring 66c electrically connects the electrode layer 22 within the laminated film 15a to the transistor 17 under the connection portion 15. Figure 4 Further details about this structure will be described later.

[0052] The semiconductor device of this embodiment also includes a wiring layer 71, an insulating film 72, an insulating film 73, an insulating film 74, a via plug 75, a metal pad 76, and an insulating film 77 within the array region 2. The wiring layer 71 and the insulating film 77 are respectively disposed on the memory cell array section 14 and the connection section 15. The insulating films 72, 73, and 74 are sequentially disposed on the wiring layer 71 and the insulating film 77, serving as passivation insulating films. The via plug 75 is disposed within the insulating film 72 on the wiring layer 71. The metal pad 76 is disposed within the insulating films 73 and 74 on the via plug 75, serving as an external connection pad (bonding pad) of the semiconductor device of this embodiment. The metal pad 76 is electrically connected to a plurality of columnar sections 25 within the memory cell array section 14 via the via plug 75 and the wiring layer 71.

[0053] Figure 2 This is another cross-sectional view showing the structure of the semiconductor device according to the first embodiment.

[0054] Figure 2 Show Figure 1 The area shown is approximately twice the size of the area shown. Specifically, Figure 1 A memory cell array section 14 and a connection portion 15 on one side of the memory cell array section 14 are shown. In contrast, Figure 2 A memory cell array section 14 and connection portions 15 on both sides of the memory cell array section 14 are shown. The semiconductor device of this embodiment includes one or more... Figure 2 The structure shown.

[0055] Figure 3 This is a cross-sectional view showing the structure of the columnar portion 25 in the first embodiment.

[0056] Figure 3 The diagram shows a memory cell array 14 that alternately includes multiple insulating layers 21 and multiple electrode layers 22, and a columnar portion 25 disposed within the memory cell array 14. Figure 3As shown, each columnar portion 25 in this embodiment includes a barrier insulating film 25a, a charge storage layer 25b, a tunnel insulating film 25c, a channel semiconductor layer 25d, and a core insulating film 25e, which are sequentially disposed within the storage cell array portion 14.

[0057] The barrier insulating film 25a is, for example, a silicon oxide film. The charge storage layer 25b is, for example, an insulating film such as a silicon nitride film, but it can also be a semiconductor layer such as a polycrystalline silicon layer. The tunnel insulating film 25c is, for example, a silicon oxide film or a silicon oxynitride film. The channel semiconductor layer 25d is, for example, a polycrystalline silicon layer. The core insulating film 25e is, for example, a silicon oxide film.

[0058] Figure 4 This is a cross-sectional view showing the structure of the storage cell array section 14 and the connection section 15 of the first embodiment.

[0059] Figure 4 and Figure 1 Similarly, the memory cell array section 14 and the connection section 15 of this embodiment are shown. However, in order to easily understand the relationship between the electrode layer 22 and the wiring 66a to 66c, Figure 4 Showing quantity ratio Figure 1 Fewer electrode layers 22.

[0060] As described above, wiring layer 66 includes wiring 66a disposed under surface S1, wiring 66b disposed under surface S2, and wiring 66c disposed under surface S3. Wiring 66a is electrically connected to transistor 17 under memory cell array section 14, wiring 66b is electrically connected to transistor 17 under connection section 15, and wiring 66c is electrically connected to transistor 17 under connection section 15. Figure 1 ).

[0061] The semiconductor device of this embodiment has a plurality of perforated plugs 28 disposed within the laminated film 15a of the connection portion 15, separated by an insulating film 27. The perforated plugs 28 are disposed on the wirings 66a and 66b under surfaces S1 and S2. The perforated plugs 28 are examples of the plugs in the first part described above.

[0062] These perforated plugs 28 electrically connect the electrode layer 22 within the laminated film 15b to the wirings 66a, 66b. Specifically, the perforated plugs 28 under surface S1 electrically connect the electrode layer 22 to the wirings 66a, thus electrically connecting the electrode layer 22 to the transistors 17 under the memory cell array section 14. Figure 1 Additionally, the perforated plug 28 under surface S2 electrically connects the electrode layer 22 and the wiring 66b, thus electrically connecting the electrode layer 22 to the transistor 17 under the connection portion 15. Figure 1 On the other hand, since the electrode layer 22 within the laminated film 15a is connected to the wiring 66c, it is electrically connected to the transistor 17 under the connection portion 15 without passing through the through-hole plug 28. Figure 1 In addition, the electrode layer 22 in the memory cell array section 14 is electrically connected to the wiring 66a to 66c via the electrode layer 22 in the connection section 15.

[0063] The following is for reference Figure 1 and Figure 4 Further details of the semiconductor device of this embodiment will be described.

[0064] The connecting portion 15 in this embodiment is provided to facilitate easy electrical connection of the electrode layer 22 to the wirings 66a to 66c. In the connecting portion 15, the electrode layer 22 is provided under the inclined surfaces S1 to S3, and the electrode layer 22 extends non-parallel to the XY plane. Therefore, the electrode layer 22 is exposed on the upper surface of the insulating film 24 or the upper surface of the interlayer insulating film 13, and can be easily connected to the perforated plug 28 or the wiring 66c on these upper surfaces. In addition, the electrode layer 22 electrically connected to the perforated plug 28 is electrically connected to the wirings 66a or 66b via the perforated plug 28.

[0065] To reduce the chip area of ​​the semiconductor device in this embodiment, it is preferable to steepen the inclination of surfaces S1 to S3 within the connection portion 15, thereby reducing the planar shape of the connection portion 15. On the other hand, if the number of electrode layers 22 within the memory cell array portion 14 and the connection portion 15 increases, the number of transistors 17 for the electrode layers 22 needs to be increased. Therefore, it may be difficult to ensure sufficient area on the substrate 11 for arranging these transistors 17. Furthermore, the transistor 17 connected to a wiring within the wiring layer 66 is preferably disposed in the area directly below or near that wiring. This is because it shortens the electrical path for connecting the wiring and the transistor 17.

[0066] Therefore, in the connection portion 15 of this embodiment, the inclination of surface S1 is made steeper, while the inclination of surfaces S2 and S3 is made gentler. As a result, compared to the case where the inclination of surfaces S1 to S3 is the same, the spacing between the wirings 66b and 66c under surfaces S2 and S3 can be ensured to be wider. Therefore, even if the transistors 17 used for wirings 66b and 66c are arranged directly below the wirings 66b and 66c, the area used for arranging these transistors 17 can be sufficiently ensured. As a result, the electrical path for connecting the wirings 66b and 66c and the transistors 17 can be shortened.

[0067] On the other hand, since the spacing between the wirings 66a under surface S1 in this embodiment is narrower, it is difficult to place the transistor 17 for wirings 66a directly below the wirings 66a. Therefore, in this embodiment, the transistor 17 for wirings 66a is placed under the memory cell array section 14 instead of under the connection section 15. This ensures sufficient area for placing the transistor 17 for wirings 66a. Furthermore, since the wirings 66a are placed near the memory cell array section 14, even if the transistor 17 for wirings 66a is placed under the memory cell array section 14, the electrical path connecting the wirings 66a and the transistor 17 can be shortened.

[0068] Thus, according to this embodiment, by making the inclination of surface S1 steeper and the inclination of surfaces S2 and S3 gentler, wiring 66a to 66c and transistor 17 can be appropriately configured.

[0069] Figure 5 is a top view showing the structure of the semiconductor device according to the first embodiment.

[0070] Figure 5A The layout of wiring layer 66 and via plug 65 is shown. Figure 5A In the wiring layer 66, each wiring extends along the Y direction. The wiring 66a closer to the memory cell array section 14 has a thinner width, while the wiring 66b farther away from the memory cell array section 14 has a thicker width. Figure 5A Also shown is a slit ST that extends in the X direction and is disposed within the memory cell array section 14 and the connection section 15.

[0071] Figures 5A to 5D The same area is shown from above. Therefore, Figure 5B The metal pad 61 shown is configured in Figure 5A Directly below the through-hole plug 65 shown. Figure 5C This shows multiple traces within the wiring layer 44 beneath these metal pads 61. Figure 5C Within wiring layer 44, the wiring below the thicker wiring 66b in wiring layer 66 has a straight planar shape, and the wiring below the thinner wiring 66a in wiring layer 66 has an L-shaped planar shape. The former wiring in wiring layer 44 is electrically connected to the corresponding wiring 66b, and the latter wiring in wiring layer 44 is electrically connected to the corresponding wiring 66a. Figure 5D Gate 17b and contact plug 41 are shown. Additionally, Figure 5D The gate 17b shown can also be divided into individual transistors 17 so that individual control can be performed.

[0072] Figure 6 This is a cross-sectional view showing the structure of a semiconductor device according to a modified example of the first embodiment.

[0073] exist Figure 2 In the middle section, the memory cell array section 14 is located in the central section, and two connecting sections 15 sandwich the memory cell array section 14. On the other hand, in Figure 6 In the middle section, the connecting part 15 is located in the central part, and the two memory cell array sections 14 sandwich the connecting part 15. The semiconductor device of this embodiment may also omit this feature. Figure 2 The structure shown is adopted. Figure 6 The structure shown.

[0074] Figure 7 and Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to the first embodiment.

[0075] Figure 7 The diagram shows a circuit wafer W1 comprising multiple circuit regions 1 and an array wafer W2 comprising multiple array regions 2. Reference numeral Sa indicates the upper surface of the circuit wafer W1, and reference numeral Sb indicates the upper surface of the array wafer W2. Figure 7 The orientation of the array wafer W2 shown is... Figure 1 The array regions 2 shown are oriented in opposite directions. The semiconductor device of this embodiment is manufactured by bonding the circuit wafer W1 and the array wafer W2 together. Figure 7 This shows the array wafer W2 being oriented in the direction it was before being flipped for bonding. Figure 1 The diagram shows the array region 2 after being reversed and fitted for bonding, as well as the cut area.

[0076] Array wafer W2 in addition to Figure 1 In addition to the components shown, it also includes a substrate 18 disposed under the memory cell array section 14 and the connection section 15. The substrate 18 is, for example, a semiconductor substrate such as a silicon substrate.

[0077] In this embodiment, firstly, as Figure 7 As shown, an interlayer insulating film 12, transistors 16 and 17, metal pads 39 and 46, etc., are formed on the substrate 11 of the circuit wafer W1. A memory cell array 14, a connection portion 15, a pillar portion 25, a beam portion 26, an interlayer insulating film 13, wiring layers 56 and 66, metal pads 51 and 61, etc., are formed on the substrate 18 of the array wafer W2. The memory cell array 14 is formed to include a laminated film 14b on the substrate 18 and a laminated film 14a on the laminated film 14b. The connection portion 15 is formed to include a laminated film 15b on the substrate 18 and a laminated film 15a on the laminated film 15b.

[0078] Next, as Figure 8As shown, mechanical pressure is used to bond the circuit wafer W1 and the array wafer W2 together. This bonds the interlayer insulating film 12 and the interlayer insulating film 13 together. Further, the circuit wafer W1 and the array wafer W2 are annealed. This bonds the metal pads 39 and 51 together, and the metal pads 46 and 61 together.

[0079] Then, substrate 11 is thinned using CMP (Chemical Mechanical Polishing), and after substrate 18 is removed by CMP, circuit wafer W1 and array wafer W2 are diced into multiple chips. This process manufactures... Figure 1 Semiconductor devices. Additionally... Figure 1 The wiring layer 71, insulating film 72, insulating film 73, insulating film 74, through-hole plug 75, metal pad 76 and insulating film 77 shown are formed on the memory cell array section 14 and the connection section 15, for example, after the substrate 11 is thinned and the substrate 18 is removed.

[0080] Figures 9-14 This is a cross-sectional view showing a method for manufacturing the array wafer W2 according to the first embodiment.

[0081] First, a laminated film 14b, 15b comprising multiple insulating layers 21, multiple sacrificial layers 22', an insulating film 23, and an insulating film 24 is formed on the substrate 18. Figure 9 The sacrificial layer 22' is the layer that replaces the electrode layer 22 in the process described later, for example, a silicon nitride film. The sacrificial layer 22' is an example of the first layer.

[0082] Figure 9 The laminated films 14b and 15b shown are formed, for example, as follows. First, an insulating film 23 is formed on a substrate 18. This insulating film 23 is formed having a surface S1 inclined at one angle relative to the upper surface of the substrate 18 and a surface S2 inclined at another angle relative to the upper surface of the substrate 18. Surfaces S1 and S2 are... Figure 1 The middle part is the lower surface of the insulating film 23, while... Figure 9 The upper surface of the insulating film 23 is located in the middle. The angle of surface S2 relative to the upper surface of the substrate 18 is set to be smaller than the angle of surface S1 relative to the upper surface of the substrate 18. Therefore, surface S1 is steeply inclined, while surface S2 is gently inclined. Next, a plurality of insulating layers 21 and a plurality of sacrificial layers 22' are alternately formed on the substrate 18 with the insulating film 23 in between. As a result, a portion of these insulating layers 21 and sacrificial layers 22' are formed on surfaces S1 and S2. These insulating layers 21 and sacrificial layers 22' are processed to make the upper surfaces of the insulating layers 21 and sacrificial layers 22' nearly flat, and the insulating film 24 is formed on the upper surfaces of the insulating layers 21 and sacrificial layers 22'.

[0083] In this embodiment, the upper and lower surfaces of each sacrificial layer 22' in the laminated film 14b are parallel to the upper surface of the substrate 18, and surfaces S1 and S2 are inclined relative to the upper and lower surfaces of each sacrificial layer 22' in the laminated film 14b.

[0084] Next, multiple pores are formed penetrating the laminated membranes 14b and 15b. Within the pores of the laminated membrane 14b, a portion of a plurality of columnar portions 25 is formed, and within the pores of the laminated membrane 15b, a portion of a plurality of beam portions 26 is formed. Figure 10 The columnar portion 25 within the laminated film 14b is formed by sequentially forming a barrier insulating film 25a, a charge storage layer 25b, a tunnel insulating film 25c, a channel semiconductor layer 25d, and a core insulating film 25e within the pores of the laminated film 14b (see reference). Figure 3 The beam portion 26 within the laminated film 15b is formed by embedding a silicon oxide film within the pores of the laminated film 15b.

[0085] Next, after forming the remaining portion of the insulating film 24 on the substrate 18, laminated films 14a and 15a comprising multiple insulating layers 21, multiple sacrificial layers 22', an insulating film 23, and an insulating film 24 are formed on the laminated films 14b and 15b. Figure 11 These sacrificial layers 22' are also layers that are replaced by electrode layers 22 in processes described later, such as silicon nitride films. These sacrificial layers 22' are also examples of the first layer.

[0086] Figure 11 The laminated films 14a and 15a shown are formed, for example, as follows. First, an insulating film 23 is formed on the laminated films 14b and 15b. This insulating film 23 is formed having a surface S3 that is inclined at a certain angle relative to the upper surface of the substrate 18. Surface S3 is... Figure 1 The middle part is the lower surface of the insulating film 23, while... Figure 11 The upper surface of the insulating film 23 is shown in the middle. The angle of surface S3 relative to the upper surface of the substrate 18 is set to be approximately the same as the angle of surface S2 relative to the upper surface of the substrate 18. Therefore, surface S1 is steeply inclined, while surfaces S2 and S3 are gently inclined. Surface S1 is an example of a first upper surface, and surfaces S2 and S3 are examples of a second upper surface. Next, a plurality of insulating layers 21 and a plurality of sacrificial layers 22' are alternately formed on the laminated films 14b and 15b, separated by the insulating film 23. As a result, a portion of these insulating layers 21 and sacrificial layers 22' are formed on surface S3. These insulating layers 21 and sacrificial layers 22' are processed to make the upper surfaces of the insulating layers 21 and sacrificial layers 22' nearly flat.

[0087] In this embodiment, the upper and lower surfaces of each sacrificial layer 22' in the laminated films 14b and 14a are parallel to the upper surface of the substrate 18, and surfaces S1 to S3 are inclined relative to the upper and lower surfaces of each sacrificial layer 22' in the laminated films 14b and 14a.

[0088] Next, multiple pores penetrating the laminated membranes 14a and 15a are formed. The remaining portions of multiple columnar portions 25 are formed within the pores of the laminated membrane 14a, and the remaining portions of multiple beam portions 26 are formed within the pores of the laminated membrane 15a. Figure 12 The apertures in the laminated film 14a are formed such that they extend to the columnar portions 25 in the laminated film 14b. The apertures in the laminated film 15a are formed such that they extend to the beam portions 26 in the laminated film 15b. The columnar portions 25 in the laminated film 14a are formed on the columnar portions 25 in the laminated film 14b by sequentially forming a barrier insulating film 25a, a charge storage layer 25b, a tunnel insulating film 25c, a channel semiconductor layer 25d, and a core insulating film 25e within the apertures of the laminated film 14a. The beam portions 26 in the laminated film 15a are formed on the beam portions 26 in the laminated film 15b by embedding a silicon oxide film within the apertures of the laminated film 15a. In this way, columnar portions 25 are formed in the laminated films 14b and 14a, and beam portions 26 are formed in the laminated films 15b and 15a.

[0089] Additionally, in this embodiment, it is also possible to... Figure 10 In the process, multiple pores are formed within the 14b and 15b layers of the laminated film. Figure 12 In the process, multiple holes are formed in the laminated films 14a and 15a, and then columnar portions 25 and beam portions 26 are formed in the holes of the laminated films 14b, 14a, 15b, and 15a. Thus, the columnar portions 25 and beam portions 26 in the laminated films 14b and 15b, as well as the columnar portions 25 and beam portions 26 in the laminated films 14a and 15a, can be formed in the same process.

[0090] Alternatively, in this embodiment, a joint may be formed within the insulating film 24 between a portion of the columnar portion 25 and the remaining portion of the columnar portion 25. The joint may, for example, be formed with a diameter larger than the diameter of these portions of the columnar portion 25.

[0091] In addition, Figure 12 In the process, holes for the insulating film 27 and the perforated plug 28 are formed as holes within the laminated film 15a (see reference). Figure 4 The hole is formed in such a way that it reaches the sacrificial layer 22' within the laminated film 15b. The insulating film 27 and the perforated plug 28 are located within... Figure 12 The process involves sequentially forming the hole.

[0092] Next, the sacrificial layer 22' within the stacked films 14b, 14a, 15b, and 15a is replaced with the electrode layer 22. Figure 13 As a result, a stacked film 14b, 14a, 15b, 15a, alternatingly comprising multiple insulating layers 21 and multiple electrode layers 22, is formed on the substrate 18.

[0093] The replacement from the sacrificial layer 22' to the electrode layer 22 is performed as follows: First, a slit (not shown) is formed through the stacked films 14b, 14a or 15b, 15a. Next, the sacrificial layer 22' is removed by wet etching from the slit. Then, by removing the sacrificial layer 22', the electrode layer 22 is formed in the cavity formed between the insulating layers 21. Then, the slit is filled with an insulating film. In this way, the memory cell array portion 14 and the interconnect portion 15 are formed on the substrate 18.

[0094] In addition, Figure 9 and Figure 11 In the process of forming electrode layer 22 without forming sacrificial layer 22', it is not necessary to Figure 13 The replacement during the process. In this case, electrode layer 22 is an example of the first layer.

[0095] Next, an interlayer insulating film 13, wiring layers 56 and 66, metal pads 51 and 61 are formed on the memory cell array section 14 and the connection section 15. Figure 14 In this way, the array wafer W2 of this embodiment is manufactured. Figures 9-14 The process shown is equivalent to Figure 7 An example of the process shown. Then, the array wafer W2 is... Figure 8 In the process shown, it is bonded together with the circuit wafer W1.

[0096] Figure 15 is a top view and a cross-sectional view showing the method of forming the insulating film 23 according to the first embodiment.

[0097] Figure 15A The area on the upper surface of the array wafer W2 is shown, corresponding to a semiconductor device (an array region 2). Figure 15A Multiple storage cell array sections 14 (plane) and multiple connection sections 15 are shown.

[0098] Figure 15B schematically shown in Figure 9 The cross-section of the array wafer W2 when the insulating film 23 is formed on the substrate 18 during the process. Figure 15B The insulating film 23 shown is formed in conjunction with Figure 15A At the position corresponding to the connecting portion 15 shown. Each of the insulating films 23 has surfaces S1, S2, and S2' as its upper surface. Surfaces S1 and S2 are inclined relative to the XY plane, while surface S2' is approximately parallel to the XY plane.

[0099] Figure 15C Showing the formation Figure 15BThe cross-section of the template 3 for the insulating film 23 is shown. The template 3 includes a portion 3a and a portion 3b disposed below the portion 3a, and a plurality of recesses P1 are provided in the portion 3b. Each recess P1 has surfaces T1, T2, T2' with the same area and inclination as surfaces S1, S2, S2' of the insulating film 23. Figure 15C In this design, the upper and lower surfaces of template 3 are parallel to the XY plane. Surfaces T1 and T2 are inclined relative to the upper and lower surfaces of template 3, while surface T2' is approximately parallel to the upper and lower surfaces of template 3. The upper and lower surfaces of template 3 are examples of defined surfaces. Furthermore, surfaces T1, T2, and T2' are examples of the first, second, and third lower surfaces, and the angles of surfaces T1 and T2 relative to the upper and lower surfaces of template 3 are examples of the first and second angles. The angle of surface T2 relative to the XY plane is smaller than the angle of surface T1 relative to the XY plane. The angle of surface T2' relative to the XY plane is approximately 0 degrees.

[0100] Figure 15B Insulating film 23, for example, using Figure 15C The template 3 is formed. Specifically, an insulating film 23 material is coated on the upper surface of the substrate 18, and the template 3 is pressed onto the material to solidify the material entering the recess P1 of the template 3, thereby forming an insulating film 23 having surfaces S1, S2, and S2'. The material in the recess P1 can be solidified by irradiating the material with light or by heating the material. In the former case, the template 3 is formed by a light-transmitting member, and in the latter case, the template 3 is formed by a heat-conducting member. In this embodiment, in order to solidify the material in the recess P1 using light, the template 3 is formed from a quartz substrate.

[0101] Figure 15D schematically shown in Figure 11 The cross-section of the array wafer W2 when the insulating film 23 is formed on the laminated film 15b during the process. Figure 15D The insulating film 23 shown is formed in conjunction with... Figure 15A At the position corresponding to the connecting portion 15 shown. Each of the insulating films 23 has a surface S3 as its upper surface. Surface S3 is inclined relative to the XY plane. In addition, the insulating layer 21 and the sacrificial layer 22' are actually inclined near surfaces S1 and S2 (see reference). Figure 9 (etc.), but Figure 15D For convenience, the illustrations are presented in a straight line without any tilt.

[0102] Figure 15E Showing the formation Figure 15D The diagram shows a cross-section of the template 4 for the insulating film 23. The template 4 includes a portion 4a and a portion 4b disposed below the portion 4a, with a plurality of recesses P2 within the portion 4b. Each recess P2 has a surface T3 with an area and inclination identical to the surface S3 of the insulating film 23. Figure 15EIn the template, the upper and lower surfaces of template 4 are parallel to the XY plane. Surface T3 is inclined relative to the upper and lower surfaces of template 4. The angle of surface T3 relative to the XY plane is approximately the same as the angle of surface T2 relative to the XY plane.

[0103] Figure 15D The insulating film 23, for example, uses Figure 15E Template 4 is formed. Specifically, the material of insulating film 23 is coated on the upper surface of laminated films 14b and 15b, and template 4 is pressed onto this material to solidify the material entering the recess P2 of template 4, thereby forming insulating film 23 with surface S3. The material in the recess P2 can be solidified by irradiating the material with light or by heating the material. In the former case, template 4 is formed by a light-transmitting member, and in the latter case, template 4 is formed by a heat-conducting member. In this embodiment, in order to solidify the material in the recess P2 using light, template 4 is formed from a quartz substrate.

[0104] Figure 16 is another top view and cross-sectional view showing the method of forming the insulating film 23 according to the first embodiment.

[0105] Figure 16A The area on the upper surface of the array wafer W2 that corresponds to the eight semiconductor devices (eight array regions 2) is shown. Figure 16A and Figure 15A Similarly, multiple memory cell array sections 14 (plane) and multiple connection sections 15 are shown. Figure 16A The cutting line L between array regions 2 is also shown in thick lines.

[0106] Figure 16B schematically shown in Figure 9 The cross-section of the array wafer W2 when the insulating film 23 is formed on the substrate 18 during the process. Figure 16B The insulating film 23 shown is formed in conjunction with Figure 16A At the position corresponding to the connecting part 15 shown. Figure 16B In the middle, the insulating film 23 is disposed on the cutting line L.

[0107] Figure 16C Showing the formation Figure 16B The cross-section of the template 3 of the insulating film 23 shown. Figure 16C A cross-section of the template 3 as a whole is shown. The template 3 of this embodiment can simultaneously form insulating films 23 for eight array regions 2. The same applies to the template 4.

[0108] Figure 17 This is another top view showing the method of forming the insulating film 23 according to the first embodiment.

[0109] Figure 17The planar shape of the insulating film 23 formed on the substrate 18 by repeatedly using templates 3 and 4 is shown. In this embodiment, a plurality of insulating films 23 are formed on the substrate 18 that are adjacent to each other in the X direction and extend in the Y direction.

[0110] Figures 18 and 19 are another cross-sectional view showing the method of forming the insulating film 23 according to the first embodiment.

[0111] First, an insulating film 23 is coated on the upper surface of the substrate 18. Figure 18A Next, after pressing the template 3 onto the material, the material entering the recess P1 of the template 3 is cured. Figure 18B Next, demold template 3 from the material. Figure 18C In this way, an insulating film 23 with surfaces S1, S2, and S2' is formed.

[0112] Next, after the above... Figure 9 and Figure 10 After the process, the material of insulating film 23 is coated on the upper surface of laminated films 14b and 15b. Figure 19A Next, after pressing the template 4 onto the material, the material entering the recess P2 of the template 4 is cured. Figure 19B Next, demold template 4 from the material. Figure 19C In this way, an insulating film 23 having a surface S3 is formed on an insulating film 23 having surfaces S1, S2, and S2'. Furthermore, the insulating layer 21 and the sacrificial layer 22' are actually inclined near surfaces S1 and S2 (see reference). Figure 9 (etc.), but Figures 19A-19C For convenience, the diagram is shown without any tilt.

[0113] Figures 20A-20D This is a cross-sectional view showing a method for forming the insulating film 23 according to a modified example of the first embodiment.

[0114] Figure 20A Showing the formation Figure 15B The cross-section of the template 5 for the insulating film 23 is shown. The template 5 includes a portion 5a and a portion 5b disposed below the portion 5a, and a plurality of recesses P3 are provided in the portion 5b. Each recess P3 has surfaces U1, U2, U2' with the same area and inclination as surfaces S1, S2, S2' of the insulating film 23. Figure 20AIn this design, the upper and lower surfaces of template 5 are parallel to the XY plane. Surfaces U1 and U2 are inclined relative to the upper and lower surfaces of template 5, while surface U2' is approximately parallel to the upper and lower surfaces of template 5. The upper and lower surfaces of template 5 are examples of defined surfaces. Furthermore, surfaces U1, U2, and U2' are examples of the first, second, and third lower surfaces, and the angles of surfaces U1 and U2 relative to the upper and lower surfaces of template 5 are examples of the first and second angles. The angle of surface U2 relative to the XY plane is smaller than the angle of surface U1 relative to the XY plane. The angle of surface U2' relative to the XY plane is approximately 0 degrees.

[0115] Figure 20B schematically shown in Figure 9 The cross-section of the array wafer W2 during the formation of the insulating film 23 on the substrate 18 in the process. In this modified example, the template 5 is used to form the insulating film 23 by inkjet printing. Specifically, the template 5 is placed on the substrate 18, and the material of the insulating film 23 is sprayed into the space (i.e., the recess P3) surrounded by the upper surface of the substrate 18 and the surfaces U1, U2, and U2' of the template 5, so that the material in the recess P3 is cured, thereby forming the insulating film 23 having surfaces S1, S2, and S2'. Figure 20C The material within the recess P3 can be cured by irradiating it with light or by heating it. In the former case, the template 5 is formed of a light-transmitting member, while in the latter case, the template 5 is formed of a heat-conducting member. In this modified example, in order to use light to cure the material within the recess P3, the template 5 is formed of a quartz substrate.

[0116] Figure 20D Showing the formation Figure 15D The cross-section of the template 6 for the insulating film 23 is shown. The template 6 includes a portion 6a and a portion 6b disposed below the portion 6a, and a plurality of recesses P4 are provided within the portion 6b. Each recess P4 has a surface U3 with the same area and inclination as surface S3 of the insulating film 23. Figure 20D In the template, the upper surface and bottom edge of template 6 are parallel to the XY plane. Surface U3 is inclined relative to the upper surface and bottom edge of template 6. The angle of surface U3 relative to the XY plane is approximately the same as the angle of surface U2 relative to the XY plane.

[0117] In this modified example, template 6, like template 5, is used to form the insulating film 23 by inkjet printing. Therefore, template 6 is formed, for example, by a light-transmitting member or a heat-conducting member. In this modified example, in order to use light to cure the material within the recess P4, template 6 is formed from a quartz substrate.

[0118] Figures 21A-21E These are top and cross-sectional views showing a method for forming the insulating film 23, which is another variation of the first embodiment.

[0119] Figures 21A-21ECorresponding to Figures 15A-15E . Figures 15A-15E The method shown is, for example, in forming a structure containing two Figure 2 The insulating film 23 of the semiconductor device with the structure shown is used. On the other hand, Figures 21A-21E The method shown is, for example, in forming a structure containing two Figure 6 The insulating film 23 of the semiconductor device with the structure shown is used.

[0120] As described above, the connecting portion 15 of this embodiment includes an insulating film 23, which has a steeply inclined surface S1 and gently inclined surfaces S2 and S3. Therefore, according to this embodiment, the insulating layer 21 and electrode layer 22 of the laminated films 15a and 15b can be provided on the inclined surfaces, i.e., surfaces S1, S2, and S3, which have appropriate shapes. For example, the inclination of surface S1 is steep, and the inclination of surfaces S2 and S3 is gentle, thereby allowing for the appropriate arrangement of wirings 66a to 66c and transistors 17.

[0121] (Second Implementation)

[0122] Figure 22 This is a cross-sectional view showing an example of the shape of template 3 in the second embodiment.

[0123] Figure 22 Template 3 is the same as template 3 described in the first embodiment, and can be used in... Figure 18B It is used in the process. Figure 22 The template 3 includes a portion 3a and a portion 3b disposed below the portion 3a, and the portion 3b has a recess P1.

[0124] The recess P1 has surfaces T1, T2, T2' with the same area and inclination as the surfaces S1, S2, S2' of the insulating film 23. Figure 22 In this design, the upper and lower surfaces of template 3 are parallel to the XY plane. Surface T1 is inclined at an angle θ1 relative to the upper and lower surfaces of template 3, and surface T2 is inclined at an angle θ2 smaller than θ1 relative to the upper and lower surfaces of template 3. On the other hand, surface T2' is approximately parallel to the upper and lower surfaces of template 3, and the angle of surface T2' relative to the XY plane is approximately 0 degrees. The upper and lower surfaces of template 3 are examples of defined surfaces. Furthermore, surfaces T1, T2, and T2' are examples of the first, second, and third lower surfaces, and angles θ1 and θ2 are examples of the first and second angles.

[0125] Figures 23-25 ​​illustrate... Figure 22 A cross-sectional view of the manufacturing method of template 3.

[0126] First, prepare the substrate for template 3 ( Figure 23AIn this embodiment, the template 3 is manufactured by etching the substrate. Hereinafter, the substrate will be referred to as "substrate 3". Substrate 3 is, for example, a transparent substrate such as a quartz substrate.

[0127] Next, after cleaning the substrate 3, a mask 81 and a resist film 82 are sequentially formed on the substrate 3. Figure 23A Mask 81 is, for example, a hard mask such as silicon oxide (SiO2). Mask 81 can be formed by any method capable of uniformly forming mask 81 on substrate 3, such as by sputtering, CVD (Chemical Vapor Deposition), PVD (Physical Vapor Deposition), ALD (Atomic Layer Deposition), LPD (Liquid Phase Deposition), or vapor deposition. Mask 81 is an example of a first film. The resist film 82 is formed, for example, by coating it onto the upper surface of mask 81 using a coating machine.

[0128] Next, a pattern is formed on the resist film 82 by photolithography and etching, and the mask 81 is processed by dry etching using the resist film 82 as a mask. Figure 23B As a result, an opening H1 is formed within the mask 81, exposing the upper surface of the substrate 3 within the opening H1. On the other hand, the mask 81 remains on region R1 of the substrate 3. Region R1 is an example of a first region. The photolithography of the resist film 82 is performed, for example, using an EB (Electron Beam) device. Alternatively, the mask 81 can also be processed by wet etching instead of dry etching.

[0129] Next, after removing the resist film 82 from the substrate 3, mask 83 and mask 84 are sequentially formed on the substrate 3 and mask 81. Figure 24A Mask 83 is, for example, a hard mask such as a silicon oxide film or a TEOS (tetraethyl orthosilicate) film doped with impurity atoms. Mask 84 is, for example, a hard mask containing a metal element or an organic compound. Examples of such metal elements are platinum group elements such as chromium (Cr), molybdenum (Mo), tungsten (W), gold (Au), silver (Ag), or platinum (Pt). In this embodiment, mask 84 is a chromium film with a thickness of about 100 nm. In order not to change the quality of masks 81 and 83, it is preferable that the formation temperature of mask 84 is lower than that of masks 81 and 83. Masks 83 and 84 can be formed, for example, by sputtering, CVD, PVD, ALD, LPD, or vapor deposition. Masks 83 and 84 are examples of the second and third films, respectively.

[0130] Next, a resist film 85 is formed on the mask 84. Figure 24BThe resist film 85 is formed, for example, by applying it to the upper surface of the mask 84 using a coating machine.

[0131] Next, a pattern is formed on the resist film 85 by photolithography and etching, and the mask 84 is processed by dry etching using the resist film 85 as a mask. Figure 24B As a result, an opening H2 is formed within the mask 84, and the upper surface of the mask 83 is exposed within the opening H2. On the other hand, the mask 83 remains on regions R1, R2, and R3 of the substrate 3, and the mask 84 remains on regions R1 and R2 of the substrate 3. Regions R2 and R3 are examples of the second and third regions, respectively. The photolithography of the resist film 85 is performed, for example, using an EB device. Alternatively, the mask 84 can also be processed by wet etching instead of dry etching.

[0132] Next, after removing the mask 83 inside the opening H2 (on region R3), the substrate 3 is processed starting from region R3 by wet etching using masks 81, 83, and 84 as masks. Figure 25A This wet etching is performed, for example, using a solution (etching solution) containing HF (hydrogen fluoride). Additionally, the mask 83 within the opening H2 can be... Figure 24B If the etching using the aforementioned solution is uniform, then it can also be removed by dry etching in the process. Figure 25A The process involves wet etching to remove the material.

[0133] Figure 25A The wet etching process is performed, for example, using a solution that allows the etching rate of mask 83 to be greater than that of mask 81 and substrate 3. In this case, the wet etching is used to process substrate 3, masks 81 and 83 into... Figure 25A The substrate 3, masks 81 and 83 are further processed in the manner shown in the diagram. Figure 25B The shape shown is used in this manner. Figure 25A In the substrate 3, a recess P1 with surfaces T2 and T2' as its upper surface is formed in regions R2 and R3. Figure 25B In, with Figure 25A In comparison, the heights of surfaces T2 and T2' are reduced, and a recess P1 with surfaces T1, T2, and T2' as upper surfaces is formed in regions R1, R2, and R3 of substrate 3. That is, in Figure 25A The recess P1 formed in regions R2 and R3 is in Figure 25B The extension extends to region R1.

[0134] Figure 25A and Figure 25B The area and inclination of surfaces T1, T2, and T2' shown are related to... Figure 22 The same as shown. In Figure 25A and Figure 25BIn this design, the upper and lower surfaces of substrate 3 are parallel to the XY plane. Surface T1 is inclined at an angle θ1 relative to the upper and lower surfaces of substrate 3, and surface T2 is inclined at an angle θ2 less than θ1 relative to the upper and lower surfaces of substrate 3. On the other hand, surface T2' is approximately parallel to the upper and lower surfaces of substrate 3, and the angle of surface T2' relative to the XY plane is approximately 0 degrees. The upper and lower surfaces of substrate 3 are examples of defined surfaces. Furthermore, surfaces T1, T2, and T2' are examples of a first surface, a second surface, and a third upper surface, and angles θ1 and θ2 are examples of a first angle and a second angle.

[0135] Figure 25A The lateral penetration amount of the solution can be controlled by the etching rate of the mask 83. For example, when the etching rate of the mask 83 is 5 times that of the substrate 3, the angle θ2 is approximately 11 degrees. Furthermore, when the etching rate of the mask 83 is 10 times that of the substrate 3, the angle θ2 is approximately 5 degrees. In this embodiment, the solution is, for example, a 10% dilute HF aqueous solution, and the substrate 3 is processed such that the length of the surface T2 in the X direction is 8 μm. Alternatively, the solution in this embodiment can also be a mixed aqueous solution containing 30% NH4F (ammonium fluoride), 6% HF, and a surfactant, thereby enabling the formation of a surface T2 with good smoothness.

[0136] When the etching of substrate 3 and mask 83 is performed, such as Figure 25A As shown, mask 81 is exposed within the recess P1. Then, the etching rate of mask 81 determines the angle θ1 of surface T1. Figure 25B In this process, substrate 3 is fabricated such that the length of surface T1 in the X direction is 1 μm.

[0137] Then, masks 81, 83, and 84 are removed from substrate 3. In this way, a product is manufactured from substrate 3. Figure 22 Template 3.

[0138] Furthermore, the method of this embodiment can also be applied to the case where the angle θ2 is greater than the angle θ1 of the template 3. In addition, the method of this embodiment can be applied not only to the case where a recess P1 with two inclined surfaces (T1, T2) is formed in the template 3, but also to the case where a recess with three or more inclined surfaces is formed in the template 3.

[0139] Figure 26 This is a cross-sectional view showing another example of the shape of template 3 in the second embodiment.

[0140] Figure 26 Template 3 is the same as template 3 described in the first embodiment, and can be used in... Figure 18B It is used in the process. Figure 26The template 3 includes a portion 3a and a portion 3b disposed below the portion 3a, and the portion 3b has a recess P1.

[0141] The recess P1 has surfaces T1, T2, T2' with the same area and inclination as the surfaces S1, S2, S2' of the insulating film 23. Figure 26 In this design, the upper and lower surfaces of template 3 are parallel to the XY plane. Surface T1 is inclined at an angle θ1 relative to the upper and lower surfaces of template 3, and surface T2 is inclined at an angle θ2 smaller than θ1 relative to the upper and lower surfaces of template 3. On the other hand, surface T2' is approximately parallel to the upper and lower surfaces of template 3, and the angle of surface T2' relative to the XY plane is approximately 0 degrees. The upper and lower surfaces of template 3 are examples of defined surfaces. Furthermore, surfaces T1, T2, and T2' are examples of the first surface, the second surface, and the third lower surface, and angles θ1 and θ2 are examples of the first and second angles.

[0142] Figures 27A to 29B It is shown Figure 26 A cross-sectional view of the manufacturing method of template 3. Figures 27A to 29B In the explanation, the omission of and Figures 23A to 25B Explanation of the same items.

[0143] First, prepare the substrate for template 3 ( Figure 27A Hereinafter, this substrate will be referred to as "substrate 3".

[0144] Next, after cleaning the substrate 3, a mask 83 and a resist film 86 are sequentially formed on the substrate 3. Figure 27A Mask 83 is, for example, a hard mask such as a silicon oxide film or a TEOS (tetraethyl orthosilicate) film doped with impurity atoms. Mask 83 is an example of a second film. The resist film 86 is formed, for example, by coating it onto the upper surface of mask 83 using a coating machine.

[0145] Next, a pattern is formed on the resist film 86 by photolithography and etching, and the mask 83 is processed by dry etching using the resist film 86 as a mask. Figure 27B As a result, an opening H3 is formed within the mask 83, exposing the upper surface of the substrate 3 within the opening H3. The photolithography of the resist film 86 is performed, for example, using an EB apparatus. Alternatively, the mask 83 can be processed using wet etching instead of dry etching.

[0146] Next, after removing the resist film 86 from the substrate 3, a mask 81 and a mask 84 are sequentially formed on the substrate 3 and the mask 83. Figure 28A Mask 81 is, for example, a hard mask such as a silicon oxide film. Mask 84 is, for example, a hard mask containing a metallic element or an organic compound. Examples of such metallic elements are platinum group elements such as chromium, molybdenum, tungsten, gold, silver, or platinum. Masks 81 and 84 are examples of the first and third films, respectively.

[0147] Next, a resist film 87 is formed on the mask 84. Figure 28B The resist film 87 is formed, for example, by applying it to the upper surface of the mask 84 using a coating machine.

[0148] Next, a pattern is formed on the resist film 87 by photolithography and etching, and the masks 84 and 81 are processed by dry etching using the resist film 87 as a mask. Figure 28B As a result, an opening H4 is formed within masks 84 and 81, and the upper surface of mask 83 is exposed within the opening H4. On the other hand, mask 81 remains on regions R1 and R2 of substrate 3, mask 83 remains on regions R2 and R3 of substrate 3, and mask 84 remains on regions R1 and R2 of substrate 3. Regions R1, R2, and R3 are examples of the first region, the second region, and the third region, respectively. Photolithography of the resist film 87 is performed, for example, using an EB apparatus. Alternatively, masks 84 and 81 can be processed by wet etching instead of dry etching.

[0149] Next, after removing the mask 83 within the opening H4 (on region R3), the substrate 3 is processed from region R3 by wet etching using masks 81, 83, and 84 as masks. Figure 29A This wet etching is performed, for example, using a solution (etching solution) containing HF. Additionally, the mask 83 within the opening H4 can be... Figure 28B If the etching using the aforementioned solution is uniform, then it can also be removed by dry etching in the process. Figure 29A The process involves wet etching to remove the material.

[0150] Figure 29A The wet etching process is performed, for example, using a solution that allows the etching rate of mask 83 to be greater than that of mask 81 and substrate 3. In this case, the wet etching is used to process substrate 3, masks 81 and 83 into... Figure 29A The substrate 3, masks 81 and 83 are further processed in the manner shown in the diagram. Figure 29B The shape shown is used in this manner. Figure 29A In the substrate 3, a recess P1 with surfaces T2 and T2' as its upper surface is formed in regions R2 and R3. Figure 29B In, with Figure 29A In comparison, the heights of surfaces T2 and T2' are reduced, and a recess P1 with surfaces T1, T2, and T2' as upper surfaces is formed in regions R1, R2, and R3 of substrate 3. That is, in Figure 29A The recess P1 formed in regions R2 and R3 is in Figure 29B The extension extends to region R1.

[0151] Figure 29Aand Figure 29B The area and inclination of surfaces T1, T2, and T2' shown are related to... Figure 26 The same as shown. In Figure 29A and Figure 29B In this design, the upper and lower surfaces of substrate 3 are parallel to the XY plane. Surface T1 is inclined at an angle θ1 relative to the upper and lower surfaces of substrate 3, and surface T2 is inclined at an angle θ2 less than θ1 relative to the upper and lower surfaces of substrate 3. On the other hand, surface T2' is approximately parallel to the upper and lower surfaces of substrate 3, and the angle of surface T2' relative to the XY plane is approximately 0 degrees. The upper and lower surfaces of substrate 3 are examples of defined surfaces. Furthermore, surfaces T1, T2, and T2' are examples of a first upper surface, a second upper surface, and a third upper surface, and angles θ1 and θ2 are examples of a first angle and a second angle.

[0152] Figure 29A The lateral immersion amount of the drug solution can be controlled by the etching rate of mask 83. When the substrate 3 and mask 83 are being etched, as... Figure 29A As shown, the interface between the substrate and the mask 81 is exposed within the recess P1. Then, the etching rate of the mask 81 determines the angle θ1 of the surface T1.

[0153] Then, masks 81, 83, and 84 are removed from substrate 3. In this way, a product is manufactured from substrate 3. Figure 26 Template 3.

[0154] Figure 30 This is a cross-sectional view showing another example of the shape of template 3 in the second embodiment.

[0155] Figure 30 The shape of template 3 and Figure 22 The shape of template 3 is similar, but Figure 30 In addition to surfaces T1, T2, and T2', the recess P1 also has surface T1'. Surface T1' is positioned such that the upper end of surface T1' connects with the lower end of surface T1. Surface T1' is inclined relative to the upper and lower surfaces of template 3 at an angle θ1' less than angle θ1. In this way, the recess P1 of template 3 can also have more than three inclined surfaces.

[0156] As described above, in this embodiment, the substrate 3 is processed by using masks 81, 83, and 84 as masks, and the template 3 is manufactured from the substrate 3. Therefore, according to this embodiment, it is possible to manufacture a template 3 having surfaces T1 and T2.

[0157] Alternatively, embodiments of the present invention may also be implemented in the following manner.

[0158] (Note 1)

[0159] A method for manufacturing a semiconductor device, comprising:

[0160] A first laminate and a second laminate, alternately comprising multiple insulating layers and multiple first layers, are formed on a substrate; and

[0161] A plurality of columnar portions, including a charge storage layer and a semiconductor layer, are formed within the insulating layer and the first layer of the first laminated film.

[0162] The second layer of film is formed in the following manner:

[0163] An insulating film having a first upper surface and a second upper surface is formed on the substrate. The first upper surface is inclined at a first angle relative to the upper surface of one of the first layers in the first laminated film, and the second upper surface is inclined at a second angle less than the first angle relative to the upper surface of one of the first layers in the first laminated film.

[0164] The insulating layer and the first layer of the second laminated film are alternately formed on the first and second upper surfaces of the insulating film.

[0165] (Note 2)

[0166] The method for manufacturing a semiconductor device according to Appendix 1 further includes:

[0167] Prepare a template having a first lower surface and a second lower surface, the first lower surface being inclined at a first angle relative to a predetermined surface, and the second lower surface being inclined at a second angle relative to the predetermined surface; and

[0168] The insulating film having the first upper surface and the second upper surface is formed on the substrate by pressing the template onto the material of the insulating film.

[0169] (Note 3)

[0170] The method for manufacturing a semiconductor device according to Appendix 1 further includes:

[0171] Prepare a template having a first lower surface and a second lower surface, the first lower surface being inclined at a first angle relative to a predetermined surface, and the second lower surface being inclined at a second angle relative to the predetermined surface; and

[0172] The insulating film having the first upper surface and the second upper surface is formed on the substrate by spraying the material of the insulating film into the space surrounded by the upper surface of the substrate, the first lower surface and the second lower surface of the template.

[0173] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A template for setting an insulating layer of a semiconductor device on an inclined surface, the template being formed of a quartz substrate. The template has: A first lower surface, the first lower surface being inclined at a first angle relative to a predetermined surface; and The second lower surface is inclined at a second angle less than the first angle relative to the specified surface.

2. The template according to claim 1, wherein, The specified surface is the upper or lower surface of the quartz substrate.

3. The template according to claim 1, wherein, The upper end of the second lower surface is connected to the lower end of the first lower surface, and the point of tangency between the upper end and the lower end is an inflection point.

4. The template according to claim 1, wherein, The template also has a third lower surface, the angle of which relative to the specified surface is smaller than the second angle.

5. The template according to claim 1, wherein, The first angle is 4.5 to 10 degrees.

6. The template according to claim 1, wherein, The second angle is 0.1 to 4 degrees.

7. A method for manufacturing a template, comprising: Prepare the substrate for the template; A first film is formed on at least a first region of the substrate; A second film is formed on at least a second region of the substrate; A third film is formed on at least the first region and the second region of the substrate; Using the first film, the second film, and the third film as masks, the substrate is processed from a third region of the substrate, thereby forming a first upper surface inclined at a first angle relative to a predetermined surface in the first region, and a second upper surface inclined at a second angle smaller than the first angle relative to the predetermined surface in the second region.

8. The method for manufacturing a template according to claim 7, wherein, By processing the substrate from the third region, a third upper surface with an angle smaller than the second angle relative to the specified surface is also formed in the third region.

9. The method for manufacturing a template according to claim 7, wherein, The first membrane contains silicon, the second membrane contains silicon, and the third membrane contains a metal element or an organic compound.

10. The method for manufacturing a template according to claim 7, wherein, The substrate is processed using an etching solution that allows the etching rate of the second film to be greater than that of the first film and the substrate.

11. The method for manufacturing a template according to claim 7, wherein, The first film, the second film, and the third film are formed on the substrate in the order of the first film, the second film, and the third film.

12. The method for manufacturing a template according to claim 7, wherein, The first film, the second film, and the third film are formed on the substrate in the order of the second film, the first film, and the third film.

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