Memory device

Abstract

A memory device is provided. The memory device includes: a semiconductor layer; a first wiring layer arranged apart from the semiconductor layer in a first direction; a plurality of second wiring layers each arranged apart from the first wiring layer in the first direction and located on an opposite side of the semiconductor layer from the first wiring layer; a plurality of memory pillars each extending in the first direction and in contact with the semiconductor layer, portions of the plurality of second wiring layers each intersecting the plurality of memory pillars functioning as memory cells; and a member extending in a first plane including the first direction and a second direction intersecting the first direction and intersecting the first wiring layer and the plurality of second wiring layers in a third direction intersecting the first and second directions. The member includes: a filler extending in the first plane and having both ends of the first direction on a side of the plurality of second wiring layers than on a side of the first wiring layer of the semiconductor layer; and an insulating member disposed between the filler and the semiconductor layer, the first wiring layer, and each of the plurality of second wiring layers, the insulating member having a lower thermal conductivity than the filler.

Description

Technical Field

[0001] The implementation involves storage devices. Background Technology

[0002] NAND flash memory is a known type of storage device capable of storing data non-volatilely. NAND flash memory employs a three-dimensional storage structure for high integration and large capacity. Summary of the Invention

[0003] This improves the yield rate of storage devices.

[0004] The memory device according to the embodiment includes: a semiconductor layer; a first wiring layer arranged separately from the semiconductor layer in a first direction without being separated by other wiring layers; a plurality of second wiring layers located on the side opposite to the semiconductor layer relative to the first wiring layer, each arranged separately in the first direction; a plurality of memory pillars extending in the first direction and connected to the semiconductor layer, the portions intersecting with each of the plurality of second wiring layers functioning as memory cells; and a member extending in a first surface including the first direction and a second direction intersecting the first direction, and cutting off the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first direction and the second direction. The aforementioned component includes a filler and an insulating member. The filler extends within the first surface on the side of the semiconductor layer relative to the first wiring layer, and the insulating member is disposed between the filler and the semiconductor layer, the first wiring layer, and each of the plurality of second wiring layers, and has a lower thermal conductivity than the filler. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating an example of the configuration of a storage system including the storage device according to the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the memory device according to the first embodiment.

[0007] Figure 3 This is a top view showing an example of the planar layout of the memory cell array included in the memory device according to the first embodiment.

[0008] Figure 4 This refers to the memory cell array included in the memory device according to the first embodiment. Figure 3 A top view of an example of the plan layout of area IV.

[0009] Figure 5This is an example of a cross-sectional structure of the memory cell array included in the memory device according to the first embodiment, along... Figure 4 A cross-sectional view of the VV line.

[0010] Figure 6 This is an example of the cross-sectional structure of the memory pillars included in the memory device according to the first embodiment, along... Figure 5 A cross-sectional view of the VI-VI line.

[0011] Figure 7 This is a perspective view showing the outline of the bonding structure of the storage device according to the first embodiment.

[0012] Figure 8 This is a cross-sectional view showing an example of the cross-sectional structure of the bonding pads provided in the storage device according to the first embodiment.

[0013] Figure 9 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment.

[0014] Figure 10 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0015] Figure 11 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0016] Figure 12 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0017] Figure 13 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0018] Figure 14 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0019] Figure 15 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0020] Figure 16 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0021] Figure 17 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0022] Figure 18This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment during manufacturing.

[0023] Figure 19 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to a variation of the first embodiment.

[0024] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the second embodiment.

[0025] Figure 21 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the second embodiment during manufacturing.

[0026] Figure 22 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the second embodiment during manufacturing.

[0027] Figure 23 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the second embodiment during manufacturing.

[0028] Figure 24 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the second embodiment during manufacturing.

[0029] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the first modification of the second embodiment.

[0030] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the second modification of the second embodiment.

[0031] Figure 27 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the third embodiment.

[0032] Figure 28 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the third embodiment during manufacturing.

[0033] Figure 29 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the third embodiment during manufacturing.

[0034] Figure 30 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the third embodiment during manufacturing.

[0035] Figure 31This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the third embodiment during manufacturing.

[0036] Figure 32 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the third embodiment during manufacturing.

[0037] Figure 33 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the first modification of the third embodiment.

[0038] Figure 34 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the second variation of the third embodiment.

[0039] Figure 35 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the third modification of the third embodiment.

[0040] Figure 36 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the fourth variation of the third embodiment.

[0041] Figure 37 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fourth embodiment.

[0042] Figure 38 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the fourth embodiment during manufacturing.

[0043] Figure 39 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the fourth embodiment during manufacturing.

[0044] Figure 40 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to a variation of the fourth embodiment.

[0045] Label Explanation

[0046] 1…Storage System

[0047] 2… Storage Controller

[0048] 3… Storage devices

[0049] 10… Storage cell array

[0050] 11…Instruction Register

[0051] 12… Address Register

[0052] 13… Sequencer

[0053] 14…Driver Module

[0054] 15…line decoder module

[0055] 16…Sense Amplifier Module

[0056] 21, 22, 23, 24… Wiring layers

[0057] 21a, 21b, 25, 26, 27, 62, 63, 64, 65… Conductor layers

[0058] 30…protective layer

[0059] 31, 32, 33, 34, 35, 36, 61, 71, 73… Insulating layers

[0060] 37, 38, 39… Stop membrane

[0061] 41…core membrane

[0062] 42… Semiconductor film

[0063] 43…Laminated film

[0064] 44…Tunnel insulation film

[0065] 45…charge storage membrane

[0066] 46…blocks of insulating film

[0067] 51, 52, 53… Insulating film

[0068] 60, 70…Substrate

[0069] 74, 75, 76... Sacrificial layer

[0070] 77…Sacrificial membrane

[0071] 100…memory chip

[0072] 200…circuit chip Detailed Implementation

[0073] The embodiments will now be described with reference to the accompanying drawings. The dimensions and scale of the drawings may not be the same as those in reality.

[0074] Furthermore, in the following description, constituent elements that have substantially the same function and structure are labeled with the same number. When it is necessary to specifically distinguish between elements with the same structure, sometimes different characters or numbers are appended to the end of the same number.

[0075] 1. First Implementation Method

[0076] 1.1 Composition

[0077] 1.1.1 Composition of the storage system

[0078] Figure 1 This is a block diagram illustrating an example of the configuration of a storage system including the storage device according to the first embodiment. Storage system 1 is a storage device configured to connect to an external host (not shown). Storage system 1 is, for example, an SD card. TM Storage systems include memory cards (like memory cards), UFS (universal flash storage), and SSDs (solid state drives). Storage system 1 includes a storage controller 2 and storage devices 3.

[0079] The storage controller 2 is, for example, an integrated circuit such as a system-on-a-chip (SoC). The storage controller 2 controls the storage device 3 based on requests from the host. Specifically, for example, the storage controller 2 writes data requested to be written from the host to the storage device 3. Additionally, the storage controller 2 reads data requested to be read from the host from the storage device 3 and sends it to the host.

[0080] Storage device 3 is non-volatile memory. Storage device 3 is, for example, NAND flash memory. Storage device 3 stores data non-volatilely.

[0081] Communication between the storage controller 2 and the storage device 3 follows, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0082] 1.1.2 Structure of Storage Devices

[0083] Next, refer to Figure 1 The block diagram shown illustrates the internal structure of the memory device according to the first embodiment. The memory device 3 includes, for example, a memory cell array 10, an instruction register 11, an address register 12, a sequencer 13, a driver module 14, a line decoder module 15, and a sense amplifier module 16.

[0084] The memory cell array 10 includes multiple blocks BLK0 to BLKn (n is an integer greater than or equal to 1). The number of blocks BLK included in the memory cell array 10 can also be one. A block BLK is a collection of multiple memory cells. A block BLK is used, for example, as a unit for data erasure. Furthermore, the memory cell array 10 is provided with multiple bit lines and multiple word lines. Each memory cell is associated with, for example, one bit line and one word line. A detailed description of the configuration of the memory cell array 10 is given below.

[0085] Instruction register 11 stores the instructions CMD received by storage device 3 from storage controller 2. Instructions CMD include, for example, commands that cause sequencer 13 to perform read operations, write operations, erase operations, etc.

[0086] Address register 12 stores the address information ADD received by storage device 3 from storage controller 2. The address information ADD includes, for example, block address BAd, page address PAd, and column address CAd. For example, block address BAd, page address PAd, and column address CAd are used for the selection of block BLK, word line, and bit line, respectively.

[0087] The sequencer 13 controls the overall operation of the storage device 3. For example, the sequencer 13 controls the driver module 14, the line decoder module 15, and the sense amplifier module 16, etc., based on the instruction CMD stored in the instruction register 11 to perform read operations, write operations, erase operations, etc.

[0088] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Furthermore, the driver module 14 applies the generated voltage to the signal line corresponding to the selected word line, for example, based on the page address PAd stored in the address register 12.

[0089] The row decoder module 15 selects a block BLK within the corresponding memory cell array 10 based on the block address BAd stored in the address register 12. Furthermore, the row decoder module 15, for example, transmits the voltage applied to the signal line corresponding to the selected word line to the selected word line within the selected block BLK.

[0090] During the write operation, the sensing amplifier module 16 applies the desired voltage to each bit line based on the write data DAT received from the memory controller 2. Furthermore, during the read operation, the sensing amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit lines and transmits the determination result as read data DAT to the memory controller 2.

[0091] 1.1.3 Storage Cell Array

[0092] Next, the configuration of the memory cell array included in the memory device according to the first embodiment will be described.

[0093] 1.1.3.1 Circuit Structure

[0094] Figure 2 This is a circuit diagram illustrating an example of the circuit configuration of the memory cell array included in the memory device according to the first embodiment. Figure 2 The image shows one block BLK among the multiple block BLKs contained in the storage cell array 10. For example... Figure 2 As shown, block BLK includes, for example, four string units SU0 to SU3.

[0095] Each string cell SU includes multiple NAND strings NS associated with bit lines BL0 to BLm (where m is an integer greater than or equal to 1). The number of bit lines BL can also be one. Each NAND string NS includes, for example, memory cell transistors MT0 to MT7, and select transistors ST1 and ST2. Each memory cell transistor MT includes a control gate and a charge storage film, storing data non-volatilely. Select transistors ST1 and ST2 are used to select the string cell SU during various operations.

[0096] In each NAND string NS, memory cell transistors MT0 to MT7 are connected in series. The drain of selector transistor ST1 is connected to the associated bit line BL. The source of selector transistor ST1 is connected to one end of the series-connected memory cell transistors MT0 to MT7. The drain of selector transistor ST2 is connected to the other end of the series-connected memory cell transistors MT0 to MT7. The source of selector transistor ST2 is connected to the source line SL.

[0097] Within the same memory block (BLK), the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of selection transistors ST1 within serial cells SU0 to SU3 are connected to selection gate lines SGD0 to SGD3, respectively. The gates of multiple selection transistors ST2 are connected to selection gate line SGS.

[0098] Bit lines BL0 to BLm are assigned different column addresses. Each bit line BL is shared by the NAND string NS, which is assigned the same column address, across multiple BLK blocks. Word lines WL0 to WL7 are each set for each BLK block. Source lines SL are shared, for example, across multiple BLK blocks.

[0099] A collection of multiple memory cell transistors MT connected to a common word line WL within a single string cell SU is called a cell group CU. For example, the storage capacity of a cell group CU, which includes memory cell transistors MT that each store 1 bit of data, is defined as "1 page of data". A cell group CU can have a storage capacity of more than 2 pages of data, corresponding to the number of bits of data stored by the memory cell transistors MT.

[0100] Furthermore, the circuit configuration of the memory cell array 10 included in the memory device 3 according to the first embodiment is not limited to the configuration described above. For example, the number of string cells SU included in each BLK can be designed to be arbitrary. The number of memory cell transistors MT and selection transistors ST1 and ST2 included in each NAND string NS can also be designed to be arbitrary.

[0101] 1.1.3.2 Floor Plan

[0102] Figure 3 This is a top view showing an example of the planar layout of the memory cell array included in the memory device according to the first embodiment. Figure 3 The example shown is four blocks BLK0 to BLK3 of the multiple blocks BLK in the storage cell array 10.

[0103] The memory cell array 10 includes a stacked wiring structure. The stacked wiring structure is a structure formed by stacking wiring layers (word lines WL0 to WL7, and select gate lines SGD and SGS).

[0104] Hereinafter, the plane that is approximately parallel to the stack-up plane of the wiring layer is designated as the XY plane. Directions orthogonal to each other within the XY plane are designated as the X direction and the Y direction. Furthermore, the direction approximately perpendicular to the XY plane and extending from the select gate line SGS towards the select gate line SGD is designated as the Z1 direction. The direction approximately perpendicular to the XY plane and extending from the select gate line SGD towards the select gate line SGS is designated as the Z2 direction. Without specifying either the Z1 or Z2 direction, it is denoted as the Z direction.

[0105] like Figure 3 As shown, the stacked wiring structure has memory regions MRa and MRb arranged in the X direction, and a lead-out region HR. Memory regions MRa and MRb are areas where memory cell transistors MT are disposed. The lead-out region HR is an area where contacts that electrically connect each wiring layer to the line decoder module 15 are disposed. The lead-out region HR is, for example, located between memory regions MRa and MRb.

[0106] Each of the multiple block BLKs includes a portion extending in the X direction that traverses the storage region MRa, the lead-out region HR, and the storage region MRb in the stacked wiring structure. The multiple block BLKs are arranged in the Y direction. The storage cell array 10 includes, for example, multiple components SLT and multiple components SHE.

[0107] For example, although in Figure 3Illustrations are omitted, but each component SLT has a structure in which a plate-shaped filler LI is embedded within a plate-shaped insulating element SP. Each component SLT extends in the X direction, traversing the memory region MRa, the lead-out region HR, and the memory region MRb. Multiple component SLTs are arranged in the Y direction. Each component SLT truncates the wiring layer adjacent to it. In the memory cell array 10, each region divided by a component SLT corresponds to one block BLK.

[0108] Each component SHE is, for example, a plate-shaped insulator. The multiple component SHEs include multiple component SHEs arranged in the Y direction within the storage region MRa and multiple component SHEs arranged in the Y direction within the storage region MRb. Each component SHE located in the storage region MRa extends in the X direction traversing the storage region MRa. Each component SHE located in the storage region MRb extends in the X direction traversing the storage region MRb.

[0109] exist Figure 3 In the example, in each of the memory regions MRa and MRb, three components SHE are arranged between two adjacent components SLT in the Y direction. Each component SHE has, for example, a structure with embedded insulator. Each component SHE cuts off the select gate line SGD in the wiring layer adjacent to that component SHE. In the memory cell array 10, each region divided by a group of adjacent components SLT and SHE, or a group of two adjacent components SHE, corresponds to one string cell SU.

[0110] Furthermore, the planar layout of the storage cell array 10 can also be other layouts. For example, the number of components SHEs configured between two adjacent components SLT can be designed to be arbitrary. The number of string cells SU in each BLK can be varied based on the number of components SHEs configured between two adjacent components SLT.

[0111] Figure 4 This refers to the memory cell array included in the memory device according to the first embodiment. Figure 3 A top view of an example of the plan layout in region IV. Figure 4 The image shows a portion of the storage region MRb within block BLK0. Furthermore, in... Figure 4 Although the illustration is omitted, the storage region MRa has the same structure as the storage region MRb.

[0112] like Figure 4 As shown, the memory cell array 10 includes multiple memory pillars MP, multiple contacts CV, and multiple bit lines BL in the memory region MR.

[0113] Each memory column (MP) functions as a NAND string (NS). Multiple memory columns (MPs) are arranged in an alternating pattern of, for example, 19 columns in the area between two adjacent components (SLTs). For example, one component (SHE) is arranged overlappingly in each of the memory columns (5th, 10th, and 15th columns counting from the top of the paper).

[0114] Multiple bit lines BL each extend in the Y direction and are arranged in the X direction. Each bit line BL is configured to overlap with at least one memory column MP per string unit SU. Figure 4 In the example, two bit lines BL are arranged overlappingly in one memory column MP. The memory column MP is electrically connected to one of the multiple overlapping bit lines BL via a contact CV. On the other hand, the contact CV between the memory column MP and the bit line BL, which is arranged overlappingly with the component SHE (i.e., connected to two different select gate lines SGD), can be omitted.

[0115] Furthermore, the planar layout within the memory region (MR) can also be other layouts. For example, the number and arrangement of memory cylinders (MPs) and / or components (SHEs) positioned between two adjacent components (SLTs) can be appropriately varied. The number of bit lines (BLs) overlapping each memory cylinder (MP) can be designed to be arbitrary.

[0116] 1.1.3.3 Cross-sectional structure

[0117] Figure 5 This is an example of a cross-sectional structure of the memory cell array included in the memory device according to the first embodiment, along... Figure 4 A cross-sectional view of the VV line. In Figure 5 The YZ cross-sectional structure of the storage region MR is shown in the figure.

[0118] like Figure 5 As shown, the memory cell array 10 includes, for example, wiring layers 21, 22, 23, and 24, a conductive layer 25, and insulating layers 31, 32, 33, 34, 35, and 36. Insulating layers 31, 32, 33, 34, 35, and 36, for example, comprise silicon oxide. Figure 5 In the middle, the Z1 direction corresponds to the top of the paper.

[0119] A wiring layer 21 is provided on the insulating layer 31. The wiring layer 21 is formed, for example, as a plate extending in the XY plane. The wiring layer 21 is used as a source line SL. The wiring layer 21 includes conductor layers 21a and 21b, and semiconductor layers 21c and 21d. The Z2 direction side surfaces of the conductors 21a and 21b, and the semiconductor layer 21c are formed to have unevenness in the region that overlaps with the memory pillar MP and the component SLT when viewed from the Z direction.

[0120] A conductive layer 21a is disposed on the Z1-direction side of the insulating layer 31. The conductive layer 21a has a recessed shape in the Z2 direction in the region including the portion overlapping with the storage pillar MP and the component SLT when viewed from the Z direction. The conductive layer 21a contains, for example, tungsten, and functions to reduce the resistance value of the source line SL.

[0121] A conductive layer 21b is disposed on the Z1-direction side of the conductive layer 21a. The conductive layer 21b has a shape that is recessed in the Z2 direction in the region including the portion overlapping with the storage pillar MP and the component SLT when viewed from the Z direction. The conductive layer 21b contains, for example, titanium nitride and is used as a barrier metal.

[0122] Semiconductor layer 21c is disposed on the Z1-direction side of conductive layer 21b. Semiconductor layer 21c has a Z2-direction recessed shape in the region including the portion overlapping with the memory pillar MP and the component SLT when viewed from the Z direction. Semiconductor layer 21c covers the Z2-direction side end of the semiconductor film 42 of the memory pillar MP (described later) and the Z2-direction side end of the insulating film 52 of the component SLT (described later). Semiconductor layer 21c, for example, comprises polycrystalline silicon.

[0123] Semiconductor layer 21d is disposed on the Z1 direction side of semiconductor layer 21c. Semiconductor layer 21d is formed, for example, as a plate extending in the XY plane. Semiconductor layer 21d contains, for example, polysilicon.

[0124] An insulating layer 32 is formed on the Z1-direction side of the semiconductor layer 21d. A wiring layer 22 is formed on the Z1-direction side of the insulating layer 32. The wiring layer 22 is formed, for example, as a plate extending in the XY plane. The wiring layer 22 contains, for example, tungsten or molybdenum and is used as a select gate line (SGS).

[0125] Multiple insulating layers 33 and wiring layers 23 are alternately disposed on the Z1 direction side of the wiring layer 22. The multiple wiring layers 23 are formed, for example, as plates extending in the XY plane. The multiple wiring layers 23 contain, for example, tungsten or molybdenum, and are used as word lines WL0 to WL7 sequentially from the wiring layer 21 side.

[0126] An insulating layer 34 is provided on the Z1 direction side surface of the uppermost wiring layer 23. A wiring layer 24 is provided on the Z1 direction side surface of the insulating layer 34. The wiring layer 24 is formed, for example, as a plate extending in the XY plane. The wiring layer 24 contains, for example, tungsten or molybdenum and is used as a select gate line (SGD). An insulating layer 35 is provided on the Z1 direction side surface of the wiring layer 24.

[0127] Each of the plurality of memory pillars MP extends in the Z direction, penetrating wiring layers 22-24 and insulating layers 32-34. Each of the plurality of memory pillars MP includes, for example, a core film 41, a semiconductor film 42, and a laminated film 43. The core film 41 is an insulator extending in the Z direction. The semiconductor film 42 covers the core film 41. The Z2-direction side end of the semiconductor film 42 is in contact with the semiconductor layer 21c. The laminated film 43 covers the side surface of the semiconductor film 42, except for the Z2-direction side end. The Z2-direction side end face of the laminated film 43 is, for example, aligned with the Z2-direction side face of the semiconductor layer 21d.

[0128] Figure 6 This is an example of the cross-sectional structure of the memory pillars included in the memory device according to the first embodiment, along... Figure 5 A cross-sectional view of the VI-VI line. Figure 6 The image shows a cross-section including the storage pillar MP and wiring layer 23, parallel to the XY plane. (See image for details.) Figure 6 As shown, the laminated membrane 43 includes, for example, a tunnel insulating membrane 44, a charge storage membrane 45, and a block insulating membrane 46.

[0129] The core film 41 is disposed, for example, in the central portion of the memory pillar MP. Viewed from the Z-direction, the semiconductor film 42 surrounds the core film 41. Viewed from the Z-direction, the tunnel insulating film 44 surrounds the semiconductor film 42. Viewed from the Z-direction, the charge storage film 45 surrounds the tunnel insulating film 44. Viewed from the Z-direction, the block insulating film 46 surrounds the charge storage film 45. Viewed from the Z-direction, the wiring layer 23 surrounds the block insulating film 46. The semiconductor film 42 is used as the channel (current path) for the memory cell transistors MT0 to MT7 and the selection transistors ST1 and ST2. The tunnel insulating film 44 and the block insulating film 46 each contain, for example, silicon oxide. The charge storage film 45 contains, for example, silicon nitride.

[0130] With the above configuration, each memory pillar MP functions as a NAND string NS. Specifically, the portion where memory pillar MP intersects with wiring layer 22 functions as selection transistor ST2. The portion where memory pillar MP intersects with wiring layer 23 functions as memory cell transistor MT. The portion where memory pillar MP intersects with wiring layer 24 functions as selection transistor ST1.

[0131] A contact CV is provided on the Z1 direction side surface of the semiconductor film 42 in the storage column MP. A conductive layer 25 is provided on the Z1 direction side surface of the contact CV. The conductive layer 25 is formed, for example, as a line extending in the Y direction. The conductive layer 25 contains, for example, copper and is used as a bit line BL. An insulating layer 36 is provided on the Z1 direction side surface of the conductive layer 25. The layer on which the conductive layer 25 is provided is also referred to as layer M0.

[0132] The filler LI is a plate-shaped component extending in the XZ plane. The filler LI has a higher thermal conductivity and Young's modulus than the insulator SP. The filler LI contains, for example, tungsten or polysilicon. The filler LI intersects with wiring layers 23 and 24, and insulating layers 33-35. The end face of the filler LI in the Z2 direction is located closer to the Z1 direction side than the Z2 direction side face of the wiring layer 22.

[0133] The insulating element SP includes insulating films 51 and 52. Insulating film 51 is an insulator covering the side surface and the end face in the Z2 direction of the filler LI. Insulating film 51 has a portion (bottom) extending in the Z direction beyond the filler LI in the Z2 direction. The bottom of insulating film 51, for example, reaches the semiconductor layer 21c. Insulating film 52 is disposed such that it covers the bottom of insulating film 51 in the Z2 direction. Insulating films 51 and 52, for example, contain silicon oxide. When the filler LI is conductive, insulating films 51 and 52 electrically insulate the filler LI from each of the wiring layers 22-24.

[0134] In the component SLT composed of the filler LI and the insulating member SP as described above, the width b in the Y direction of the component SLT is more than twice the film thickness a of the portion of the insulating film 51 covering the side of the filler LI. The distance c from the end face of the insulating member SP in the Z2 direction to the end face of the filler LI in the Z2 direction is greater than the film thickness a of the insulating film 51.

[0135] 1.1.4 Structure of Storage Devices

[0136] Next, the structure of the storage device according to the first embodiment will be described.

[0137] 1.1.4.1 Adhesion Structure

[0138] Figure 7 This is a perspective view showing the outline of the bonding structure of the storage device according to the first embodiment. (As shown) Figure 7 As shown, the storage device 3 includes a storage chip 100 and a circuit chip 200. The storage chip 100 includes structures corresponding to the storage cell array 10. The circuit chip 200 includes, for example, structures corresponding to the instruction register 11, the address register 12, the sequencer 13, the driver module 14, the line decoder module 15, and the sense amplifier module 16.

[0139] In addition, the memory chip 100 and the circuit chip 200 each include multiple bonding pads BP. The memory device 3 is formed by bonding the memory chip 100 and the circuit chip 200 together using the multiple bonding pads BP.

[0140] 1.1.4.2 Bonding Pads

[0141] Figure 8 This is a cross-sectional view showing an example of the cross-sectional structure of the bonding pads provided in the storage device according to the first embodiment. Figure 8 In the example, the bonding pads BP of the memory chip 100 and the circuit chip 200 at the bonding surface are shown, as well as the contacts connected to each bonding pad BP.

[0142] like Figure 8 As shown, in the bonding process, the bonding pad BP of the memory chip 100 is connected to the bonding pad BP of the circuit chip 200. Figure 8 In the example, the bonding pads BP of the memory chip 100 and the circuit chip 200 at the bonding surface are approximately equal in area. In this case, when copper is used for the bonding pads BP, the copper of the bonding pads BP of the memory chip 100 and the copper of the bonding pads BP of the circuit chip 200 become integrated, making it difficult to determine the copper boundaries between them. However, bonding can be confirmed by the shape deformation caused by the positional offset of the bonding pads BP and the positional offset of the copper blocking metal (discontinuities appearing on the sides).

[0143] Furthermore, when the bonding pads BP are formed by the inlay method, they have a tapered shape on each side. Therefore, in the cross-sectional shape along the Z direction, the portion where the bonding pads BP are joined together has a non-rectangular shape with non-straight sidewalls.

[0144] Furthermore, when the bonding pads (BP) are bonded together, the bottom, side, and top surfaces of the copper forming them are covered with a barrier metal. In contrast, in typical wiring layers using copper, an insulating layer (such as silicon nitride or silicon carbonitride) is placed on the top surface of the copper to prevent oxidation, without a barrier metal. Therefore, even without bonding position misalignment, it can be distinguished from typical wiring layers.

[0145] 1.1.4.3 Cross-sectional structure

[0146] Figure 9 This is a cross-sectional view showing an example of the cross-sectional structure of the storage device according to the first embodiment. Figure 9 In the middle, the Z2 direction corresponds to the top of the paper.

[0147] like Figure 9 As shown, the memory device 3 in the memory chip 100 further includes conductive layers 26 and 27, a protective layer 30, and contacts V0 and V1. The memory device 3 in the circuit chip 200 includes a substrate 60, an insulating layer 61, conductive layers 62, 63, 64 and 65, a transistor TR, and contacts CS, C1, C2, C3 and C4.

[0148] First, let's explain the memory chip 100.

[0149] A protective layer 30 is disposed on the Z2 direction side of the insulating layer 31. The protective layer 30 is a layer corresponding to the surface of the storage device 3, and may contain, for example, a resin material such as polyimide. In an area not shown, a portion of the protective layer 30 is removed. Furthermore, power pads responsible for electrical connections to the outside are provided in the portion where the protective layer 30 has been removed.

[0150] A contact V0 is provided on the Z1 direction side of the conductive layer 25. A conductive layer 26 is provided on the Z1 direction side of the contact V0.

[0151] A contact V1 is provided on the Z1 direction side of the conductive layer 26. A conductive layer 27 is provided on the Z1 direction side of the contact V1. The conductive layer 27 functions as a bonding pad BP at the bonding surface of the memory chip 100 and the circuit chip 200. The conductive layers 26 and 27, as well as the contacts V0 and V1, are covered by an insulating layer 36. The layers on which the conductive layers 26 and 27 are provided are also referred to as layer M1 and bonding layer B1, respectively.

[0152] Next, the circuit chip 200 will be described.

[0153] The substrate 60 is a silicon substrate. An insulating layer 61 is disposed on the Z2 direction side of the substrate 60. A transistor TR is disposed on the substrate 60 and the insulating layer 61.

[0154] Transistor TR is a structure that constitutes various circuits disposed on circuit chip 200. Figure 9 In the example, transistor TR corresponds to a circuit connected to bit line BL (e.g., a transistor within sense amplifier module 16).

[0155] A contact C1 is provided on the Z2-direction side surface of the gate electrode of the transistor TR. A contact CS is provided on the Z2-direction side surface of the substrate 50, which serves as the source or drain of the transistor TR. A conductive layer 62 is provided on the Z2-direction side surfaces of both contacts CS and C1. The contacts CS and C1, and the conductive layer 62, contain, for example, tungsten.

[0156] A contact C2 is provided on the Z2-direction side surface of conductive layer 62. A conductive layer 63 is provided on the Z2-direction side surface of contact C2. A contact C3 is provided on the Z2-direction side surface of conductive layer 63. A conductive layer 64 is provided on the Z2-direction side surface of contact C3. A contact C4 is provided on the Z2-direction side surface of conductive layer 64. A conductive layer 65 is provided on the Z2-direction side surface of contact C4. Conductive layer 65 is connected to the corresponding conductive layer 27 and functions as a bonding pad BP in the bonding surface of circuit chip 200 and memory chip 100. Conductive layers 62, 63, 64 and 65, and contacts CS, C1, C2, C3 and C4 are covered by insulating layer 61. The layers on which conductive layers 62, 63, 64 and 65 are provided are also referred to as layers D0, D1, D2 and bonding layer B2, respectively.

[0157] 1.2 Manufacturing Method

[0158] Figures 10-18 This is a diagram illustrating an example of the structure during the manufacturing process of the storage device according to the first embodiment. Wherein, Figures 10-15 This is a cross-sectional view of the memory cell array 10 in the memory chip 100 during the manufacturing process before bonding, and... Figure 5 correspond. Figures 16-18 This is a cross-sectional view of the assembled memory chip 100 and circuit chip 200 during the manufacturing process. Figure 9 correspond.

[0159] The memory chip 100 and the circuit chip 200 are manufactured independently. The following focuses on the manufacturing method of the memory chip 100.

[0160] First, such as Figure 10 As shown, an insulating layer 71 is provided on the Z1 direction side surface of the substrate 70. The substrate 70 is the substrate of the memory chip 100, and may contain silicon, for example. The insulating layer 71 may contain silicon oxide, for example.

[0161] A semiconductor layer 72 is disposed on the Z1 direction side surface of the insulating layer 71. An insulating layer 73 is disposed on the Z1 direction side surface of the semiconductor layer 72. A semiconductor layer 21d is disposed on the Z1 direction side surface of the insulating layer 73. The semiconductor layer 72 comprises, for example, polysilicon. The insulating layer 73 comprises, for example, silicon oxide.

[0162] Furthermore, a stacked structure corresponding to the stacked wiring structure is provided on the Z1 direction side of the semiconductor layer 21d. Specifically, an insulating layer 32 and a sacrificial layer 74 are disposed in this order on the Z1 direction side surface of the semiconductor layer 21d. An insulating layer 33 and a sacrificial layer 75 are alternately stacked on the Z1 direction side surface of the sacrificial layer 74. An insulating layer 34 and a sacrificial layer 76 are disposed in this order on the Z1 direction side surface of the uppermost sacrificial layer 75. An insulating layer 35 is disposed on the Z1 direction side surface of the sacrificial layer 76. The sacrificial layers 74 and 76, for example, contain silicon nitride.

[0163] Next, as Figure 11 As shown, multiple holes (not shown) are formed in a predetermined area of ​​the storage pillar MP in the stacked structure. The bottom surfaces of the multiple holes, for example, reach the semiconductor layer 72. Furthermore, a stacked film 43, a semiconductor film 42, and a core film 41 are formed in this order within each hole, and each hole is filled. Thus, a structure corresponding to the storage pillar MP is formed. In the structure corresponding to the storage pillar MP, the stacked film 43 covers the Z2 direction end of the semiconductor film 42.

[0164] Next, as Figure 12 As shown, a trench SH1 is formed in a predetermined area where the component SLT is set. The bottom surface of the trench SH1 reaches, for example, the semiconductor layer 72. Furthermore, a displacement process of the stacked structure is performed via the trench SH1.

[0165] In the replacement process of the stacked structure, sacrificial layers 74, 75, and 76 are selectively removed via trench SH1 by wet etching based on hot phosphoric acid or the like. Conductors are then buried in the space left after removing sacrificial layers 74, 75, and 76 via trench SH1. Subsequently, the conductors formed inside trench SH1 are removed by a back-etching process. Thus, the conductors formed inside trench SH1 are separated into multiple conductor layers. This forms a wiring layer 22 that functions as a select gate line (SGS), multiple wiring layers 23 that function as word lines (WL), and a wiring layer 24 that functions as a select gate line (SGD). The wiring layers 22, 23, and 24 formed in this process may also include a barrier metal. In this case, in the formation of the conductors after removing sacrificial layers 74, 75, and 76, for example, tungsten is formed after titanium nitride is deposited as a barrier metal.

[0166] Next, as Figure 13 As shown, in the tank SH1, the insulating film 52 and the sacrificial film 77 are formed in this order, and the tank SH1 is filled. The sacrificial film 77 contains, for example, SOC (spin-on carbon).

[0167] Next, as Figure 14As shown, a groove SH2 is formed, for example, in a predetermined area where the component SLT is set. Specifically, firstly, a portion of the sacrificial film 77 is etched back, leaving a portion corresponding to the bottom of the insulating film 51. Then, the insulating film 52 is removed until it reaches approximately the same height as the Z1 direction side of the sacrificial film 77 remaining after the etch-back treatment. Afterward, the groove SH2 is formed by removing the sacrificial film 77 remaining after the etch-back treatment.

[0168] Inside the slot SH2, at least a portion of the wiring layer 24 and the wiring layer 23 are exposed. The wiring layer 22 may be partially exposed, but preferably not completely exposed. That is, on the Z1 side of the insulating film 52 remaining on the Z2 side of the slot SH2, it is preferably located on the Z1 side of the wiring layer 22.

[0169] Next, as Figure 15 As shown, the insulating film 51 and the filler LI are formed in the groove SH2 in this order, and the groove SH2 is filled. The width of the groove SH2 at the remaining height of the insulating film 52 is less than twice the film thickness a of the insulating film 51. Therefore, the portion of the groove SH2 at the remaining height of the insulating film 52 is closed by the insulating film 51. Conversely, the width b of the portion of the groove SH2 on the Z1 direction side of the insulating film 52 is greater than twice the film thickness a of the insulating film 51. Therefore, the portion of the groove SH2 on the Z1 direction side of the insulating film 52 is not closed by the insulating film 51. Furthermore, the portion of the groove SH2 not closed by the insulating film 51 is filled by the filler LI. Through the above, the component SLT is formed.

[0170] Afterwards, the components SHE and the structure on the Z1 direction side of the stacked wiring structure are formed, and the manufacturing of the memory chip 100 is completed.

[0171] Next, as Figure 16 As shown, the memory chip 100 and the circuit chip 200 are bonded together.

[0172] Next, as Figure 17 As shown, substrate 70, insulating layer 71, and semiconductor layer 72 are removed. Furthermore, the portion of insulating layer 73 and the laminated film 43 that is closer to the semiconductor layer 21d in the Z2 direction is removed. This exposes the portion of semiconductor film 42 that is closer to the semiconductor layer 21d in the Z2 direction. Additionally, during the removal of insulating layer 73 and laminated film 43, the portion of insulating film 52 that is closer to the semiconductor layer 21d in the Z2 direction is also partially removed.

[0173] Next, as Figure 18As shown, a semiconductor is disposed such that it covers a semiconductor layer 21d, a semiconductor film 42, and an insulating film 52. The semiconductor may include, for example, amorphous silicon. After film formation, impurities such as arsenic are implanted into the semiconductor. Furthermore, the semiconductor is heated and crystallized, for example, by laser annealing. Thus, a conductive semiconductor layer 21c is formed.

[0174] Conductor layers 21b and 21a are stacked in this order on the Z2 direction side of semiconductor layer 21c. Thus, wiring layer 21, which functions as source line SL, is formed.

[0175] Next, an insulating layer 31 and a protective layer 30 are formed on the side of the wiring layer 21 in the Z2 direction. Through the above, the storage device 3 is formed.

[0176] 1.3 Effects of the first embodiment

[0177] According to the first embodiment, the yield of the storage device 3 can be improved. This effect will be explained below.

[0178] The filler LI extends in the XZ plane, closer to the side of the multiple wiring layers 23 than the semiconductor layer 21d side of the wiring layer 22. An insulating member SP is disposed between the filler LI and the semiconductor layer 21d, the wiring layer 22, each of the multiple wiring layers 23, and the wiring layer 24, and has a lower thermal conductivity than the filler LI. Therefore, an insulating member SP of sufficient thickness can be positioned between the filler LI and the semiconductor layer 21c. Thus, when the semiconductor layer 21c is heated by laser annealing, the situation where heat is absorbed by the filler LI, which has a relatively high thermal conductivity, preventing the semiconductor layer 21c near the component SLT from sufficiently crystallizing can be suppressed. Therefore, the characteristic degradation of the wiring layer 21 near the component SLT can be suppressed.

[0179] Furthermore, the length b in the Y direction of the component SLT is twice the length a of the portion between the filler LI in the insulating member SP (insulator film 51) and each of the multiple wiring layers 23. The length c in the Z direction of the portion of the insulating member SP closer to the semiconductor layer 21d than the filler LI is longer than the length a. Thus, the film thickness of the insulating member SP closer to the semiconductor layer 21d than the filler LI is intentionally greater than the film thickness of the insulating member SP at the side of the filler LI. As a result, the amount of heat transferred to the filler LI during the laser annealing process can be reduced. Therefore, the crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0180] Furthermore, the filler LI has a higher Young's modulus than the insulator SP. Therefore, compared to the case where the component SLT is composed solely of the insulator SP, the flexural strength of the memory cell array 10 can be improved.

[0181] 1.4 Variations of the first embodiment

[0182] Various modifications can be applied to the first embodiment described above.

[0183] In the first embodiment described above, the case where the insulating member SP is formed of two insulating films 51 and 52 has been explained, but it is not limited to this. The insulating member SP may also be formed of a single insulating film.

[0184] Figure 19 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to a variation of the first embodiment. Figure 19 Compared with the first embodiment Figure 5 correspond.

[0185] like Figure 19 As shown, in a variation of the first embodiment, the insulating member SP replaces the insulating films 51 and 52, and includes the insulating film 53.

[0186] The insulating film 53 is an insulator covering the side surface of the filler LI and its end face in the Z2 direction. The insulating film 53 has a portion (bottom) extending in the Z direction beyond the filler LI in the Z2 direction. The bottom of the insulating film 53 is thicker than the portion covering the side surface of the filler LI by film thickness a, and reaches the semiconductor layer 21c. The insulating film 53 contains, for example, silicon oxide. When the filler LI is conductive, the insulating film 53 electrically insulates the filler LI from each of the wiring layers 22-24.

[0187] In the component SLT formed by the aforementioned filler LI and insulating member SP, the width b in the Y direction of component SLT is more than twice the film thickness a of the portion of insulating film 53 covering the side of filler LI. The distance c from the end face of insulating member SP in the Z2 direction to the end face of filler LI in the Z2 direction is greater than the film thickness a of the portion of insulating film 53 on the Z1 direction side compared to the bottom.

[0188] Such an insulating film 53 can be achieved by using a film-forming process (bottom-up filling process) in which the thickness of the film formed on the bottom surface of the groove SH1 is greater than that of the film formed on the side surface.

[0189] In the configuration described above, similar to the first embodiment, the thickness of the insulating member SP on the semiconductor layer 21d side of the filler LI can be intentionally made greater than the thickness of the insulating member SP on the side of the filler LI. This reduces the amount of heat transferred to the filler LI during laser annealing. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0190] 2. Second Implementation Method

[0191] Next, the storage device according to the second embodiment will be described. In the second embodiment, unlike the first embodiment, the wiring layer 21 is not reached at the Z2 direction end of the component SLT. In the following description, the configuration and manufacturing method that differ from the first embodiment will be mainly described. Configurations and manufacturing methods that are equivalent to those in the first embodiment will be omitted as appropriate.

[0192] 2.1 Composition

[0193] Figure 20 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the second embodiment. Figure 20 Compared with the first embodiment Figure 5 correspond.

[0194] like Figure 20 As shown, in the second embodiment, the storage cell array 10 further includes a stop membrane 37.

[0195] The Z2 direction end of the component SLT does not reach the wiring layer 21. Therefore, the regions of each of the conductor layers 21a and 21b and the semiconductor layer 21c, including the portion overlapping with the component SLT when viewed from the Z direction, have a flat shape. On the other hand, in the region overlapping with the memory pillar MP when viewed from the Z direction, the Z2 direction surface of the conductor layers 21a and 21b and the semiconductor layer 21c is also topographically formed with unevenness, similar to the first embodiment.

[0196] A stop film 37 is formed on the entire surface of the semiconductor layer 21d along the Z1 direction. The stop film 37 functions to hinder etching during the formation of the groove corresponding to the component SLT. The stop film 37 is, for example, an insulator comprising at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 37 has a different film type than the insulating layer 32.

[0197] An insulating layer 32 is provided on the Z1 direction side of the stop film 37. The structure on the Z1 direction side of the insulating layer 32 is the same as in the first embodiment.

[0198] The filler LI intersects with wiring layers 23 and 24, and insulating layers 33-35. The filler LI may or may not intersect with wiring layer 22.

[0199] The insulating element SP covers the side surface of the filler LI and the end face of the Z2 direction side. The end of the insulating element SP on the Z2 direction side is located within the stop film 37.

[0200] 2.2 Manufacturing Method

[0201] Figure 21 , Figure 22 , Figure 23 as well as Figure 24 This is a diagram illustrating an example of the structure during the manufacturing process of the storage device according to the second embodiment. Figure 21 , Figure 22 , Figure 23 as well as Figure 24 This is a cross-sectional view of the memory cell array 10 in the memory chip 100 during manufacturing, and... Figure 20 correspond.

[0202] First, such as Figure 21 As shown, on the Z1 direction side of the substrate 70, the insulating layer 71, the semiconductor layer 72, the insulating layer 73, the semiconductor layer 21d, and the stop film 37 are arranged in this order.

[0203] Furthermore, a stacked structure corresponding to the stacked wiring structure is provided on the Z1 direction side of the stop film 37. Specifically, an insulating layer 32 and a sacrificial layer 74 are provided in this order on the Z1 direction side of the stop film 37. An insulating layer 33 and a sacrificial layer 75 are alternately stacked on the Z1 direction side of the sacrificial layer 74. An insulating layer 34 and a sacrificial layer 76 are provided in this order on the Z1 direction side of the uppermost sacrificial layer 75. An insulating layer 35 is provided on the Z1 direction side of the sacrificial layer 76.

[0204] Next, as Figure 22 As shown, multiple holes (not shown) are formed in a predetermined area of ​​the stacked structure where the memory pillars MP are disposed. The bottom surfaces of the multiple holes, for example, reach the stop film 37. Then, the bottom of each hole is further etched. Thus, the bottom surfaces of the multiple holes reach the semiconductor layer 72.

[0205] Subsequently, the laminated film 43, the semiconductor film 42, and the core film 41 are formed in this order within each hole, thus filling each hole. This forms a structure corresponding to the memory pillar MP. In the structure corresponding to the memory pillar MP, the laminated film 43 covers the Z2 direction end of the semiconductor film 42.

[0206] Next, as Figure 23 As shown, a groove SH3 is formed in a predetermined area where the component SLT is set. The bottom surface of the groove SH3, for example, reaches the stop membrane 37. Furthermore, a replacement process of the stacked structure is performed via the groove SH3. As a result, wiring layers 22, 23, and 24 are formed.

[0207] Next, as Figure 24 As shown, the insulating component SP and the filler component LI are filmed in this order within the groove SH3, and the groove SH3 is filled. Thus, the component SLT is formed.

[0208] Afterwards, the component SHE and the structure on the Z1 direction side relative to the stacked wiring structure are formed, and the manufacturing of the memory chip 100 is completed. Subsequent processes are the same as in the first embodiment.

[0209] 2.3 Effects of the second embodiment

[0210] According to the second embodiment, a stop film 37 is disposed between the insulating member SP and the semiconductor layer 21d, and extends in the XY plane such that it encloses the insulating member SP when viewed from the Z direction. The stop film 37 comprises at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C). Therefore, during the formation of the component SLT, the etching of the stacked structure can be stopped using the stop film 37. Thus, when the semiconductor film 42 of the storage pillar MP is exposed, the exposure of the filler LI can be suppressed. Therefore, when the semiconductor layer 21c is heated using laser annealing, the situation where heat is captured by the filler LI, which has a higher thermal conductivity, and the semiconductor layer 21c near the component SLT cannot be sufficiently crystallized can be suppressed. Furthermore, the crystallization of the semiconductor layer 21d near the component SLT can be promoted.

[0211] 2.4 Variations of the second embodiment

[0212] Various modifications can be applied to the second embodiment described above.

[0213] 2.4.1 First Modification of the Second Embodiment

[0214] In the second embodiment described above, the case where the stop film 37 is disposed between the semiconductor layer 21d and the insulating layer 32 has been explained, but it is not limited to this. The stop film 37 may also be disposed between the insulating layer 32 and the wiring layer 22.

[0215] Figure 25 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the first modification of the second embodiment. Figure 25 Compared with the second embodiment Figure 20 correspond.

[0216] like Figure 25 As shown, an insulating layer 32 is provided on the Z1-direction side surface of the semiconductor layer 21d. A stop film 37 is provided across the entire Z1-direction side surface of the insulating layer 32. A wiring layer 22 is provided on the Z1-direction side surface of the stop film 37. The structure on the Z1-direction side of the wiring layer 22 is the same as in the second embodiment.

[0217] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 37. This allows the insulating layer 32, the insulating member SP, and the stop film 37 to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the second embodiment, the amount of heat transferred to the filler LI during laser annealing is reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0218] 2.4.2 Second variation of the second embodiment

[0219] In the second embodiment and the first variation thereof described above, the case in which a stop film 37 and an insulating layer 32 are stacked between the semiconductor layer 21d and the wiring layer 22 has been described, but it is not limited thereto. It is sufficient to provide a stop film 37 between the semiconductor layer 21d and the wiring layer 22, and the insulating layer 32 may not be provided.

[0220] Figure 26 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the second modification of the second embodiment. Figure 26 Compared with the second embodiment Figure 20 correspond.

[0221] like Figure 26 As shown, a stop film 37 is provided on the entire surface of the semiconductor layer 21d in the Z1 direction. A wiring layer 22 is provided on the surface of the stop film 37 in the Z1 direction. The structure of the wiring layer 22 on the Z1 direction side is the same as in the second embodiment.

[0222] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 37. This allows the insulator, including the insulating member SP and the stop film 37, to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the second embodiment, the amount of heat transferred to the filler LI during laser annealing is reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0223] 3. Third Implementation Method

[0224] Next, the storage device according to the third embodiment will be described. In the third embodiment, the stop film is disposed on the same layer as the insulating layer 32, which differs from the second embodiment. In the following description, the different configuration and manufacturing method compared to the second embodiment will be mainly explained. Configurations and manufacturing methods identical to those in the second embodiment will be omitted as appropriate.

[0225] 3.1 Composition

[0226] Figure 27This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the third embodiment. Figure 27 Compared with the second embodiment Figure 20 correspond.

[0227] like Figure 27 As shown, in the third embodiment, the storage cell array 10 includes a stop membrane 38 instead of a stop membrane 37.

[0228] Similar to the second embodiment, the Z2 direction end of the component SLT does not reach the wiring layer 21. Therefore, the regions of each of the conductor layers 21a and 21b and the semiconductor layer 21c, including the portion that overlaps with the component SLT when viewed from the Z direction, have a flat shape.

[0229] A stop film 38 is provided on the Z1-direction side of the semiconductor layer 21d, including the region overlapping with the component SLT when viewed from the Z direction. The stop film 38 functions to hinder etching when forming the trench corresponding to the component SLT. The stop film 38 is, for example, an insulator containing at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 38 has a different film type than the insulating layer 32.

[0230] An insulating layer 32 is disposed in a region on the Z1-direction side of the semiconductor layer 21d where the stop film 38 is not disposed. The Z1-direction side of the insulating layer 32 is aligned with the Z1-direction side of the stop film 38. That is, the thicknesses of the insulating layer 32 and the stop film 38 are approximately equal.

[0231] A wiring layer 22 is provided on the Z1 direction side of both the insulating layer 32 and the stop film 38. The structure on the Z1 direction side of the wiring layer 22 is the same as in the second embodiment.

[0232] The filler LI intersects with wiring layers 23 and 24, and insulating layers 33-35. The filler LI may or may not intersect with wiring layer 22.

[0233] The insulating element SP covers the side surface of the filler LI and the end face of the Z2 direction side. The end of the insulating element SP on the Z2 direction side is located within the stop film 38.

[0234] 3.2 Manufacturing Method

[0235] Figure 28 , Figure 29 , Figure 30 , Figure 31 as well as Figure 32 This is a diagram illustrating an example of the structure during the manufacturing process of the storage device according to the third embodiment. Figure 28 , Figure 29, Figure 30 , Figure 31 as well as Figure 32 This is a cross-sectional view of the memory cell array 10 in the memory chip 100 during manufacturing, and... Figure 27 correspond.

[0236] First, such as Figure 28 As shown, the insulating layer 71, semiconductor layer 72, insulating layer 73, semiconductor layer 21d, and insulating layer 32 are disposed in this order on the Z1 direction side of the substrate 70.

[0237] Furthermore, the predetermined area in the insulating layer 32 where the stop film 38 is disposed is removed, for example, by anisotropic etching. This forms the trench SH4. The semiconductor layer 21d is exposed on the bottom surface of the trench SH4.

[0238] Next, as Figure 29 As shown, the trench SH4 is filled with the stop film 38. The portion of the stop film 38 located on the outside of the trench SH4 is etched back. As a result, the insulation layer 32 has the same thickness as the stop film 38.

[0239] Furthermore, a stacked structure corresponding to the stacked wiring structure is provided on the Z1 direction side of the insulating layer 32 and the stop film 38. Specifically, a sacrificial layer 74 is provided on the Z1 direction side surface of the insulating layer 32 and the stop film 38. Insulating layers 33 and 75 are alternately stacked on the Z1 direction side surface of the sacrificial layer 74. Insulating layers 34 and 76 are arranged in this order on the Z1 direction side surface of the uppermost sacrificial layer 75. An insulating layer 35 is provided on the Z1 direction side surface of the sacrificial layer 76.

[0240] Next, as Figure 30 As shown, multiple holes (not shown) are formed in a predetermined area of ​​the storage pillar MP in the stacked structure. The bottom surfaces of the multiple holes reach the semiconductor layer 72. Then, a stacked film 43, a semiconductor film 42, and a core film 41 are formed in this order within each hole, and each hole is filled. Thus, a structure corresponding to the storage pillar MP is formed. In the structure corresponding to the storage pillar MP, the stacked film 43 covers the Z2 direction end of the semiconductor film 42.

[0241] Next, as Figure 31 As shown, a groove SH5 is formed in a predetermined area where the component SLT is set. The bottom surface of the groove SH5, for example, reaches the stop membrane 38. Furthermore, a replacement process of the stacked structure is performed via the groove SH5. As a result, wiring layers 22, 23, and 24 are formed.

[0242] Next, as Figure 32 As shown, in the groove SH5, the insulating component SP and the filler component LI are formed into a film in this order, and the groove SH5 is filled. Thus, the component SLT is formed.

[0243] Afterwards, the component SHE and the structure on the Z1 direction side relative to the stacked wiring structure are formed, and the manufacturing of the memory chip 100 is completed. Subsequent processes are the same as in the second embodiment.

[0244] 3.3 Effects of the third embodiment

[0245] According to the third embodiment, the stop film 38 has a portion disposed at the same position as the insulating layer 32 in the Z direction. The stop film 38 comprises at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 38 extends in the XY plane such that, when viewed from the Z direction, it at least encloses a portion of the insulating element SP that is closer to the Z2 direction side than the filler LI (the bottom of the groove corresponding to the component SLT). Thus, when forming the component SLT, the etching of the stacked structure can be stopped with the stop film 38. Therefore, when the semiconductor film 42 of the storage pillar MP is exposed, the exposure of the filler LI can be suppressed. Therefore, the situation where heat is taken away by the filler LI, which has a higher thermal conductivity, during the heating of the semiconductor layer 21c by laser annealing, and the semiconductor layer 21c near the component SLT cannot be sufficiently crystallized, can be suppressed. In addition, the crystallization of the semiconductor layer 21d near the component SLT can be promoted.

[0246] 3.4 Variations of the third embodiment

[0247] Various modifications can be applied to the third embodiment described above.

[0248] 3.4.1 First variation of the third embodiment

[0249] In the third embodiment described above, the case where the thickness of the stop film 38 is approximately equal to that of the insulating layer 32 was explained, but this is not a limitation. The thickness of the stop film 38 may also be thinner than that of the insulating layer 32.

[0250] Figure 33 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the first modification of the third embodiment. Figure 33 Compared with the third embodiment Figure 27 correspond.

[0251] like Figure 33 As shown, an insulating layer 32 is disposed on the surface of the semiconductor layer 21d in the Z1 direction. The insulating layer 32 has a shape that is recessed in the Z2 direction in the region including the portion that overlaps with the component SLT when viewed from the Z direction.

[0252] A stop film 38 is provided on the Z1-direction side surface of the insulating layer 32, including the region that overlaps with the component SLT when viewed from the Z direction (the region recessed in the Z2 direction). The Z1-direction side surface of the insulating layer 32 is aligned with the Z1-direction side surface of the stop film 38. That is, the stop film 38 has a film thickness that is thinner than that of the insulating layer 32. Such a structure can be obtained by removing a portion of the insulating layer 32 using anisotropic etching during the formation of the trench SH4.

[0253] A wiring layer 22 is provided on the surface of the insulating layer 32 and the stop film 38 in the Z1 direction. The structure of the wiring layer 22 on the Z1 direction side is the same as that in the third embodiment.

[0254] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 38. This allows the insulating layer 32, the insulating member SP, and the stop film 38 to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat transferred to the filler LI during laser annealing is reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0255] 3.4.2 Second variation of the third embodiment

[0256] In addition, the thickness of the stop film 38 can be thicker than that of the insulating layer 32.

[0257] Figure 34 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the second variation of the third embodiment. Figure 34 Compared with the third embodiment Figure 27 correspond.

[0258] like Figure 34 As shown, a stop film 38 is provided in the area of ​​the surface of the semiconductor layer 21c on the Z1 direction side, including the portion that overlaps with the component SLT when viewed from the Z direction.

[0259] In the region on the Z1-direction side of the semiconductor layer 21c where the stop film 38 is not disposed, the semiconductor layer 21d and the insulating layer 32 are stacked in this order. The Z1-direction side of the insulating layer 32 is aligned with the Z1-direction side of the stop film 38. That is, the thickness of the stop film 38 is greater than the thickness of the insulating layer 32, and approximately equal to the combined thickness of the semiconductor layer 21d and the insulating layer 32. This structure can be obtained by removing the insulating layer 32 and the semiconductor layer 21d using anisotropic etching during the formation of the SH4.

[0260] A wiring layer 22 is provided on the surface of the insulating layer 32 and the stop film 38 in the Z1 direction. The structure of the wiring layer 22 on the Z1 direction side is the same as that in the third embodiment.

[0261] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 38. This allows the insulator, including the insulating member SP and the stop film 38, to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat transferred to the filler LI during laser annealing can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0262] 3.4.3 Third variation of the third embodiment

[0263] In addition, the stop film 38 can reach into the semiconductor layer 21c.

[0264] Figure 35 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the third modification of the third embodiment. Figure 35 Compared with the third embodiment Figure 27 correspond.

[0265] like Figure 35 As shown, each of the conductor layers 21a and 21b and the semiconductor layer 21c has a shape that is recessed in the Z2 direction in a region including the portion that overlaps with the storage pillar MP and the component SLT when viewed from the Z direction.

[0266] A stop film 38 is provided in a region on the Z1-direction side of the surface of semiconductor layer 21c that is recessed in the Z2 direction corresponding to component SLT. In the region on the Z1-direction side of the surface of semiconductor layer 21c where the stop film 38 is not provided, semiconductor layer 21d and insulating layer 32 are stacked in this order. The Z1-direction side of insulating layer 32 is aligned with the Z1-direction side of stop film 38. This structure can be obtained by removing insulating layer 32, semiconductor layer 21d, and insulating layer 73 using anisotropic etching during the formation of trench SH4, thereby removing a portion of semiconductor layer 72.

[0267] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 38. This allows the insulator, including the insulating member SP and the stop film 38, to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat transferred to the filler LI during laser annealing is reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0268] 3.4.4 Fourth variation of the third embodiment

[0269] Additionally, the stop film 38 may have a film thickness thinner than the insulating layer 32 and be configured to be covered by the insulating layer 32.

[0270] Figure 36 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to the fourth variation of the third embodiment. Figure 36 Compared with the third embodiment Figure 27 correspond.

[0271] like Figure 36 As shown, a stop film 38 is provided on the Z1-direction side surface of the semiconductor layer 21d, including the region overlapping with the component SLT when viewed from the Z direction. Furthermore, an insulating layer 32 is provided to cover the stop film 38 and the region on the Z1-direction side surface of the semiconductor layer 21d where the stop film 38 is not provided. This structure can be obtained by further forming an insulating layer 32 on the Z1-direction side surface of the structure after the stop film 38 has been buried in the trench SH4.

[0272] A wiring layer 22 is provided on the surface of the insulating layer 32 in the Z1 direction. The structure on the Z1 direction side of the wiring layer 22 is the same as in the third embodiment.

[0273] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 38. This allows the insulator, including the insulating member SP and the stop film 38, to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the third embodiment, the amount of heat transferred to the filler LI during laser annealing is reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0274] 4. Fourth Implementation Method

[0275] Next, the storage device according to the fourth embodiment will be described. In the fourth embodiment, the stop film is provided on the Z2 direction side relative to the insulating layer 32, which differs from the third embodiment. In the following description, the different configuration and manufacturing method compared to the third embodiment will be mainly explained. Configurations and manufacturing methods equivalent to those in the third embodiment will be omitted as appropriate.

[0276] 4.1 Composition

[0277] Figure 37 This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array included in the memory device according to the fourth embodiment. Figure 37 Compared with the third embodiment Figure 27 correspond.

[0278] like Figure 37As shown, in the fourth embodiment, the storage cell array 10 includes a stop membrane 39 instead of a stop membrane 38.

[0279] Similar to the third embodiment, the Z2 direction end of the component SLT does not reach the wiring layer 21. Therefore, the regions of each of the conductive layers 21a and 21b and the semiconductor layer 21c, including the portion that overlaps with the component SLT when viewed from the Z direction, have a flat shape.

[0280] A stop film 39 is provided on the Z1-direction side of the surface of semiconductor layer 21c, including the region overlapping with the component SLT when viewed from the Z direction. The stop film 39 functions to hinder etching during the formation of the trench corresponding to the component SLT. The stop film 39 is, for example, an insulator comprising at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 39 has a different film type than the insulating layer 32.

[0281] In the area on the Z1 direction side of the semiconductor layer 21c where the stop film 39 is not disposed, a semiconductor layer 21d is disposed. The Z1 direction side of the semiconductor layer 21d is aligned with the Z1 direction side of the stop film 39.

[0282] An insulating layer 32 is provided on the Z1 direction side of both the semiconductor layer 21d and the stop film 39. The structure on the Z1 direction side of the insulating layer 32 is the same as in the third embodiment.

[0283] The filler LI intersects with wiring layers 23 and 24, and insulating layers 33-35. The filler LI may or may not intersect with wiring layer 22.

[0284] The insulating element SP covers the side surface of the filler LI and the end face of the filler LI in the Z2 direction. The end of the insulating element SP in the Z2 direction is located within the stop film 39.

[0285] 4.2 Manufacturing Method

[0286] Figure 38 as well as Figure 39 This is a diagram illustrating an example of the structure during the manufacturing process of the storage device according to the fourth embodiment. Figure 38 as well as Figure 39 This is a cross-sectional view of the memory cell array 10 in the memory chip 100 during manufacturing, and... Figure 37 correspond.

[0287] First, such as Figure 38 As shown, the insulating layer 71, the semiconductor layer 72, the insulating layer 73, and the semiconductor layer 21d are arranged in this order on the Z1 direction side of the substrate 70.

[0288] Furthermore, the predetermined region in the semiconductor layer 21d where the stop film 39 is disposed is removed, for example, by anisotropic etching. This forms the trench SH6. The insulating layer 73 is exposed at the bottom surface of the trench SH6.

[0289] Next, as Figure 39 As shown, trench SH6 is filled with stop film 39. The portion of stop film 39 located outside trench SH6 is etched back. Thus, the semiconductor layer 21d and stop film 39 have the same thickness.

[0290] Furthermore, a stacked structure corresponding to the stacked wiring structure is provided on the Z1 direction side of the semiconductor layer 21d and the stop film 39. Specifically, the insulating layer 32 and the sacrificial layer 74 are stacked in this order on the Z1 direction side surface of the semiconductor layer 21d and the stop film 39. The insulating layer 33 and the sacrificial layer 75 are alternately stacked on the Z1 direction side surface of the sacrificial layer 74. The insulating layer 34 and the sacrificial layer 76 are provided in this order on the Z1 direction side surface of the uppermost sacrificial layer 75. The insulating layer 35 is provided on the Z1 direction side surface of the sacrificial layer 76.

[0291] The subsequent procedures are the same as those in the third embodiment.

[0292] 4.3 Effects of the fourth embodiment

[0293] According to the fourth embodiment, the surface of the stop film 39 on the wiring layer 22 side is aligned with the surface of the semiconductor layer 21d side of the insulating layer 32. The stop film 39 comprises at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C). The stop film 39 extends in the XY plane such that, when viewed from the Z direction, it at least encloses the portion of the insulating element SP (the bottom of the trench corresponding to the component SLT) that is closer to the Z2 direction side than the filler LI. Thus, when forming the component SLT, the etching of the stacked structure can be stopped by the stop film 39. Therefore, when the semiconductor film 42 of the memory pillar MP is exposed, the exposure of the filler LI can be suppressed. Therefore, when the semiconductor layer 21c is heated by laser annealing, the situation where heat is taken away by the filler LI, which has a higher thermal conductivity, and the semiconductor layer 21c near the component SLT cannot be sufficiently crystallized can be suppressed. In addition, the crystallization of the semiconductor layer 21d near the component SLT can be promoted.

[0294] 4.4 Variations of the fourth embodiment

[0295] Various modifications can be applied to the fourth embodiment described above.

[0296] For example, the stop film 39 can also reach into the semiconductor layer 21c.

[0297] Figure 40This is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array provided by the memory device according to a variation of the fourth embodiment. Figure 40 Compared with the fourth embodiment Figure 37 correspond.

[0298] like Figure 40 As shown, each of the conductor layers 21a and 21b and the semiconductor layer 21c has a shape that is recessed in the Z2 direction in the region including the portion that overlaps with the storage pillar MP and the component SLT when viewed from the Z direction.

[0299] A stop film 39 is provided in a region on the Z1-direction side of the surface of semiconductor layer 21c that is recessed in the Z2 direction corresponding to component SLT. A semiconductor layer 21d is provided in a region on the Z1-direction side of the surface of semiconductor layer 21c where the stop film 39 is not provided. The Z1-direction side of semiconductor layer 21d is aligned with the Z1-direction side of stop film 39. This structure can be obtained by removing semiconductor layer 21d and insulating layer 73, and then a portion of semiconductor layer 72, using anisotropic etching during the formation of trench SH6.

[0300] In the configuration described above, the Z2-direction end of the insulating member SP is located within the stop film 39. This allows the insulator, including the insulating member SP and the stop film 39, to be positioned between the filler LI and the wiring layer 21. Therefore, similar to the fourth embodiment, the amount of heat transferred to the filler LI during laser annealing can be reduced. Consequently, crystallization of the semiconductor layers 21c and 21d near the component SLT can be promoted.

[0301] Several embodiments of the present invention have been described, but these embodiments are presented by way of example and are not intended to limit the scope of the invention. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and / or variations thereof are included in the scope and spirit of the invention, and are included within the scope of the invention as set forth in the claims and its equivalents.

Claims

1. A storage device comprising: Semiconductor layer; The first wiring layer is arranged separately from the semiconductor layer in the first direction without being separated by other wiring layers; Multiple second wiring layers are located on the opposite side of the semiconductor layer relative to the first wiring layer, and are each arranged separately in the first direction; Multiple memory pillars, each extending in the first direction and connected to the semiconductor layer, and the portions intersecting with each of the multiple second wiring layers function as memory cells; as well as The component extends within a first surface including the first direction and a second direction intersecting the first direction, and truncates the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first and second directions. The component includes: The filler has two ends in the first direction and extends within the first surface on the side of the plurality of second wiring layers that is closer to the semiconductor layer side than the first wiring layer; and An insulating element is disposed between the filler and the semiconductor layer, the first wiring layer and each of the plurality of second wiring layers, and has a lower thermal conductivity than the filler.

2. The storage device according to claim 1, The length of the component in the third direction is twice the length of the portion between the insulating element and each of the plurality of second wiring layers.

3. The storage device according to claim 1, The length of the portion of the insulating member that is closer to the semiconductor layer than the filler in the first direction is longer than the length of the portion of the insulating member between the filler and each of the plurality of second wiring layers.

4. The storage device according to claim 1, The filler has a higher Young's modulus than the insulator.

5. The storage device according to claim 1, The portion of the insulating member that is closer to the semiconductor layer side than the filler includes: A first insulating film that is partially continuous with the insulating element and between each of the plurality of second wiring layers; and A second insulating film is disposed between the first insulating film and the semiconductor layer.

6. The storage device according to claim 1, The side of the semiconductor layer opposite to the first wiring layer has an uneven surface in the region that overlaps with the plurality of memory pillars along the first direction.

7. A storage device comprising: Semiconductor layer; The first wiring layer is arranged separately from the semiconductor layer in the first direction without being separated by other wiring layers; Multiple second wiring layers are located on the opposite side of the semiconductor layer relative to the first wiring layer, and are each arranged separately in the first direction; Multiple memory pillars, each extending in the first direction and connected to the semiconductor layer, and the portions intersecting with each of the multiple second wiring layers function as memory cells; A component extends in a first surface including the first direction and a second direction intersecting the first direction, and cuts off the first wiring layer and the plurality of second wiring layers in a third direction intersecting each of the first direction and the second direction. The component includes a filler and an insulating member. The insulating member is disposed between the filler and the semiconductor layer, the first wiring layer and each of the plurality of second wiring layers, and has a lower thermal conductivity than the filler. as well as An insulating film is disposed between the insulating member and the semiconductor layer, and when viewed from the first direction, encapsulates the portion of the insulating member that is closer to the semiconductor layer than the filler.

8. The storage device according to claim 7, The insulating film comprises at least one material selected from alumina (Al2O3), silicon carbide (SiC), and carbon (C).

9. The storage device according to claim 7, The insulating film extends within a second surface that includes the second direction and the third direction.

10. The storage device according to claim 9, It also includes a first insulating layer disposed between the insulating film and the first wiring layer and having a film type different from that of the insulating film.

11. The storage device according to claim 9, It also includes a second insulating layer disposed between the insulating film and the semiconductor layer and having a different type of film than the insulating film.

12. The storage device according to claim 9, The insulating film is connected to each of the semiconductor layer and the first wiring layer.

13. The storage device according to claim 7, It also includes a third insulating layer, which has a portion disposed at the same position as the insulating film in the first direction, and has a different film type than the insulating film.

14. The storage device according to claim 13, The insulating film has a thickness approximately equal to that of the third insulating layer.

15. The storage device according to claim 13, The insulating film has a film thickness that is thinner than the third insulating layer. The third insulating layer also has a portion between the insulating film and the semiconductor layer.

16. The storage device according to claim 13, The insulating film has a film thickness that is thicker than the third insulating layer.

17. The storage device according to claim 13, The insulating film has a film thickness that is thinner than the third insulating layer and is in contact with the semiconductor layer.

18. The storage device according to claim 7, It also includes a fourth insulating layer disposed between the semiconductor layer and the first wiring layer, and having a film type different from the insulating film. The surface of the insulating film on the first wiring layer side is aligned with the surface of the fourth insulating layer on the semiconductor layer side.

19. The storage device according to claim 7, The filler has a higher Young's modulus than the insulator.

20. The storage device according to claim 7, The surface of the semiconductor layer opposite to the first wiring layer has an uneven formation in the region that overlaps with the plurality of memory pillars along the first direction.

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