Display package module, forming method, device, related equipment and terminal

Abstract

Embodiments of the present application provide a display packaging module, a forming method, an apparatus, related equipment and a terminal, wherein the method comprises: providing an initial display packaging module comprising a substrate, a target medium layer, a core particle electrode, and a light-transmitting protective layer; the target medium layer is provided with a conductive plug structure connected with the core particle electrode and penetrating the target medium layer; etching the substrate from the back to the front with the conductive plug structure as an etching stop structure to form a via penetrating the substrate and exposing the conductive plug structure and / or the core particle electrode; wherein the etching rate of the conductive plug structure is less than the etching rate of the substrate; forming an insulating layer covering the sidewall of the via and the substrate; forming a rewiring layer filling the via to obtain a target display packaging module. Embodiments of the present application improve the yield of the display packaging module.

Description

Technical Field

[0001] This application relates to the field of optoelectronic device technology, specifically to a display packaging module, a forming method, an apparatus, related equipment, and a terminal. Background Technology

[0002] Display packaging modules are core display and light-emitting devices in the field of optoelectronic devices. A typical example is the MicroLED (Micro Light-Emitting Diode) display packaging module. Display packaging modules are modular display units that are independently driven at the pixel level and emit light themselves. They feature high brightness, high contrast, long lifespan, and low power consumption.

[0003] However, the current display packaging module still suffers from a low manufacturing yield, which needs further improvement. Summary of the Invention

[0004] In view of this, embodiments of this application provide a display packaging module, a method for forming it, an apparatus, related equipment, and a terminal to improve the manufacturing yield of the display packaging module.

[0005] This application provides a method for forming a display packaging module, including: An initial display packaging module is provided, the initial display packaging module including a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode; wherein, a conductive plug structure connected to the chip electrode and penetrating the target dielectric layer is disposed in the target dielectric layer; the side of the initial display packaging module where the light-transmitting protective layer is disposed is the front side, and the side of the initial display packaging module where the substrate is disposed is the back side; Using the conductive plug structure as the etching stop structure, the substrate is etched from the back side to the front side to form a through-hole that penetrates the substrate and exposes the conductive plug structure and / or the chip electrode; wherein the etching rate of the conductive plug structure is less than the etching rate of the substrate; An insulating layer is formed to cover the sidewalls of the through-hole and the substrate; A redistribution layer is formed to fill the vias, resulting in the target display package module.

[0006] Optionally, the number of the conductive plug structures is one or more; When there are multiple conductive plug structures, the multiple conductive plug structures are arranged in a linear array, a matrix array, or a ring array.

[0007] Optionally, the substrate includes a substrate and a polycrystalline silicon layer located between the substrate and the target dielectric layer; In the step of etching the substrate from the back side to the front side using the conductive plug structure as the etching stop structure, the etching rate of the conductive plug structure is less than the etching rate of the substrate and the polysilicon layer.

[0008] Optionally, the diameter of the conductive plug structure ranges from 0.02μm to 50μm, and the depth ranges from 0.02μm to 200μm.

[0009] Optionally, the cross-sectional shape of the conductive plug structure in the direction parallel to the substrate includes a circle, a square, a rectangle, or a frustum.

[0010] Optionally, the conductive plug structure is made of tungsten.

[0011] Optionally, the step of forming an insulating layer covering the sidewalls of the through-hole and the substrate includes: An initial insulating layer is formed covering the bottom and sidewalls of the through-hole, as well as the substrate; Remove the initial insulating layer located at the bottom of the through hole, and use the remaining initial insulating layer as the insulating layer.

[0012] Optionally, after the step of forming the redistribution layer filling the via, the method further includes: A solder mask layer is formed that exposes a portion of the redistribution layer.

[0013] Optionally, the front and back sides of the target display packaging module are respectively divided into a light-emitting area and an edge area surrounding the light-emitting area. The edge area of ​​the back side of the target display packaging module includes a stepped area. The top surface of the stepped area on the back side of the target display packaging module is lower than the top surface of the light-emitting area, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area. The chip electrode is located in the stepped area.

[0014] This application embodiment also provides a display packaging module, formed according to the method for forming a display packaging module as described in the first aspect above, including: Base; A target dielectric layer located on a substrate; wherein a conductive plug structure is provided in the target dielectric layer; Core electrodes located on the target dielectric layer; A light-transmitting protective layer located on the core electrode; Through the substrate, and exposing the conductive plug structure and / or the core electrode; wherein the conductive plug structure is connected to the core electrode; An insulating layer covering the sidewalls of the through-hole and the substrate; Redistribution layer that fills the via.

[0015] Optionally, the number of the conductive plug structures is one or more; When there are multiple conductive plug structures, the multiple conductive plug structures are arranged in a linear array, a matrix array, or a ring array.

[0016] Optionally, the substrate includes a substrate and a polycrystalline silicon layer located between the substrate and the target dielectric layer; The via penetrates the substrate and the polysilicon layer.

[0017] Optionally, the diameter of the conductive plug structure ranges from 0.02μm to 50μm, and the depth ranges from 0.02μm to 200μm.

[0018] Optionally, the cross-sectional shape of the conductive plug structure in the direction parallel to the substrate includes a circle, a square, a rectangle, or a frustum.

[0019] Optionally, the conductive plug structure is made of tungsten.

[0020] Optional, also includes: The solder mask layer of a portion of the redistribution layer is exposed.

[0021] Optionally, the initial display packaging module is defined as a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode. The side of the initial display packaging module with the light-transmitting protective layer is defined as the front side, and the side of the initial display packaging module with the substrate is defined as the back side. The target display packaging module is defined as a display packaging module with a redistribution layer that fills the vias. The front and back sides of the target display packaging module are respectively divided into a light-emitting area and an edge area surrounding the light-emitting area. The edge area of ​​the back side of the target display packaging module includes a stepped area. The top surface of the stepped area on the back side of the target display packaging module is lower than the top surface of the light-emitting area, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area. The chip electrode is located in the stepped area.

[0022] This application also provides a display device, including: a display packaging module as described in the second aspect above.

[0023] This application also provides a display device, including: a display packaging module as described in the second aspect above.

[0024] This application also provides an optoelectronic device, including: a display packaging module as described in the second aspect above.

[0025] This application also provides a terminal, including: a display packaging module as described in the second aspect above.

[0026] This application provides a display packaging module, a forming method, an apparatus, related equipment, and a terminal. The method for forming the display packaging module includes: providing an initial display packaging module, the initial display packaging module including a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode; wherein a conductive plug structure connected to and penetrating the target dielectric layer is disposed in the target dielectric layer; taking the side of the initial display packaging module where the light-transmitting protective layer is disposed as the front side, and the side of the initial display packaging module where the substrate is disposed as the back side; using the conductive plug structure as an etch stop structure, etching the substrate from the back side to the front side to form a through-hole penetrating the substrate and exposing the conductive plug structure and / or the chip electrode; wherein the etching rate of the conductive plug structure is less than the etching rate of the substrate; forming a sidewall covering the through-hole and an insulating layer on the substrate; forming a redistribution layer filling the through-hole to obtain the target display packaging module.

[0027] As can be seen, in the solution provided by the embodiments of this application, the initial display packaging module is provided with a conductive plug structure that is connected to the chip electrode and penetrates the target dielectric layer. The conductive plug can simultaneously serve as a vertical conductive path and an etching stop structure. In the process of etching the substrate from the back side to the front side to prepare the via, since the etching rate of the conductive plug structure is less than the etching rate of the substrate, the substrate has a higher etching selectivity relative to the conductive plug structure. Based on this characteristic, the conductive plug structure can be used as an etching stop structure, so that the etching rate is reduced when the etching reaches the conductive plug structure, thereby avoiding over-etching and damage to the chip electrode during the etching process from the back side to the front side, and thus improving the manufacturing yield of the display packaging module.

[0028] Furthermore, in this scheme, when etching the substrate from the back side to the front side to form a through hole, the etching endpoint can be at the conductive plug structure (i.e., the through hole only exposes the conductive plug structure), or it can continue etching to the core electrode (i.e., the through hole exposes both the conductive plug structure and the core electrode, or only the core electrode). Both etching results meet the requirements of subsequent fabrication, eliminating the need for precise control of the etching depth, reducing the precision constraints of the etching process, thereby improving the process tolerance of the etching process and making it suitable for mass production. Attached Figure Description

[0029] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0030] Figure 1 This is a schematic diagram of a display packaging module in the prior art; Figure 2 This is a schematic diagram of some steps in the method for forming a display packaging module provided in the embodiments of this application; Figure 3 A first structural schematic diagram showing a single core electrode with multiple conductive plug structures disposed below it, as provided in an embodiment of this application. Figure 4 A schematic diagram of a second structure provided in an embodiment of this application, showing a plurality of conductive plug structures disposed below a single core electrode; Figure 5 A schematic diagram of a third structure provided in an embodiment of this application, showing multiple conductive plug structures disposed below a single core electrode; Figure 6 A schematic diagram of a fourth structure provided in an embodiment of this application, showing multiple conductive plug structures disposed below a single core electrode; Figures 7 to 11 This is a schematic diagram of some steps in the method for forming a display packaging module provided in the embodiments of this application; Figure 12 This is a first structural schematic diagram of the display packaging module provided in an embodiment of this application; Figure 13 Provided for the embodiments of this application Figure 12 Enlarged view of the area within the dashed box; Figure 14 This is a schematic diagram of the second structure of the display packaging module provided in the embodiments of this application; Figure 15 Provided for the embodiments of this application Figure 14 Enlarged view of the area within the dashed box; Figure 16 This is a schematic diagram of the third structure of the display packaging module provided in the embodiments of this application; Figure 17 Provided for the embodiments of this application Figure 16 Enlarged view of the area within the dashed box; Figure 18 This is a schematic diagram of the fourth structure of the display packaging module provided in the embodiments of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] As described in the background section, display packaging modules are the core display and light-emitting devices in the field of optoelectronic devices. Typical devices, such as MicroLED display packaging modules, have advantages such as self-illumination, ultra-high brightness, high contrast, low power consumption, long lifespan, and inorganic stability. Therefore, they are widely used in near-eye displays, automotive optoelectronic devices, and have gradually penetrated into professional displays, transparent displays, optical communications, medical detection, and other scenarios, becoming a key carrier of optoelectronic device technology.

[0033] However, the current display packaging module still suffers from low manufacturing yield. Specifically, the inventors have discovered that the main reason for the low manufacturing yield of display packaging modules is: In the field of optoelectronic devices, through-silicon via (TSV) technology is a core technology for realizing vertical interconnection of chips. Taking MicroLED display packaging modules as an example, through-holes need to be etched from the back of the chip to expose the chip electrodes, and then the chip electrodes are brought out through the back redistribution layer (RDL) to realize the vertical interconnection and surface mounting of the chip.

[0034] refer to Figure 1 , Figure 1 This is a structural schematic diagram of a prior art display packaging module. (Example) Figure 1 As shown, in this display packaging module, the chip electrode 102 is led out by forming a through-hole 103 in the silicon substrate 100 and then filling the through-hole 103 with copper as a vertical conductive path. Figure 1 101 is a transparent protective layer, and 104 is a solder ball.

[0035] However, the inventors discovered that when etching the silicon substrate 100 from the back of the chip to form vias 103 exposing the die electrodes 102, due to limited etching rate control precision, wafer thickness uniformity deviations, and lag in endpoint detection signals, etching is difficult to precisely stop at the surface of the die electrodes 102, easily leading to over-etching—that is, etching through the die electrodes 102. Once over-etching occurs, it can damage the die electrodes, leading to increased contact resistance, or even penetrate the die electrodes 102, destroying the circuit structure and causing the chip to fail completely. This results in a low yield rate for the fabrication of display packaging modules.

[0036] In view of the above, embodiments of this application provide a display packaging module, a forming method, an apparatus, related equipment, and a terminal. The method for forming the display packaging module includes: providing an initial display packaging module, the initial display packaging module including a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode; wherein a conductive plug structure connected to and penetrating the target dielectric layer is disposed in the target dielectric layer; taking the side of the initial display packaging module where the light-transmitting protective layer is disposed as the front side, and the side of the initial display packaging module where the substrate is disposed as the back side; using the conductive plug structure as an etch stop structure, etching the substrate from the back side to the front side to form a through-hole penetrating the substrate and exposing the conductive plug structure and / or the chip electrode; wherein the etching rate of the conductive plug structure is less than the etching rate of the substrate; forming a sidewall covering the through-hole and an insulating layer on the substrate; forming a redistribution layer filling the through-hole to obtain the target display packaging module.

[0037] As can be seen, in the solution provided by the embodiments of this application, the initial display packaging module is provided with a conductive plug structure that is connected to the chip electrode and penetrates the target dielectric layer. The conductive plug can simultaneously serve as a vertical conductive path and an etching stop structure. In the process of etching the substrate from the back side to the front side to prepare the via, since the etching rate of the conductive plug structure is less than the etching rate of the substrate, the substrate has a higher etching selectivity relative to the conductive plug structure. Based on this characteristic, the conductive plug structure can be used as an etching stop structure, so that the etching rate is reduced when the etching reaches the conductive plug structure, thereby avoiding over-etching and damage to the chip electrode during the etching process from the back side to the front side, and thus improving the manufacturing yield of the display packaging module.

[0038] Furthermore, in this scheme, when etching the substrate from the back side to the front side to form a through hole, the etching endpoint can be at the conductive plug structure (i.e., the through hole only exposes the conductive plug structure), or it can continue etching to the core electrode (i.e., the through hole exposes both the conductive plug structure and the core electrode, or only the core electrode). Both etching results meet the requirements of subsequent fabrication, eliminating the need for precise control of the etching depth, reducing the precision constraints of the etching process, thereby improving the process tolerance of the etching process and making it suitable for mass production.

[0039] To make the above-mentioned objects, features and advantages of the embodiments of this disclosure more apparent and understandable, the specific embodiments of this disclosure will be described in detail below with reference to the accompanying drawings.

[0040] As an optional example of the content disclosed in the embodiments of this application, Figure 2 and Figures 7-11The schematic diagram shows the structural diagrams corresponding to each step in one embodiment of the method for forming a display packaging module.

[0041] refer to Figure 2 An initial display packaging module is provided, the initial display packaging module including a substrate, a target dielectric layer 202 located on the substrate, a chip electrode 203 located on the target dielectric layer 202, and a light-transmitting protective layer 204 located on the chip electrode 203.

[0042] In an optional implementation, the substrate may include a substrate 200 and a polysilicon layer 201 located between the substrate 200 and the target dielectric layer 202. The substrate material may be one or more combinations of silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. Alternatively, the substrate may be another type of substrate, such as a silicon-on-insulator substrate or a germanium-on-insulator substrate. The polysilicon layer 201 may be doped polysilicon with n-type impurities such as phosphorus or arsenic, or p-type impurities such as boron. The target dielectric layer 202 may be made of silicon oxide. The chip electrode 203 is used for electrically leading out auxiliary devices inside the display packaging module; that is, the chip electrode is used to electrically connect the auxiliary devices to the external electrical connection structure of the display packaging module.

[0043] The side of the initial display packaging module with the light-transmitting protective layer 204 is considered the front side, and the side of the initial display packaging module with the substrate is considered the back side. The target dielectric layer 202 contains a conductive plug structure 205 that is connected to the chip electrode 203 and penetrates the target dielectric layer 202.

[0044] In an optional implementation, the number of the conductive plug structures 205 can be one or more ( Figure 2 (The example shown uses a scheme with multiple conductive plug structures.) For ordinary core electrodes, a one-to-one layout can be used, where one conductive plug structure is placed under each core electrode. For core electrodes that need to carry large currents, a one-to-many layout can be used, where multiple conductive plug structures are placed under each core electrode. These multiple conductive plug structures are then connected in parallel at the redistribution layer to reduce the overall conduction resistance and disperse the thermal stress generated during conduction.

[0045] In optional implementations, when there are multiple conductive plug structures 205, the multiple conductive plug structures 205 are arranged in a linear array, a matrix array, or a ring array. A "ring array" refers to multiple conductive plug structures being distributed circumferentially around the center of the core electrode. In optional implementations, the cross-sectional shape of the conductive plug structure 205 in the direction parallel to the substrate may include, but is not limited to, a circle, a square, a rectangle, or a frustum.

[0046] refer to Figures 3-4 , Figure 3 A schematic diagram of a first structure in which multiple conductive plug structures are arranged below a single core electrode. Figure 4 A second structural diagram showing multiple conductive plug structures 205 arranged in a matrix array below a single core electrode. (Reference) Figures 5-6 , Figure 5 A schematic diagram of a third structure in which multiple conductive plug structures are arranged below a single core electrode. Figure 6 A fourth structural diagram showing multiple conductive plug structures configured below a single core electrode, wherein the multiple conductive plug structures 205 are arranged in a linear array.

[0047] In optional implementations, the diameter of the conductive plug structure 205 ranges from 0.02 μm to 50 μm, for example, the diameter of the conductive plug structure 205 can be 0.02 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc.; the depth ranges from 0.02 μm to 200 μm, for example, the depth of the conductive plug structure 205 can be 0.02 μm, 50 μm, 100 μm, 150 μm, or 200 μm, etc. Selecting the above-mentioned size range of the conductive plug structure can both meet the fine processing requirements of small-pitch interconnection of micro electrodes and satisfy the cross-sectional area requirements for high current conduction in power supply and grounding paths.

[0048] In existing technologies, when vertical interconnects and surface mount chips are achieved by leading out the die electrodes through a back redistribution layer (RDL), the back redistribution layer is made of copper. Copper readily diffuses rapidly into silicon or silicon dioxide. Therefore, when using copper to fabricate vertical interconnect structures, a complex diffusion barrier layer needs to be prepared, which not only increases the overall process difficulty but also introduces the risk of leakage. In this application, the conductive plug structure 205 is made of tungsten. This application selects tungsten as the conductive material for vertical interconnects. Tungsten has a coefficient of thermal expansion (CTE ≈ 4.5 × 10⁻⁶). -6 / ℃) and silicon (CTE≈2.6×10 -6 The coefficient of thermal expansion (°C) is highly adaptable, thus avoiding the thermal stress failure and leakage defects that exist when using copper materials to prepare vertical interconnect structures.

[0049] In an optional implementation, the light-transmitting protective layer 204 and the core electrode 203 are connected by a damming adhesive 11 and an adhesive 12. Specifically, the thickness of the damming adhesive 11 determines the vertical height of the cavity. The light-transmitting protective layer 204 is bonded to the upper surface of the damming adhesive 11, and the core electrode 203 is bonded to the lower surface by the adhesive 12, thus sealing the central light-emitting pixel into an independent, sealed cavity. The cavity is generally filled with dry inert gas or evacuated to isolate moisture and oxygen, thereby ensuring that the light-emitting pixel is not oxidized or corroded.

[0050] The damming adhesive 11 is a rigid encapsulating colloid, while the core electrode 203 is a hard metal layer. Direct bonding between the two results in poor adhesion and easy delamination. Therefore, the adhesive 12 acts as an bonding medium, firmly adhering the damming adhesive 11 while simultaneously bonding the core electrode 203.

[0051] In an optional implementation, the light-transmitting protective layer 204 has the same outer dimensions as the substrate, with the two structures completely overlapping; alternatively, the outer dimensions of the light-transmitting protective layer 204 are slightly larger than the outer dimensions of the substrate. Since the display area (i.e., the light-emitting pixel area) needs to maintain high light transmittance and high flatness optical properties, a transparent cover layer (e.g., cover glass) can be used as the light-transmitting protective layer, thereby protecting the display packaging module while ensuring the light transmittance of the light-emitting pixels. In a specific example, the material of the light-transmitting protective layer can be glass or sapphire, etc.

[0052] Using the conductive plug structure as the etching stop structure, the substrate is etched from the back side to the front side to form a through-hole that penetrates the substrate and exposes the conductive plug structure and / or the core electrode. In other words, the through-hole formed by etching the substrate can expose only the conductive plug structure, simultaneously expose both the conductive plug structure and the core electrode, or only expose the core electrode. All of these scenarios meet the requirements for subsequent fabrication, eliminating the need for precise control of the etching depth, reducing the precision constraints of the etching process, thereby improving the process tolerance of the etching step and making it suitable for mass production.

[0053] Understandably, "exposing only the conductive plug structure" means that the etching stops after reaching the conductive plug structure. During the etching process, part of the conductive plug structure can be removed, but the core electrode is not etched. "Exposing both the conductive plug structure and the core electrode" means that the etching continues after reaching the conductive plug structure until both the conductive plug structure and the core electrode are exposed simultaneously before stopping the etching. "Exposing only the core electrode" means that the etching continues after reaching the conductive plug structure, completely removing the conductive plug structure, and stopping the etching without penetrating the core electrode, ultimately exposing only the core electrode.

[0054] The following example demonstrates how etching the substrate from the back to the front forms a through-hole that penetrates the substrate and exposes the conductive plug structure.

[0055] refer to Figure 7 Using the conductive plug structure as the etching stop structure, from the back side to the front side (e.g.) Figure 7 The substrate is etched in the direction indicated by the middle arrow to form a through-hole 206 that penetrates the substrate and exposes the conductive plug structure 205.

[0056] The etching rate of the conductive plug structure 205 is lower than that of the substrate. The substrate includes a substrate 200 and a polysilicon layer 201 located between the substrate 200 and the target dielectric layer 202. In the step of etching the substrate from the back side to the front side using the conductive plug structure 205 as an etching stop structure, the etching rate of the conductive plug structure is lower than that of the substrate and the polysilicon layer. In this application, during the process of etching the substrate from the back side to the front side to prepare vias, since the etching rate of the conductive plug structure is lower than that of the substrate and the polysilicon layer, the substrate and the polysilicon layer have a higher etching selectivity relative to the conductive plug structure. Based on this characteristic, the conductive plug structure can be used as an etching stop structure, so that the etching rate is reduced when the etching reaches the conductive plug structure, thereby avoiding over-etching during the etching process from the back side to the front side and damaging the chip electrodes, thus improving the manufacturing yield of the display packaging module.

[0057] Furthermore, in this scheme, when etching the substrate and the polysilicon layer from the back side to the front side to form a via, the etching endpoint can be at the conductive plug structure (i.e., the via only exposes the conductive plug structure), or it can continue etching to the core electrode (i.e., the via exposes both the conductive plug structure and the core electrode, or only the core electrode). Both etching results meet the requirements of subsequent fabrication, eliminating the need for precise control of the etching depth, reducing the precision constraints of the etching process, thereby improving the process tolerance of the etching process and making it suitable for mass production.

[0058] In an optional implementation, a photoresist layer can be coated on the side of the substrate 200 away from the polysilicon layer 201, and the photoresist can be patterned using photolithography processes (including exposure, development, etc.) to form a patterned photolithography layer. The patterned photolithography layer is used to define the areas of the substrate 200 and polysilicon layer 201 that need to be removed or retained in subsequent processes, thereby indirectly defining the location and shape of the vias.

[0059] Then, the substrate 200 exposed by the photolithographic layer and the corresponding polysilicon layer 201 are etched away to form a via 206 that penetrates the substrate 200 and the polysilicon layer 201 and exposes the conductive plug structure 205. The etching process can be one or a combination of dry etching and wet etching. That is, the etching process can be dry etching, wet etching, or a combination of both.

[0060] It should be noted that, in an optional implementation, the side of the substrate 200 away from the polysilicon layer 201 can be thinned before this step is performed, for example, by thinning the substrate through a thinning process, thereby reducing the overall thickness of the substrate and further reducing the overall size of the device.

[0061] In a specific implementation, the thinning process can be, for example, a grinding thinning process, thereby reducing the substrate thickness to the target thickness. In an optional example, after thinning the substrate, the entire surface of the substrate away from the polysilicon layer can be further etched to remove the grinding damage layer on the side of the substrate away from the polysilicon layer, release residual stress, and improve thickness uniformity.

[0062] refer to Figures 8-9 An insulating layer 217 is formed to cover the sidewall of the through hole 206 and the substrate.

[0063] In an optional implementation, the step of forming an insulating layer covering the sidewalls of the through-hole and the substrate may include: forming an initial insulating layer covering the bottom and sidewalls of the through-hole and the substrate; removing the initial insulating layer located at the bottom of the through-hole, leaving the remaining initial insulating layer as the insulating layer. Correspondingly, the process of forming the insulating layer 217 covering the sidewalls of the through-hole 206 and the substrate may, for example, be as follows: refer to Figure 8 This forms an initial insulating layer 207 covering the bottom and sidewalls of the through-hole 206, as well as the substrate.

[0064] In an optional implementation, an initial insulating layer 207 can be formed by uniformly depositing an insulating material on the bottom and sidewalls of the via 206, as well as on the surface of the substrate, using a deposition process (e.g., chemical vapor deposition (CVD), physical vapor deposition (PVD), or atomic layer deposition (ALD)). The initial insulating layer 207 prevents subsequent redistribution layers from making electrical contact with the materials surrounding the via (e.g., the substrate and polysilicon layer structure), thereby ensuring circuit stability.

[0065] refer to Figure 9 Remove the initial insulating layer 207 located at the bottom of the through hole 206, and use the remaining initial insulating layer 207 as the insulating layer 217.

[0066] Remove the initial insulating layer 207 located at the bottom of the via 206 to ensure reliable electrical contact between the subsequent redistribution layer and the conductive plug structure 205 in the target dielectric layer 202.

[0067] The insulating layer 217 may be made of materials such as silicon oxide or silicon nitride.

[0068] It should be noted that the material of the above-mentioned insulating layer is only an optional example. In practical applications, the material of the insulating layer can be selected from various materials well known to those skilled in the art, depending on the actual situation. This application does not limit the material of the insulating layer.

[0069] refer to Figure 10 A redistribution layer 208 is formed to fill the via 206, thereby obtaining the target display packaging module.

[0070] In an optional implementation, a redistribution layer 208 can be deposited, which then contacts the die electrode 203 via a conductive plug structure 205, thereby establishing an electrical connection between the redistribution layer 208 and the die electrode 203. Then, photolithography and etching processes are used to pattern the conductive layer, creating a redistribution lead pattern with a preset configuration, fanning the signal outward to a suitable surface mount location.

[0071] The redistribution layer 208 may include a seed layer and an electrical connection layer. The seed layer is a composite material of one or more of titanium, titanium nitride, tantalum, and tantalum nitride. The electrical connection layer may be a composite material of one or more of gold, silver, copper, and aluminum. When multiple materials are present, they may be an alloy of multiple materials or a stack of multiple materials.

[0072] In an optional implementation, after the step of forming a redistribution layer that fills the via, the method may further include: forming a solder mask layer that exposes a portion of the redistribution layer.

[0073] For details, please refer to Figure 11 A solder mask layer 209 is formed that exposes a portion of the redistribution layer 208.

[0074] The solder mask layer 209 provides protection for the packaging substrate, thereby ensuring the electrical functions of the display packaging module and preventing short circuits, leakage, etc. in the electrical circuits. The area of ​​the redistribution layer 208 exposed by the solder mask layer 209 is designated as the area for external terminals, which are used to achieve direct connection with external electrical connection structures. In specific implementations, the external terminals can be, for example, solder balls, planar pads, or three-dimensional pads.

[0075] In this configuration, when the external terminal is a solder ball, the solder mask layer 209 exposes a portion of the redistribution layer so that the solder ball can connect to the exposed redistribution layer. Correspondingly, this structure can be understood as a BGA (Ball Grid Array) package type. When the external terminal is a planar pad, the exposed redistribution layer of the solder mask layer 209 can serve as the pad. Correspondingly, this structure can be understood as an LGA (Land Grid Array) package type. When the external terminal is a 3D pad, the 3D pad can be implemented based on the exposed redistribution layer. Correspondingly, this structure can be understood as a QFN-like package type. The placement of the solder ball, planar pad, or 3D pad is determined based on a preset placement scheme.

[0076] In an optional implementation, the front and back sides of the target display packaging module are respectively divided into a light-emitting area and an edge area surrounding the light-emitting area. The edge area of ​​the back side of the target display packaging module includes a stepped area. The top surface of the stepped area on the back side of the target display packaging module is lower than the top surface of the light-emitting area, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area. The chip electrode is located in the stepped area.

[0077] In a specific layout scheme, the core electrode can be located on one side of the substrate, or evenly distributed on opposite sides of the substrate, or evenly surrounding the periphery of the substrate. It is understood that the position of the core electrode can define the location of the stepped area, and the projection of the stepped area onto the substrate completely covers the projection of the core electrode onto the substrate. It should be noted that the stepped area can extend beyond the projection area of ​​the core electrode; for example, the stepped area can surround the light-emitting area, thereby facilitating the cutting of the display packaging module.

[0078] For details, please refer to Figure 12 and Figure 13 , Figure 12 This is a first structural schematic diagram of the display packaging module provided in an embodiment of this application. Figure 13 for Figure 12 Enlarged view of the area within the dashed box. The side of the display packaging module with the light-transmitting protective layer 204 is the front side, and the side with the substrate is the back side. The front and back sides of the display packaging module are respectively divided into a light-emitting area 23 and an edge area 24 surrounding the light-emitting area 23. The edge area 24 of the back side of the display packaging module includes a stepped area 25. The top surface of the stepped area 25 on the back side of the display packaging module is lower than the top surface of the light-emitting area 23, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area 23. The chip electrode 203 is located in the stepped area 25.

[0079] The light-emitting area 23 is the area where the light-emitting array is disposed. Since the light-emitting area 23 is usually located in the central region of the substrate, the edge area 24 is the area surrounding the light-emitting area 23. The auxiliary devices are usually disposed in the edge area 24.

[0080] Further reference Figure 14 and Figure 15 , Figure 14 This is a schematic diagram of the second structure of the display packaging module provided in an embodiment of this application. Figure 15 for Figure 14 Enlarged view of the area within the dashed box. The side of the display packaging module with the light-transmitting protective layer 204 is the front side, and the side with the substrate is the back side. The front and back sides of the display packaging module are respectively divided into a light-emitting area 23 and an edge area 24 surrounding the light-emitting area 23. The edge area 24 of the back side of the display packaging module includes a stepped area 25. The top surface of the stepped area 25 on the back side of the display packaging module is lower than the top surface of the light-emitting area 23, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area 23. The chip electrode 203 is located in the stepped area 25.

[0081] Furthermore, refer to Figure 16 and Figure 17 , Figure 16 This is a schematic diagram of the third structure of the display packaging module provided in the embodiments of this application. Figure 17 for Figure 16 Enlarged view of the area within the dashed box. The side of the display packaging module with the light-transmitting protective layer 204 is the front side, and the side with the substrate is the back side. The front and back sides of the display packaging module are respectively divided into a light-emitting area 23 and an edge area 24 surrounding the light-emitting area 23. The edge area 24 of the back side of the display packaging module includes a stepped area 25. The top surface of the stepped area 25 on the back side of the display packaging module is lower than the top surface of the light-emitting area 23, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area 23. The chip electrode 203 is located in the stepped area 25.

[0082] like Figure 13 , Figure 15 and Figure 17 As shown, since the etching rate of the conductive plug structure 205 is much lower than that of the substrate 200 and the polysilicon layer 201, various etching endpoints can be flexibly selected when etching the via. Etching can be terminated at the surface of the conductive plug, or it can be over-etched to slightly remove some material from the top of the conductive plug. This application does not require strict limitation on the etching depth, effectively relaxing the etching process precision limit and improving process tolerance and mass production yield.

[0083] It is understood that the display packaging module of this application is a display unit that can be used independently and electrically connected to the outside, and is used as the core component of the micro-projection optical engine to achieve imaging in augmented reality (AR) near-eye display devices by precisely coupling with components such as optical waveguides and lenses.

[0084] As can be seen, in the solution provided by the embodiments of this application, the initial display packaging module is provided with a conductive plug structure that is connected to the chip electrode and penetrates the target dielectric layer. The conductive plug can simultaneously serve as a vertical conductive path and an etching stop structure. In the process of etching the substrate from the back side to the front side to prepare the via, since the etching rate of the conductive plug structure is less than the etching rate of the substrate, the substrate has a higher etching selectivity relative to the conductive plug structure. Based on this characteristic, the conductive plug structure can be used as an etching stop structure, so that the etching rate is reduced when the etching reaches the conductive plug structure, thereby avoiding over-etching and damage to the chip electrode during the etching process from the back side to the front side, and thus improving the manufacturing yield of the display packaging module.

[0085] Furthermore, in this scheme, when etching the substrate from the back side to the front side to form a through hole, the etching endpoint can be at the conductive plug structure (i.e., the through hole only exposes the conductive plug structure), or it can continue etching to the core electrode (i.e., the through hole exposes both the conductive plug structure and the core electrode, or only the core electrode). Both etching results meet the requirements of subsequent fabrication, eliminating the need for precise control of the etching depth, reducing the precision constraints of the etching process, thereby improving the process tolerance of the etching process and making it suitable for mass production.

[0086] This application also provides a display packaging module, which is formed according to the method for forming a display packaging module as described above. Specifically, refer to... Figure 18 An exemplary schematic diagram of the fourth structure of a display packaging module is shown. Figure 18 As shown, the display packaging module may include: The substrate includes a substrate 300 and a polycrystalline silicon layer 301 located between the substrate 300 and the target dielectric layer 302. The substrate may be made of one or more of the following materials: silicon, germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate. Alternatively, the substrate may be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The polycrystalline silicon layer 301 may be doped polycrystalline silicon with n-type impurities such as phosphorus or arsenic, or with p-type boron impurities.

[0087] A target dielectric layer 302 is located on the substrate; wherein, a conductive plug structure 305 is provided in the target dielectric layer 302; the material of the target dielectric layer 302 may be silicon oxide.

[0088] In an optional implementation, the number of conductive plug structures 305 can be one or more. For ordinary core electrodes, a one-to-one layout can be adopted, that is, one conductive plug structure is configured under a single core electrode; for core electrodes that need to carry large currents, a one-to-many layout can be adopted, that is, multiple conductive plug structures are configured under a single core electrode, and the multiple conductive plug structures are subsequently connected in parallel at the redistribution layer, thereby reducing the overall conduction resistance and dispersing the thermal stress generated by conduction.

[0089] In optional implementations, when there are multiple conductive plug structures 305, the multiple conductive plug structures 305 are arranged in a linear array, a matrix array, or a ring array. A "ring array" refers to multiple conductive plug structures being distributed circumferentially around the center of the core electrode. In optional implementations, the cross-sectional shape of the conductive plug structure 305 in the direction parallel to the substrate may include, but is not limited to, a circle, a square, a rectangle, or a frustum.

[0090] In optional implementations, the diameter of the conductive plug structure 305 ranges from 0.02 μm to 50 μm. For example, the diameter of the conductive plug structure 305 can be 0.02 μm, 10 μm, 20 μm, 30 μm, 40 μm, or 50 μm, etc.; the depth ranges from 0.02 μm to 200 μm. For example, the depth of the conductive plug structure 305 can be 0.02 μm, 50 μm, 100 μm, 150 μm, or 200 μm, etc. Selecting the above-mentioned size range of the conductive plug structure can both meet the fine processing requirements of small-pitch interconnection of micro electrodes and satisfy the cross-sectional area requirements for high current conduction in power supply and grounding paths.

[0091] In existing technologies, when vertical interconnects and surface mount chips are achieved by leading out the die electrodes through a back redistribution layer (RDL), the back redistribution layer is made of copper. Copper readily diffuses rapidly into silicon or silicon dioxide. Therefore, when using copper to fabricate vertical interconnect structures, a complex diffusion barrier layer needs to be prepared, which not only increases the overall process difficulty but also introduces the risk of leakage. In this application, the conductive plug structure 305 is made of tungsten. This application selects tungsten as the conductive material for vertical interconnects. Tungsten has a coefficient of thermal expansion (CTE ≈ 4.5 × 10⁻⁶). -6 / ℃) and silicon (CTE≈2.6×10 -6 The coefficient of thermal expansion (°C) is highly adaptable, thus avoiding the thermal stress failure and leakage defects that exist when using copper materials to prepare vertical interconnect structures.

[0092] A chip electrode 303 is located on the target dielectric layer 302. The chip electrode 303 is used to electrically lead out auxiliary devices inside the display packaging module, that is, the chip electrode is used to electrically connect the auxiliary devices and the external electrical connection structure of the display packaging module.

[0093] A light-transmitting protective layer 304 is located on the core electrode 303.

[0094] In an optional implementation, the light-transmitting protective layer 304 and the core electrode 303 are connected by a damming adhesive 21 and an adhesive 22. Specifically, the thickness of the damming adhesive 21 determines the vertical height of the cavity. The light-transmitting protective layer 304 is bonded to the upper surface of the damming adhesive 21, and the core electrode 303 is bonded to the lower surface by the adhesive 22, thus sealing the central light-emitting pixel into an independent, sealed cavity. The cavity is generally filled with dry inert gas or evacuated to isolate moisture and oxygen, thereby ensuring that the light-emitting pixel is not oxidized or corroded.

[0095] The damming adhesive 21 is a rigid encapsulating colloid, while the core electrode 303 is a hard metal layer. Direct bonding between the two results in poor adhesion and easy delamination. Therefore, the adhesive 22 acts as an bonding medium, firmly adhering the damming adhesive 21 while simultaneously bonding the core electrode 303.

[0096] In an optional implementation, the light-transmitting protective layer 304 has the same outer dimensions as the substrate, with the two structures completely overlapping; alternatively, the outer dimensions of the light-transmitting protective layer 304 are slightly larger than the outer dimensions of the substrate. Since the display area (i.e., the light-emitting pixel area) needs to maintain high light transmittance and high flatness optical properties, a transparent cover layer (e.g., cover glass) can be used as the light-transmitting protective layer, thereby protecting the display packaging module while ensuring the light transmittance of the light-emitting pixels. In a specific example, the material of the light-transmitting protective layer can be glass or sapphire, etc.

[0097] Through the substrate, and exposing the conductive plug structure and / or the core electrode via a through-hole. Figure 18 The example shown is a through-hole that penetrates the substrate and exposes the conductive plug structure.

[0098] A via is formed through the substrate and exposes the conductive plug structure 305; wherein the conductive plug structure 305 is connected to the die electrode 303. The substrate includes a substrate 300 and a polysilicon layer 301 located between the substrate 300 and the target dielectric layer 302; the via penetrates the substrate 300 and the polysilicon layer 301.

[0099] An insulating layer 317 covers the sidewalls of the through-hole and the substrate. The insulating layer 317 may be made of materials such as silicon oxide or silicon nitride.

[0100] It should be noted that the material of the above-mentioned insulating layer is only an optional example. In practical applications, the material of the insulating layer can be selected from various materials well known to those skilled in the art, depending on the actual situation. This application does not limit the material of the insulating layer.

[0101] Redistribution layer 308 that fills the via.

[0102] In an optional implementation, a redistribution layer 308 can be deposited, which then contacts the die electrode 303 via a conductive plug structure 305, thereby establishing an electrical connection between the redistribution layer 308 and the die electrode 303. Then, photolithography and etching processes are used to pattern the conductive layer, creating a redistribution lead pattern with a preset configuration, fanning the signal outward to a suitable surface mount location.

[0103] The redistribution layer 308 may include a seed layer and an electrical connection layer. The seed layer is a composite material of one or more of titanium, titanium nitride, tantalum, and tantalum nitride. The electrical connection layer may be a composite material of one or more of gold, silver, copper, and aluminum. When multiple materials are present, they may be an alloy of multiple materials or a stack of multiple materials.

[0104] In an optional implementation, the display packaging module may further include a solder mask layer 309 that exposes a portion of the redistribution layer 308.

[0105] The solder mask layer 309 is used to provide protection for the packaging substrate, thereby ensuring the electrical function of the display packaging module and preventing short circuits, leakage, etc. in the electrical circuits. The area of ​​the redistribution layer 308 exposed by the solder mask layer 309 is the area for setting external terminals. In specific implementations, the external terminals can be, for example, solder balls, planar pads, or three-dimensional pads.

[0106] In this configuration, when the external terminal is a solder ball, the solder mask layer 309 exposes a portion of the redistribution layer so that the solder ball can connect to the exposed redistribution layer. Correspondingly, this structure can be understood as a BGA (Ball Grid Array) package type. When the external terminal is a planar pad, the exposed redistribution layer of the solder mask layer 309 can serve as the pad. Correspondingly, this structure can be understood as an LGA (Land Grid Array) package type. When the external terminal is a 3D pad, the 3D pad can be implemented based on the exposed redistribution layer. Correspondingly, this structure can be understood as a QFN-like package type. The placement of the solder ball, planar pad, or 3D pad is determined based on a preset placement scheme.

[0107] In an optional implementation, the initial display packaging module consists of a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode. The side of the initial display packaging module with the light-transmitting protective layer is the front side, and the side of the initial display packaging module with the substrate is the back side. The target display packaging module consists of a display packaging module with a redistribution layer that fills the vias. The front and back sides of the target display packaging module are respectively divided into a light-emitting area and an edge area surrounding the light-emitting area. The edge area of ​​the back side of the target display packaging module includes a stepped area. The top surface of the stepped area on the back side of the target display packaging module is lower than the top surface of the light-emitting area, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area. The chip electrode is located in the stepped area. The light-emitting area is the region where the light-emitting array is disposed, and since the light-emitting area is usually located in the central region of the substrate, the edge area is the region surrounding the light-emitting area. Auxiliary devices are usually disposed in the edge area.

[0108] In a specific layout scheme, the core electrode can be located on one side of the substrate, or evenly distributed on opposite sides of the substrate, or evenly surrounding the periphery of the substrate. It is understood that the position of the core electrode can define the location of the stepped area, and the projection of the stepped area onto the substrate completely covers the projection of the core electrode onto the substrate. It should be noted that the stepped area can extend beyond the projection area of ​​the core electrode; for example, the stepped area can surround the light-emitting area, thereby facilitating the cutting of the display packaging module.

[0109] This application also provides a display device, including: a display packaging module as described in the above embodiments.

[0110] The display device may include a flexible circuit board assembly, including connection points that are adapted to each three-dimensional electrical connection structure of the display packaging module, for establishing an electrical connection with the display packaging module.

[0111] As can be seen, in the display device provided in this application embodiment, the display packaging module can be independently manufactured and used independently, possessing the capability to operate independently when powered on; therefore, the display packaging module can be used separately from the flexible circuit board assembly. When a combined product of the display packaging module and the flexible circuit board assembly is required, the three-dimensional electrical connection structure of the display packaging module can be adapted to the connection points of the flexible circuit board assembly to achieve combined use of the two; when the flexible circuit board assembly is not required, the display packaging module can be provided directly, allowing for flexible design and application in different scenarios; this avoids the limitation of the application scenarios of the display packaging module caused by the integrated use of the two in related technologies.

[0112] This application also provides a display device, including: a display packaging module as described in the above embodiments.

[0113] The display device is a device with image / video / information display functions. For example, it can be an AR / VR (Virtual Reality) near-eye display device, a smartwatch display device, a mobile phone display device, an in-vehicle display device, a television display device, a monitor, an industrial control display device, etc.

[0114] This application also provides an optoelectronic device, including: a display packaging module as described in the above embodiments.

[0115] The display packaging module can be applied to optoelectronic devices in the optoelectronic field, such as vehicle lights, wearable devices, and lighting equipment.

[0116] This application also provides a terminal, including: a display packaging module as described in the above embodiments.

[0117] The terminal is a complete device that is designed for end users and can be used independently, including but not limited to consumer electronics terminals, vehicle terminals, home display terminals, industrial control terminals, medical display terminals, and smart home terminals.

[0118] It should be noted that MicroLED microdisplay chips are devices designed for high-end displays in the future, with their core characteristics lying in chip size and light emission method. Specifically, their chip size can range from 1 to 100 micrometers, with a typical size usually less than 50 micrometers. They achieve self-illumination through the configuration of independent driving circuits, allowing them to display images by forming independent pixels (usually one pixel corresponds to one driving circuit), resulting in ultra-high precision and extremely high speed display characteristics.

[0119] The foregoing describes multiple embodiment schemes provided by the embodiments of this application. The optional methods described in each embodiment scheme can be combined and cross-referenced with each other without conflict, thereby extending to a variety of possible embodiment schemes. These can all be considered as the embodiment schemes disclosed and published by the embodiments of this application.

[0120] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. A method for forming a display packaging module, characterized in that, include: An initial display packaging module is provided, the initial display packaging module including a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode; wherein, a conductive plug structure connected to the chip electrode and penetrating the target dielectric layer is disposed in the target dielectric layer; the side of the initial display packaging module where the light-transmitting protective layer is disposed is the front side, and the side of the initial display packaging module where the substrate is disposed is the back side; Using the conductive plug structure as the etching stop structure, the substrate is etched from the back side to the front side to form a through-hole that penetrates the substrate and exposes the conductive plug structure and / or the chip electrode; wherein the etching rate of the conductive plug structure is less than the etching rate of the substrate; An insulating layer is formed to cover the sidewalls of the through-hole and the substrate; A redistribution layer is formed to fill the vias, resulting in the target display package module.

2. The method for forming a display packaging module as described in claim 1, characterized in that, The number of the conductive plug structures is one or more; When there are multiple conductive plug structures, the multiple conductive plug structures are arranged in a linear array, a matrix array, or a ring array.

3. The method for forming a display packaging module as described in claim 2, characterized in that, The substrate includes a substrate and a polycrystalline silicon layer located between the substrate and the target dielectric layer; In the step of etching the substrate from the back side to the front side using the conductive plug structure as the etching stop structure, the etching rate of the conductive plug structure is less than the etching rate of the substrate and the polysilicon layer.

4. The method for forming a display packaging module as described in claim 1, characterized in that, The diameter of the conductive plug structure ranges from 0.02μm to 50μm, and the depth ranges from 0.02μm to 200μm.

5. The method for forming a display packaging module as described in claim 1, characterized in that, The conductive plug structure has a cross-sectional shape that includes a circle, a square, a rectangle, or a frustum shape in the direction parallel to the substrate.

6. The method for forming a display packaging module as described in claim 1, characterized in that, The conductive plug structure is made of tungsten.

7. The method for forming a display packaging module as described in claim 1, characterized in that, The step of forming an insulating layer covering the sidewalls of the through-hole and the substrate includes: An initial insulating layer is formed covering the bottom and sidewalls of the through-hole, as well as the substrate; Remove the initial insulating layer located at the bottom of the through hole, and use the remaining initial insulating layer as the insulating layer.

8. The method for forming a display packaging module as described in claim 1, characterized in that, After the step of forming the redistribution layer filling the via, the method further includes: A solder mask layer is formed that exposes a portion of the redistribution layer.

9. The method for forming a display packaging module as described in claim 1, characterized in that, The front and back sides of the target display packaging module are respectively divided into a light-emitting area and an edge area surrounding the light-emitting area. The edge area of ​​the back side of the target display packaging module includes a stepped area. The top surface of the stepped area on the back side of the target display packaging module is lower than the top surface of the light-emitting area, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area. The chip electrode is located in the stepped area.

10. A display packaging module, formed according to the method for forming a display packaging module as described in any one of claims 1-9, characterized in that, include: Base; A target dielectric layer located on a substrate; wherein a conductive plug structure is provided in the target dielectric layer; Core electrodes located on the target dielectric layer; A light-transmitting protective layer located on the core electrode; Through the substrate, and exposing the conductive plug structure and / or the core electrode; wherein the conductive plug structure is connected to the core electrode; An insulating layer covering the sidewalls of the through-hole and the substrate; A redistribution layer that fills the via.

11. The display packaging module as described in claim 10, characterized in that, The number of the conductive plug structures is one or more; When there are multiple conductive plug structures, the multiple conductive plug structures are arranged in a linear array, a matrix array, or a ring array.

12. The display packaging module as described in claim 11, characterized in that, The substrate includes a substrate and a polycrystalline silicon layer located between the substrate and the target dielectric layer; The via penetrates the substrate and the polysilicon layer.

13. The display packaging module as described in claim 10, characterized in that, The diameter of the conductive plug structure ranges from 0.02μm to 50μm, and the depth ranges from 0.02μm to 200μm.

14. The display packaging module as described in claim 10, characterized in that, The conductive plug structure has a cross-sectional shape that includes a circle, a square, a rectangle, or a frustum shape in the direction parallel to the substrate.

15. The display packaging module as described in claim 10, characterized in that, The conductive plug structure is made of tungsten.

16. The display packaging module as described in claim 10, characterized in that, Also includes: The solder mask layer of a portion of the redistribution layer is exposed.

17. The display packaging module as described in claim 10, characterized in that, The initial display packaging module is defined by a substrate, a target dielectric layer on the substrate, a chip electrode on the target dielectric layer, and a light-transmitting protective layer on the chip electrode. The side of the initial display packaging module with the light-transmitting protective layer is defined as the front side, and the side of the initial display packaging module with the substrate is defined as the back side. The target display packaging module is defined by a redistribution layer that fills the vias. The front and back sides of the target display packaging module are respectively divided into a light-emitting area and an edge area surrounding the light-emitting area. The edge area of ​​the back side of the target display packaging module includes a stepped area. The top surface of the stepped area on the back side of the target display packaging module is lower than the top surface of the light-emitting area, so that the thickness of the substrate in the stepped area is lower than the thickness of the light-emitting area. The chip electrode is located in the stepped area.

18. A display device, characterized in that, include: The display packaging module as described in any one of claims 10-17.

19. A display device, characterized in that, include: The display packaging module as described in any one of claims 10-17.

20. A photoelectric device, characterized in that, include: The display packaging module as described in any one of claims 10-17.

21. A terminal, characterized in that, include: The display packaging module as described in any one of claims 10-17.

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