A 3c-sic-based post-al ion implantation activation annealing process

Abstract

This disclosure belongs to the field of semiconductor device technology, and specifically relates to an activation annealing process based on Al ion implantation in 3C-SiC. The activation annealing process of this disclosure is based on a homoepitaxial 3C-SiC system, depositing an 800-1000 nm SiO2 layer or other high-temperature resistant dielectric protective layer on the p-region formed by Al ion implantation; after densifying the protective layer through medium-temperature vacuum annealing, activation annealing is performed in an Ar atmosphere at 1100℃-1500℃. This disclosure utilizes the homoepitaxial structure to eliminate substrate thermal mismatch limitations, and, in conjunction with the dense protective layer to suppress high-temperature silicon volatilization, achieves sufficient lattice damage repair and efficient Al atom substitution activation, enabling the p-region Hall mobility to reach 100-300 cm² / Vs. This process avoids complex carbon film deposition and removal steps, is highly compatible with existing silicon-based production lines, significantly reduces equipment costs, and improves production efficiency.

Description

Technical Field

[0001] This disclosure belongs to the field of semiconductor device technology, and in particular relates to an Al ion implantation post-activation annealing process based on 3C-SiC. Background Technology

[0002] Silicon carbide (SiC), as a third-generation wide-bandgap semiconductor material, has significant application value in high-voltage, high-frequency, and high-temperature power devices. Among them, 3C-SiC (cubic silicon carbide) is considered an important material platform for future integrated power electronic devices due to its high carrier mobility, good compatibility with silicon-based processes, and relatively low epitaxial defect density. In the fabrication of 3C-SiC devices, ion implantation is the core method for achieving localized doping, and the subsequent thermal activation annealing directly determines the electrical activation rate of the doped atoms, the quality of lattice damage repair, and the final electrical performance of the device. Aluminum (Al), as the most commonly used p-type dopant in 3C-SiC, has a high substitutional activation energy in the lattice and usually requires thermal annealing at high temperatures to achieve effective electrical activation.

[0003] However, traditional 3C-SiC devices mostly employ a heteroepitaxial growth process on silicon (Si) substrates. Due to the significant lattice mismatch (approximately 20%) and difference in thermal expansion coefficients between Si and 3C-SiC, large thermal stresses easily accumulate at the interface during high-temperature heat treatment, leading to microcracks, dislocation proliferation, and even film peeling in the epitaxial layer. To avoid structural failure, the activation annealing temperature of heteroepitaxial 3C-SiC has long been limited to below 1300℃. Within this limited temperature window, lattice damage caused by ion implantation is difficult to fully recombine, Al atom substitution activation is incomplete, and residual defects and unactivated impurities in the bulk form strong ionized impurity scattering centers; simultaneously, surface silicon volatilization at high temperatures leads to carbon enrichment and interface state deterioration, further exacerbating carrier interface scattering and channel mobility degradation. Consequently, the Hall mobility of conventional 3C-SiC p-type regions is generally low, making it difficult to meet the transport requirements of high-performance power devices.

[0004] From the perspective of carrier transport physics, the improvement of Hall mobility is highly dependent on the restoration of lattice integrity and the suppression of interface scattering. In heterogeneous substrates where high-temperature annealing is impossible due to thermal mismatch, lattice defects cannot be fully annealed and reorganized, and doped atoms cannot fully occupy substitution sites, resulting in persistently high scattering center density. Therefore, there is an urgent need for a process route that can overcome the limitations of substrate thermal mismatch and implement activation annealing in a higher temperature range (1100℃~1500℃). If a homoepitaxial system perfectly matched to the 3C-SiC lattice and thermal expansion is used, supplemented by a dense protective layer that can withstand this temperature window, sufficient thermal budget can be provided for lattice damage repair and efficient Al atom activation without inducing structural stress, thereby fundamentally weakening bulk and interface scattering and achieving a significant leap in Hall mobility. In view of this, there is an urgent need in the field for a new activation annealing process that combines homoepitaxial structure with high-temperature resistant dielectric protection to fill the process gap for efficient activation of 3C-SiCp-type doped materials.

[0005] In view of this, this disclosure is hereby made. Summary of the Invention

[0006] The purpose of this disclosure is to overcome the shortcomings of the prior art and provide an Al ion implantation post-activation annealing process based on 3C-SiC, which breaks through the temperature limit of traditional Si substrate heteroepitaxialization, suppresses high-temperature surface degradation, achieves full repair of lattice damage and efficient activation of Al atoms, and simplifies the process flow and reduces the investment cost of production line equipment.

[0007] To achieve the above technical objectives, this disclosure provides the following technical solution: An Al ion implantation followed by activation annealing process based on 3C-SiC includes the following steps: p-regions are formed on the epitaxial layer of a 3C-SiC epitaxial wafer by Al ion implantation. A protective layer is formed on the 3C-SiC epitaxial wafer after the formation of the p-region; The 3C-SiC epitaxial wafer after the formation of the protective layer is subjected to activation annealing; The 3C-SiC epitaxial wafer uses 3C-SiC as a substrate and homogeneous 3C-SiC as an epitaxial layer.

[0008] According to some embodiments of this disclosure, the 3C-SiC epitaxial wafer uses N-type 3C-SiC as the substrate and homogeneous N-type 3C-SiC as the epitaxial layer. In some embodiments, the substrate and the epitaxial layer are homogeneous heavily doped N-type 3C-SiC.

[0009] According to some embodiments of this disclosure, the peak doping concentration of the p-region is 2 × 10⁻⁶. 19 ~3×10 19 cm-3 .

[0010] According to some embodiments of this disclosure, the junction depth of the p-region is 1.2~1.5μm.

[0011] According to some embodiments of this disclosure, the material of the protective layer is selected from any one of SiO2, Si3N4, and Al2O3. These materials exhibit excellent thermal stability, low coefficient of thermal expansion, and can effectively suppress silicon volatilization on the SiC surface within an annealing window of 1100~1500℃.

[0012] According to some embodiments of this disclosure, the thickness of the protective layer is 800-1000 nm. In some preferred embodiments, the thickness of the protective layer is 850-950 nm.

[0013] According to some embodiments of this disclosure, forming the protective layer includes depositing the protective layer on the surface of the 3C-SiC epitaxial wafer after the formation of the p-region using plasma-enhanced vapor deposition (PECVD), atomic layer deposition (ALD), or low-pressure chemical vapor deposition (LPCVD). These processes are advantageous for achieving high-quality protective layer deposition. In some embodiments, plasma-enhanced vapor deposition (PECVD) is used to deposit the protective layer on the surface of the 3C-SiC epitaxial wafer after the formation of the p-region.

[0014] According to some embodiments of this disclosure, forming the protective layer includes densifying the deposited protective layer. In some embodiments, a thermal annealing process is used to densify the deposited protective layer. In some embodiments, the densification process includes annealing at 900-970°C for 50-70 minutes. In some embodiments, the densification process is performed under vacuum conditions.

[0015] According to some embodiments of this disclosure, the 3C-SiC epitaxial wafer after the protective layer is formed is activated by heat treatment. In some embodiments, the activation annealing temperature is 1100-1500℃, preferably 1300-1500℃, and more preferably 1400-1500℃. In some embodiments, the activation annealing time is 25-35 minutes. In some embodiments, the activation annealing is performed under an Ar atmosphere.

[0016] Compared with the prior art, this disclosure has at least the following beneficial effects: Beneficial effects: 1. Significantly Enhanced Hall Mobility: This disclosure utilizes activated annealing at 1100℃~1500℃ in a homoepitaxial 3C-SiC system, fully leveraging the thermal stress release characteristics of mismatch-free interfaces to ensure sufficient recombination energy for interstitial-vacancy defect pairs generated during implantation, resulting in a significant restoration of lattice integrity. Simultaneously, the high-temperature thermal budget enables Al atoms to overcome diffusion barriers and efficiently occupy substitutional sites, significantly improving the electrical activation rate. The protective layer maintains surface stoichiometry during annealing, preventing carbon segregation and interface state deterioration. The dual weakening of bulk defect scattering and interface Coulomb scattering significantly reduces the obstruction of holes in the transport path, ultimately enabling the Hall mobility of Al-implanted p-regions to stably reach 100~300 cm² / V. The doping level is far superior to that of traditional heteroepitaxial low-temperature processes and also better than that of similar 4H-SiC p-type doping.

[0017] 2. Process compatibility and cost advantages: This disclosure uses PECVD to deposit SiO2 mask layer, which makes full use of its process compatibility with mature silicon-based production lines, avoiding the introduction of dedicated carbon film deposition and plasma ashing equipment. This not only significantly reduces the investment cost of production line equipment, but also effectively shortens the process cycle and improves device manufacturing yield and production efficiency.

[0018] 3. Low thermal budget requirements and reduced equipment threshold: The activation annealing temperature window (1100~1500℃) disclosed in this paper is much lower than the 1700~1800℃ required for conventional activation of 4H-SiC, which greatly reduces the dependence on ultra-high temperature annealing equipment, reduces equipment depreciation and maintenance costs, and is more compatible with the thermal process modules of existing semiconductor production lines, which is conducive to the large-scale mass production of 3C-SiC devices. Attached Figure Description

[0019] To more clearly illustrate the technical solutions in the specific embodiments of this disclosure or the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0020] Figure 1 This illustrates the step of forming a p-region on a 3C-SiC epitaxial layer by ion implantation in the Al ion implantation post-activation annealing process based on 3C-SiC according to an embodiment of the present disclosure; Figure 2 This is a schematic diagram of the mask structure formed after depositing a protective layer on the 3C-SiC epitaxial wafer in the Al ion implantation and activation annealing process based on 3C-SiC according to an embodiment of the present disclosure. Figure 3This illustrates the steps of densifying the protective layer in the Al ion implantation post-activation annealing process based on 3C-SiC according to an embodiment of the present disclosure; Figure 4 The present invention illustrates the steps of activating and annealing a densified epitaxial wafer in an Al ion implantation post-activation annealing process based on 3C-SiC according to an embodiment of the present disclosure.

[0021] Figure 5 The surface morphology of a 3C-SiC epitaxial wafer obtained by the activation annealing process as a comparative example is magnified 50 times under an optical microscope. Figure 6 The image shows the surface morphology of the 3C-SiC epitaxial wafer obtained by the activation annealing process in Example 1, magnified 50 times under an optical microscope.

[0022] Explanation of reference numerals in the attached figures: 1. 3C-SiC epitaxial layer; 2. p-type region; 3. 3C-SiC substrate; 4. SiO2 protective layer. Detailed Implementation

[0023] It should be noted that the following detailed descriptions are illustrative and intended to provide further explanation of this application. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains.

[0024] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the exemplary embodiments according to this application. As used herein, the singular form includes the plural form unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used herein, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof. Unless otherwise stated, all parts, percentages, and ratios used herein are based on mass meters.

[0025] In the description of this disclosure, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and are not intended to indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present invention.

[0026] Furthermore, it should be understood that the one or more method steps mentioned in this disclosure do not preclude the existence of other method steps before or after the combined steps, or the insertion of other method steps between these explicitly mentioned steps, unless otherwise stated; and unless otherwise stated, the numbering of each method step is merely a convenient tool for identifying each method step, and not for limiting the order of the method steps or limiting the scope of implementation of this disclosure. Changes or adjustments to their relative relationships, without substantially altering the technical content, should also be considered as within the scope of implementation of this disclosure.

[0027] The "range" disclosed in this paper is defined by a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, which define the boundaries of the specific range. Ranges defined in this way can include or exclude endpoints and can be combined arbitrarily; that is, any lower limit can be combined with any upper limit to form a range. For example, if 60 is listed for a specific parameter... 120 and 80 The range of 110 is understood to be 60. 110 and 80 The range of 120 is also expected. Furthermore, if the minimum range values ​​1 and 2 are listed, and if the maximum range values ​​3, 4, and 5 are listed, then the following ranges are all expected: 1 3.1 4.1 5.2 3, 2 4 and 2 5. In this document, unless otherwise specified, the numerical range "a" is defined as follows: "b" represents a shortened representation of any combination of real numbers from a to b, where both a and b are real numbers. For example, the numerical range "0" represents a combination of real numbers from a to b. "5" indicates that all "0"s have been listed in this article. All real numbers between "5" and "0". "5" is simply an abbreviation for these numerical combinations. In addition, when a parameter is expressed as an integer greater than or equal to 2, it is equivalent to disclosing that the parameter is, for example, an integer such as 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0028] Furthermore, the numerical ranges and parameters used to define this disclosure are approximate values, and the relevant values ​​in the specific embodiments have been presented as precisely as possible. However, any numerical value inevitably contains standard deviations due to individual test methods. Therefore, unless explicitly stated otherwise, it should be understood that all ranges, quantities, values, and percentages used in this disclosure are modified with the word "approximately." Here, "approximately" generally means an actual value within plus or minus 10%, 5%, 1%, or 0.5% of a particular value or range.

[0029] This disclosure provides an Al ion implantation followed by activation annealing process based on 3C-SiC. This process is implemented in a homoepitaxial 3C-SiC system, breaking through the temperature limitations of traditional Si substrate heteroepitaxialization and raising the activation annealing temperature window to 1100℃~1500℃. By introducing a protective layer that can withstand this temperature window, high-temperature surface degradation is effectively suppressed, achieving full repair of lattice damage and efficient activation of Al atoms, resulting in a p-region Hall mobility of 100~300 cm² / V. This also simplifies the process flow and reduces the investment cost of production line equipment.

[0030] In some implementations, the process disclosed herein is based on the construction of an activation annealing mask structure using a homoepitaxial 3C-SiC system, which completely eliminates the lattice and thermal expansion mismatch problem of heteroepitaxial Si substrate, providing a structural stability basis for high-temperature annealing at 1100℃~1500℃.

[0031] In some implementations, the process disclosed herein uses an 800-1000 nm dense SiO2 layer (or an equivalent high-temperature resistant dielectric protective layer) to cover the p-region, effectively suppressing silicon volatilization and surface reconstruction over a wide temperature range, ensuring that the annealing process focuses on in-cell lattice repair.

[0032] In some embodiments, the process disclosed herein sets the activation annealing temperature window to 1100℃~1500℃, taking into account both the full substitution activation of Al atoms and the intrinsic thermal stability of 3C-SiC, and the process thermal budget is significantly lower than the conventional activation temperature of 4H-SiC.

[0033] The technical solutions of this disclosure will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of this disclosure, not all embodiments. Based on the embodiments of this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0034] Unless otherwise stated, all reagents used in the examples are commercially available or synthesized using conventional methods and are ready for use without further processing, as are the instruments used in the examples.

[0035] Example 1 This embodiment provides an Al ion implantation followed by activation annealing process based on 3C-SiC, including the following steps: Step 1: Using ion implantation, a p-type region 2 is formed on the epitaxial layer 1 of an N-type homogeneous 3C-SiC epitaxial wafer (whose substrate 3 and epitaxial layer 1 are homogeneous heavily doped N-type 3C-SiC). Figure 1 The peak doping concentration of p-type region 2 is 2 × 10⁻⁶. 19 cm-3 ~3×10 19 cm -3 The junction depth is controlled at 1.2~1.5μm.

[0036] Step 2: Using PECVD or other processes capable of dielectric deposition, deposit an 800-1000 nm SiO2 layer or other alternative protective layer 4 on the surface of the unannealed epitaxial wafer after implantation, forming a layer as shown in Figure 4. Figure 2 The mask structure shown is for Al ion implantation followed by activation annealing of 3C-SiC, wherein Layer 1 is an N-type heavily doped 3C-SiC homogeneous substrate 3; Layer 2 is an N-type 3C-SiC homogeneous epitaxial layer 1 before ion implantation; Layer 3 is a p-type region 2 formed by Al ion implantation process; and Layer 4 is a deposited protective layer 4.

[0037] Step 3: The deposited protective layer 4 is densified by thermal annealing at 900℃~970℃ in a vacuum for 60 minutes, causing the protective layer 4 network to shrink and the structure to become denser. Figure 4 ).

[0038] Step 4: The densified epitaxial wafer is activated and annealed using a heat treatment process at 1500℃ for 30 minutes under an Ar atmosphere. Figure 5 ), to complete lattice repair and Al doping activation.

[0039] Example 2 Except for the activation annealing temperature of 1100℃ in step 4, the other steps and operations are the same as in Example 1.

[0040] Comparative Example Except for the absence of step 2 and therefore the absence of protective layer 4, the other steps and operations are the same as in Example 1.

[0041] Test case The 3C-SiC epitaxial wafers obtained by the activation annealing process in Examples 1, 2 and the comparative example were tested respectively.

[0042] The surface morphology was examined using an optical microscope, and the results are as follows: Figure 5 and Figure 6 As shown, the epitaxial wafer without SiO2 mask protection in the comparative example had many pits and protrusions on its surface after annealing at 1500℃ for 30 mins; the 3C-SiC epitaxial wafer in Example 1 had a smooth surface morphology without any abnormalities, indicating that the SiO2 mask can suppress silicon volatilization and surface reconstruction.

[0043] Hall mobility was measured using a Swin Hall 8800 Hall effect meter. The Hall mobilities of the p-regions of the 3C-SiC epitaxial wafers obtained by the activation annealing process in Examples 1 and 2 were 267.5 cm⁻¹, respectively. 2 / V s and 122.1cm 2 / V The 3C-SiC epitaxial wafers obtained by the comparative activation annealing process have no ohmic characteristics in the p region, and the Hall mobility cannot be measured.

[0044] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this disclosure, and are not intended to limit them. Although this disclosure has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this disclosure.

Claims

1. An Al ion implantation followed by activation annealing process based on 3C-SiC, characterized in that, Includes the following steps: p-regions are formed on the epitaxial layer of a 3C-SiC epitaxial wafer by Al ion implantation. A protective layer is formed on the 3C-SiC epitaxial wafer after the formation of the p-region; The 3C-SiC epitaxial wafer after the protective layer is formed is then activated by annealing. The 3C-SiC epitaxial wafer uses 3C-SiC as a substrate and homogeneous 3C-SiC as an epitaxial layer.

2. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The peak doping concentration of the p-region is 2 × 10⁻⁶. 19 ~3×10 19 cm -3 .

3. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The junction depth of the p-region is 1.2~1.5μm.

4. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The material of the protective layer is selected from any one of SiO2, Si3N4 and Al2O3.

5. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The thickness of the protective layer is 800~1000nm.

6. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The formation of the protective layer includes depositing the protective layer on the surface of the 3C-SiC epitaxial wafer after the formation of the p-region using plasma-enhanced vapor deposition, atomic layer deposition, or low-pressure chemical vapor deposition processes.

7. The Al ion implantation followed by activation annealing process according to claim 6, characterized in that, The formation of the protective layer includes densifying the deposited protective layer, which includes annealing at 900~970°C for 50-70 minutes.

8. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The activation annealing temperature is 1100~1500℃.

9. The Al ion implantation followed by activation annealing process according to claim 1, characterized in that, The activation annealing is performed under an Ar atmosphere protection.

10. The Al ion implantation followed by activation annealing process according to any one of claims 1-9, characterized in that, The 3C-SiC epitaxial wafer uses N-type 3C-SiC as the substrate and homogeneous N-type 3C-SiC as the epitaxial layer.

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