Method of manufacturing a semiconductor device

Abstract

A method of manufacturing a semiconductor device includes forming a mask layer on a pattern target layer; exposing and developing the mask layer by using a multi-tone mask to form a first mask pattern region having a first thickness exposing the pattern target layer and a second initial mask pattern region having a second sub-thickness smaller than the first thickness without exposing the pattern target layer; etching the pattern target layer located under the first mask pattern region and the mask layer and the pattern target layer remaining under the second initial mask pattern region to form a first pattern having a first depth and a second pattern having a second depth smaller than the first depth; and removing the mask layer.

Description

Cross-reference of related applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2025-0029200, filed on March 6, 2025, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to methods for manufacturing semiconductor devices, and more specifically, to methods for manufacturing semiconductor devices including patterning processes. Background Technology

[0003] Manufacturing semiconductor devices may include a patterning process that involves forming patterns multiple times on a semiconductor substrate (or wafer). An increase in the number of patterning processes during semiconductor device manufacturing may reduce the productivity, reliability, and electrical performance of the semiconductor device. Summary of the Invention

[0004] Various aspects of the present invention provide a method for manufacturing a semiconductor device that can reduce the number of patterning processes.

[0005] According to one aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a mask layer on a patterned target layer; exposing and developing the mask layer using a multi-tone mask including white and gray regions to form a first mask pattern region having a first thickness that exposes the patterned target layer and a second initial mask pattern region having a second sub-thickness smaller than the first thickness that does not expose the patterned target layer; etching the patterned target layer located below the first mask pattern region and the mask layer and patterned target layer remaining below the second initial mask pattern region to form a first pattern having a first depth in the patterned target layer and a second pattern having a second depth smaller than the first depth in the patterned target layer; and removing the mask layer.

[0006] According to another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a mask layer on a patterned target layer; exposing and developing the mask layer using a multi-tone mask including a white region and a first gray region to a third gray region to form a first mask pattern region having a first thickness that exposes the patterned target layer and a second initial mask pattern region to a fourth initial mask pattern region having a second sub-thickness to a fourth sub-thickness that is sequentially smaller than the first thickness and does not expose the patterned target layer; etching the patterned target layer located below the first mask pattern region, while simultaneously etching the mask layer and the patterned target layer located below the second initial mask pattern region to the fourth initial mask pattern region to form a first pattern to a fourth pattern having a first depth to a fourth depth that is sequentially smaller; and removing the mask layer.

[0007] According to another aspect of the present invention, a method of manufacturing a semiconductor device includes: forming a high-density mask pattern and a low-density mask pattern separated from each other on a semiconductor substrate, wherein the semiconductor substrate is a pattern target layer, the high-density mask patterns are spaced apart from each other, and the low-density mask patterns are spaced apart from each other; forming a mask layer on the high-density mask pattern and the low-density mask pattern; exposing and developing the mask layer using a multi-tone mask including white areas and gray areas to form a first mask exposure pattern area that exposes the semiconductor substrate and the low-density mask pattern and a second mask pattern area that does not expose the semiconductor substrate or the high-density mask pattern; and etching below the first mask exposure pattern area. The semiconductor substrate is used to form a first initial pattern, and a second mask pattern region is further etched to form a second mask exposure pattern region that exposes a high-density mask pattern and the semiconductor substrate; and the semiconductor substrate located below the first mask exposure pattern region and the first initial pattern is further etched to form a first pattern with a first depth, and the semiconductor substrate located below the high-density mask pattern in the second mask exposure pattern region is etched to form a second pattern with a second depth smaller than the first depth, wherein the first pattern is a first trench pattern, the second pattern is a second trench pattern, a low-density active pattern is formed between the first trench patterns, and a high-density active pattern is formed between the second trench patterns. Attached Figure Description

[0008] The embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which: Figures 1A to 1E This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment; Figure 2 It is shown Figure 1B A planar view of the multi-tone mask used in the exposure process; Figures 3A to 3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment; Figure 4 It is shown Figure 3A A planar view of the multi-tone mask used in the exposure process; Figure 5A This is a perspective view showing the mask pattern region formed on the pattern target layer according to an embodiment; Figure 5B This is a perspective view showing the pattern formed according to the embodiment; Figure 6 This is a plan view illustrating a semiconductor device that can be manufactured according to an embodiment; Figure 7 This is a schematic layout diagram showing the main components of a cell region of a semiconductor device that can be manufactured according to an embodiment; Figure 8AThis is a cross-sectional view showing a semiconductor device that can be manufactured according to an embodiment; Figure 8B yes Figure 8A A magnified view of a portion; Figure 9A This is a cross-sectional view showing a semiconductor device that can be manufactured according to an embodiment; Figure 9B yes Figure 9A A magnified view of a portion; Figures 10A to 10G This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment; Figure 11A , Figure 11B and Figures 12 to 18 It shows the manufacturing process. Figure 8A and Figure 9A A cross-sectional view of the method for using a semiconductor device is shown in the figure; and Figure 19 This is a cross-sectional view showing the cell region and peripheral circuit region of a semiconductor device manufactured according to an embodiment. Detailed Implementation

[0009] Hereinafter, embodiments of the inventive concept are described in detail with reference to the accompanying drawings. Embodiments of the inventive concept can be implemented by a single embodiment described in conjunction with the various drawings, and also by a combination of more than one embodiment described in more than one example depicted in the various drawings. Therefore, the technical concept of the inventive concept should not be interpreted as one of the described embodiments.

[0010] In this document, unless the context clearly indicates otherwise, the singular form of a component may include the plural form. In this document, the accompanying drawings are exaggerated to more clearly illustrate the inventive concept.

[0011] In this document, the terms "first," "second," etc., are used to describe various elements or components, but it will be understood that these elements or components are not limited by these terms. These terms are only used to distinguish one element or component from another. Therefore, within the technical concept of the present invention, the first element or first component mentioned below may also be described as a second element or second component. The terms "first," "second," etc., may be used purely as a naming convention, and therefore even if the "first" of the same named item is not listed in the claims, the claims may describe the "second" item for naming purposes.

[0012] Throughout this specification, when a component is described as “comprising” a particular element or group of elements, it will be understood that, unless the context otherwise indicates, the component is formed solely by that element or group of elements, or that the element or group of elements may be combined with other elements to form the component. On the other hand, the term “composed of” indicates that a component is formed solely by the listed element(s).

[0013] Figures 1A to 1E This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment, and Figure 2 It is shown Figure 1B A planar image of a multi-tone mask used in the exposure process.

[0014] The first, second, and other steps described below have a sequential meaning, but the inventive concept is not limited thereto. Figures 1A to 1E In this context, the X direction and Y direction refer to the first horizontal direction and the second horizontal direction, which can be perpendicular to each other, respectively, and the Z direction can be the direction perpendicular to the plane defined by the X direction and Y direction.

[0015] like Figure 1A As shown, a mask layer 12 is formed on a patterned target layer 10. In some embodiments, the patterned target layer 10 may be a semiconductor substrate. In some embodiments, the patterned target layer 10 may be an insulating layer or a conductive layer used in the manufacture of a semiconductor device. Figures 1A to 1E For ease of explanation, the thickness of mask layer 12 is not changed.

[0016] Mask layer 12 may be a photoresist layer that reacts to wavelengths of 248 nm, 193 nm, 157 nm, extreme ultraviolet, or combinations thereof. Mask layer 12 may be a chemically amplified photoresist layer. Mask layer 12 may be a positive photoresist layer or a negative photoresist layer.

[0017] like Figure 1B , Figure 1C and Figure 2 As shown, a multi-tone mask MK1, including a white area 16a and a gray area 16c, is used to expose and develop the mask layer 12. The multi-tone mask MK1 may include a halftone mask. A halftone mask can be considered the opposite concept of a binary mask. The mask layer 12 can be exposed by light 13 from the photolithography apparatus.

[0018] The multi-tone mask MK1 may include a white region 16a and a gray region 16c located on a mask substrate 14. The mask substrate 14 may be light-sensitive (…). Figure 1B 13) The black area that cannot be passed through. The white area 16a can be light ( Figure 1B13) The area passing through the multitone mask MK1. Although in this example the mask has only two types of openings with two different amounts of light transmission, as discussed in the various embodiments below, different amounts of light can pass through many different types of openings in the multitone mask. Openings can include fully open openings (e.g., open windows) and partially blocked openings (e.g., filter windows). Therefore, a multitone mask can have two or more windows with different transmittance (e.g., fully open windows and one or more different filter windows).

[0019] The white area 16a may include a light-transmitting pattern 18. The gray area 16c may be light ( Figure 1B A portion of 13) passes through the area of ​​the multi-tone mask MK1. The gray area 16c may include multiple slit pattern 20c-1 and a space pattern 20c-2 located between the slit pattern 20c-1.

[0020] White region 16a may be an area that exposes the mask layer 12 and has a high light transmittance. Gray region 16c may be an area that exposes the mask layer 12 and has a lower light transmittance than white region 16a. In some embodiments, the light transmittance of white region 16a may be 100%, and the light transmittance of gray region 16c may be 50%. However, gray regions may provide other light transmittance, for example, between 25% and 75%, or less than 100% and greater than 0%.

[0021] like Figure 1B As shown in the light intensity diagram, when the mask layer 12 is exposed by light 13 from the photolithography apparatus, the portions of the multi-tone mask MK1 that cannot be penetrated by light 13 are indicated by black, the portions of the multi-tone mask MK1 that are completely penetrated by light 13 are indicated by white, and the portions of the multi-tone mask MK1 that are partially penetrated by light 13 are indicated by gray (Gray2). The transmittance of white can be greater than that of gray (Gray2).

[0022] After the mask layer 12 is exposed to the light 13 of the photolithography apparatus, when the development process is performed, it can be as follows: Figure 1B and Figure 1C The diagram shows the formation of a first mask pattern region 12a-1 and a second initial mask pattern region 12c-1. The first mask pattern region 12a-1 can be formed to correspond to the white region 16a of the multi-tone mask MK1.

[0023] The first mask pattern region 12a-1 exposes the pattern target layer 10 and may have a first thickness d1a-1. The second initial mask pattern region 12c-1 may have a second sub-thickness d1c-1 smaller than the first thickness d1a-1, without exposing the pattern target layer 10.

[0024] like Figure 1D and Figure 1E As shown, a first pattern 10a-2 and a second pattern 10c-1 are formed in the patterned target layer 10. For example, in one embodiment, the patterned target layer 10 located below the first mask pattern region 12a-1 is etched, and the second initial mask pattern region is retained. Figure 1C The mask layer 12 and the pattern target layer 10 below 12c-1 are used to form a first pattern 10a-2 with a first depth d2a-2 and a second pattern 10c-1 with a second depth d2c-1 that is smaller than the first depth d2a-2.

[0025] The formation process of the first pattern 10a-2 and the second pattern 10c-1 is described in more detail below. For example, in Figure 1D As shown, the pattern target layer 10 located below the first mask pattern region 12a-1 is etched to form a first initial pattern 10a-1 with a first sub-depth d2a-1.

[0026] Furthermore, further etching is retained in the area of ​​the second initial mask pattern ( Figure 1C The mask layer 12 below (12c-1) forms a second mask pattern region 12c-2 with a second thickness d1c-2 that exposes the pattern target layer 10. The second thickness d1c-2 can be the same as the first thickness d1a-1. The second initial mask pattern region ( Figure 1C The 12c-1 area and the second mask pattern area 12c-2 can be formed to correspond to the gray area 16c of the multi-tone mask MK1.

[0027] Subsequently, as Figure 1E As shown, further etching is performed on the first mask pattern region 12a-1 and the first initial pattern ( Figure 1D The pattern target layer 10 below (10a-1) is used to form a first pattern 10a-2 having a first depth d2a-2. The first depth d2a-2 can be greater than the first sub-depth ( Figure 1D (d2a-1) is deep.

[0028] Furthermore, the pattern target layer 10 located below the second mask pattern region 12c-2 is etched to form a second pattern 10c-1 having a second depth d2c-1 smaller than the first depth d2a-2. The first pattern 10a-2 and the second pattern 10c-1 can be trench patterns. When the pattern target layer 10 is a semiconductor substrate, the first pattern 10a-2 and the second pattern 10c-1 can be trench patterns formed within the semiconductor substrate.

[0029] Subsequently, by removing the mask layer 12, a method for manufacturing layers in a semiconductor device including the first pattern 10a-2 and the second pattern 10c-1 can be completed. The method for manufacturing a semiconductor device according to this embodiment can improve the reliability and electrical performance of the semiconductor device by forming two patterns of different depths via a single exposure and development process and using a single mask. For example, although... Figures 1A to 1E It shows different stages, but from Figure 1A The stages shown in the diagram Figure 1E The progression of the stages shown can be implemented using a single exposure and development process without interruption within the exposure and development portions of the process, and without the need to insert additional mask layers or masks. Therefore, multiple trenches of different depths can be formed simultaneously in a single patterning process.

[0030] Figures 3A to 3F This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment, and Figure 4 It is shown Figure 3A A planar image of a multi-tone mask used in the exposure process.

[0031] In detail, the terms "first," "second," etc., used in the following description have a consecutive meaning, but the inventive concept is not limited thereto. Figures 3A to 3F In this context, the X direction and Y direction refer to the first horizontal direction and the second horizontal direction, respectively, and the Z direction can be a direction perpendicular to the plane defined by the X direction and Y direction.

[0032] like Figure 1A As shown, a mask layer 12 is formed on the pattern target layer 10. (See above reference.) Figure 1A The pattern target layer 10 and mask layer 12 are described, so their descriptions are omitted here.

[0033] like Figure 3A , Figure 3B and Figure 4 As shown, a multi-tone mask MK2, including a white area (White, 16a) and first gray areas to third gray areas 16b, 16c and 16d, is used to expose and develop the mask layer 12. The mask layer 12 can be exposed by light 13 from a photolithography apparatus.

[0034] The multi-tone mask MK2 may include a white region 16a and first gray regions to third gray regions 16b, 16c, and 16d located on a mask substrate 14. The mask substrate 14 may be light-sensitive ( Figure 3A 13) The black area that cannot be penetrated. The white area 16a can be light ( Figure 3A 13) Completely passes through the area of ​​the multi-tone mask MK2.

[0035] The white area 16a may include a light-transmitting pattern 18. The first gray area to the third gray areas 16b, 16c and 16d may be light ( Figure 3A A portion of 13) passes through the area of ​​the multi-tone mask MK2. The first gray area 16b may include a plurality of first slit line patterns 20b-1 and a first space pattern 20b-2 located between the first slit line patterns 20b-1.

[0036] The second gray area 16c may include a plurality of second slit line patterns 20c-1 and a second spatial pattern 20c-2 located between the second slit line patterns 20c-1. The third gray area 16d may include a plurality of third slit line patterns 20d-1 and a third spatial pattern 20d-2 located between the third slit line patterns 20d-1.

[0037] The widths of the second slit pattern 20c-1 and the second spatial pattern 20c-2 can be smaller than the widths of the first slit pattern 20b-1 and the first spatial pattern 20b-2, respectively. The widths of the third slit pattern 20d-1 and the third spatial pattern 20d-2 can be smaller than the widths of the second slit pattern 20c-1 and the second spatial pattern 20c-2, respectively.

[0038] White region 16a may be a region that exposes the mask layer 12 and has a large amount of light transmittance. The first gray region through the third gray regions 16b, 16c, and 16d may be regions whose light transmittance of the exposed mask layer 12 is successively less than that of white region 16a. In some embodiments, the light transmittance of white region 16a may be 100%, the light transmittance of the first gray region 16b may be between 60% and 80% (e.g., 75%), the light transmittance of the second gray region 16c may be between 40% and 60% (e.g., 50%), and the light transmittance of the third gray region 16d may be between 20% and 40% (e.g., 25%).

[0039] like Figure 3A As shown in the light intensity diagram, when the mask layer 12 is exposed by the light 13 of the photolithography device, the parts of the multi-tone mask MK2 that cannot be transmitted by the light 13 are indicated in black, and the parts of the multi-tone mask MK2 that are completely transmitted by the light 13 are indicated in white.

[0040] Furthermore, the portion of light 13 passing through the first gray area 16b of the multi-tone mask MK2 is designated as Gray 1, the portion passing through the second gray area 16c of the multi-tone mask MK2 is designated as Gray 2, and the portion passing through the third gray area 16d of the multi-tone mask MK2 is designated as Gray 3. The transmittance of the white portion can be greater than the transmittance of Gray 1 to Gray 3. The transmittance can decrease in the order of Gray 1, Gray 2, and Gray 3.

[0041] After the mask layer 12 is exposed to the light 13 of the photolithography apparatus, when the development process is performed, it can be as follows: Figure 3A and Figure 3B The diagram shows the formation of a first mask pattern region 12a-1 and second to fourth initial mask pattern regions 12b-1, 12c-1, and 12d-1. The first mask pattern region 12a-1 can be formed to correspond to the white region 16a of the multi-tone mask MK1.

[0042] The first mask pattern region 12a-1 may expose the pattern target layer 10 and may have a first thickness d1a-1. The second initial mask pattern region 12b-1 may not expose the pattern target layer 10 and may have a second sub-thickness d1b-1 that is smaller than the first thickness d1a-1.

[0043] The third initial mask pattern region 12c-1 may not expose the pattern target layer 10 and may have a third sub-thickness d1c-1 smaller than the second sub-thickness d1b-1. The fourth initial mask pattern region 12d-1 may not expose the pattern target layer 10 and may have a fourth sub-thickness d1d-1 smaller than the third sub-thickness d1c-1.

[0044] like Figures 3C to 3F As shown, first to fourth patterns 10a-4, 10b-3, 10c-2, and 10d-1 are formed within the pattern target layer 10. The pattern target layer 10 located below the first mask pattern region 12a-1, and the mask layer 12 and pattern target layer 10 located below the second to fourth initial mask pattern regions 12b-1, 12c-1, and 12d-1 are etched to form first to fourth patterns 10a-4, 10b-3, 10c-2, and 10d-1 having sequentially sized first to fourth depths d2a-4, d2b-3, d2c-2, and d2d-1 (e.g., their depths decrease sequentially).

[0045] The formation process of the first to fourth patterns 10a-4, 10b-3, 10c-2, and 10d-1 is described in detail below. The operation of forming the first to fourth patterns 10a-4, 10b-3, 10c-2, and 10d-1 may include forming the second to fourth mask pattern regions 12b-2, 12c-3, and 12d-4, and etching the patterned target layer 10 using the first to fourth mask pattern regions 12a-1, 12b-2, 12c-3, and 12d-4 as etching masks. The second to fourth mask pattern regions 12b-2, 12c-3, and 12d-4 may be formed to correspond to the first to third gray regions 16b, 16c, and 16d, respectively.

[0046] like Figure 3C As shown, the pattern target layer 10 located below the first mask pattern region 12a-1 is etched to form a first initial pattern 10a-1. The first initial pattern 10a-1 may have a first sub-depth d2a-1. It should be noted that the sub-depth may refer to a depth that can occur during intermediate processes and can become deeper during subsequent processes. Furthermore, further etching is retained in the second initial mask pattern region ( Figure 3B The mask layer 12 below the patterned target layer 10 is used to form a second mask pattern region 12b-2 that exposes the patterned target layer 10. The second mask pattern region 12b-2 may have a second thickness d1b-2. The second thickness d1b-2 may be the same as the first thickness d1a-1.

[0047] exist Figure 3C In the manufacturing process, further etching is performed on the third initial mask pattern area ( Figure 3B 12c-1) and the fourth initial mask pattern region ( Figure 3B The mask layer 12 below (12d-1). The third initial mask pattern area ( Figure 3B 12c-1) and the fourth initial mask pattern region ( Figure 3B 12d-1 in the original text can be transformed into the third initial mask pattern region 12c-2 and the fourth initial mask pattern region 12d-2, respectively. The third initial mask pattern region 12c-2 and the fourth initial mask pattern region 12d-2 can have increased third sub-thickness d1c-2 and increased fourth sub-thickness d1d-2, respectively.

[0048] like Figure 3D As shown, further etching is performed on the first initial pattern ( Figure 3C The pattern target layer 10 below (10a-1) is etched, and the pattern area located in the second mask pattern region ( Figure 3C The pattern target layer 10 below 12b-2 is used to form two initial patterns 10b-1.

[0049] The second initial pattern 10b-1 can have a second sub-depth d2b-1. The first initial pattern ( Figure 3C The first initial pattern 10a-1 is transformed into the first initial pattern 10a-2. The first initial pattern 10a-2 may have an increased first sub-depth d2a-2.

[0050] Furthermore, the mask layer 12 remaining below the third initial mask pattern region 12c-2 is further etched to form a third mask pattern region 12c-3 exposing the pattern target layer 10. The third mask pattern region 12c-3 may have a third thickness d1c-3. The third thickness d1c-3 may be equal to the second thickness d1b-2.

[0051] exist Figure 3D In the manufacturing process, further etching is performed on the fourth initial mask pattern area ( Figure 3C The mask layer 12 below (12d-2). The fourth initial mask pattern area ( Figure 3C The 12d-2 region can be transformed into the fourth initial mask pattern region 12d-3. The fourth initial mask pattern region 12d-3 can have an increased fourth sub-thickness d1d-3.

[0052] like Figure 3E As shown, further etching is performed on the first initial pattern ( Figure 3D 10a-2) and the second initial pattern ( Figure 3D The target pattern layer 10 below (10b-1). First initial pattern ( Figure 3D 10a-2 in the middle) and the second initial pattern ( Figure 3D In the original pattern 10b-1, the first initial pattern 10a-3 and the second initial pattern 10b-2 are respectively transformed into the first initial pattern 10a-3 and the second initial pattern 10b-2. The first initial pattern 10a-3 and the second initial pattern 10b-2 can respectively have an increased first sub-depth d2a-3 and an increased second sub-depth d2b-2.

[0053] Etching is located in the third mask pattern area ( Figure 3D The pattern target layer 10 below (12c-3) is used to form the third initial pattern 10c-1. Further etching is performed to retain the fourth initial mask pattern area ( Figure 3D The mask layer 12 below (12d-3) forms a fourth mask pattern region 12d-4 that exposes the pattern target layer 10. The fourth mask pattern region 12d-4 may have a fourth thickness d1d-4. The fourth thickness d1d-4 may be equal to the third thickness d1c-3.

[0054] like Figure 3F As shown, further etching is performed on the first mask pattern region 12a-1 and the first initial pattern ( Figure 3EThe pattern target layer 10 below 10a-3) is used to form a first pattern 10a-4 with a first depth d2a-4.

[0055] Further etching is performed in the area of ​​the second mask pattern ( Figure 3E The pattern target layer 10 below the first initial pattern 10b-2 (12b-2) and the second initial pattern 10b-2 is used to form a second pattern 10b-3 with a second depth d2b-3 that is smaller than the first depth d2a-4.

[0056] Further etching is performed in the third mask pattern area ( Figure 3E 12c-3 in the middle) and the third initial pattern ( Figure 3E The pattern target layer 10 below 10c-1 is used to form a third pattern 10c-2 with a third depth d2c-2 that is smaller than the second depth d2b-3. Etching is performed in the fourth mask pattern area ( Figure 3E The pattern target layer 10 below 12d-4 is used to form a fourth pattern 10d-1 with a fourth depth d2d-1 that is smaller than the third depth d2c-2.

[0057] The first pattern 10a-4, the second pattern 10b-3, the third pattern 10c-2, and the fourth pattern 10d-1 can be trench patterns. When the pattern target layer 10 is a semiconductor substrate, the first pattern 10a-4, the second pattern 10b-3, the third pattern 10c-2, and the fourth pattern 10d-1 can be trench patterns formed in the semiconductor substrate.

[0058] Subsequently, by removing the mask layer 12, a method for manufacturing a semiconductor device comprising a first pattern 10a-4, a second pattern 10b-3, a third pattern 10c-2, and a fourth pattern 10d-1 can be completed. This method of manufacturing a semiconductor device can improve the reliability and electrical performance of the semiconductor device by forming four patterns of different depths via a single exposure and development process. For example, although Figures 3A to 3F It shows different stages, but from Figure 3A The stages shown in the diagram Figure 3F The progression of the stages shown can be implemented using a single exposure and development process without interruption within the exposure and development portions of the process, and without the need to insert additional mask layers or masks. Therefore, multiple trenches of different depths can be formed simultaneously in a single patterning process.

[0059] Figure 5A This is a perspective view showing a mask pattern region formed on a pattern target layer according to an embodiment, and Figure 5B This is a perspective view showing a pattern formed according to an embodiment.

[0060] In detail, Figure 5A The above references are shown. Figure 3A Mask layer 12 for the described mask pattern regions (i.e., 12a-1, 12b-1, 12c-1, and 12d-1). Figure 5A As shown, mask pattern regions (i.e., 12a-1, 12b-1, 12c-1, and 12d-1) can be formed in a stepped shape along the X direction on the pattern target layer 10. In some embodiments, with Figure 5A Unlike other mask patterns, mask pattern regions (i.e., 12a-1, 12b-1, 12c-1, and 12d-1) can be formed in a stepped shape along the Y direction.

[0061] Figure 5B The above references are shown. Figure 3F The pattern target layer 10 describes the first pattern 10a-4, the second pattern 10b-3, the third pattern 10c-2, and the fourth pattern 10d-1. For example... Figure 5B As shown, the first pattern 10a-4, the second pattern 10b-3, the third pattern 10c-2, and the fourth pattern 10d-1 can be formed in a stepped shape along the X direction. In some embodiments, with Figure 5B Differently, the first pattern 10a-4, the second pattern 10b-3, the third pattern 10c-2, and the fourth pattern 10d-1 can be formed in a stepped shape along the Y direction.

[0062] Figure 6 This is a plan view showing a semiconductor device EX1 that can be manufactured according to an embodiment.

[0063] In detail, the semiconductor device EX1 may include a cell region CELR and a peripheral circuit region PPCR planarly surrounding the cell region CELR. The cell region CELR may include a cell center region UBC and a cell edge region UBE planarly surrounding the cell center region UBC.

[0064] The element edge region UBE can be arranged on one (or both) side of the element center region UBC in the first horizontal direction (X direction). The element edge region UBE can also be arranged on one (or both) side of the element center region UBC in the second horizontal direction (Y direction). The element center region UBC and the element edge region UBE can also be referred to as the element block center region and the element block edge region, respectively.

[0065] The cell region CELR can have lengths of X2 and Y2 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. The X2 and Y2 lengths can range from a few millimeters to tens of millimeters. In the cell region CELR, the cell center region UBC can have lengths of X1 and Y1 in the first horizontal direction (X direction) and the second horizontal direction (Y direction), respectively. The region in the cell region CELR other than the cell center region UBC can be the cell edge region UBE.

[0066] In some embodiments, the length of the cell edge region UBE may be less than or equal to 5% of the length of the cell region CELR. For example, the cell edge region UBE may have a length X2-X1 obtained by subtracting the length X1 of the cell center region UBC in the first horizontal direction (X direction) from the length X2 of the cell region CELR in the first horizontal direction (X direction). The length X2-X1 may be equal to or less than 5% of the length X2. The cell edge region UBE may have a length Y2-Y1 obtained by subtracting the length Y1 of the cell center region UBC in the second horizontal direction (Y direction) from the length Y2 of the cell region CELR in the second horizontal direction (Y direction). The length Y2-Y1 may be equal to or less than 5% of the length Y2.

[0067] The peripheral circuit region PPCR may include an interface region INF surrounding the cell region CELR and a core region COR planarly surrounding the interface region INF. The peripheral circuitry PCI may be placed within the core region COR. In this embodiment, the interface region INF is included within the peripheral circuit region PPCR, but the interface region INF may also be included within the cell region CELR.

[0068] Semiconductor device EX1 can be a memory device. Therefore, the aforementioned cell region CELR can be a memory cell region. The memory device can be a dynamic random access memory (DRAM) device.

[0069] Figure 7 This is a schematic layout diagram showing the main components of a cell region of a semiconductor device that can be manufactured by means of an embodiment of the present invention.

[0070] In detail, Figure 7 It can be shown Figure 6 A diagram of the main component of the cell region CELR of the semiconductor device EX1. The semiconductor device EX1 may include multiple active regions AC1 (or active patterns). The multiple active regions AC1 (or active patterns) may be arranged diagonally relative to a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0071] Multiple word lines WL can extend parallel to each other across multiple active regions AC1 (or active patterns) in a first horizontal direction (X direction). Multiple bit lines BL can extend parallel to each other above the multiple word lines WL in a second horizontal direction (Y direction) intersecting the first horizontal direction (X direction). Multiple bit lines BL can be connected to multiple active regions AC1 (or active patterns) via direct contacts DC.

[0072] Multiple embedded contact plugs BC can be formed between two adjacent bit lines BL. The embedded contact plugs BC can also be referred to as embedded contacts. In some embodiments, the multiple embedded contact plugs BC can be arranged in rows in a first horizontal direction (X direction) and a second horizontal direction (Y direction).

[0073] Multiple landing pads LP can be formed on multiple buried contact plugs BC. The landing pads LP may include conductive material. The multiple buried contact plugs BC and the multiple landing pads LP can connect the storage electrode (or lower electrode, not shown) of a capacitor formed on top of multiple bit lines BL to an active region AC1 (or active pattern). At least a portion of each of the multiple landing pads LP may vertically overlap with the buried contact plugs BC.

[0074] Figure 8A This is a cross-sectional view showing a semiconductor device that can be manufactured according to an embodiment, and Figure 8B yes Figure 8A A magnified view of a portion of it.

[0075] In detail, Figure 8A Is Figure 7 A cross-sectional view in the first horizontal direction (X direction) (i.e., A1-A1'). Figure 8B yes Figure 8A A magnified view of part of EN1. Figure 8A and Figure 8B The above references are briefly given or omitted. Figure 7 The given description.

[0076] Semiconductor device EX1 includes a semiconductor substrate 110 having a device isolation film 112 and a plurality of active regions AC1 (or active patterns). The active regions AC1 (or active patterns) can be easily formed by a single exposure and development process as described above. The device isolation film 112 can be formed on the semiconductor substrate 110. The device isolation film 112 may include a silicon oxide film.

[0077] The semiconductor substrate 110 may include silicon, such as monocrystalline silicon, polycrystalline silicon, or amorphous silicon. In some embodiments, the semiconductor substrate 110 includes at least one selected from Ge, SiGe, SiC, GaAs, InAs, and InP.

[0078] In some embodiments, the semiconductor substrate 110 may include conductive regions such as doped wells or doped structures. The device isolation film 112 may include an oxide film, a nitride film, or a combination thereof.

[0079] A buffer layer 122 is formed on the semiconductor substrate 110. The buffer layer 122 can be formed on the upper surface of a plurality of active regions AC1 (or active patterns) and on the upper surface of the device isolation film 112. The buffer layer 122 may include at least one of a silicon oxide film and a silicon nitride film. In some embodiments, the buffer layer 122 may include a first silicon oxide film 122a, a second silicon oxide film 122b, and a silicon nitride film 122c sequentially formed on the semiconductor substrate 110.

[0080] In some embodiments, depending on the manufacturing process, the first silicon oxide film 122a of the buffer layer 122 may not be formed. In this case, the buffer layer 122 may include a second silicon oxide film 122b and a silicon nitride film 122c.

[0081] Multiple bit lines BL are formed on the buffer layer 122, spaced apart from each other in a first horizontal direction (X direction). In some embodiments, depending on the material forming the buffer layer 122, the bit lines BL may be formed on a silicon oxide film or a silicon nitride film.

[0082] Multiple bit lines BL can be connected to the active region AC1 (or active pattern) via direct contacts DC. Multiple direct contacts DC can be configured. These direct contacts DC can be spaced apart from each other in the first horizontal direction (X direction).

[0083] Direct contacts DC are formed on a portion of multiple active regions AC1 (or active patterns). The direct contacts DC are embedded in direct contact holes DCH that expose the active regions AC1 (or active patterns) of the semiconductor substrate 110. The lower end of the direct contacts DC may be located at a level lower than the upper surface of the semiconductor substrate 110 and embedded within the semiconductor substrate 110.

[0084] In some embodiments, the direct contact DC may include a lower conductive pattern 130. The lower conductive pattern 130 may include a polycrystalline silicon film doped with impurities such as boron (B), arsenic (As), or phosphorus (P). In some embodiments, the lower conductive pattern 130 may include Si, Ge, W, WN, Co, Ni, Al, Mo, Ru, Ti, TiN, Ta, TaN, Cu, or combinations thereof.

[0085] Each of the multiple bit lines BL may include an intermediate conductive pattern 132 and an upper conductive pattern 134 sequentially formed on the direct contact DC. An insulating capping pattern 136r is formed on each of the multiple bit lines BL. The insulating capping pattern 136r may be placed on the upper conductive pattern 134. The upper surface of the lower conductive pattern 130 may be flush with the upper surface of the direct contact DC.

[0086] although Figure 8A The invention illustrates a dual conductive layer structure with multiple bit lines BL including an intermediate conductive pattern 132 and an upper conductive pattern 134, but the concept of the invention is not limited thereto.

[0087] For example, multiple bit lines BL can be described as including a lower conductive pattern 130, a middle conductive pattern 132, and an upper conductive pattern 134. Multiple bit lines BL can be formed as a single conductive pattern or as a stacked structure of multiple conductive patterns including four or more conductive patterns.

[0088] In some embodiments, the intermediate conductive pattern 132 may include a barrier metal layer. In some embodiments, the upper conductive pattern 134 may include a metal layer. In some embodiments, the intermediate conductive pattern 132 and the upper conductive pattern 134 may include materials such as Ti, TiN, TiSiN, tungsten (W), WN, or tungsten silicide (WSi). x ), silicon tungsten nitride (WSi) x N y Membranes of ruthenium (Ru) or combinations thereof.

[0089] For example, the intermediate conductive pattern 132 may include a TiN film and / or a TiSiN film, and the upper conductive pattern 134 may include tungsten (W). In some embodiments, the insulating capping pattern 136r may include a silicon nitride film.

[0090] Multiple buried contact plugs BC can be arranged on the semiconductor substrate 110. The buried contact plugs BC can also be simply referred to as contact plugs. The multiple buried contact plugs BC can be spaced apart in a first horizontal direction (X direction). The buried contact plugs BC can have a cylindrical shape extending in the vertical direction (Z direction) in the space between multiple bit lines BL. The multiple buried contact plugs BC can contact the active region AC1 (or active pattern).

[0091] The buried contact plug BC is embedded in the buried contact hole BCH that exposes the active region AC1 (or active pattern) of the semiconductor substrate 110. The lower end of the buried contact plug BC may be located at a level lower than the upper surface of the semiconductor substrate 110 and embedded within the semiconductor substrate 110.

[0092] The buried contact plug BC may include a semiconductor material, metal, conductive metal nitride, or a combination thereof doped with impurities such as boron (B), arsenic (As), or phosphorus (P)). In some embodiments, the buried contact plug BC may include a plug conductive layer 154 and a plug metal silicide layer 156.

[0093] In some embodiments, the plug conductive layer 154 may comprise a semiconductor material doped with impurities such as boron (B), arsenic (As), or phosphorus (P). In some embodiments, the plug metal silicide layer 156 may comprise cobalt silicide, nickel silicide, or manganese silicide.

[0094] A direct contact DC and a pair of embedded contact plugs BC facing each other with the direct contact DC located therebetween can be connected to different active regions AC1 (or active patterns) in multiple active regions AC1 (or active patterns).

[0095] Semiconductor device EX1 may include a first internal spacer 144 and a gap-filling insulating pattern 146 located between a plurality of direct contacts DC and a plurality of buried contact plugs BC. The first internal spacer 144 may be formed on the sidewalls of the direct contacts DC and the bottom of the direct contact holes DCH. In some embodiments, the first internal spacer 144 may include a silicon nitride layer.

[0096] A gap-filling insulating pattern 146 may be formed on the lower sidewall of the embedded contact plug BC and the sidewall of the first internal spacer 144. In some embodiments, the gap-filling insulating pattern 146 may include a silicon oxide layer.

[0097] like Figure 8B As shown, the semiconductor device EX1 may include a plurality of spacer structures BLS located between the bit line BL and the buried contact plug BC. The spacer structure BLS may include a second inner spacer 148, an intermediate spacer 150, and an outer spacer 152. The intermediate spacer 150 may be located between the second inner spacer 148 and the outer spacer 152. The second inner spacer 148 may include the same material as the first inner spacer 144. In some embodiments, the intermediate spacer 150 may include a silicon oxide layer. In some embodiments, the outer spacer 152 may include a silicon nitride layer.

[0098] Multiple first landing pads LP1 can be formed above multiple embedded contact plugs BC. The multiple first landing pads LP1 can be arranged spaced apart from each other in a first horizontal direction (X direction) on the multiple embedded contact plugs BC. The first landing pads LP1 protrude from the surface of the insulating cap pattern 136r above the bit line BL.

[0099] The first landing pad LP1 can be connected to the buried contact plug BC. The first landing pad LP1 may include a lower conductive pattern 158. The lower conductive pattern 158 may include doped polysilicon, metal, metal silicide, conductive metal nitride, or a combination thereof. In some embodiments, the lower conductive pattern 158 may include tungsten (W).

[0100] Semiconductor device EX1 may include a landing insulating layer 166 that covers the upper portion of a plurality of first landing pads LP1 and surrounds the upper sidewalls of the plurality of protruding first landing pads LP1. The landing insulating layer 166 may fill the separation space around the plurality of protruding first landing pads LP1. The plurality of protruding first landing pads LP1 may be electrically insulated from each other by the landing insulating layer 166.

[0101] In some embodiments, the landing insulation layer 166 may include a material having a dielectric constant lower than that of the silicon nitride layer. In some embodiments, the landing insulation layer 166 may include a silicon oxide film or a silicon carbide (SiOC) film.

[0102] A barrier insulating layer 168 may be placed on the landing insulating layer 166. In some embodiments, the barrier insulating layer 168 may include a silicon nitride layer. A plurality of second landing pads LP2 electrically connected to the first landing pad LP1 are arranged.

[0103] The second landing pad LP2 may include an upper conductive pattern 172. The upper conductive pattern 172 may include doped polysilicon, metal, metal silicide, conductive metal nitride, or a combination thereof. In some embodiments, the upper conductive pattern 172 may include tungsten (W).

[0104] Multiple second landing pads LP2 can be arranged spaced apart from each other in a first horizontal direction (X direction) on the first landing pad LP1. The second landing pads LP2 can be embedded in landing openings 170 formed in landing insulation layer 166 through barrier insulation layer 168. Therefore, the second landing pads LP2 can be electrically connected to the first landing pad LP1.

[0105] Here, refer to Figure 8B Describe the arrangement and interrelationship of bit line BL, embedded contact plug BC, first landing pad LP1, second landing pad LP2 and landing insulation layer 166.

[0106] Specifically, multiple bit lines BL are arranged in the first horizontal direction (X direction) with a first separation distance IS1. Multiple embedded contact plugs BC are arranged in the first horizontal direction (X direction) with a second separation distance IS2. The embedded contact plugs BC can be placed between two bit lines BL in the first horizontal direction (X direction).

[0107] Multiple first landing pads LP1 can be formed such that the upper surface of the insulating cap pattern 136r on the bit line BL protrudes from the first horizontal line PL1. The first landing pads LP1 protrude from the upper surface of the insulating cap pattern 136r on the bit line BL by a first vertical distance D1. The first vertical distance D1 can suppress vertical short circuits between the second landing pad LP2 and the embedded contact plug BC located below the second landing pad LP2.

[0108] Multiple first landing pads LP1 are spaced apart from each other by a third separation distance IS3 in the first horizontal direction (X direction). The third separation distance IS3 can suppress horizontal short circuits between two adjacent first landing pads LP1.

[0109] The landing insulation layer 166 can be arranged between a first horizontal line PL1 located at a first vertical distance D1 from the upper surface of the first landing pad LP1 in the direction toward the embedded contact plug BC, and a second horizontal line PL2 located at a second vertical distance D2 from the upper surface of the first landing pad LP1 in the direction toward the blocking insulation layer 168. The vertical distance between the first horizontal line PL1 and the second horizontal line PL2 can be a third vertical distance D3.

[0110] As described above, the landing insulating layer 166 may include a material having a lower dielectric constant than the silicon nitride layer, such as silicon oxide or silicon carbide (SiOC) film. In this way, the parasitic capacitance between the plurality of first landing pads LP1 or second landing pads LP2 can be reduced.

[0111] Multiple second landing pads LP2 penetrate the barrier insulating layer 168 and are embedded in the landing aperture 170 within a portion of the landing insulating layer 166. After forming the landing insulating layer 166 and the barrier insulating layer 168, the landing aperture 170 can be formed using a photolithography process. The separation distance between the multiple second landing pads LP2 can be a fifth separation distance IS5. Horizontal short circuits between two adjacent second landing pads LP2 can be suppressed due to the fifth separation distance IS5. The second landing pads LP2 are formed by embedding the conductive layer for the second landing pads within the landing aperture 170. Therefore, the second landing pads LP2 can be reliably formed during the manufacturing process.

[0112] The second landing pad LP2 can be positioned by moving horizontally from the first landing pad LP1 by a first offset OX1 in the first horizontal direction (X direction). A portion of the second landing pad LP2 may not vertically overlap with the first landing pad LP1. Therefore, the separation distance between the second landing pad LP2 and the first landing pad LP1 can be a fourth separation distance IS4, which is smaller than the fifth separation distance IS5.

[0113] Although the fourth separation distance IS4 is smaller than the fifth separation distance IS5, it can suppress horizontal short circuits between multiple second landing pads LP2 or between adjacent first landing pads LP1. The second landing pads LP2 can be electrically connected to the first landing pads LP1 in the vertical direction.

[0114] As described above, the semiconductor device EX1 can improve reliability and electrical performance by forming the active region AC1 (or active pattern) via a single exposure and development process. This is used to form the bonding... Figures 6 to 8A One or more of the photolithography processes used to depict the patterns of semiconductor devices described can utilize photomasks and, for example, combinations of... Figures 1A to 5B The process described. Furthermore, the semiconductor device EX1 can reliably implement the vertical connection between the buried contact plug BC and the first landing pad LP1 and the second landing pad LP2, and reduce the parasitic capacitance between the first landing pad LP1 and the second landing pad LP2.

[0115] Figure 9A This is a cross-sectional view showing a semiconductor device EX1 that can be manufactured according to an embodiment, and Figure 9B yes Figure 9A A magnified view of a portion of it.

[0116] In detail, Figure 9A Is Figure 7 A cross-sectional view in the second horizontal direction (Y direction) (i.e., A2-A2'). Figure 9B yes Figure 9A A magnified view of part of EN2. Figure 9A and Figure 9B The above references are briefly given or omitted. Figure 7 , Figure 8A and Figure 8B The given description.

[0117] Semiconductor device EX1 includes a semiconductor substrate 110 with multiple active regions AC1 (or active patterns) defined by multiple device isolation films 112. The device isolation films 112 may be formed on the semiconductor substrate 110. The device isolation films 112 may include a silicon oxide film 112a and a silicon nitride film 112b.

[0118] Multiple word lines 119 can be arranged within the device isolation film 112. The multiple word lines 119 are spaced apart from each other in the second horizontal direction (Y direction). The word lines 119 can be buried in word line trenches formed in the semiconductor substrate 110.

[0119] Word line 119 may include gate conductive layers 114, 116, and 118. Gate conductive layers 114, 116, and 118 may include a lower gate conductive layer 114, a middle gate conductive layer 116, and an upper gate conductive layer 118. A gate dielectric film (not shown) may be formed beneath the gate conductive layers 114, 116, and 118 (e.g., the lower gate conductive layer 114).

[0120] The gate dielectric film may include at least one selected from silicon oxide film, silicon nitride film, silicon oxynitride film, oxide / nitride / oxide (ONO) film, and high-k dielectric film having a dielectric constant higher than that of silicon oxide film. Gate conductive layers 114, 116, and 118 may include Ti, TiN, Ta, TaN, W, WN, TiSiN, WSiN, or combinations thereof.

[0121] A gate capping layer 120 may be formed on the upper gate conductive layer 118 among the gate conductive layers 114, 116, and 118. In some embodiments, the gate capping layer 120 may include a silicon nitride layer. A plurality of buried contact plugs BC may be formed on a plurality of active regions AC1 (or active patterns).

[0122] Multiple embedded contact plugs BC may be arranged spaced apart from each other in a second horizontal direction (Y direction). In some embodiments, the embedded contact plugs BC may include a plug conductive layer 154 and a plug metal silicide layer 156.

[0123] A plurality of gate insulating layers 160r are formed on the gate cap layer 120 and the device isolation film 112. The gate insulating layers 160r are spaced apart from each other in a second horizontal direction (Y direction). In some embodiments, the gate insulating layers 160r may include silicon nitride layers. The gate insulating layers 160r may be formed between a plurality of buried contact plugs BC.

[0124] Multiple first landing pads LP1 can be formed above multiple embedded contact plugs BC. A fence insulation layer 160r can be formed to cover the lower portion of the first landing pads LP1. The multiple first landing pads LP1 can be arranged spaced apart from each other in a second horizontal direction (Y direction) on the multiple embedded contact plugs BC. The first landing pads LP1 protrude from the surface of the fence insulation layer 160r.

[0125] The first landing pad LP1 can be connected to the buried contact plug BC. The first landing pad LP1 may include a lower conductive pattern 158. The semiconductor device EX1 may include a landing insulating layer 166 that covers the upper portion of the plurality of first landing pads LP1 and surrounds the upper sidewalls of the plurality of protruding first landing pads LP1.

[0126] A barrier insulation layer 168 may be placed on the landing insulation layer 166. A plurality of second landing pads LP2 are arranged on a plurality of first landing pads LP1 and electrically connected to the first landing pads LP1. The second landing pads LP2 may include an upper conductive pattern 172.

[0127] Multiple second landing pads LP2 can be arranged spaced apart from each other in a second horizontal direction (Y direction) on the first landing pad LP1. The second landing pads LP2 can be embedded in landing openings 170 formed in landing insulation layer 166 by penetrating barrier insulation layer 168.

[0128] Here, refer to Figure 9B The arrangement and interrelationship of the embedded contact plug BC, the first landing pad LP1, the second landing pad LP2, and the landing insulation layer 166 are described.

[0129] In detail, multiple embedded contact plugs BC are spaced apart from each other by a sixth separation distance IS6 in the second horizontal direction (Y direction). The embedded contact plugs BC can be placed between two fence insulation layers 160r in the second horizontal direction (Y direction).

[0130] Multiple first landing pads LP1 can be formed to protrude from the first horizontal line PL1 on the upper surface of the fence insulation layer 160r. The first horizontal line PL1 can be located relative to the above reference. Figure 8B The first horizontal line PL1 is described at the same level.

[0131] The first landing pad LP1 protrudes a first vertical distance D1 from the first horizontal line PL1 on the upper surface of the fence insulation layer 160r. The first vertical distance D1 can suppress the vertical short circuit between the second landing pad LP2 and the embedded contact plug BC located below the second landing pad LP2.

[0132] Multiple first landing pads LP1 are arranged with a seventh separation distance IS7 in the second horizontal direction (Y direction). Horizontal short circuits between two adjacent first landing pads LP1 can be suppressed due to the seventh separation distance IS7.

[0133] The landing insulation layer 166 can be arranged between a first horizontal line PL1 located at a first vertical distance D1 from the upper surface of the first landing pad LP1 in the direction toward the embedded contact plug BC, and a second horizontal line PL2 located at a second vertical distance D2 from the upper surface of the first landing pad LP1 in the direction toward the blocking insulation layer 168. The second horizontal line PL2 can be located at the same location as the above reference. Figure 8B The second horizontal line PL2 is at the same level as the first horizontal line PL1. The vertical distance between the first horizontal line PL1 and the second horizontal line PL2 can be a third vertical distance D3.

[0134] As described above, the landing insulating layer 166 may include a material having a lower dielectric constant than the silicon nitride layer, such as a silicon oxide film or a silicon carbide (SiOC) film. In this way, the parasitic capacitance between the plurality of first landing pads LP1 or second landing pads LP2 can be reduced.

[0135] Multiple second landing pads LP2 penetrate the barrier insulating layer 168 and are embedded in the landing aperture 170 within a portion of the landing insulating layer 166. After forming the landing insulating layer 166 and the barrier insulating layer 168, the landing aperture 170 can be formed using a photolithography process. The separation distance between the multiple second landing pads LP2 can be an eighth separation distance IS8. Horizontal short circuits between two adjacent second landing pads LP2 can be suppressed due to the eighth separation distance IS8. The second landing pads LP2 are formed by embedding the conductive layer for the second landing pads within the landing aperture 170. Therefore, the second landing pads LP2 can be reliably formed during the manufacturing process.

[0136] The second landing pad LP2 can be vertically overlapped with the first landing pad LP1 without offset in the second horizontal direction (Y direction). The separation distance between the second landing pads LP2 can be an eighth separation distance IS8, which is approximately the same as the seventh separation distance IS7. Therefore, horizontal short circuits between adjacent second landing pads LP2 or between adjacent first landing pads LP1 can be suppressed. The second landing pads LP2 can be electrically connected to the first landing pad LP1 in the vertical direction.

[0137] As described above, the semiconductor device EX1 can improve reliability and electrical performance by forming the active region AC1 (or active pattern) via a single exposure and development process. For example, the active region AC1 includes trenches of different depths in which the device isolation film 112 and word lines 119 are formed, and trenches of different depths can be formed using the single exposure and development process discussed earlier. Furthermore, the semiconductor device EX1 can reliably implement the vertical connection between the buried contact plug BC and the first landing pad LP1 and the second landing pad LP2, and reduce the parasitic capacitance between the first landing pad LP1 and the second landing pad LP2.

[0138] Figures 10A to 10G This is a cross-sectional view illustrating a method for manufacturing a semiconductor device according to an embodiment.

[0139] Specifically, Figures 10A to 10G Showing the formation Figures 6 to 9B An embodiment of a method for the active region AC1 (or active pattern) of a semiconductor device EX1. Figures 10A to 10G The above references are briefly given or omitted. Figures 1A to 2 and Figures 6 to 9BThe given description.

[0140] Reference Figure 10A A first high-density mask pattern 30a and a second high-density mask pattern 32a, as well as a first low-density mask pattern 30b and a second low-density mask pattern 32b, are formed on a semiconductor substrate 110 having a cell region (CELR) and a peripheral circuit region (PPCR). The first high-density mask pattern 30a may be formed from a first layer at a first vertical level. The second high-density mask pattern 32a may be formed on the first high-density mask pattern 30a and may be formed from a second layer at a second vertical level. The first low-density mask pattern 30b may be formed from the first layer at the first vertical level. The second low-density mask pattern 32b may be formed on the first low-density mask pattern 30b and may be formed from a second layer at a second vertical level. The first high-density mask pattern 30a and the second high-density mask pattern 32a may form separate patterns, each formed as a protrusion or an opening. The first low-density mask pattern 30b and the second low-density mask pattern 32b may each form a separate pattern formed as a protrusion or an opening. High-density mask patterns have a higher density than low-density mask patterns, and therefore throughout this specification, "high density" and "low density" are used as relative terms. The semiconductor substrate 110 can be such a patterned target layer as described above. The peripheral circuit region PPCR can include the core region COR. The peripheral circuit region PPCR can be a region in which peripheral circuit transistors are formed, specifically the operating cell region CELR.

[0141] The cell region CELR, in which the first high-density mask pattern 30a and the second high-density mask pattern 32a are formed, can be a high-density pattern forming region (HDPR). The peripheral circuit region PPCR, in which the first low-density mask pattern 30b and the second low-density mask pattern 32b are formed, can be a low-density pattern forming region (LDPR).

[0142] The first high-density mask pattern 30a and the second high-density mask pattern 32a can be formed by multiple patterning processes (e.g., dual patterning or quadruple patterning). The first low-density mask pattern 30b and the second low-density mask pattern 32b can be formed by multiple patterning processes or a single patterning process.

[0143] The first high-density mask pattern 30a and the second high-density mask pattern 32a comprise individual patterns spaced apart from each other in a first horizontal direction (X direction). The first high-density mask pattern 30a and the second high-density mask pattern 32a comprise individual patterns that may have a width of several nanometers in the first horizontal direction. A narrow first opening 33a exposing the surface of the semiconductor substrate 110 may be formed between each individual pattern of the first high-density mask pattern 30a and the second high-density mask pattern 32a.

[0144] A wide second opening 33b exposing the surface of the semiconductor substrate 110 may be formed on one side of the first high-density mask pattern 30a and the second high-density mask pattern 32a. The first high-density mask pattern 30a and the second high-density mask pattern 32a may respectively include a silicon oxide layer and a polysilicon layer (e.g., the first high-density mask pattern 30a may be a silicon oxide layer and the second high-density mask pattern 32a may be a polysilicon layer).

[0145] The first low-density mask pattern 30b and the second low-density mask pattern 32b comprise separate patterns spaced apart from each other in a first horizontal direction (X direction). In the first horizontal direction, the width of the separate patterns of the first low-density mask pattern 30b and the second low-density mask pattern 32b may be greater than the width of the separate patterns of the first high-density mask pattern 30a and the second high-density mask pattern 32a.

[0146] The width of each individual pattern of the first low-density mask pattern 30b and the second low-density mask pattern 32b can be tens of nanometers. A third opening 33c exposing the surface of the semiconductor substrate 110 can be formed between the two individual patterns of the first low-density mask pattern 30b and the second low-density mask pattern 32b. The first low-density mask pattern 30b and the second low-density mask pattern 32b can each comprise a silicon oxide layer and a polysilicon layer (e.g., the first low-density mask pattern 30b can be a silicon oxide layer and the second low-density mask pattern 32b can be a polysilicon layer).

[0147] Reference Figure 10B A mask layer 34 is formed on the first high-density mask pattern 30a, the second high-density mask pattern 32a, and the low-density mask patterns 30b and 23b. In some embodiments, the mask layer 34 may be a photoresist layer. In some embodiments, the mask layer 34 may be a hard mask layer. In some embodiments, the mask layer 34 may be a spin-coated hard mask (SOH) layer.

[0148] Here, the SOH layer may comprise a material containing a hydrocarbon or derivative thereof having a relatively high carbon content of approximately 85 wt% to approximately 99 wt% based on total weight. The mask layer 34 may have a first thickness d3a.

[0149] Subsequently, using the above references Figure 1B and Figure 2 The description includes the white area ( Figure 2 16a) and gray area ( Figure 2 16c) multi-tone mask ( Figure 2 The MK1 is used to expose the mask layer 34. In this way, the mask layer 34 can be divided into layers that are formed with a multi-tone mask (MK1). Figure 2 The white area of ​​MK1 in the middle ( Figure 2 The high-exposure layer 34a corresponding to 16a) and the layer formed with the multi-tone mask ( Figure 2 The gray area of ​​MK1 in ( Figure 2 The low-exposure layer 34b corresponds to 16c in the model.

[0150] Reference Figure 10C Selective removal of overexposed layers ( Figure 10B The developer in 34a) is used to make the high-exposure layer ( Figure 10B 34a) and low exposure layer ( Figure 10B Developed in this way, a first mask exposure pattern region 34a-1 can be formed in the peripheral circuit region PPCR and the low-density patterning region LDPR, exposing the semiconductor substrate 110 and the first low-density mask pattern 30b and the second low-density mask pattern 32b. The first mask exposure pattern region 34a-1 can be formed by making the white area of ​​the multi-tone mask MK1 ( Figure 2 The high-exposure layer corresponding to 16a in ( Figure 10B 34a) The area formed by exposure and development.

[0151] Furthermore, in the cell region CELR and the high-density patterning region HDPR, a second mask pattern region 34b-1 can be formed that does not expose the semiconductor substrate 110, the first high-density mask pattern 30a, and the second high-density mask pattern 32a. The second mask pattern region 34b-1 can be formed by using a multi-tone mask (…). Figure 2 The gray area of ​​MK1 in ( Figure 2 The low-exposure layer corresponding to 16c in (in) Figure 10B (34b) The area formed by exposure and development.

[0152] When by making the high-exposure layer ( Figure 10B 34a) and low exposure layer ( Figure 10B When developing the second mask pattern region 34b-1 using the development of 34b), the second mask pattern region 34b-1 may have a second thickness d3b. The second thickness d3b may be less than... Figure 10B The first thickness d3a.

[0153] Reference Figure 10D The semiconductor substrate 110 located below the first mask exposure pattern region 34a-1 is etched using the second mask pattern region 34b-1 as an etching mask to form a first initial pattern 36. In this embodiment, for convenience, only a single first initial pattern 36 is shown, but if multiple first low-density mask patterns 30b and second low-density mask patterns 32b are provided, the first initial pattern 36 can be formed in multiple ways.

[0154] When forming the first initial pattern 36, the second mask pattern region 34b-1 can be etched to give the second mask pattern region 34b-1 a third thickness d3c. The third thickness d3c can be less than... Figure 10C The second thickness d3b. The first initial pattern 36 may have a first sub-depth d4a.

[0155] Reference Figure 10E Further etching of the second mask pattern area ( Figure 10D The second mask exposure pattern region 34b-2 is formed to expose the first high-density mask pattern 30a and the semiconductor substrate 110. When forming the second mask exposure pattern region 34b-2, the second high-density mask pattern 32a and the second low-density mask pattern 32b can be etched.

[0156] When forming the second mask exposure pattern region 34b-2, the first initial pattern 36 of the first mask exposure pattern region 34a-1 can be further etched to give the first initial pattern 36 of the first mask exposure pattern region 34a-1 a second sub-depth d4b. The second sub-depth d4b can be greater than the first sub-depth d4a.

[0157] In this embodiment, refer to respectively Figure 10D and Figure 10E This describes the formation of the second mask exposure pattern region 34b-2 and the first initial pattern 36, but can be performed in a single manufacturing process. Figure 10D and Figure 10E The manufacturing process.

[0158] Reference Figure 10F Further etching is performed on the first mask exposure pattern area 34a-1 and the first initial pattern ( Figure 10E The semiconductor substrate 110 below the first high-density mask pattern 30a in the second mask exposure pattern region 34b-2 is etched to form a second pattern 38b with a second depth d4d smaller than the first depth d4c (e.g., including a first separate pattern with a space therebetween, wherein the space is formed by a trench with a first depth d4d).

[0159] Based on the above example, the semiconductor substrate 110 is further etched using the first low-density mask pattern 30b of the first mask exposure pattern region 34a-1 and the first high-density mask pattern 30a of the second mask exposure pattern region 34b-2 as an etching mask to form the first pattern 38a and the second pattern 38b. During the formation of the first pattern 38a and the second pattern 38b, a third pattern 40 (e.g., a trench) with a large width can be formed in the boundary region between the cell region CELR and the peripheral circuit region PPCR.

[0160] The first pattern 38a, the second pattern 38b, and the third pattern 40 can be the first trench pattern, the second trench pattern, and the third trench pattern, respectively. Furthermore, a low-density active pattern AC1 is formed around or within the first pattern 38a in the first mask exposure pattern region 34a-1. Additionally, a high-density active pattern AC1 is formed between the second patterns 38b in the second mask exposure pattern regions 34b-2.

[0161] Reference Figure 10G A method for manufacturing a semiconductor device by removing a first low-density mask pattern 30b and a first high-density mask pattern 30a, including the process of forming an active region AC1 (or an active pattern).

[0162] Figures 11A to 18 It shows the manufacturing process. Figure 8A and Figure 9A A cross-sectional view of the method of semiconductor device EX1 shown in the figure.

[0163] In detail, Figures 11A to 18 The above references are shown. Figures 10A to 10G The described manufacturing process for the active region AC1 (or active pattern) is used to manufacture semiconductor devices. Figures 6 to 9B The method of EX1).

[0164] Figure 11A , Figure 13 , Figure 15 and Figure 17 This illustrates the manufacturing method in the first horizontal direction (X direction) (i.e., Figure 7 A cross-sectional view on A1-A1' in the diagram. Figure 11B yes Figure 11A A magnified view of part of EN3. Figure 12 , Figure 14 and Figure 16 This illustrates the manufacturing method in the second horizontal direction (Y direction) (i.e., Figure 7 A cross-sectional view on A2-A2' (in the diagram). Figures 11A to 18 The above references are briefly given or omitted. Figures 8A to 9B The given description.

[0165] like Figure 11A and Figure 11B As shown, on the semiconductor substrate ( Figure 8A Multiple active regions AC1 (or active patterns) are formed in the active region AC1, and a device isolation film 112 is formed between the active regions AC1. A buffer layer 122 is formed on the active regions AC1 (or active patterns) and the device isolation film 112.

[0166] In the active region AC1 (or active pattern), a lower conductive pattern 130, an intermediate conductive pattern 132, an upper conductive pattern 134, a first insulating capping pattern 136, a second insulating capping pattern 138, and a third insulating capping pattern 140 are formed on some of the upper surfaces. In some embodiments, the second insulating capping pattern 138 and the third insulating capping pattern 140 may include or may be silicon nitride layers.

[0167] Spacer structures BLS can be formed on opposite sides of the intermediate conductive pattern 132, the upper conductive pattern 134, the first insulating cap pattern 136, the second insulating cap pattern 138, and the third insulating cap pattern 140. The spacer structure BLS may include a second inner spacer 148, an intermediate spacer 150, and an outer spacer 152. The intermediate conductive pattern 132 and the upper conductive pattern 134 may form a bit line BL.

[0168] The lower conductive pattern 130 can form a direct contact DC. During the formation of the lower conductive pattern 130, a device isolation film and active region AC1 (or active pattern) surrounding the lower conductive pattern 130 can be etched to form a direct contact via DCH. A first internal spacer 144 and a gap-filling insulating pattern 146 can be formed on the bottom and sidewalls of the lower conductive pattern 130 within the direct contact via DCH. The first internal spacer 144 and the second internal spacer 148 can be formed during the same process.

[0169] In the first horizontal direction (X direction), the semiconductor substrate between the lower conductive pattern 130, the middle conductive pattern 132, the upper conductive pattern 134, the first insulating capping pattern 136, the second insulating capping pattern 138, and the third insulating capping pattern 140 ( Figure 8A In 110), a plug conductive layer 154, a plug metal silicide layer 156 and a lower conductive pattern 158 are formed.

[0170] A plug conductive layer 154 is formed within a buried contact hole BCH adjacent to the direct contact hole DCH, passing through the buffer layer 122. This can be achieved on a semiconductor substrate ( Figure 8AA buried contact hole BCH is formed on the active region AC1 (or active pattern) within 110. A plug conductive layer 154 and a plug metal silicide layer 156 can form a buried contact plug BC. A lower conductive pattern 158 can form a first landing pad LP1.

[0171] like Figure 12 As shown, multiple word lines WL can be formed within the device isolation film 112. The word lines WL may include gate conductive layers 114, 116, and 118. A gate capping layer 120 may be formed on the upper gate conductive layer 118.

[0172] Multiple buried contact plugs BC and lower conductive patterns 158 are formed on the active region AC1 (or active pattern). Multiple gate insulating material layers 160 spaced apart from each other in a second horizontal direction (Y direction) are formed between the multiple buried contact plugs BC and lower conductive patterns 158 on the gate cap layer 120 and the device isolation film 112. The gate insulating material layers 160 may include silicon nitride layers.

[0173] Reference Figure 13 and Figure 14 ,like Figure 13 As shown, the third insulating cap pattern is etched back ( Figure 11A 140), second insulating cover pattern ( Figure 11A 138), First insulating cover pattern ( Figure 11A Some parts and spacer structures of (136) Figure 11B Some parts of the BLS.

[0174] In this way, multiple lower conductive patterns 158 can be exposed, while the multiple lower conductive patterns 158 are spaced apart from each other in the first horizontal direction (X direction). The first insulating capping pattern can be etched back. Figure 11A Some parts of 136) and the first insulating cover pattern ( Figure 11A Some portions of 136) are transformed into insulating capping patterns 136r with reduced height. A first recessed opening 162 exposing the insulating capping pattern 136r may be formed between a plurality of lower conductive patterns 158. The lower conductive patterns 158 may be formed such that the lower conductive patterns 158 protrude a first vertical distance D1 from the first horizontal line PL1 on the upper surface of the insulating capping pattern 136r.

[0175] like Figure 14 As shown, the etched fence insulation material layer ( Figure 12 The portion 160 in the middle. In this way, multiple lower conductive patterns 158 can be spaced apart from each other and exposed in the second horizontal direction (Y direction). The fence insulating material layer can be etched back ( Figure 12 160 in the middle) and the fence insulation material layer ( Figure 12The 160 in the middle is transformed into a fence insulating layer 160r with a reduced height. A second recessed opening 164 exposing the fence insulating layer 160r can be formed between a plurality of lower conductive patterns 158. The lower conductive patterns 158 can be formed such that the lower conductive patterns 158 protrude a third vertical distance D3 from the first horizontal line PL1 on the upper surface of the fence insulating layer 160r.

[0176] Reference Figure 15 and Figure 16 A landing insulating layer 166 is formed on the lower conductive pattern 158, and the landing insulating layer 166 fills the first recessed opening between a plurality of lower conductive patterns 158 spaced apart in the first horizontal direction (X direction). Figure 13 (of 162), such as Figure 15 As shown in the diagram, a landing insulating layer 166 can be formed on the lower conductive pattern 158 at a third vertical distance D3.

[0177] A barrier insulation layer 168 is formed on the landing insulation layer 166. A second horizontal line PL2 can be formed on the upper surface of the landing insulation layer 166 and the lower surface of the barrier insulation layer 168. The vertical distance between the lower conductive pattern 158 and the second horizontal line PL2 can be a second vertical distance D2.

[0178] like Figure 16 As shown, a landing insulating layer 166 is formed on the lower conductive pattern 158, while the landing insulating layer 166 fills the second recessed openings between a plurality of lower conductive patterns 158 spaced apart in the second horizontal direction (Y direction). Figure 14 (164 in the text). A landing insulation layer 166 can be formed on the fence insulation layer 160r at a third vertical distance D3. A barrier insulation layer 168 is formed on the landing insulation layer 166. A second horizontal line PL2 can be formed on the upper surface of the landing insulation layer 166 and the lower surface of the barrier insulation layer 168.

[0179] Reference Figure 17 and Figure 18 In such Figure 17 A plurality of landing apertures 170 spaced apart from each other in a first horizontal direction (X direction) are formed within the barrier insulating layer 168 and the landing insulating layer 166 shown. The landing apertures 170 can be formed by patterning the landing insulating layer 166 and the barrier insulating layer 168 using a photolithography process. The landing apertures 170 can be filled with a conductive material layer and then the conductive material layer can be etched back to form upper conductive patterns 172 spaced apart from each other in the first horizontal direction (X direction).

[0180] The upper conductive pattern 172 constitutes the second landing pad LP2. The second landing pad LP2 can be moved horizontally relative to the first landing pad LP1 in the first horizontal direction (X direction) to be properly positioned. A portion of the second landing pad LP2 may not vertically overlap with the first landing pad LP1.

[0181] like Figure 18 As shown, a plurality of landing apertures 170 spaced apart from each other in the second horizontal direction (Y direction) are formed within the barrier insulating layer 168 and the landing insulating layer 166. The landing apertures 170 can be formed by patterning the landing insulating layer 166 and the barrier insulating layer 168 using a photolithography process. The landing apertures 170 can be filled with a conductive material layer, and then the conductive material layer is etched back to form a plurality of upper conductive patterns 172 spaced apart from each other in the second horizontal direction (Y direction).

[0182] The upper conductive pattern 172 forms the second landing pad LP2. The second landing pad LP2 can be positioned so as not to move horizontally relative to the first landing pad LP1 in the second horizontal direction (Y direction). The second landing pad LP2 can vertically overlap with the first landing pad LP1 to form a bond. Figures 11A to 18 One or more of the photolithography processes used to depict the patterns of semiconductor devices described can utilize photomasks and, for example, combinations of... Figures 1A to 5B The described process.

[0183] Figure 19 This is a cross-sectional view showing the cell region and peripheral circuit region of a semiconductor device manufactured according to an embodiment.

[0184] In detail, Figure 19 This illustrates the inclusion of, according to an embodiment. Figure 8A A cross-sectional view of the semiconductor device EX1 comprising the cell region CELR and the peripheral circuit region PPCR adjacent to the cell region CELR. Figure 19 The above references are briefly given or omitted. Figure 8A The given description.

[0185] Semiconductor device EX1 may include a semiconductor substrate ( Figure 8A The device isolation film 112 and the active region AC1 (or active pattern) are located within 110. The device isolation film 112 may include a silicon oxide film 112a and a silicon nitride film 112b.

[0186] The buffer layer 122 formed in the cell region CELR can also be formed in the peripheral circuit region PPCR. The buffer layer 122 may include a first silicon oxide film 122a, a second silicon oxide film 122b, and a silicon nitride film 122c.

[0187] Multiple bit lines BL, spaced apart from each other in the first horizontal direction (X direction), are formed on the buffer layer 122. Bit lines BL can also be formed in the peripheral circuit region PPCR. Bit lines BL may include an intermediate conductive pattern 132 and an upper conductive pattern 134. Spacer structure ( Figure 11B The BLS in the middle can be formed on one side of multiple bit lines BL.

[0188] In the cell region CELR, a direct contact DC can be formed below the bit line BL and connected to the active region AC1 (or active pattern). An embedded contact plug BC can be formed between multiple bit lines BL in the cell region CELR. The embedded contact plug BC may include a plug conductive layer 154 and a plug metal silicide layer 156.

[0189] A first insulating capping pattern 136r is formed on the bit line BL in the cell region CELR. A second insulating capping pattern 138 and a third insulating capping pattern 140 may be formed on the first insulating capping pattern 136r. The second insulating capping pattern 138 and the third insulating capping pattern 140 may include a silicon nitride layer.

[0190] A peripheral circuit spacer structure (184, BLS) may be formed on a bit line BL, a first insulating cap pattern 136r, and a second insulating cap pattern 138, on one sidewall. The peripheral circuit spacer structure 184 may include a silicon nitride film 184a, a silicon oxide film 184b, and a silicon nitride film 184c. A peripheral circuit interlayer insulating layer 185 may be formed in the peripheral circuit region PPCR. The peripheral circuit interlayer insulating layer 185 may include a silicon oxide layer.

[0191] Multiple embedded patterns BP can be formed on the third insulating capping pattern 140 and the peripheral circuit interlayer insulating layer 185. The embedded patterns BP may include a conductive layer 186. The conductive layer 186 may include doped polysilicon, metal, metal silicide, conductive metal nitride, or a combination thereof. In some embodiments, the conductive layer 186 may include tungsten (W).

[0192] First landing pads LP1, spaced apart from each other in the first horizontal direction (X direction), can be formed on the embedded contact plug BC of the cell region CELR. The first landing pads LP1 protrude from the surface of the insulating cap pattern 136r above the bit line BL. The first landing pads LP1 may include a lower conductive pattern 158. The upper surface of the first landing pads LP1 may be substantially the same as the upper surface of the third insulating cap pattern 140.

[0193] A landing insulating layer 166 can be formed, covering the upper portion of a plurality of first landing pads LP1 and surrounding the sidewalls of the first landing pads LP1 in the cell region CELR. An opening 188 can be formed within the conductive layer 186 using a photolithography process. In some embodiments, the lower surface of the opening 188 can be located on the upper surface of the second insulating cap pattern 138.

[0194] An insulating layer 190 is formed within the opening 188. The insulating layer 190 may include a silicon oxide layer. The landing insulating layer 166 and the insulating layer 190 of the cell region CELR can be formed during the same process.

[0195] A barrier insulating layer 168 is formed on the landing insulating layer 166 of the cell region CELR. A landing aperture 170 is formed within the landing insulating layer 166 and the barrier insulating layer 168 in the cell region CELR. A second landing pad LP2, connected to the first landing pad LP1, is formed in the landing aperture 170. The second landing pad LP2 may include an upper conductive pattern 172. Figure 19 One or more of the patterns described for forming semiconductor devices can use photomasks and, for example, bonding... Figures 1A to 5B The described process.

[0196] Although the inventive concept has been specifically shown and described with reference to embodiments thereof, it will be understood that various changes in form and detail may be made herein without departing from the spirit and scope of the appended claims.

Claims

1. A method for manufacturing a semiconductor device, the method comprising: A mask layer is formed on the target pattern layer; The mask layer is exposed and developed by using a multi-tone mask that includes white and gray areas to form a first mask pattern region with a first thickness that exposes the pattern target layer and a second initial mask pattern region with a second sub-thickness that is smaller than the first thickness but does not expose the pattern target layer. The pattern target layer located below the first mask pattern area and the mask layer and the pattern target layer retained below the second initial mask pattern area are etched to form a first pattern with a first depth in the pattern target layer and a second pattern with a second depth smaller than the first depth in the pattern target layer. as well as Remove the mask layer.

2. The method according to claim 1, wherein, The gray area includes multiple slit line patterns and spatial patterns located between the multiple slit line patterns.

3. The method according to claim 1, wherein, The white area includes a pattern that allows light to pass through when the window is open.

4. The method according to claim 1, wherein, The white area is the region that exposes the mask layer and has a relatively large amount of light transmittance. The gray area is the region that exposes the mask layer and has a relatively lower light transmittance than the white area.

5. The method according to claim 4, wherein: The white area has 100% light transmittance, and The light transmittance of the gray area is between 25% and 75%.

6. The method according to claim 1, wherein, Forming the first pattern and the second pattern includes: Further forming a second mask pattern area; and The pattern target layer is etched to form the first pattern and the second pattern by using the first mask pattern area and the second mask pattern area as etch masks.

7. The method according to claim 6, wherein, The formation of the second mask pattern region, the first pattern, and the second pattern includes: Etching the pattern target layer located below the first mask pattern region to form a first initial pattern with a first sub-depth, and further etching the mask layer remaining below the second initial mask pattern region to form a second mask pattern region with a second thickness exposing the pattern target layer; and The pattern target layer located below the first mask pattern region and the first initial pattern is further etched to form the first pattern having the first depth, and the pattern target layer located below the second mask pattern region is etched to form the second pattern having a second depth smaller than the first depth.

8. The method according to claim 7, wherein, The first thickness is equal to the second thickness, and the first depth is deeper than the first sub-depth.

9. The method according to claim 1, wherein, The gray area is a first gray area, and the multi-tone mask further includes at least a second gray area, wherein the method further includes: While exposing and developing the mask layer using the multi-tone mask to form a first mask pattern region with a first thickness that exposes the pattern target layer and a second initial mask pattern region with a second sub-thickness smaller than the first thickness that does not expose the pattern target layer, a third initial mask pattern region with a third sub-thickness smaller than the second sub-thickness that does not expose the pattern target layer is also formed. While etching the pattern target layer located below the first mask pattern region and the mask layer and the pattern target layer remaining below the second initial mask pattern region to form the first pattern having the first depth in the pattern target layer and the second pattern having a second depth smaller than the first depth in the pattern target layer, the mask layer and the pattern target layer located below the third initial mask pattern region are etched to form a third pattern having a third depth smaller than the second depth in the pattern target layer.

10. The method according to claim 9, wherein, The first gray area of ​​the multi-tone mask is configured to allow a greater amount of light to pass through it than the second gray area of ​​the multi-tone mask.

11. A method of manufacturing a semiconductor device, the method comprising: A mask layer is formed on the target pattern layer; The mask layer is exposed and developed by using a multi-tone mask including a white area and a first gray area to a third gray area to form a first mask pattern area with a first thickness that exposes the pattern target layer and a second to a fourth initial mask pattern area that has a second sub-thickness to a fourth sub-thickness that is sequentially smaller than the first thickness and does not expose the pattern target layer. The pattern target layer located below the first mask pattern region is etched, and the mask layer and the pattern target layer located below the second initial mask pattern region to the fourth initial mask pattern region are etched to form a first pattern to a fourth pattern having successively smaller first to fourth depths; as well as Remove the mask layer.

12. The method according to claim 11, wherein: Each of the first gray region to the third gray region includes a plurality of first slit line patterns to a plurality of third slit line patterns, and a first spatial pattern to a third spatial pattern respectively located between the plurality of first slit line patterns to the plurality of third slit line patterns. The widths of the plurality of second slit patterns and the second spatial pattern are respectively smaller than the widths of the plurality of first slit patterns and the first spatial pattern, and The widths of the plurality of third slit patterns and the third spatial pattern are respectively smaller than the widths of the plurality of second slit patterns and the second spatial pattern.

13. The method according to claim 11, wherein: The white area includes a pattern that allows light to pass through when the window is open. The white area is the region that exposes the mask layer and has a relatively large amount of light transmittance. The first gray region to the third gray region are areas that expose the mask layer and have a relatively lower light transmittance than the white region. The light transmittance of the first gray area is between 60% and 80%. The light transmittance of the second gray area is between 40% and 60%, and The light transmittance of the third gray area is between 20% and 40%.

14. The method of claim 11, wherein: The first mask pattern area is formed to correspond to the white area, and The second to the fourth initial mask pattern regions are formed to correspond to the first to the third gray regions, respectively.

15. The method according to claim 11, wherein: Forming the first to the fourth patterns includes: Further forming a second mask pattern region, a third mask pattern region, and a fourth mask pattern region; and The patterned target layer is etched by using the first to the fourth mask patterned regions as etch masks.

16. The method according to claim 15, wherein, Forming the second mask pattern region, the third mask pattern region, and the fourth mask pattern region includes: The pattern target layer located below the first mask pattern area is etched to form a first initial pattern, and the mask layer remaining below the second initial mask pattern area is further etched to form a second mask pattern area exposing the pattern target layer; The pattern target layer located below the first initial pattern is further etched, and the pattern target layer located below the second mask pattern region is etched to form a second initial pattern. Furthermore, the mask layer remaining below the third initial mask pattern region is etched to form a third mask pattern region exposing the pattern target layer. The pattern target layer located below the first initial pattern and the second initial pattern is further etched, the pattern target layer located below the third mask pattern region is etched to form a third initial pattern, and the mask layer remaining below the fourth initial mask pattern region is further etched to form a fourth mask pattern region exposing the pattern target layer.

17. The method according to claim 16, wherein, Forming the first to the fourth patterns includes: Further etching of the pattern target layer located below the first mask pattern area and the first initial pattern to form the first pattern having the first depth; The pattern target layer located below the second mask pattern area and the second initial pattern is further etched to form a second pattern with a second depth smaller than the first depth; Further etching is performed on the pattern target layer located below the third mask pattern region and the third initial pattern to form the third pattern having a third depth smaller than the second depth. The pattern target layer located below the fourth mask pattern region is etched to form the fourth pattern having a fourth depth that is smaller than the third depth.

18. A method of manufacturing a semiconductor device, the method comprising: A high-density mask pattern and a low-density mask pattern are formed on a semiconductor substrate, wherein the semiconductor substrate is a pattern target layer, the high-density mask patterns are spaced apart from each other, and the low-density mask patterns are spaced apart from each other. A mask layer is formed on the high-density mask pattern and the low-density mask pattern; The mask layer is exposed and developed by using a multi-tone mask that includes white and gray areas to form a first mask exposure pattern area that exposes the semiconductor substrate and the low-density mask pattern, and a second mask pattern area that does not expose the semiconductor substrate or the high-density mask pattern. The semiconductor substrate located below the first mask exposure pattern area is etched to form a first initial pattern, and the second mask pattern area is further etched to form a second mask exposure pattern area exposing the high-density mask pattern and the semiconductor substrate; and The semiconductor substrate located below the first mask exposure pattern area and the first initial pattern is further etched to form a first pattern with a first depth, and the semiconductor substrate located below the high-density mask pattern located in the second mask exposure pattern area is etched to form a second pattern with a second depth smaller than the first depth. Wherein, the first pattern is a first trench pattern, the second pattern is a second trench pattern, a low-density active pattern is formed between the first trench patterns, and a high-density active pattern is formed between the second trench patterns.

19. The method according to claim 18, wherein, The high-density mask pattern is formed in the cell region of the semiconductor substrate, and The low-density mask pattern is formed in the peripheral circuit region of the semiconductor substrate.

20. The method according to claim 18, wherein, The mask layer is removed when the second mask exposure pattern area is formed.

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