Managing air gaps in three-dimensional semiconductor devices

Abstract

Systems, apparatuses, and methods for managing air gaps in semiconductor devices are provided. In one aspect, a semiconductor device includes a first array structure including bit lines, wherein two adjacent bit lines are separated by a first isolation structure having a first air gap, a second array structure adjacent to the first array structure in a first direction, the second array structure including connection lines, wherein two adjacent connection lines are separated by a second isolation structure having a second air gap, and a gate line. A first end of the first air gap is on a first side of a first end of the second air gap, and the gate line is on a second side of the first end of the second air gap.

Description

Technical Field

[0001] This disclosure relates to semiconductor devices and manufacturing processes for semiconductor devices. Background Technology

[0002] Semiconductor devices can be categorized into non-volatile memory devices (such as flash memory devices) and volatile memory devices (such as dynamic random access memory (DRAM)). Semiconductor memory devices can have different structures with varying densities of memory cells and lines on the chip. Memory devices typically include a memory array of memory cells and control circuitry. The control circuitry facilitates the operation of the memory array. Summary of the Invention

[0003] This disclosure describes methods, apparatus, systems, and techniques for managing air gaps in three-dimensional (3D) semiconductor devices.

[0004] One aspect of this disclosure features a semiconductor device comprising: a first array structure including bit lines, wherein two adjacent bit lines are separated along a first direction by a first isolation structure, the first isolation structure including a first air gap; a second array structure adjacent to the first array structure along the first direction, the second array structure including interconnects, wherein two adjacent interconnects are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and a gate line extending along the first direction and adjacent to both the first and second array structures. Along a second direction perpendicular to the first direction, a first end of the first air gap rests on a first side of the first end of the second air gap, the gate line rests on a second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap rests between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap rests between the first end of the first air gap and the gate line along the second direction.

[0005] In some embodiments, along the second direction, the first end of the first air gap is above one end of one of the two adjacent bit lines, and the first end of the second air gap is below one end of one of the two adjacent bit lines.

[0006] In some implementations, the area of ​​the second air gap is smaller than the area of ​​the first air gap.

[0007] In some embodiments, along the second direction, the second end of the first air gap is on one side of the second end of the second air gap, and the gate line is on one side of the second end of the second air gap.

[0008] In some embodiments, the dimension of the second air gap along the first direction is smaller than the dimension of the first air gap along the first direction.

[0009] In some embodiments, the dimension of the second air gap along the second direction is smaller than the dimension of the first air gap along the second direction.

[0010] In some embodiments, the first array structure includes a semiconductor body extending along a second direction, a first end of the semiconductor body coupled to a corresponding bit line in the bit line, and a second end of the semiconductor body coupled to a capacitor. The first end of the semiconductor body is opposite to the second end of the semiconductor body along the second direction.

[0011] In some embodiments, a first array structure is located in an array region, and a second array structure is located in an edge region adjacent to the array region. A gate line includes a first portion in the array region, a third portion in the edge region, and a second portion along a first direction between the first and third portions. The height of the second portion of the gate line along a second direction is greater than the height of the first portion of the gate line along the second direction.

[0012] In some implementations, the height of the first portion of the gate line along the second direction is the same as the height of the third portion of the gate line along the second direction.

[0013] In some embodiments, bit line contact structures are arranged in a first alternating pattern along a first direction, and bit line contact structures in the bit line contact structures are coupled to corresponding bit lines in the bit lines; a plurality of gate lines including gate lines; and gate line contact structures are coupled to corresponding gate lines in the plurality of gate lines, and are arranged in a second alternating pattern along a third direction. The third direction is perpendicular to the first and second directions.

[0014] Another aspect of this disclosure features a semiconductor device comprising: a first array structure including bit lines, wherein two adjacent bit lines are separated along a first direction by a first isolation structure, the first isolation structure including a first air gap; a second array structure adjacent to the first array structure along the first direction, the second array structure including interconnects, wherein two adjacent interconnects are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and a gate line extending along the first direction and adjacent to both the first and second array structures. The area of ​​the second air gap is smaller than the area of ​​the first air gap.

[0015] In some embodiments, along a second direction perpendicular to the first direction, the first end of the first air gap is above one end of one of the two adjacent bit lines, and the first end of the second air gap is below one end of one of the two adjacent bit lines.

[0016] In some embodiments, along a second direction perpendicular to the first direction, the first end of the first air gap is on the first side of the first end of the second air gap, the gate line is on the second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction.

[0017] In some embodiments, along the second direction, the second end of the first air gap is on one side of the second end of the second air gap, and the gate line is on one side of the second end of the second air gap.

[0018] In some embodiments, the dimension of the second air gap along the first direction is smaller than the dimension of the first air gap along the first direction.

[0019] In some embodiments, the dimension of the second air gap along the second direction is smaller than the dimension of the first air gap along the second direction, and the second direction is perpendicular to the first direction.

[0020] Another aspect of this disclosure features a method comprising: forming a first array structure including bit lines, wherein two adjacent bit lines are separated along a first direction by a first isolation structure, the first isolation structure including a first air gap; forming a second array structure adjacent to the first array structure along the first direction, the second array structure including connecting lines, wherein two adjacent connecting lines are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and forming a gate line extending along the first direction and adjacent to both the first and second array structures. Along a second direction perpendicular to the first direction, a first end of the first air gap is on a first side of the first end of the second air gap, the gate line is on a second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction.

[0021] In some embodiments, the method includes: forming a third air gap surrounded by a first dielectric layer in a second isolation structure; removing the third air gap and the first dielectric layer in the second isolation structure; and forming a second air gap surrounded by a second dielectric layer in the second isolation structure.

[0022] In some implementations, the method includes: the size of the third air gap is substantially equal to the size of the first air gap.

[0023] In some embodiments, forming a second air gap surrounded by a second dielectric layer in a second isolation structure includes depositing a second dielectric layer in the second isolation structure by atomic layer deposition (ALD).

[0024] In some embodiments, the method includes: depositing a conductive layer on a first initial array structure and a second initial array structure; depositing a hard mask that covers a first portion of the conductive layer on the second initial array structure; at least partially removing a second portion of the conductive layer on the first initial array structure; and removing the hard mask.

[0025] In some embodiments, the method includes: depositing a conductive material on a semiconductor line of a first initial array structure; and annealing the conductive material such that the conductive material reacts with the material of the semiconductor line to form a composite conductive material.

[0026] Details of one or more embodiments of the subject matter of this disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of this subject matter will become apparent from the specification, drawings, and claims. Attached Figure Description

[0027] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate various aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to implement and use this disclosure.

[0028] Figure 1 A cross-sectional view of an exemplary 3D semiconductor device is shown.

[0029] Figure 2A It shows Figure 1 A cross-sectional view of a semiconductor device.

[0030] Figures 2B to 2E It shows Figure 2A An unfolded diagram of the air gap of a semiconductor device.

[0031] Figure 3 It shows Figure 2A A plan view of a semiconductor device.

[0032] Figures 4A to 4J It shows Figure 2A Cross-sectional views of semiconductor devices at various stages of the manufacturing process.

[0033] Figure 5 It shows the formation Figure 2A A flowchart of an exemplary process for a semiconductor device.

[0034] Figure 6 A block diagram of the system is shown.

[0035] It should be understood that the various exemplary embodiments shown in the accompanying drawings are merely illustrative representations and are not necessarily drawn to scale. Detailed Implementation

[0036] In some cases, a DRAM memory device may include a memory array having multiple active memory cells, and the memory array may be surrounded by a dummy array structure having multiple dummy memory cells. The dummy array structure may include interconnects extending in the bit line direction and having dimensions and spacing substantially similar to the bit lines. During the manufacturing process, air gaps may form between adjacent interconnects of the dummy array structure. These air gaps may trap gases generated during the film deposition step, causing problems in subsequent etching processes. In some cases, when contact holes are etched through the air gap to reach the structure beneath the air gap, outgassing may cause under-etching during contact formation. Under-etching problems can result in overall yield loss.

[0037] Embodiments of this disclosure provide a semiconductor device and a method for forming such a semiconductor device. In some embodiments, a semiconductor device includes: a first array structure including bit lines, wherein two adjacent bit lines are separated along a first direction by a first isolation structure, the first isolation structure including a first air gap; a second array structure adjacent to the first array structure along the first direction, the second array structure including interconnects, wherein two adjacent interconnects are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and a gate line extending along the first direction and adjacent to both the first array structure and the second array structure. Along a second direction perpendicular to the first direction, a first end of the first air gap is on a first side of the first end of the second air gap, the gate line is on a second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction.

[0038] Embodiments of this disclosure may provide one or more of the following technical advantages and / or benefits. For example, the techniques described in this disclosure can significantly improve yield by about 50% by eliminating or mitigating outgassing problems. When depositing a film (e.g., a dielectric layer) in the openings between adjacent interconnects of a dummy array structure, outgassing may occur in the air gaps between those adjacent interconnects and be trapped therein. In some cases, the dielectric layer comprises a black diamond dielectric film and is deposited by chemical vapor deposition (CVD). When etching through the air gap to form a conductive structure (e.g., a contact) connected to the structure below the air gap (e.g., a TISO described below), the gas generated by the deposition process may subsequently cause etching problems (e.g., under-etching). Under-etching problems can lead to overall yield loss. Additionally, the air gap may be close to the word lines in a vertical direction (e.g., within a few nanometers), causing impurities to migrate from the word lines into the air gap. These impurities may further exacerbate the under-etching problem. In some embodiments, prior to the etching step, the techniques described in this disclosure remove outgassing trapped in the air gap and deposit a new dielectric material layer in the opening using a different deposition method (e.g., atomic layer deposition (ALD)). In some cases, unlike CVD, ALD may not generate outgassing (e.g., BDII gas), thereby eliminating or reducing under-etching problems and improving yield. Furthermore, the air gap formed during the ALD deposition process can be smaller than the air gap formed during the CVD process, and the air gap formed during the ALD deposition process can be further away from the word line. Due to the increased distance between the word line and the air gap, contamination from impurities from the word line can also be reduced, thereby further improving yield.

[0039] This technology can be applied to various types of semiconductor devices, volatile memory devices (e.g., DRAM memory devices), or non-volatile memory (NVM) devices (e.g., NAND flash memory, NOR flash memory, resistive random access memory (RRAM), phase-change memory (PCM) (e.g., PCRAM), spin-transfer torque (STT) magnetoresistive random access memory (MRAM), etc.). It can also be applied to charge-trapping based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating-gate based memory devices. This technology can be applied to three-dimensional (3D) memory devices. It can be applied to various memory types, such as SLC (single-level storage) devices, MLC (multi-level storage) devices (e.g., 2-level storage devices), TLC (triple-level storage) devices, QLC (quadruple-level storage) devices, or PLC (five-level storage) devices. Additionally or alternatively, this technology can be applied to various types of devices and systems, such as secure digital cards (SD cards), embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0040] Figure 1 A side view of a cross-section of an exemplary 3D semiconductor device 100 is shown. The 3D semiconductor device 100 may be a 3D dynamic random access memory (DRAM). It should be understood that... Figure 1 This is for illustrative purposes only and may not necessarily reflect the actual device structure (e.g., interconnects) in practice. In some embodiments, the 3D semiconductor device 100 is a bonded chip including a first semiconductor structure 102 and a second semiconductor structure 104 stacked on top of the first semiconductor structure 102. The first semiconductor structure 102 and the second semiconductor structure 104 may be bonded at a bonding interface 106 between them.

[0041] like Figure 1 As shown, the first semiconductor structure 102 may include a substrate 110, which may include silicon (e.g., single-crystal silicon, c-Si), SiGe, GaAs, Ge, SOI, or any other suitable material. The first semiconductor structure 102 may include peripheral circuitry 112 on and / or within the substrate 110. In some embodiments, the peripheral circuitry 112 includes a plurality of transistors 114 (e.g., planar transistors and / or 3D transistors). Trench isolation (e.g., shallow trench isolation (STI)) and doped regions (e.g., wells, sources, and drains of transistors 114) may also be formed on or within the substrate 110. In some examples, the peripheral circuitry 112 is formed using complementary metal-oxide-semiconductor (CMOS) technology, and the first semiconductor structure 102 may also be formed on a semiconductor die, which may be referred to as a control die or CMOS die 102.

[0042] In some embodiments, the first semiconductor structure 102 further includes an interconnect layer 116 located above the peripheral circuitry 112 to transmit electrical signals to and from the peripheral circuitry 112. The interconnect layer 116 may include multiple interconnects (also referred to herein as “contacts”), including lateral interconnects and via contacts. The interconnect layer 116 may also include one or more interlayer dielectric (ILD) layers, in which interconnects and via contacts may be formed. That is, the interconnect layer 116 may include interconnects and via contacts in multiple ILD layers. In some embodiments, the peripheral circuitry 112 is coupled to each other via interconnects in the interconnect layer 116. The interconnects in the interconnect layer 116 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0043] like Figure 1 As shown, the first semiconductor structure 102 has a front side and a back side, and the first semiconductor structure 102 may also include a bonding layer 118, which is located on the back side at the bonding interface 106 and above the interconnect layer 116 and the peripheral circuitry 112. The bonding layer 118 may include a plurality of bonding contacts 119 and a dielectric that electrically isolates the bonding contacts 119. The bonding contacts 119 may include a conductive material, such as Cu. The remaining region of the bonding layer 118 may be formed of a dielectric material such as silicon oxide. The bonding contacts 119 in the bonding layer 118 and the surrounding dielectric may be used for hybrid bonding. Similarly, as Figure 1 As shown, the second semiconductor structure 104 may further include a bonding layer 120 at the bonding interface 106 and above the bonding layer 118 of the first semiconductor structure 102. The bonding layer 120 may include a plurality of bonding contacts 121 and a dielectric that electrically isolates the bonding contacts 121. The bonding contacts 121 may include a conductive material, such as Cu. The remaining region of the bonding layer 120 may be formed of a dielectric material such as silicon oxide. The bonding contacts 121 in the bonding layer 120 and the surrounding dielectric may be used for mixed bonding. The bonding contacts 121 may contact the bonding contacts 119 at the bonding interface 106. In some embodiments, such as Figure 1 As shown, the bonding layer 120 includes a dielectric layer opposite to a memory cell (e.g., a DRAM cell) 124, wherein bit lines 123 are located between the dielectric layer and the memory cell 124. The dielectric layer may include a bonding interface 106 having bonding contacts 121.

[0044] The second semiconductor structure 104 can be bonded face-to-face to the top of the first semiconductor structure 102 at the bonding interface 106. In some embodiments, as a result of hybrid bonding (also known as “metal / dielectric hybrid bonding”), the bonding interface 106 is disposed between the bonding layers 120 and 118, the hybrid bonding being a direct bonding technique (e.g., forming a bond between surfaces without the use of an intermediate layer such as solder or adhesive), and both metal-to-metal and dielectric-to-dielectric bonding can be achieved simultaneously. In some embodiments, the bonding interface 106 is the location where the bonding layers 120 and 118 meet and bond. In some instances, the bonding interface 106 can be a layer of a certain thickness having a top surface including the bonding layer 118 of the first semiconductor structure 102 and a bottom surface including the bonding layer 120 of the second semiconductor structure 104.

[0045] In some embodiments, the second semiconductor structure 104 further includes an interconnect layer 122, which includes bit lines 123 located above the bonding layer 120 for transmitting electrical signals. The interconnect layer 122 may include multiple interconnects, such as mid-stage (MEOL) interconnects and back-end stage (BEOL) interconnects. In some embodiments, the interconnects in the interconnect layer 122 also include local interconnects, such as bit lines 123 and word line contacts (not shown). The interconnect layer 122 may also include one or more ILD layers in which interconnect lines and via contacts can be formed. The interconnects in the interconnect layer 122 may include conductive materials, including but not limited to W, Co, Cu, Al, doped silicon, silicides, or any combination thereof. The ILD layers may be formed of dielectric materials, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof.

[0046] In some embodiments, peripheral circuitry 112 includes a word line driver / row decoder coupled to word line contacts in interconnect layer 122 via bonding contacts 121 and 119 located in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, peripheral circuitry 112 includes a bit line driver / column decoder coupled to bit line 123 and bit line contacts in interconnect layer 122 via bonding contacts 121 and 119 located in bonding layers 120 and 118 and interconnect layer 116. In some embodiments, bit line 123 is a metal bit line, rather than a semiconductor bit line (e.g., a doped silicon bit line). For example, bit line 123 may include W, Co, Cu, Al, or any other suitable metal having a higher conductivity than doped silicon. In some embodiments, the bit line contact is an ohmic contact, rather than a Schottky contact.

[0047] In some embodiments, bit line 123 is made of a composite conductive material, which may be based on a metallic material (e.g., W, Co, Cu, Al) and a semiconductor material (e.g., Si)). For example, the composite conductive material may include metal silicides such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon.

[0048] In some embodiments, the second semiconductor structure 104 includes a DRAM device, wherein memory cells are disposed above the interconnect layer 122 and the bonding layer 120 in the form of an array of DRAM cells 124. That is, the interconnect layer 122, including bit lines 123, may be disposed between the bonding layer 120 and the array of DRAM cells 124. The bit lines 123 in the interconnect layer 122 may be coupled to a string of DRAM cells 124. In some embodiments, the second semiconductor structure 104 is formed on a semiconductor die and may be referred to as an array die 104.

[0049] In some embodiments, a semiconductor device may include a plurality of array dies (e.g., array die 104) and CMOS dies (e.g., CMOS die 102). The array dies and CMOS dies may be stacked and bonded together. A CMOS die may be coupled to each of the array dies individually and may drive each of the array dies individually to operate in a manner similar to that of the semiconductor device. The semiconductor device may be any suitable device. In some examples, the semiconductor device includes at least a first wafer and a second wafer bonded face-to-face. Array dies may be disposed on the first wafer along with other array dies, and CMOS dies may be disposed on the second wafer along with other CMOS dies. The first and second wafers may be bonded together, and thus the array dies on the first wafer may be bonded to corresponding CMOS dies on the second wafer. In some examples, the semiconductor device is a chip having at least array dies and CMOS dies bonded together. In this example, the chip is diced from the bonded wafer. In another example, the semiconductor device is a semiconductor package including one or more semiconductor chips assembled on a packaging substrate.

[0050] Each DRAM cell 124 may include a vertical transistor 126 and a capacitor 128 coupled to the vertical transistor 126. The DRAM cell 124 may be a 1T1C cell consisting of one transistor and one capacitor. It should be understood that the DRAM cell 124 may be any suitable configuration, such as a 2T1C cell, a 3T1C cell, etc. The vertical transistor 126 may be a MOSFET for switching the corresponding DRAM cell 124. In some embodiments, the vertical transistor 126 includes a vertically (in the z-direction) extending semiconductor body 130 (in which an active region may form a channel) and a gate structure 136 contacting one side of the semiconductor body 130. In a single-gate vertical transistor, the semiconductor body 130 may have a cuboid or cylindrical shape, and in a planar view, for example as shown in the figure below. Figure 1 As shown, gate structure 136 may be adjacent to one side of semiconductor body 130. In some embodiments, vertical transistor 126 has a structure including two or more gates, such as a dual-gate structure, a tri-gate structure, or a gate all-around (GAA) structure. In some embodiments, gate structure 136 includes gate electrode 134 and gate dielectric 132, the gate dielectric 132 being laterally located between gate electrode 134 and semiconductor body 130 in the bit line direction (e.g., in the Y direction). In some embodiments, gate dielectric 132 is adjacent to one side of semiconductor body 130, and gate electrode 134 is adjacent to gate dielectric 132.

[0051] like Figure 1 As shown, in some embodiments, the semiconductor body 130 has two ends in the vertical direction (z-direction). Figure 1 The semiconductor body 130 has two ends (upper and lower) extending in the vertical direction (z-direction) beyond the gate dielectric 132 into the ILD layer. In some embodiments, one end (e.g., the upper end) of the semiconductor body 130 is flush with the corresponding end (e.g., the upper end) of the gate dielectric 132. In some embodiments, both ends (upper and lower) of the semiconductor body 130 extend in the vertical direction (z-direction) beyond the gate electrode 134 into the ILD layer. That is, the semiconductor body 130 may have a larger vertical dimension (e.g., depth) than the vertical dimension (e.g., in the z-direction) of the gate electrode 134, and neither the upper nor lower end of the semiconductor body 130 is flush with the corresponding end of the gate electrode 134. This avoids short circuits between the bit line 123 and the word line / gate electrode 134, or between the word line / gate electrode 134 and the capacitor 128. The vertical transistor 126 may also include a source and a drain (both referred to as 138, as their positions can be interchanged) respectively disposed at both ends (upper and lower ends) of the semiconductor body 130 in the vertical direction (z-direction). In some embodiments, one of the source and drain 138 (e.g., in...) Figure 1 At the upper end of the middle) it is coupled to capacitor 128, and the other of the source and drain 138 (e.g., in the upper end of the middle) ... Figure 1 At the lower end of the line, it is coupled to line 123. That is to say, as... Figure 1 As shown, the vertical transistor 126 may have a first terminal in the positive z-direction and a second terminal opposite to the first terminal in the negative z-direction.

[0052] In some embodiments, the semiconductor body 130 comprises a semiconductor material, such as monocrystalline silicon, polycrystalline silicon, amorphous silicon, Ge, any other semiconductor material, or any combination thereof. In one example, the semiconductor body 130 may comprise monocrystalline silicon. The source and drain 138 may be doped with an N+ type dopant (e.g., phosphorus (P) or arsenic (As)) or a P type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. In some embodiments, a silicide layer (e.g., a metal silicide layer) is formed between the source / drain 138 of the vertical transistor 126 and the bit line 123 as a bit line contact, or formed between the source / drain 138 of the vertical transistor 126 and the first electrode of the capacitor 128 as a capacitor contact 142 to reduce contact resistance. In some embodiments, the gate dielectric 132 comprises a dielectric material, such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. In some embodiments, the gate electrode 134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicide, or any combination thereof. In some embodiments, the gate electrode 134 comprises multiple conductive layers, such as a W layer over a TiN layer. In one example, the gate structure 136 may be a "gate oxide / gate polysilicon" gate, wherein the gate dielectric 132 comprises silicon oxide and the gate electrode 134 comprises doped polysilicon. In another example, the gate structure 136 may be an HKMG, wherein the gate dielectric 132 comprises a high-k dielectric and the gate electrode 134 comprises a metal.

[0053] As described above, since the gate electrode 134 can be part of a word line or extend as a word line in the word line direction (e.g., the X direction), the second semiconductor structure 104 of the 3D semiconductor device 100 can also include multiple word lines, each extending in the word line direction. Each word line 134 can be coupled to a row of DRAM cells 124. That is, the bit line 123 and the word line 134 can extend in two perpendicular lateral directions, and the semiconductor body 130 of the vertical transistor 126 can extend in a direction perpendicular to the two lateral directions in which the bit line 123 and the word line 134 extend. The word line 134 contacts a word line contact (not shown). In some embodiments, the word line 134 comprises a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, silicides, or any combination thereof. In some embodiments, such as Figure 1 As shown, word line 134 includes multiple conductive layers, such as a W layer on top of a TiN layer.

[0054] In some implementations, such as Figure 1 As shown, the vertical transistor 126 extends vertically through and contacts the word line 134, and the source or drain 138 at the lower end of the vertical transistor 126 contacts the bit line 123 (or bit line contact, if any). Therefore, due to the vertical arrangement of the vertical transistor 126, the word line 134 and the bit line 123 can be arranged in different planes in the vertical direction, which simplifies the wiring of the word line 134 and the bit line 123. In some embodiments, the bit line 123 is vertically disposed between the bonding layer 120 and the word line 134, and the word line 134 is vertically disposed between the bit line 123 and the capacitor 128. The word line 134 can be coupled to the peripheral circuitry 112 in the first semiconductor structure 102 via word line contacts (not shown) in the interconnect layer 122, bonding contacts 121 and 119 in the bonding layers 120 and 118, and interconnects in the interconnect layer 116. Similarly, bit lines 123 in interconnect layer 122 can be coupled to peripheral circuits 112 in the first semiconductor structure 102 via bonding contacts 121 and 119 in bonding layers 120 and 118, and interconnects in interconnect layer 116.

[0055] In some implementations, the vertical transistors 126 may be arranged in a mirror-symmetric manner to increase the density of DRAM cells 124 in the bit-line direction (Y direction). For example... Figure 1As shown, two adjacent vertical transistors 126 in the bit line direction are mirror-symmetrical to each other with respect to the trench isolation 160. That is, the second semiconductor structure 104 may include a plurality of trench isolations 160, each trench isolation 160 extending parallel to the word line 134 in the word line direction (X direction) and disposed between the vertical gates 134 of two adjacent rows of vertical transistors 126. In some embodiments, rows of vertical transistors 126 separated by trench isolations 160 are mirror-symmetrical to each other with respect to the trench isolations 160. The trench isolations 160 may be formed of a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, low-k dielectrics, or any combination thereof. It should be understood that the trench isolations 160 may include air gaps, each air gap being laterally disposed between adjacent vertical gates 134. The air gaps may be formed due to the relatively small spacing of the vertical transistors 126 in the bit line direction (e.g., the Y direction). On the other hand, the relatively small dielectric constant of the air in the air gap (e.g., about 1 / 4 of the dielectric constant of silicon oxide) compared to some dielectrics (e.g., silicon oxide) can improve the insulation effect between the vertical transistors 126 (and the rows of DRAM cells 124). Similarly, in some embodiments, depending on the spacing of the word line / gate electrodes 134 in the bit line direction, the air gap is also formed laterally between the word line / gate electrodes 134 in the bit line direction.

[0056] In some embodiments, a shielding conductive structure 170 (e.g., comprising a metal such as W) is disposed between adjacent semiconductor bodies 130 of two adjacent rows of vertical transistors 126, instead of a trench isolation 160 with an air gap disposed between adjacent vertical gates 134 of two adjacent rows of vertical transistors 126. The shielding conductive structure 170 may contact at least one of the adjacent semiconductor bodies 130 and may be coupled to a low voltage (e.g., a fixed negative voltage), which can reduce charge buildup in the memory cells 124, thereby mitigating the floating body effect in the memory cells 124. Furthermore, by applying a fixed low voltage to the shielding conductive structure 170 between the memory cells 124, the threshold voltage of the memory cells 124 can be easily adjusted, which can reduce overall manufacturing complexity and cost and improve the reliability of the memory cells 124. Additionally, the shielding conductive structure 170 may be coupled out from the same side as the word line or from a side different from the word line. For example, the shielding conductive structure 170 may be coupled out from the back side of the second semiconductor structure 104. The shielding conductive structure 170 may also be referred to as a shielding conductive material. The trench isolation having such a shielded conductive structure 170 may also be referred to as trench isolation (TISO) in this disclosure.

[0057] like Figure 1As shown, in some embodiments, capacitor 128 includes a first electrode 144 above the source or drain 138 of vertical transistor 126 and coupled to the source or drain 138 of vertical transistor 126 (e.g., at the upper end of semiconductor body 130) via capacitor contact 142. In some embodiments, capacitor contact 142 is an ohmic contact, such as a metal silicide contact, rather than a Schottky contact. For example, capacitor contact 142 may include a metal silicide, such as WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide having a higher conductivity than doped silicon. Capacitor 128 may also include a capacitor dielectric above and in contact with the first electrode 144, and a second electrode above and in contact with the capacitor dielectric. That is, capacitor 128 may be a vertical capacitor in which the electrodes and capacitor dielectric are stacked vertically (in the z-direction), and the capacitor dielectric may be sandwiched between the electrodes. In some implementations, each first electrode is coupled to the source or drain 138 of a corresponding vertical transistor 126 in the same DRAM cell, while all second electrodes are coupled to a common plate 146, which is coupled to ground (e.g., common ground). Figure 1 As shown, capacitor 128 may have a first end in the negative z-direction and a second end in the positive z-direction opposite to the first end. In some embodiments, the first end of capacitor 128 is coupled to the first terminal of vertical transistor 126 via an ohmic contact (e.g., capacitor contact 142 made of metal silicide material). Figure 1 As shown, the second semiconductor structure 104 may also include capacitor contacts 147 (e.g., conductors) in contact with the common plate 146 for coupling the capacitor 128 to the peripheral circuit 112 or directly to ground. In some embodiments, such as Figure 1 As shown, capacitor contacts 147 (e.g., conductors) extend in the z-direction from the dielectric layer of bonding layer 120 to be coupled to a second end of capacitor 128 via common plate 146. In some embodiments, the ILD layer in which capacitor 128 is formed has the same dielectric material, such as silicon oxide, as the two ILD layers into which semiconductor body 130 extends.

[0058] It should be understood that the structure and construction of capacitor 128 are not limited to... Figure 1Examples are provided, and any suitable structure and construction may be included, such as a parallel-plate capacitor, a stacked capacitor, a multi-fin capacitor, a cylindrical capacitor, a trench capacitor, or a substrate-plate capacitor. In some embodiments, the capacitor dielectric includes a dielectric material such as silicon oxide, silicon nitride, or a high-k dielectric, including but not limited to Al2O3, HfO2, Ta2O5, ZrO2, TiO2, or any combination thereof. It should be understood that in some examples, capacitor 128 may be a ferroelectric capacitor used in FRAM cells, and the capacitor dielectric may be replaced by a ferroelectric layer having a ferroelectric material (e.g., PZT or SBT). In some embodiments, the electrodes include conductive materials, including but not limited to W, Co, Cu, Al, TiN, TaN, polycrystalline silicon, silicides, or any combination thereof.

[0059] like Figure 1 As shown, the vertical transistor 126 extends vertically through and contacts the word line 134. The source or drain 138 of the vertical transistor 126 contacts the bit line 123 at its lower end, and the source or drain 138 is coupled to the capacitor 128 at its upper end. That is, due to the vertical arrangement of the vertical transistor 126, the bit line 123 and the capacitor 128 can be arranged in different planes in the vertical direction and coupled vertically to opposite ends of the vertical transistor 126 of the DRAM cell 124. In some embodiments, the bit line 123 and the capacitor 128 are arranged on opposite sides of the vertical transistor 126 in the vertical direction. This simplifies the wiring of the bit line 123 and reduces the coupling capacitance between the bit line 123 and the capacitor 128 compared to a DRAM cell where the bit line and capacitor are arranged on the same side of a planar transistor.

[0060] like Figure 1 As shown, in some embodiments, the vertical transistor 126 is vertically disposed between the capacitor 128 and the bonding interface 106. That is, the vertical transistor 126 can be arranged closer to the peripheral circuitry 112 and the bonding interface 106 of the first semiconductor structure 102 than the capacitor 128. Since the bit line 123 is coupled to the opposite end of the vertical transistor 126 to the capacitor 128, the bit line 123 (as part of the interconnect layer 122) is vertically disposed between the vertical transistor 126 and the bonding interface 106. As a result, the interconnect layer 122, including the bit line 123, can be arranged close to the bonding interface 106 to reduce interconnect wiring distance and complexity.

[0061] In some embodiments, the second semiconductor structure 104 further includes a substrate 148 disposed above the DRAM cell 124. The substrate 148 may be part of a carrier wafer. It should be understood that in some instances, the substrate 148 may not be included in the second semiconductor structure 104.

[0062] like Figure 1 As shown, the second semiconductor structure 104 may further include a pad output interconnect layer 150 located above the substrate 148 and the DRAM cell 124. The pad output interconnect layer 150 may include interconnects in one or more ILD layers, such as contact pads 154. The pad output interconnect layer 150 and interconnect layer 122 may be formed on opposite sides of the DRAM cell 124. A capacitor 128 may be vertically disposed between the vertical transistor 126 and the pad output interconnect layer 150. In some embodiments, the interconnects in the pad output interconnect layer 150 may transmit electrical signals between the 3D semiconductor device 100 and external circuitry, for example, for pad output purposes.

[0063] In some embodiments, the second semiconductor structure 104 further includes one or more contacts 152 extending through a portion of the substrate 148 and the pad output interconnect layer 150 to couple the pad output interconnect layer 150 to the DRAM cell 124 and the interconnect layer 122. As a result, peripheral circuitry 112 can be coupled to the DRAM cell 124 via interconnect layers 116 and 122 and bonding layers 120 and 118, and peripheral circuitry 112 and the DRAM cell 124 can be coupled to external circuitry via the contacts 152 and the pad output interconnect layer 150. The contact pads 154 and contacts 152 may include conductive materials, including but not limited to W, Co, Cu, Al, silicides, or any combination thereof. In one example, the contact pads 154 may include Al, and the contacts 152 may include W. In some embodiments, the contacts 152 include vias surrounded by dielectric spacers (e.g., having silicon oxide) to electrically isolate the vias from the substrate 148. Depending on the thickness of the substrate 148, the contact 152 can be an ILV with a depth in the submicron range (e.g., between 10 nm and 1 μm) or a TSV with a depth in the micron range or tens of micron range (e.g., between 1 μm and 100 μm).

[0064] Although not shown, it should be understood that the pad outputs of the 3D memory device are not limited to those from sources such as... Figure 1The second semiconductor structure 104 shown has DRAM cells 124 and may be derived from a first semiconductor structure 102 having peripheral circuitry 112. Although not shown, it should be understood that the air gaps between word lines 134 and / or between semiconductor bodies 130 may be partially or completely filled with dielectric. Although not shown, it should be understood that an array of more than one DRAM cell 124 may be stacked on top of each other to vertically increase the number of DRAM cells 124.

[0065] In some embodiments, the second semiconductor structure 104 includes a substrate disposed beneath the DRAM cell 124, instead of... Figure 1 The diagram shows a substrate 148 above DRAM cell 124. The substrate may be part of a carrier wafer. DRAM cell 124 may be formed on the front side of the substrate, and bit line 123 may be formed on the back side of the substrate. Bit line 123 may be electrically coupled through the substrate to DRAM cell 124 (e.g., terminal 138 of vertical transistor 126).

[0066] Figure 2A A cross-sectional view of the semiconductor device 100 in the XZ plane is shown. Figures 2B-2E This is an unfolded view of the air gap of the semiconductor device 100. As shown, the memory device 100 includes a first array structure 202 and a second array structure 204 adjacent to the first array structure 202. For ease of description, reference will be made when describing the structure of the semiconductor device 100. Figures 2A-2E It should be noted that, with Figure 1 compared to, Figures 2A-2E It is shown from a flipped perspective along the z-axis. In Figures 2A-2E In the middle, bit line 123 is located in the positive z-direction compared to capacitor 128. This is consistent with... Figure 1 In contrast, Figure 1 The median line 123 is located in the negative z-direction of capacitor 128. Therefore, Figure 2A The "upper" or "top" end of the structure in the middle can be Figure 1 The "lower" or "bottom" end of the same structure. See below for reference. Figures 2A-2E The Z direction described refers to Figures 2A-2E The coordinate system used. It should be noted that... Figures 2A-2C It can be a composite view with superimposed cross-sectional planes. For example, Figure 2A It can be similar to passing through Figure 3 A composite view of the cross-sectional planes of the A-A' and B-B' axes, making Figure 2A The gate line 134 and the TISO contact structure 245 can be shown in a single side view. It should also be understood that, although the TISO contact structure 245 and the gate line 134 are shown in a composite view due to the cross-sectional plane, Figure 2A and Figure 2B While they appear to be in contact, in a real device, the TISO contact structure 245 and the gate line 134 are isolated from each other. The TISO contact structure 245 can be coupled to a TISO 170 (e.g., as shown in the image). Figure 3 (As shown). Figures 2A-2E For illustrative purposes only, and may not depict individual cross-sectional views within the actual device.

[0067] In some embodiments, the first array structure 202 includes active memory cells 124 for storing user data, while the second array structure 204 is a dummy array structure that does not include active memory cells 124. The second array structure 204 may be located at one or more edges of the first array structure 202. In some embodiments, the first array structure 202 includes bit lines 123, while the second array structure 204 does not include bit lines 123. In some embodiments, the first array structure 202 is coupled to a capacitor 128, while the second array structure 204 is not coupled to a capacitor 128.

[0068] In some embodiments, the first array structure 202 includes a bit line 123 extending in the y-direction and a first semiconductor body 206 extending in the z-direction. The bit line 123 may be coupled to a plurality of first semiconductor bodies 206 arranged in a line along the y-direction (see reference). Figure 1 The first semiconductor body 206 can be, for example, Figure 1 The semiconductor body 130 is located within the array. In some embodiments, the second array structure 204 includes a connecting line 223 extending in the y-direction and a second semiconductor body 208 extending in the z-direction. The connecting line 223 may be coupled to a plurality of second semiconductor bodies 208 arranged in a line along the y-direction. In some embodiments, the connecting line 223 comprises the same material as the second semiconductor bodies 208 (e.g., silicon). Unlike bit lines 123, the connecting line 223 in the second array structure 204 may not have a silicide material. Therefore, the connecting line 223 may not be used as bit lines 123.

[0069] In some embodiments, in the first array structure 202, two adjacent bit lines 123 of bit lines 123 are separated by a first isolation structure 212 along a first direction (e.g., the x-direction in FIG2), and the first isolation structure 212 includes a first air gap 210. The first isolation structure 212 may refer to the structure between adjacent bit lines 123. Without being limited to any particular theory, the first air gap 210 may be formed in the first isolation structure 212 during the film deposition process due to the relatively small spacing of the bit lines 123. In some embodiments, the first isolation structure 212 includes a first spacer layer 222, and the first air gap 210 is surrounded by the first spacer layer 222. The first spacer layer 222 may include a low-k (low dielectric constant) dielectric material. Adjacent first semiconductor bodies 206 may be isolated by a dielectric material 213. The dielectric material 213 may be the same as or different from the material of the first spacer layer 222. In some embodiments, the first spacer layer 222 includes, but is not limited to, silicon carbide (SiOC), organosilicon glass (OSG), carbon-doped oxide (CDO), or black diamond (BD). In some embodiments, the dielectric material 213 comprises silicon oxide. In some embodiments, the first spacer layer 222 comprises BDII and is deposited by CVD.

[0070] In some embodiments, in the second array structure 204, two adjacent connecting lines 223 are separated by a second isolation structure 226 along a first direction (e.g., Figure 2A The second isolation structure 226 may include a structure located between adjacent connection lines 223. In some embodiments, the second isolation structure 226 includes a second air gap 220. In some embodiments, the second isolation structure 226 includes a second spacer layer 224. The second spacer layer 224 may be a dielectric layer made of a dielectric material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the second spacer layer 224 is deposited by ALD.

[0071] In some embodiments, as described above, the semiconductor device 100 further includes a gate line 134 extending along a first direction (e.g., the x-direction). Figure 1 As shown in Figure 2, gate line 134 can be adjacent to both the first array structure 202 and the second array structure 204. In some embodiments, as referenced above... Figure 1As described, gate lines are coupled to memory cells 124 in the first array structure 202 for controlling vertical transistors 126 in memory cells 124. In some embodiments, the second array structure 204 does not include active memory cells 124 or bit lines 123, and therefore, gate lines 134 adjacent to the second array structure 204 are not used as transistor gates for the second array structure 204.

[0072] In some implementations, reference Figures 2A-2E Along a second direction perpendicular to the first direction (e.g., the x-direction) (e.g., the z-direction), the first end 214 of the first air gap 210 is on the first side 229a of the first end 228 of the second air gap 220. Figure 2D and 2E Gate line 134 is located on the second side 229b of the first end 228 of the second air gap 220, and the second side 229b of the first end 228 of the second air gap 220 is opposite to the first side 229a of the first end 228 of the second air gap 220 along a second direction (e.g., the z-direction). The second end 238 of the second air gap 220 is located between the first end 228 of the second air gap 220 and gate line 134 along the second direction, and the second end 234 of the first air gap 210 is located between the first end 214 of the first air gap 210 and gate line 134 along the second direction. In other words, along the z-direction, the first end 214 of the first air gap 210 is farther away from the capacitor 128 than the first end 228 of the second air gap 220.

[0073] In some embodiments, the distance 252 between the first end 228 of the second air gap 220 and one end 232 of the gate line 134 (refer to) Figure 2B The distance 254 between the first end 214 of the first air gap 210 and one end 232 of the gate line 134 is less than the distance between the first end 214 of the first air gap 210 and one end 232 of the gate line 134 (reference). Figure 2C The first end 214 of the first air gap 210 may refer to the top of the first air gap 210 further away from the gate line 134 or the capacitor 128 in the positive z direction. Similarly, the first end 228 of the second air gap 220 may refer to the top of the second air gap 220 further away from the gate line 134 or the capacitor 128 in the positive z direction. In some embodiments, one end 232 of the gate line 134 may refer to the end directly below the corresponding air gap along the negative z direction.

[0074] In some implementations, such as Figure 2A and Figure 2C As shown, the first air gap 210 extends beyond the adjacent bit line 123. In other words, the first end 214 of the air gap 210 is above one end 216 of the bit line 123 of the two adjacent bit lines 123. One end 216 of the bit line 123 can refer to the top of the bit line 123 further away from the capacitor 128. In contrast, as Figure 2A and Figure 2B As shown, the first end 228 of the second air gap 220 can be below one end 216 of the bit line 123 of the two adjacent bit lines 123.

[0075] In some embodiments, the area of ​​the second air gap 220 is smaller than the area of ​​the first air gap 210. The area can be the cross-sectional area of ​​the air gap in the xz plane. The xz plane can be a plane perpendicular to the bit line direction (y direction). In some embodiments, reference... Figure 2B and Figure 2C The second air gap 220 has a dimension 262 (e.g., width) along the letter direction (e.g., the x-direction) that is smaller than the first air gap 210's dimension 264 (e.g., width) along the same direction. In some embodiments, the second air gap 220 has a dimension 266 (e.g., height) along the vertical direction (e.g., the z-direction) that is smaller than the first air gap 210's dimension 268 (e.g., height) along the same direction. In some embodiments, the ratio of the width of the first air gap 210 to the width of the second air gap 220 is between 2 and 6. In some embodiments, the ratio of the height of the first air gap 210 to the height of the second air gap 220 is between 8 and 18.

[0076] In some implementations, reference Figure 2D and Figure 2E Along a second direction (e.g., the z-direction), the second end 234 of the first air gap 210 is on the second side 231b of the second end 238 of the second air gap 220, and the gate line 134 is on the second side 231b of the second end 238 of the second air gap 220. The second side 231b of the second end 238 of the second air gap 220 is opposite to the first side 231a of the second end 238 of the second air gap 220 along the second direction (e.g., the z-direction). The first end 228 of the second air gap 220 is on the first side 231a of the second end 238 of the second air gap 220. In other words, along the positive z-direction, the second end 238 of the second air gap 220 is farther away from the gate line 134 than the second end 234 of the first air gap 210. In some embodiments, reference is made to... Figure 2B and Figure 2C The distance 256 between the second end 238 of the second air gap 220 and one end 232 of the gate line 134 is greater than the distance 258 between the second end 234 of the first air gap 210 and one end 232 of the gate line 134.

[0077] In some embodiments, the second air gap 220 is formed by an ALD, as shown in the reference. Figures 4A-4J Further details will be discussed. Without being limited to any particular theory, CVD or PVD using black diamond (BDII) may produce particles that can be trapped in the air gap (e.g., below). Figure 4GThe gas released from the third air gap 440 in the gate line 134 can cause under-etching problems when the TISO contact structure 245 is formed in a later stage of the process. This gas release, along with impurities from tungsten (W) (e.g., W in gate line 134), can lead to under-etching issues. By using ALD instead of CVD or PVD, the gas release from BDII can be eliminated or mitigated. Furthermore, the increased distance along the z-direction between the second air gap 220 and gate line 134 also reduces impurities from W in gate line 134. Therefore, under-etching problems can be reduced, which in turn significantly improves manufacturing yield.

[0078] In some implementations, as referenced above Figure 1 and Figure 2A As mentioned, the first array structure 202 includes at least one first semiconductor body 206 extending along the z-direction. For example... Figure 2A As shown, a first end (e.g., the upper end) of the semiconductor body is coupled to a corresponding bit line 123 in bit line 123, and a second end (e.g., the lower end) of the first semiconductor body 206 is coupled to a capacitor 128. The first end of the first semiconductor body 206 is opposite to the second end of the first semiconductor body 206 along the z-direction.

[0079] In some embodiments, the first array structure 202 is located in the array region 242, and the second array structure 204 is located in the edge region 244 adjacent to the array region 242. The array region 242 may be defined as a region having active memory cells 124 for storing user data, a region having bit lines 123, or a region having capacitors 128. The edge region 244 may be defined as a region without active memory cells 124 (e.g., only having dummy memory cells 124 that do not store user data), a region without bit lines 123, a region without capacitors 128, or a region having TISO contact structures 245.

[0080] In some embodiments, the gate line 134 includes a first portion 134a in the array region 242, a third portion 134c in the edge region 244, and a second portion 134b along a first direction (e.g., the x-direction) between the first portion 134a and the third portion 134c. The height 282 of the second portion 134b of the gate line 134 along a second direction (e.g., the z-direction) is greater than the height 284 of the first portion 134a of the gate line 134 along the second direction. In some embodiments, the height 284 of the first portion 134a of the gate line 134 along the second direction is the same as the height 286 of the third portion 134c of the gate line 134 along the second direction. Without being limited to any particular theory, the higher second portion 134b of the gate line 134 may be advantageous in the following... Figure 4FThe gate line 134 in the protected array region 242 is shown during subsequent wet etching. In some embodiments, the gate line 134 includes a fourth portion 134d adjacent to the third portion 134c, and the third portion 134c is between the fourth portion 134d and the second portion 134b. It should be understood that, although Figure 2A The fourth portion 134d of the gate line 134 shown has a ramp shape, but in an actual device it can be any shape, whether irregular or regular.

[0081] Figure 3 It shows Figure 2A A plan view of the semiconductor device 100. (See attached image.) Figure 3 As shown, the semiconductor device 100 includes an array region 242 and an edge region 244. The array region 242 and the edge region 244 are adjacent to each other along the x-direction. The array region 242 includes a first array structure 202. The first array structure 202 may include multiple rows of memory cells 124. Each row of memory cells 124 extends along a first direction (e.g., the x-direction) and may include one or more memory cells 124.

[0082] In some embodiments, the semiconductor device 100 includes a plurality of partition regions 170. The partition regions 170 are located between adjacent rows of memory cells 124. In this disclosure, the partition regions 170 may also be referred to as TISO 170 or shielded conductive structure 170. As described above, TISO 170 may include a shielded conductive structure (e.g., including a metal such as W). TISO 170 may be coupled to a low voltage (e.g., a fixed negative voltage), which can reduce charge accumulation in the memory cells and thus mitigate the floating body effect in the memory cells 124. Furthermore, by applying a fixed low voltage to the TISO 170 between the memory cells 124, the threshold voltage of the memory cells 124 can be conveniently adjusted, which can reduce overall manufacturing complexity and cost and improve the reliability of the memory cells 124.

[0083] In some embodiments, the edge region 244 of the semiconductor device 100 may include a second array structure 204 and at least one TISO contact structure 245. Each TISO contact structure 245 may be coupled to a corresponding TISO 170, such as... Figure 3 As shown. In some embodiments, reference is made to... Figure 2AThe TISO contact structure 245 extends vertically into the second array structure 204. The TISO contact structure 245 may extend along the z-direction into one or more connecting lines 223 and one or more second isolation structures 226 of the second array structure 204 to connect to a corresponding TISO 170. Therefore, the TISO contact structure 245 can be coupled to TISO 170 (e.g., coupling TISO 170 to a fixed negative voltage). In some embodiments, the TISO contact structure 245 is made of a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, or any combination thereof.

[0084] Semiconductor device 100 may include multiple bit lines 123 extending along the y-direction. For example... Figure 3 As shown, bit lines 123 can be arranged adjacent to each other in an alternating pattern along the x-direction. For example, bit lines 123 include a first bit line 123a, a second bit line 123b, a third bit line 123c, or a fourth bit line 123d. The first bit line 123a can extend beyond the adjacent second bit line 123b along the y-direction. Similarly, the third bit line 123c can extend beyond the fourth bit line 123d. This configuration can be repeated every two bit lines 123 to form an alternating or staggered pattern. In some cases, alternating patterns can provide a larger process window for placing bit line contact structures on the corresponding bit lines and reduce the risk of short circuits between adjacent bit lines, thereby improving yield.

[0085] In some embodiments, the semiconductor device 100 includes a plurality of bit line contact structures 302. The bit line contact structures 302 are coupled to corresponding bit lines 123 in the bit lines 123. The bit line contact structures 302 may be located at one end of the bit lines 123. Therefore, the bit line contact structures 302 may also have a first alternating pattern, similar to the pattern of the bit lines 123 described above. The bit line contact structures 302 can electrically connect the bit lines 123 to peripheral circuitry (e.g., a sense amplifier), enabling the peripheral circuitry to control and manage the operation of the memory cells 124. In some embodiments, the bit line contact structures 302 are made of a conductive material, including but not limited to W, Co, Cu, Al, TiN, TaN, polysilicon, or any combination thereof.

[0086] like Figure 3 As shown, the semiconductor device 100 may also include multiple word lines 134. The word lines 134 extend along a first direction (e.g., the X direction). In some embodiments, the word lines 134 are coupled to transistors of at least one row of memory cells 124 for controlling the operation (e.g., reading or writing) of active memory cells 124 in the array region 242. As described above, in some embodiments, the edge region 244 includes dummy memory cells that do not store user data; therefore, the word lines 134 in the edge region 244 are not used as gates of transistors.

[0087] In some embodiments, the semiconductor device 100 includes a gate line contact structure 304 coupled to a corresponding gate line 134 of a plurality of gate lines 134 and arranged in a second alternating pattern along a third direction (e.g., the y-direction). The gate line contact structure 304 can electrically connect the word lines 134 to peripheral circuitry (e.g., word line drivers), enabling the peripheral circuitry to control and manage the operation of the memory cell 124. Each gate line contact structure 304 can be coupled to a corresponding word line 134.

[0088] In some embodiments, the gate line contact structure 304 has a second alternating or staggered pattern along the y-direction. For example, the gate line contact structure 304 may include a first gate line contact structure 304a, a second gate line contact structure 304b, a third gate line contact structure 304c, and a fourth gate line contact structure 304d. The first gate line contact structure 304a and the third gate line contact structure 304c may be closer to one end 306 of the corresponding word line 134, while the second gate line contact structure 304b and the fourth gate line contact structure 304d may be closer to the second array structure 204. In some cases, the alternating configuration can provide a larger process window for placing the gate line contact structure 304 on the corresponding word line 134 and reduce the risk of short circuits between adjacent word lines 134, thereby improving yield.

[0089] Figures 4A-4J Cross-sectional views of the semiconductor device 100 at various stages of the manufacturing process are shown. It should be understood that... Figures 4A-4J It can be a composite view with superimposed cross-sectional planes. For example, Figures 4A-4J It could be similar to passing through Figure 3 A composite view of the cross-sectional planes of the A-A' and B-B' axes, making Figures 4A-4J Both gate line 134 and semiconductor body 206 can be shown in a single view. Therefore, Figures 4A-4J For illustrative purposes only, and may not depict individual cross-sectional views within the actual device.

[0090] like Figure 4A As shown, a first conductive layer 402 can be deposited on the first initial array structure 410 and the second initial array structure 420. In subsequent process stages (e.g., as...) Figure 4IAs shown), the first initial array structure 410 can become the first array structure 202, and the second initial array structure 420 can become the second array structure 204. The first initial array structure 410 and the second initial array structure 420 can respectively include a first semiconductor line 412 and a second semiconductor line 414 extending along the y-direction. The first semiconductor line 412 of the first initial array structure 410 can be added in subsequent process stages (e.g., as shown). Figure 4F As shown, it becomes bit line 123, while the second semiconductor line 414 of the second initial array structure 420 can be Figure 2A Connecting line 223 in the middle.

[0091] The first conductive layer 402 may fill the gaps 401 located between adjacent first semiconductor lines 412 and adjacent second semiconductor lines 414. In some embodiments, such as Figure 4A As shown, a thin oxide layer 403 is formed on the upper portion of the sidewalls of the first initial array structure 410 and the second initial array structure 420 before the first conductive layer 402 is deposited. In some embodiments, the first conductive layer 402 is a titanium nitride (TiN) film. The first conductive layer 402 can be deposited by one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), metal-organic chemical vapor deposition (MOCVD), sputtering, electroplating, electroless plating, electron beam evaporation, or any combination thereof.

[0092] like Figure 4B As shown, a hard mask layer 404 can be deposited on the first conductive layer 402, followed by a patterning process (e.g., photolithography and etching) to define the pattern of the hard mask layer 404. In some embodiments, the hard mask layer 404 covers the edge region 244 (e.g., covers the second initial array structure 420), but exposes at least a portion of the array region 242 (e.g., exposes at least a portion of the first initial array structure 410).

[0093] like Figure 4C As shown, exposed portions of the first conductive layer 402 (e.g., portions not covered by the hard mask layer 404) can be removed by etching. In some embodiments, after etching, the first conductive layer 402 is partially retained within the spacing 401 between adjacent first semiconductor lines 412. The etching process may involve one or more dry and / or wet etching techniques, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputtering etching, KOH (potassium hydroxide) etching, TMAH (tetramethylammonium hydroxide) etching, buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0094] like Figure 4D As shown, the hard mask layer 404 can be removed using the etching technique described above.

[0095] like Figure 4E As shown, a second conductive layer 422 comprising a conductive material can be deposited on the first semiconductor line 412 of the first initial array structure 410. The conductive material of the second conductive layer 422 can then be annealed, causing it to react with the material of the first semiconductor line 412 (e.g., silicon) to form a composite conductive material. The conductive material of the second conductive layer 422 may include Ni, W, Co, Cu, or Al. The composite conductive material may be a silicide material, including but not limited to NiSi, WSi, CoSi, CuSi, AlSi, or any other suitable metal silicide. The composite conductive material can form bit lines 123.

[0096] like Figure 4F As shown, both the first conductive layer 402 and the second conductive layer 422 can be removed. In some embodiments, the removal process involves high-temperature wet etching using a sulfuric acid peroxide mixture (SPM). In some embodiments, an additional annealing process is performed after removing the first conductive layer 402 and the second conductive layer 422.

[0097] like Figure 4G As shown, a first dielectric layer 426 can be deposited in both array region 242 and edge region 244. The first dielectric layer 426 can be, for example, Figures 2A-2E The first spacer layer 222 is formed. In some embodiments, during deposition, one or more first air gaps 210 are formed in the array region 242, and one or more third air gaps 440 are formed in the edge region 244. In some embodiments, the dimensions of the third air gaps 440 are the same as or substantially similar to the dimensions of the first air gaps 210. For example, as... Figure 4G As shown, the first air gap 210 and the third air gap 440 may have substantially similar widths along the x-direction and / or substantially similar heights along the z-direction. Without being limited to any particular theory, air gaps can be formed during the thin film deposition process due to the relatively small spacing between adjacent bit lines 123 or connector lines 223. In some embodiments, the first dielectric layer 426 may include (but is not limited to) black diamond (BD), silicon oxycarbide (SiOC), organosilicon glass (OSG), carbon-doped oxide (CDO), silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The first dielectric layer 426 may be deposited using one or more thin film deposition techniques, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or any combination thereof.

[0098] like Figure 4HAs shown, the first dielectric layer 426 can be patterned; for example, a portion of the first dielectric layer 426 can be removed in the edge region 244. During this process, the third air gap 440 in the spacing 401 between adjacent interconnects 223 can be removed. The third air gap 440 in the edge region 244 can be removed by a variety of processes, including but not limited to photolithography, dry / wet etching, and any other suitable processes.

[0099] like Figure 4I As shown, a second dielectric layer 430 can be deposited. The second dielectric layer 430 can be, for example, Figures 2A-2E The second spacer layer 224 is included. The second dielectric layer 430 may partially fill the spacers 401, such that the second air gap 220 can be formed to be surrounded by the second dielectric layer 430. In some embodiments, the second dielectric layer 430 is formed by atomic layer deposition (ALD). Without being limited to any particular theory, ALD offers better precision in controlling the thickness of the deposited film compared to other deposition methods (e.g., CVD, PVD), and can deposit more uniform films on substrates with complex geometries (e.g., structures with narrow spacing or high aspect ratios). Here, by employing ALD to deposit the second dielectric layer 430, better step coverage can be achieved in the second initial array structure 420 with a high aspect ratio. As a result, more dielectric material can be deposited in the spacers 401, thereby reducing the size of the air gaps (e.g., comparing the third air gap 440 with the second air gap 220). In some embodiments, the second dielectric layer 430 comprises silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0100] As stated above, without being limited to any particular theory, CVD or PVD using black diamond (BDII) may produce particles that can be trapped in the air gap (e.g., Figure 4G The venting from the third air gap 440 in the gate line 134 can cause under-etching problems when the TISO contact structure 245 is formed in a later stage of the process. This venting, along with impurities from W (e.g., W in gate line 134), can lead to under-etching issues. By removing the third air gap 440 and subsequently forming the second air gap 220 using ALD instead of CVD or PVD, the venting from the BDII can be eliminated or mitigated. Furthermore, the increased distance along the z-direction between the second air gap 220 and the gate line 134 also reduces impurities from W in the gate line 134. Therefore, under-etching problems can be reduced, which in turn improves manufacturing yield.

[0101] like Figure 4JAs shown, a third dielectric layer 432 can be deposited on the second dielectric layer 430. The third dielectric layer 432 may comprise silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. In some embodiments, the third dielectric layer 432 comprises tetraethyl orthosilicate (TEOS). It should be understood that in a practical device, the interface between the second dielectric layer 430 and the third dielectric layer 432 may be invisible by some imaging technique (e.g., transmission electron microscopy), but may be visible by other imaging techniques (e.g., staining).

[0102] Figure 5 A flowchart illustrating an exemplary process for forming a semiconductor device is shown. The semiconductor device may be, for example, Figures 1-4 Semiconductor device 100 in the middle.

[0103] In step 502, a first array structure including bit lines is formed. Two adjacent bit lines are separated by a first isolation structure along a first direction. The first isolation structure includes a first air gap. The first array structure may be, for example, Figures 2A-2C , Figure 3 and Figures 4G-4J The first array structure 202 in the array. The bit lines can be, for example, Figures 1-3 and Figures 4E-4J Bit line 123 in the middle. The first isolation structure can be, for example, bit line 123. Figures 2A-2E and Figures 4G-4J The first isolation structure 212 in the middle. The first direction can be, for example, Figures 2A-4J The x-direction or word line direction in the text.

[0104] At step 504, a second array structure is formed adjacent to the first array structure along the first direction. The second array structure includes connecting lines. Two adjacent connecting lines are separated along the first direction by a second isolation structure, which includes a second air gap. The second array structure can be, for example, […]. Figures 2A-2C , Figure 3 , Figure 4I and Figure 4J The second array structure 204 in the diagram. The connecting lines can be, for example,... Figures 2A-3 Connector 223 or Figures 4A-4J The second semiconductor line 414 in the structure. The second isolation structure can be, for example, a... Figures 2A-2E and Figures 4I-4J The second isolation structure 226 in the middle. The second air gap can be, for example, Figures 2A-2E , Figure 4I and Figure 4J The second air gap is 220.

[0105] At step 506, a gate line is formed, extending along a first direction and adjacent to both the first array structure and the second array structure. Along a second direction perpendicular to the first direction, a first end of the first air gap is on a first side of the first end of the second air gap, and the gate line is on a second side of the first end of the second air gap. The second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction. The second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction. The gate line can be, for example, Figures 1-4 Gate line 134 in the middle. The first end of the first air gap can be, for example, a gate line 134 in the middle. Figures 2A-2E The first end 214 of the first air gap 210. The first side of the first end of the second air gap can be, for example, Figures 2A-2E The first side 229a of the first end 228 of the second air gap 220. The second side of the first end of the second air gap can be, for example, a Figures 2A-2E The second side 229b of the first end 228 of the second air gap 220. The second end of the second air gap can be, for example, a Figures 2A-2E The second end 238 of the second air gap 220 in the first air gap. The second end of the first air gap can be, for example, the second end of the second air gap 220. Figures 2A-2E The second end 234 of the first air gap 210 in the middle.

[0106] In some embodiments, the process includes: forming a third air gap surrounded by a first dielectric layer in a second isolation structure; removing the third air gap and the first dielectric layer from the second isolation structure; and forming a second air gap surrounded by a second dielectric layer in the second isolation structure. The third air gap may, for example, be... Figure 4G The third air gap 440. The first dielectric layer can be, for example, Figures 2A-2E The first spacer layer 222 or Figure 4G The first dielectric layer 426 in the middle. The second dielectric layer may be, for example, a... Figures 2A-2E The second spacer layer 224 or Figure 4I and Figure 4J The second dielectric layer 430 in the middle.

[0107] In some implementations, the dimensions (e.g., width, height, area) of the third air gap are substantially equal to the dimensions (e.g., width, height, area) of the first air gap.

[0108] In some embodiments, forming a second air gap surrounded by a second dielectric layer in a second isolation structure includes depositing a second dielectric layer in the second isolation structure by atomic layer deposition (ALD).

[0109] In some embodiments, the process includes: depositing a conductive layer on a first initial array structure and a second initial array structure; depositing a hard mask that covers a first portion of the conductive layer on the second initial array structure; at least partially removing a second portion of the conductive layer on the first initial array structure; and removing the hard mask, as referenced above. Figures 4A-4D As described.

[0110] In some embodiments, the process includes: depositing a conductive material on semiconductor lines of a first initial array structure; and annealing the conductive material to react with the material of the semiconductor lines to form a composite conductive material, as referenced above. Figure 4E As described.

[0111] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. System 600 may be a mobile phone, desktop computer, laptop computer, tablet computer, in-vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 6 As shown, system 600 may include a host device 608 and a memory system 602 having one or more 3D memory devices 604 and a memory controller 606. The host device 608 may include a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host device 608 may be configured to send data to or receive data from one or more 3D memory devices 604.

[0112] 3D memory device 604 can be any 3D memory device disclosed herein, such as Figure 1 The 3D semiconductor device 100, or a portion thereof (e.g., Figures 2A-3 ),or Figure 1 The structure at the intermediate manufacturing process of the 3D semiconductor device 100 (e.g., Figures 4A-4J ).

[0113] 3D memory device 604 can be any 3D memory device disclosed herein, such as Figure 1The 3D memory device 604 is depicted in the present disclosure. In some embodiments, the 3D memory device 604 includes NAND flash memory. A memory controller 606 (also referred to as controller circuitry) is coupled to the 3D memory device 604 and the host device 608. According to embodiments of the present disclosure, the 3D memory device 604 may include a plurality of conductive interconnects that contact conductive pads in a conductive substrate with a cover layer, and the memory controller 606 may be coupled to the 3D memory device 604 through at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the 3D memory device 604. For example, the memory controller 606 may be configured to operate a plurality of channel structures via word lines. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host device 608.

[0114] In some embodiments, the memory controller 606 is designed / configured to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal computers, digital cameras, and mobile phones. In some embodiments, the memory controller 606 is designed / configured to operate in high duty cycle environments in SSDs or in embedded multimedia cards (eMMCs) used as data storage devices in mobile devices such as smartphones, tablets, and laptops, as well as in enterprise storage arrays. The memory controller 606 can be configured to control the operation of the 3D memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 can also be configured to manage various functions regarding data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is also configured to process error correction codes (ECC) regarding data read from or written to the 3D memory device 604. The memory controller 606 may also perform any other appropriate function, such as formatting the 3D memory device 604.

[0115] The memory controller 606 can communicate with external devices (e.g., host device 608) according to a specific communication protocol. For example, the memory controller 606 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, High Speed ​​PCI (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, FireWire protocol, etc.

[0116] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 602 can be implemented and packaged into different types of end electronic products. Figure 6 In one example shown, the memory controller 606 and a single 3D memory device 604 can be integrated into the memory card 602. The memory card 602 may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0117] The embodiments, actions, and operations of the subject matter described in this disclosure can be implemented in digital electronic circuits, tangibly embodied computer software or firmware, computer hardware (including the structures disclosed in this disclosure and their structural equivalents), or combinations thereof. Embodiments of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier for execution by or control of the operation of a data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively or additionally, the carrier can be an artificially generated propagation signal, such as a machine-generated electrical signal, optical signal, or electromagnetic signal, generated to encode information for transmission to a suitable receiving device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof, or a portion thereof. The computer storage medium is not a propagation signal.

[0118] It should be noted that the embodiments described in this disclosure, such as "an embodiment," "an embodiment," "an exemplary embodiment," "some embodiments," "some implementations," "an implementation," "implementation," "exemplary implementation," etc., may include specific features, structures, or characteristics, but not every embodiment must include that specific feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Moreover, when a specific feature, structure, or characteristic is described in connection with an embodiment, whether explicitly described or not, implementing such a feature, structure, or characteristic in conjunction with other implementations is within the knowledge of those skilled in the art.

[0119] Generally, terms can be understood at least partly from their usage in context. For example, depending at least partly on the context, the term "one or more" as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, depending at least partly on the context, terms such as "a" or "described" can also be understood to convey either a singular or a plural usage. Additionally, again depending at least partly on the context, the term "based on" can be understood to not necessarily convey an exclusive set of factors, but rather to allow for the presence of additional factors that are not necessarily explicitly described.

[0120] It should be readily understood that the meanings of “on,” “above,” and “on top of” in this disclosure should be interpreted in the broadest possible sense, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with an intermediate feature or layer between them. Furthermore, “above” or “on top of” not only means “above something” or “on top of something,” but can also include the meaning of “above something” or “on top of something” without an intermediate feature or layer between them (i.e., directly on something).

[0121] Furthermore, for ease of description, spatial relative terms such as “below,” “under,” “lower,” “above,” and “upper” may be used herein to describe the relationship between one element or feature and another (or more) elements or features as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to cover different orientations of the apparatus during use or process steps. The apparatus may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0122] As used herein, the term "substrate" refers to the material on which subsequent material layers are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of the substrate is typically where semiconductor devices are formed, and therefore, unless otherwise stated, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite to the top surface, and therefore, the bottom side of the substrate is opposite to the top side of the substrate. The substrate itself may be patterned. The material added on top of the substrate may be patterned or may remain unpatterned. Furthermore, the substrate may include a variety of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate may be made of a non-conductive material, such as glass, plastic, or sapphire wafers.

[0123] As used herein, the term "layer" refers to a portion of material comprising a region of thickness. A layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far from the substrate. A layer may extend over the entire lower or upper overlay structure, or may have a range smaller than that of the lower or upper overlay structure. Furthermore, a layer may be a region of a uniform or non-uniform continuous structure having a thickness smaller than that of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any set of horizontal planes at the top and bottom surfaces. A layer may extend horizontally, vertically, and / or along a tapered surface. A substrate may be a layer, which may include one or more layers, and / or may have one or more layers on, above, and / or below it. A layer may include multiple layers. For example, an interconnect layer may include one or more conductive and contact layers (where contacts, interconnect lines, and / or vertical interconnect channels (VIAs) are formed) and one or more dielectric layers.

[0124] As used herein, the term "nominal / nominally" refers to the expected or target value of a characteristic or parameter set for a component or process step during the design phase of a product or process, and the range of values ​​higher and / or lower than the expected value. As used herein, the range of values ​​may be due to minor variations in manufacturing processes or tolerances. As used herein, the term "about" indicates the value of a given quantity that may vary based on a specific technology node associated with the subject semiconductor device. Based on a specific technology node, the term "about" may indicate the value of a given quantity that varies within, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of the value).

[0125] As used in this disclosure, the terms “substantially” or “basically” mean a majority or majority, such as at least about 50%, 60%, 70%, 80%, 90%, 95%, 96%, 97%, 98%, 99%, 99.5%, 99.9%, 99.99%, or at least about 99.999%, or greater.

[0126] In this disclosure, the terms "horizontal / horizontally / laterally" mean nominally parallel to the lateral surface of the substrate, and the term "vertical / vertically" means nominally perpendicular to the lateral surface of the substrate.

[0127] As used herein, the term “3D memory” refers to a three-dimensional (3D) semiconductor device having strings of vertically oriented memory cell transistors (referred to herein as “memory strings”, such as NAND strings) on a laterally oriented substrate, such that the memory strings extend in a vertical direction relative to the substrate.

[0128] This disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features can be in direct contact, and may also include embodiments where an additional feature can be formed between the first and second features such that the first and second features are not in direct contact. Additionally, reference numerals and / or letters may be repeated in various examples. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or constructions discussed.

[0129] The descriptions of specific implementation methods described above can be easily modified and / or adjusted for various applications. Therefore, based on the teachings and guidance provided herein, such adjustments and modifications are intended to fall within the meaning and scope of equivalents of the disclosed implementation methods.

[0130] While this disclosure contains numerous specific implementation details, these should not be construed as limiting the scope of the claims as defined by the claims themselves, but rather as descriptions of features that may be implemented for specific embodiments of a particular invention. In the context of individual embodiments, certain features described in this disclosure may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed in this way, one or more features from the claimed combination may be removed from the combination in some cases, and the claims may be for sub-combinations or variations thereof.

[0131] Similarly, although operations are depicted in the accompanying drawings in a specific order and referenced in the claims, this should not be construed as requiring the operations to be performed in the specific order or sequence shown, or requiring all shown operations to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

[0132] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions cited in the claims can be performed in a different order and still achieve the desired result. As an example, the process depicted in the drawings does not necessarily require the specific order or sequence shown to achieve the desired result. In some cases, multitasking and parallel processing may be advantageous.

[0133] The breadth and scope of this disclosure should not be limited to any of the embodiments described above, but should be defined solely by the following claims and their equivalents.

Claims

1. A semiconductor device, comprising: A first array structure, the first array structure including bit lines, wherein two adjacent bit lines are separated by a first isolation structure along a first direction, the first isolation structure including a first air gap; A second array structure, adjacent to the first array structure along the first direction, includes connecting lines, wherein two adjacent connecting lines are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and A gate line extending along the first direction and adjacent to both the first array structure and the second array structure. Wherein, along a second direction perpendicular to the first direction, the first end of the first air gap is on a first side of the first end of the second air gap, the gate line is on a second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction.

2. The semiconductor device according to claim 1, wherein, Along the second direction, the first end of the first air gap is above one end of one of the two adjacent bit lines, and the first end of the second air gap is below the one end of the bit line in the two adjacent bit lines.

3. The semiconductor device according to claim 1 or 2, wherein, The area of ​​the second air gap is smaller than the area of ​​the first air gap.

4. The semiconductor device according to any one of claims 1 to 3, wherein, Along the second direction, the second end of the first air gap is on one side of the second end of the second air gap, and the gate line is on the same side of the second end of the second air gap.

5. The semiconductor device according to any one of claims 1 to 4, wherein, The dimension of the second air gap along the first direction is smaller than the dimension of the first air gap along the first direction.

6. The semiconductor device according to any one of claims 1 to 5, wherein, The dimension of the second air gap along the second direction is smaller than the dimension of the first air gap along the second direction.

7. The semiconductor device according to any one of claims 1 to 6, wherein, The first array structure includes a semiconductor body extending along the second direction, a first end of the semiconductor body being coupled to a corresponding bit line in the bit line, and a second end of the semiconductor body being coupled to a capacitor, the first end of the semiconductor body being opposite to the second end of the semiconductor body along the second direction.

8. The semiconductor device according to any one of claims 1 to 7, wherein, The first array structure is located in the array region, and the second array structure is located in the edge region adjacent to the array region. The gate line includes a first portion in the array region, a third portion in the edge region, and a second portion along the first direction between the first portion and the third portion. Wherein, the height of the second portion of the gate line along the second direction is greater than the height of the first portion of the gate line along the second direction.

9. The semiconductor device according to claim 8, wherein, The height of the first portion of the gate line along the second direction is the same as the height of the third portion of the gate line along the second direction.

10. The semiconductor device according to any one of claims 1 to 9, comprising: Bit line contact structure, the bit line contact structure is arranged in a first alternating pattern along the first direction, and the bit line contact structure in the bit line contact structure is coupled to the corresponding bit line in the bit line; Includes multiple gate lines, including the gate line; as well as A gate line contact structure coupled to a corresponding gate line among the plurality of gate lines and arranged in a second alternating pattern along a third direction, the third direction being perpendicular to the first direction and the second direction.

11. A semiconductor device, comprising: A first array structure, the first array structure including bit lines, wherein two adjacent bit lines are separated by a first isolation structure along a first direction, the first isolation structure including a first air gap; A second array structure, adjacent to the first array structure along the first direction, includes connecting lines, wherein two adjacent connecting lines are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and A gate line extending along the first direction and adjacent to both the first array structure and the second array structure. The area of ​​the second air gap is smaller than the area of ​​the first air gap.

12. The semiconductor device according to claim 11, wherein, Along a second direction perpendicular to the first direction, the first end of the first air gap is above one end of one of the two adjacent bit lines, and the first end of the second air gap is below the one end of the bit line in the two adjacent bit lines.

13. The semiconductor device according to claim 11 or 12, wherein, Along a second direction perpendicular to the first direction, the first end of the first air gap is on a first side of the first end of the second air gap, the gate line is on a second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction.

14. The semiconductor device according to claim 13, wherein, Along the second direction, the second end of the first air gap is on one side of the second end of the second air gap, and the gate line is on the same side of the second end of the second air gap.

15. The semiconductor device according to any one of claims 11 to 14, wherein, The dimension of the second air gap along the first direction is smaller than the dimension of the first air gap along the first direction.

16. The semiconductor device according to any one of claims 11 to 15, wherein, The second air gap is smaller in size along the second direction than the first air gap in the second direction, and the second direction is perpendicular to the first direction.

17. A method comprising: A first array structure is formed, the first array structure includes bit lines, wherein two adjacent bit lines are separated by a first isolation structure along a first direction, the first isolation structure including a first air gap; A second array structure is formed, the second array structure being adjacent to the first array structure along the first direction. The second array structure includes connecting lines, wherein two adjacent connecting lines are separated along the first direction by a second isolation structure, the second isolation structure including a second air gap; and A gate line is formed, the gate line extending along the first direction and adjacent to both the first array structure and the second array structure. Wherein, along a second direction perpendicular to the first direction, the first end of the first air gap is on a first side of the first end of the second air gap, the gate line is on a second side of the first end of the second air gap, the second side of the first end of the second air gap is opposite to the first side of the first end of the second air gap along the second direction, the second end of the second air gap is between the first end of the second air gap and the gate line along the second direction, and the second end of the first air gap is between the first end of the first air gap and the gate line along the second direction.

18. The method of claim 17, comprising: A third air gap surrounded by a first dielectric layer is formed in the second isolation structure; Remove the third air gap and the first dielectric layer from the second isolation structure; as well as A second air gap, surrounded by a second dielectric layer, is formed in the second isolation structure.

19. The method according to claim 18, wherein, Forming the second air gap surrounded by the second dielectric layer in the second isolation structure includes: The second dielectric layer is deposited in the second isolation structure by atomic layer deposition (ALD).

20. The method according to any one of claims 17 to 19, comprising: A conductive layer is deposited on the first initial array structure and the second initial array structure; A hard mask is deposited, the hard mask covering a first portion of the conductive layer on the second initial array structure; At least partially remove the second portion of the conductive layer on the first initial array structure; as well as Remove the hard mask.

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