Bonding layer formed from high thermal conductivity material

Abstract

A method for forming a structure with a backside power delivery network incorporates a high thermal conductivity material as a bonding layer. In some embodiments, the method can include forming a first layer stack including a frontside metallization (FSM) signal layer formed on a silicon die layer containing nano-silicon through vias (n-TSVs) formed on a backside metallization (BSM) power distribution layer, where the n-TSVs provide backside power connections to the FSM signal layer; forming a second layer stack including a silicon carrier layer; and forming a third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer interposed between the first layer stack and the second layer stack, where the bonding layer is formed of a cubic boron nitride-based material.

Description

Technical Field

[0001] The implementation of the principles of this invention generally involves the processing of semiconductor substrates. Background Technology

[0002] A power delivery network (PDN) supplies power to active components on the die. A PDN is an interconnect network separate from the signal network. In conventional manufacturing, the network is fabricated using a back-end-of-line (BEOL) process, where the network is formed on the front side of the die. Front-end formation causes the PDN to compete for space with the signal network, resulting in very congested network routing. However, the inventors observed that if the PDN is moved to the back side of the die, congestion is reduced, but heat dissipation becomes problematic.

[0003] Thus, the inventors have provided a method for improving the thermal performance of back-side power delivery networks. Summary of the Invention

[0004] This paper provides a method for improving the thermal performance of the bonding layer used in conjunction with a backside power delivery network.

[0005] In some embodiments, a method for forming a structure having a backside power delivery network (BS-PDN) may include: forming a first layer stack, the first layer stack including at least a front side metallization (FSM) signal layer formed on a silicon grain layer containing nano-through silicon vias (n-TSVs), the nano-through silicon vias being formed on a back side metallization (BSM) power distribution layer, wherein the n-TSVs provide backside power connections to the FSM signal layer; forming a second layer stack, the second layer stack including at least a silicon carrier layer; and forming a third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer inserted between the first layer stack and the second layer stack, wherein the bonding layer is formed of a cubic boron nitride-based material.

[0006] In some embodiments, the method further includes: a cubic boron nitride-based material, which is a cubic boron nitride material enriched with B-10 or B-11 isotopes using a process to obtain approximately 99% of the B-10 or B-11 isotope percentage; a silicon grain layer having a thickness of approximately 200 nm to approximately 300 nm; an n-TSV having a diameter of approximately 100 nm; a bonding layer having a thickness of approximately 250 nm to approximately 1.2 μm; a bonding layer having a thickness of approximately 1.0 μm; a second layer stack including a thermal interface material (TIM) layer formed on a silicon carrier layer and a heat sink layer formed on the TIM layer; a heat sink layer formed of copper; a first layer stack being a device wafer; and / or a first layer stack further including a BSM layer formed on a chip interconnect control collapse (C4) layer and a C4 layer formed on a substrate.

[0007] In some embodiments, a method for forming a structure having a back-side power delivery network may include: forming a first layer stack, the first layer stack including at least a front-side metallization (FSM) signal layer formed on a silicon grain layer containing nano-through-silicon vias (n-TSVs), the nano-through-silicon vias being formed on a back-side metallization (BSM) power distribution layer, wherein the n-TSVs provide back-side power connections to the FSM signal layer and have a diameter of approximately 100 nm; forming a second layer stack, the second layer stack including at least a silicon carrier layer; and forming a third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer inserted between the first layer stack and the second layer stack, wherein the bonding layer is formed of a cubic boron nitride-based material and has a thickness of approximately 250 nm to approximately 1.2 micrometers.

[0008] In some embodiments, the method further includes: a cubic boron nitride-based material, which is a cubic boron nitride material enriched with B-10 or B-11 isotopes using a process to obtain approximately 99% B-10 or B-11 isotope percentage; a silicon grain layer having a thickness of approximately 200 nm to approximately 300 nm; a bonding layer having a thickness of approximately 1.0 micrometer; a second layer stack including a thermal interface material (TIM) layer formed on the silicon carrier layer and a heat sink layer formed on the TIM layer; a heat sink layer formed of copper; a first layer stack, which is a device wafer; and / or the first layer stack further including a BSM layer formed on a chip interconnect control collapse (C4) layer and a C4 layer formed on a substrate.

[0009] In some embodiments, a non-transitory computer-readable medium storing instructions thereon, when executed, causes to perform a method for forming a structure having a back-side power delivery network, the method comprising: forming a first layer stack including at least a front-side metallization (FSM) signal layer formed on a silicon grain layer containing nano-through-silicon vias (n-TSVs), the nano-TSVs being formed on a back-side metallization (BSM) power distribution layer, wherein the n-TSVs provide back-side power connections to the FSM signal layer; forming a second layer stack including at least a silicon carrier layer; and forming a third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer inserted between the first layer stack and the second layer stack, wherein the bonding layer is formed of a cubic boron nitride-based material.

[0010] In some embodiments, the method of having instructions on a non-transitory computer-readable medium may further include: a cubic boron nitride-based material, which is a cubic boron nitride material enriched with B-10 or B-11 isotopes using a process to obtain a percentage of approximately 99% of B-10 or B-11 isotopes; a silicon grain layer having a thickness of approximately 200 nm to approximately 300 nm; an n-TSV having a diameter of approximately 100 nm; a bonding layer having a thickness of approximately 250 nm to approximately 1.2 μm; and / or a bonding layer having a thickness of approximately 1.0 μm.

[0011] Other and further implementation methods are disclosed below. Attached Figure Description

[0012] The embodiments of the principle briefly summarized above and discussed in more detail below can be understood by referring to the illustrative embodiments of the principle depicted in the accompanying drawings. However, the drawings only illustrate common embodiments of the principle of the invention and are therefore not intended to be limiting, as the principle of the invention allows for other equivalent and effective embodiments.

[0013] Figure 1 This is a method for forming a structure with a back-side power delivery network (BS-PDN) according to some embodiments of this principle.

[0014] Figure 2 Cross-sectional views of BS-PDN structures according to some embodiments of this principle are depicted.

[0015] Figure 3 A graph depicting a comparison of thermal resistance between a front-side power delivery network (FS-PDN) structure and a BS-PDN structure according to some embodiments of this principle is presented.

[0016] Figure 4A graph depicting a comparison of thermal resistances among BS-PDNs having a conventional oxide bonding layer, BS-PDNs having a c-BN bonding layer, and BS-PDNs having an isotope-enriched c-BN bonding layer, according to some embodiments of this principle, is presented.

[0017] To facilitate understanding, the same reference numerals have been used where possible to identify common elements in the figures. The figures are not drawn to scale and have been simplified for clarity. Elements and features of one embodiment may be advantageously incorporated into other embodiments without further description. Detailed Implementation

[0018] This method provides improved thermal performance for bonding layers in structures with back-side power delivery networks (BS-PDN) to increase heat transfer from semiconductor packages. These techniques offer an excellent pathway to BS-PDN thermal management by using bonding layers with enhanced thermal conductivity, which increase heat dissipation by up to 10% compared to conventional oxide bonding layers. Furthermore, the materials used in this method can have reduced hardness compared to other bonding materials. Reduced hardness allows for easier material handling, thereby reducing manufacturing time and cost. Heat dissipation strategies, such as engineered thermal interface materials (TIMs), heat sink design, and the use of advanced cooling techniques, significantly increase manufacturing costs. Using high thermal conductivity materials in layers that are part of the device structure, such as bonding layers, improves heat dissipation in BS-PDN packages without significantly increasing raw material costs or significantly impacting the manufacturing process.

[0019] Back-side power delivery networks require extreme silicon die thinning for nano-through-silicon via (n-TSV) integration and parasitic RC reduction. While extreme silicon die thinning helps address some n-TSV integration challenges, it negatively impacts the thermal performance of BS-PDN packages compared to conventional front-side PDN (FS-PDN) packages. In this approach, high thermal conductivity materials are used as bonding layers to further improve the thermal performance of BS-PDN packages. In some embodiments, cubic boron nitride (c-BN) and isotope-enriched c-BN are used as bonding layer materials. Cubic BN has a thermal conductivity of approximately 768 W / m*K, while isotope-enriched c-BN has a thermal conductivity of approximately 1600 W / m*K. Using c-BN and isotope-enriched c-BN materials instead of conventional oxide materials allows for thermal performance improvements in BS-PDN packages of up to approximately 9.5%. The improved thermal properties are directly related to the high thermal conductivity of c-BN and isotopically enriched c-BN, which are at least about 540 times and about 1140 times higher than those of conventional oxide materials, respectively. Both c-BN and isotopically enriched c-BN belong to the refractory compound family, and the isotopically enriched c-BN is a c-BN material enriched with the heavier isotopes of c-BN (B-10 or B-11).

[0020] Power delivery networks (PDNs) help deliver power and reference voltage to active components on the die in the most efficient way. A PDN is an interconnect network separate from the interconnect network used for the signal network on the die. Traditionally, both networks are fabricated through back-to-the-end (BEOL) processing on the front side of the die. The PDN thus competes for space with the signal network. This shared space leads to routing congestion. Moving power distribution to the back side of the die can help alleviate this congestion. BS-PDN packaging offers advantages over FS-PDN packaging because it allows direct power delivery to standard batteries, enhances system performance, increases chip area utilization, improves power integrity, and reduces the complexity of fine-pitch BEOL. BS-PDN combines 3D TSV technology and logic technology to decouple the power grid from the chip design budget and deliver power from the back side of the thinned component die.

[0021] A TSV that connects the back-side metallization (BSM) to the back-side power rail (BPR) is called an n-TSV because the via diameter is on the order of approximately 100 nm. Since the high aspect ratio of n-TSVs is unsuitable for etching and filling operations, the device wafer needs to be thinned to a few hundred nanometers. Extreme silicon die thinning helps address the integration challenges of n-TSVs, but negatively impacts the thermal performance of BS-PDN packages compared to conventional FS-PDN packages. The degradation of thermal performance in BS-PDN packages is primarily due to three factors: the lack of lateral heat dissipation due to the extreme thinning of the silicon die; the reduction in thermal conductivity of silicon from its bulk value at very small thicknesses due to increased phonon scattering; and the need for heat to pass through the low thermal conductivity bonding layer in the BS-PDN package before reaching the heatsink on the front side.

[0022] exist Figure 1 The present invention describes a method 100 for forming a structure having a back-side power delivery network. Reference will be made to the method 100 in the discussion of which. Figure 2 In box 102, as shown Figure 2 As depicted in views 200A and 200B, a first layer stack 224 is formed. In some cases, the first layer stack 224 may be referred to as a device wafer or a silicon device wafer. The first layer stack 224 includes a back-side metallization (BSM) layer 206, a front-side metallization (FSM) layer 210, and a thin silicon die layer 208 containing n-TSV 222 extending from the BSM layer 206 across the thin silicon die layer 208 to the FSM layer 210 to deliver power from the back side of the first layer stack 224 to the FSM layer 210. The BSM layer 206 distributes power to the BS-PDN. The FSM layer 210 distributes signals to the power distribution network 220 in the FSM layer 210 via the n-TSV 222 and receives power from the BS-PDN. In some embodiments, the thin silicon die layer 208 may have a thickness 230 of approximately 200 nm to approximately 300 nm. In some embodiments, the n-TSV may have a diameter of approximately 100 nm. The thickness 230 of the thin silicon grain layer 208 is crucial to ensuring that the aspect ratio of the n-TSV is manageable in order to prevent deposition and / or etching problems that could affect yield. In some embodiments, the first layer stack 224 may also include a chip interconnect control collapse (C4) layer 204 or other types of advanced electrical interconnect layers and substrate 202.

[0023] In box 104, as Figure 2Depicted in views 200A and 200B, a second layer stack 226 is formed. In some cases, the second layer stack 226 may be referred to as a carrier wafer. The second layer stack 226 includes a silicon carrier layer 214. In some embodiments, the second layer stack 226 may also include a thermal interface (TIM) layer 216 and / or a heat sink layer 218 to further assist in heat dissipation. The heat generated by the BS-PDN of the first layer stack 224 must be dissipated 228 through the second layer stack 226 because the BS-PDN is on the bottom of the completed structure. In block 106, the first layer stack 224 and the second layer stack 226 are bonded together by using bonding layers 212A, 212B inserted between the first layer stack 224 and the second layer stack 226 to form a third layer stack 234. Figure 2 In view 200A, the third layer stack 234 is formed using a c-BN bonding material to form bonding layer 212A. Figure 2 In view 200B, the third stack 234 is formed using a bonding material enriched with isotopes of c-BN to form a bonding layer 212B. Bonding layers 212A and 212B assist in dissipating the heat load generated by the BS-PDN in the first stack 224 into the second stack 226 (e.g., into the silicon carrier layer 214, TIM layer 216, and heat sink layer 218, and further). The c-BN-based bonding layers 212A and 212B exhibit a higher heat dissipation rate than conventionally used oxide materials (such as amorphous silicon dioxide), thereby allowing the third stack 234 to achieve an overall heat dissipation improvement of approximately 10% relative to conventional materials.

[0024] The inventors have discovered that the thermal resistance of BS-PDN packages with conventional oxide bonding layers increases by approximately 20% compared to FS-PDN packages, resulting in poor package thermal performance and negatively impacting the advantages of BS-PDN packages over FS-PDN packages. The inventors have found that the thermal resistance of BS-PDN packages can be improved by replacing the conventional oxides used in the bonding layer with c-BN-based materials. Cubic BN is a unique material due to a combination of inherently unique properties of c-BN, such as extremely high thermal conductivity, wide bandgap (Eg = 6.2–6.4 eV), low dielectric constant (approximately 7.1), and high breakdown field (approximately 8 MV / cm). Cubic BN exhibits excellent high-temperature stability, oxidation resistance, and abrasion resistance. The inventors have discovered that the heat dissipation of BS-PDN packages can be improved by utilizing the high thermal conductivity of c-BN in the bonding layer and the near-diamond-like carbon of isotopically enriched c-BN films. In some embodiments, the thickness 232 of bonding layers 212A, 212B is from approximately 250 nm to approximately 1.2 μm. In some embodiments, the thickness 232 of bonding layers 212A, 212B is approximately 1.0 μm. If the bonding layers are too thick, chemimechanical planarization becomes difficult when the bonding layer has high hardness. Furthermore, a thinner bonding layer will transfer more heat than a thicker bonding layer in a given amount of time.

[0025] By using c-BN and isotopically enriched c-BN as bonding layer materials, the thermal packaging performance of BS-PDN can be improved by up to approximately 10% (e.g., approximately 9.5% for isotopically enriched c-BN), and the interface between the component wafer and the carrier wafer can achieve an environmental thermal resistance value closer to that of FS-PDN packages. Figure 3 In Figure 300, the thermal resistance of the FS-PDN package 302 is compared to that of the BS-PDN package 304, which uses a bonding layer made of a conventional oxide material. The thermal resistance increment 306 between the packages indicates that the thermal resistance of the BS-PDN package 304 is approximately 20% higher than that of the FS-PDN package 302 (e.g., approximately 19%, etc.). This significant increase in thermal resistance greatly affects the usability of the BS-PDN package compared to the FS-PDN package. Despite the advantages of BS-PDN, the difference in thermal resistance makes the design appeal of the BS-PDN package much less attractive.

[0026] To enhance the usability of BS-PDN packages, the inventors were able to significantly reduce differences in thermal resistance by using c-BN-based materials in the bonding layer, such as... Figure 4As depicted in Figure 400. Using BS-PDN package 402 with a conventional oxide bonding layer as baseline 408, BS-PDN package 404 with a c-BN bonding layer provides approximately 9% reduction in thermal resistance 410, and BS-PDN package 406 with an isotopically enriched c-BN bonding layer provides approximately 9.5% reduction in thermal resistance 412. Using ion implantation with heavy isotopes (such as B-10 and / or B-11) to dope c-BN reduces thermal resistance but increases the complexity of bonding layer formation and produces an overall difference of less than 1% in terms of heat dissipation. For high-performance packaging (e.g., supercomputing applications, etc.), isotopically enriched c-BN may be beneficial despite the complexity / cost factors. Cubic boron nitride (CBN) bonding layers can be formed using any compatible method, such as ion-beam epitaxy (MBE), low-pressure plasma-enhanced chemical vapor deposition (LP-PECVD), laser deposition, reactive sputtering, and similar methods. Isotope-enriched CBN bonding layers can be formed by first depositing a c-BN layer, followed by enriching c-BN with isotopes B-10 or B-11 using ion implantation, or by enriching c-BN with isotopes B-10 or B-11 during the deposition of the c-BN layer. In ion implantation processes requiring annealing, non-enriched c-BN deposition processes may be preferred due to device thermal budget considerations. Naturally occurring c-BN contains approximately 22% B-10 isotopes and approximately 78% B-11 isotopes. In some implementations, a high thermal conductivity of approximately 1600 W / m*K is achieved by increasing the boron B-10 or B-11 isotope content to approximately 99%.

[0027] Implementations based on this principle can be carried out in hardware, firmware, software, or any combination thereof. Implementations can also be carried out using instructions stored on one or more computer-readable media, which can be read and executed by one or more processors. The computer-readable media may include any mechanism for storing or transmitting information in a machine-readable form (e.g., a computing platform or a “virtual machine” running on one or more computing platforms). For example, the computer-readable media may include any suitable form of volatile or non-volatile memory. In some implementations, the computer-readable media may include non-transitory computer-readable media.

[0028] Although the foregoing relates to implementations of this principle, other and further implementations of this principle may be designed without departing from its basic scope.

Claims

1. A method for forming a structure having a back-side power delivery network (BS-PDN), the method comprising: A first layer stack is formed, the first layer stack including at least a front-side metallization (FSM) signal layer formed on a silicon grain layer containing nano-through silicon vias (n-TSVs), the nano-through silicon vias being formed on a back-side metallization (BSM) power distribution layer, wherein the n-TSVs provide back-side power connections to the FSM signal layer; A second stack is formed, the second stack including at least a silicon carrier layer; as well as A third layer stack is formed, the third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer inserted between the first layer stack and the second layer stack, wherein the bonding layer is formed of a cubic boron nitride-based material.

2. The method of claim 1, wherein the cubic boron nitride-based material is a cubic boron nitride material enriched with B-10 or B-11 isotopes using a process to obtain approximately 99% of the B-10 or B-11 isotope percentage.

3. The method of claim 1, wherein the silicon grain layer has a thickness of about 200 nm to about 300 nm.

4. The method of claim 1, wherein the n-TSV has a diameter of approximately 100 nm.

5. The method of claim 1, wherein the bonding layer has a thickness of about 250 nm to about 1.2 micrometers.

6. The method of claim 5, wherein the bonding layer has a thickness of approximately 1.0 micrometer.

7. The method of claim 1, wherein the second layer stack comprises a thermal interface material (TIM) layer formed on the silicon carrier layer and a heat sink layer formed on the TIM layer.

8. The method of claim 7, wherein the heat sink layer is formed of copper.

9. The method of claim 1, wherein the first layer stack is a component wafer.

10. The method of claim 1, wherein the first layer stack further comprises the BSM layer formed on the chip interconnect control collapse (C4) layer and the C4 layer formed on the substrate.

11. A method for forming a structure having a back-side power delivery network, the method comprising: A first layer stack is formed, the first layer stack including at least a front-side metallization (FSM) signal layer formed on a silicon grain layer containing nano-through silicon vias (n-TSVs), the nano-through silicon vias being formed on a back-side metallization (BSM) power distribution layer, wherein the n-TSVs provide back-side power connections to the FSM signal layer and have a diameter of approximately 100 nm. A second stack is formed, the second stack including at least a silicon carrier layer; as well as A third layer stack is formed, the third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer inserted between the first layer stack and the second layer stack, wherein the bonding layer is formed of a cubic boron nitride-based material and has a thickness of about 250 nm to about 1.2 micrometers.

12. The method of claim 11, wherein the cubic boron nitride-based material is a cubic boron nitride material enriched with B-10 or B-11 isotopes using a process to obtain approximately 99% of the B-10 or B-11 isotope percentage.

13. The method of claim 11, wherein the silicon grain layer has a thickness of about 200 nm to about 300 nm.

14. The method of claim 11, wherein the bonding layer has a thickness of approximately 1.0 micrometer.

15. The method of claim 11, wherein the second layer stack comprises a thermal interface material (TIM) layer formed on the silicon carrier layer and a heat sink layer formed on the TIM layer.

16. The method of claim 15, wherein the heat sink layer is formed of copper.

17. The method of claim 11, wherein the first layer stack is a component wafer.

18. The method of claim 11, wherein the first layer stack further comprises the BSM layer formed on the chip interconnect control collapse (C4) layer and the C4 layer formed on the substrate.

19. A non-transitory computer-readable medium having instructions stored thereon, which, when executed, cause the execution of a method for forming a structure having a back-side power delivery network, the method comprising: A first layer stack is formed, the first layer stack including at least a front-side metallization (FSM) signal layer formed on a silicon grain layer containing nano-through silicon vias (n-TSVs), the nano-through silicon vias being formed on a back-side metallization (BSM) power distribution layer, wherein the n-TSVs provide back-side power connections to the FSM signal layer; A second stack is formed, the second stack including at least a silicon carrier layer; as well as A third layer stack is formed, the third layer stack including the first layer stack and the second layer stack bonded together with a bonding layer inserted between the first layer stack and the second layer stack, wherein the bonding layer is formed of a cubic boron nitride-based material.

20. The non-transitory computer-readable medium of claim 19, wherein the method further comprises at least one of a, b, c, d, or e: a) The cubic boron nitride-based material is a cubic boron nitride material enriched with B-10 or B-11 isotopes using a process that yields approximately 99% of the B-10 or B-11 isotope percentage. b) wherein the silicon grain layer has a thickness of approximately 200 nm to approximately 300 nm; c) wherein the n-TSV has a diameter of approximately 100 nm; d) The bonding layer has a thickness of approximately 250 nm to approximately 1.2 micrometers; or e) The bonding layer thereon has a thickness of approximately 1.0 micrometer.

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