Single photon detection quenching circuit for quantum key distribution terminals

Abstract

The application discloses a single-photon detection quenching circuit for a quantum key distribution terminal, wherein single-photon avalanche diodes SPAD1 and SPAD2 in a quenching unit receive the same photon signal, the single-photon avalanche diode SPAD1 is quenched and reset after avalanche, and the single-photon avalanche diode SPAD2 feeds back a Vout signal to a subsequent logic circuit for processing; comparators U1 and U4 in the quenching unit simultaneously set high or low at the output end after sampling the avalanche currents of the single-photon avalanche diodes SPAD1 and SPAD2, and then release the output level pulse width in a staggered manner; when the comparators U1 and U4 simultaneously set high or low at the output, the D flip-flops U2 and U5 will output synchronously and continuously output a low-level signal VS to show that the current dead time cannot respond to the occurrence of a missed count.

Description

Technical Field

[0001] This invention belongs to the field of quantum communication control, specifically relating to a single-photon detection quenching circuit for a quantum key distribution terminal. Background Technology

[0002] The core component of a quantum key distribution (QKD) terminal is a single-photon detector. In the field of single-photon detection, a single-photon avalanche diode (SPAD) operates in Geiger mode, with a bias voltage higher than its breakdown voltage. A single incident photon can trigger a self-sustaining avalanche breakdown and generate a macroscopic current pulse. This avalanche process must be rapidly terminated by a quenching circuit after detection, as shown in the attached diagram. Figure 1 and attached Figure 2 The different quenching circuits shown all work on the principle that after a SPAD avalanche, the SPAD anode is given a high potential by the power supply or the SPAD cathode is pulled down to achieve a SPAD bias voltage as low as the breakdown threshold to eliminate the avalanche current and restore the SPAD to the test state, thereby completing a complete detection cycle. Regardless of whether passive quenching, active quenching, or hybrid quenching is used, all rely on preset fixed timing parameters to perform this "avalanche quenching → reset test" cycle operation. According to its operating mechanism, it can be divided into two modes: the first is the gated mode, which precisely limits the opening and closing of the detection window through an external periodic clock signal, so that the SPAD is only in a sensitive state during the window period. However, because this mode must be strictly synchronized with the system clock that generates photons, it cannot be applied to continuous detection scenarios where the arrival time of photons is completely irregular. The second is the full operation mode (or free operation mode). In this mode, once the SPAD is powered on, it is continuously biased above the Geiger threshold, always maintaining the real-time response capability to incident photons at any time. There is no periodic gating or external window to cut off the detection period. The bias voltage is always higher than the breakdown voltage. Therefore, photons that arrive at the photosensitive area at any time and have enough energy to trigger the initial avalanche ionization can immediately trigger an avalanche pulse and output a corresponding current signal.

[0003] However, in full-operation mode, due to the lack of a global synchronous reference clock like in gating mode to constrain the timing relationships of each process node, this continuous and uninterrupted detection mechanism exposes two mutually restrictive problems: First, if a photon arrives within the dead time window of the previous avalanche termination process, SPAD will be unable to respond because the dead time is in an insensitive state, resulting in a systematic undercount of real photon events, and this undercount probability deteriorates sharply with the increase of the background count rate (including the sum of the dark count rate and the ambient photon flux); Second, during the step-by-step processing of the original avalanche pulse signal along the signal chain, there is a transmission delay in the front-end analog link and a processing delay in the back-end digital logic circuit. Due to uncertainty, the system must set a certain dead-zone window width. If fixed and redundant timing parameters are mechanically used to forcibly adapt to the entire "quenching, reset, and test" process, under the statistical distribution of random photon arrival, either the dead-zone window is excessively extended, artificially suppressing the maximum detectable count rate, resulting in the ineffective shielding of a large number of effective photon events, or the dead-zone window is compressed too short, sacrificing the timing margin of subsequent digital logic circuits, leading to signal metastability and causing missed detections or false triggers. To address this, a SPAD quenching scheme that optimizes the dead-zone window width is proposed. This scheme can ensure that the SPAD does not fail to respond to effective photons in the insensitive state under any detection background, and detection is performed at the maximum detectable count rate. Summary of the Invention

[0004] In view of this, to solve the above problems, this application proposes a single-photon detection quenching circuit for a quantum key distribution terminal, including a quenching unit and a processing unit. In the quenching unit, single-photon avalanche diodes SPAD1 and SPAD2 receive the same photon signal. After avalanche, SPAD1 is quenched and reset, while SPAD2 feeds back a Vout signal to the subsequent logic circuit for processing. In the quenching unit, comparators U1 and U4 sample the avalanche currents of SPAD1 and SPAD2, and their outputs are simultaneously set high or low, then the output pulse width is released in a staggered manner, ensuring that the high-level input time of pin 3 of the corresponding D flip-flop U5 is always greater than that of pin 3 of the D flip-flop U2. When D flip-flops U2 and U5 receive the simultaneous high or low outputs of comparators U1 and U4... D flip-flops U2 and U5 will synchronize their outputs and continuously output a low-level signal VS to indicate that the maximum detectable count rate under the current background will not be missed due to the dead time of the single-photon avalanche diode SPAD2 being unable to respond in the insensitive state. In the initial state, the input of En is input with the minimum delay time. When the En signal is input, the single-photon avalanche diode SPAD2 is quenched and reset, and pins 3 of both D flip-flops U2 and U5 are released from the high-level pre-emptive position, waiting for the second photon to enter before cycling again; if the second photon arrives again within the dead time window of the previous avalanche termination process of the single-photon avalanche diode SPAD2, D flip-flops U2 will be asynchronous with the output of D flip-flops U5 under the high-level pre-emptive position of D flip-flops U5 and output a high-level signal VS to indicate that the current count rate will cause count loss. The processing unit will adjust the En input time up or down based on the VS signal state;

[0005] In the quenching unit, after the single-photon avalanche diodes SPAD1 and SPAD2 receive the same photon signal, SPAD1 undergoes quenching and reset after avalanche, serving as a reference for the sensitive state of SPAD2 and not participating in subsequent logic circuit processing. However, the feedback Vout signal from SPAD2 participates normally in subsequent logic circuit processing. During circuit power-up, comparators U1 and U4 sample the avalanche currents of SPAD1 and SPAD2, and their outputs are simultaneously set high or low, followed by a staggered release of the output level pulse width. Initially, the dead time of SPAD2 is set at the highest counting rate, meaning the input of En is input with the minimum delay time. The staggered release pulse width of comparators U1 and U4 ensures that the high-level input time at pin 3 of the corresponding D flip-flop U5 is always greater than that at pin 3 of the D flip-flop U2. When the D flip-flops U2 and U4... When comparators U1 and U4 are simultaneously set to high or low, D flip-flops U2 and U5 will synchronize their outputs and continuously output a low-level signal to indicate that the maximum detectable count rate under the current background will not be missed due to the dead time of the single-photon avalanche diode SPAD2 being unable to respond in the insensitive state. When the En signal is input, the single-photon avalanche diode SPAD2 is quenched and reset, and pins 3 of both D flip-flops U2 and U5 are released from the high-level position, waiting for the second photon to enter before cycling again. If the second photon arrives again within the dead time window of the previous avalanche termination process of the single-photon avalanche diode SPAD2, D flip-flops U2 will be asynchronous with the output of D flip-flops U5 under the high-level position of D flip-flops U5, and output a high-level signal to indicate that the current count rate will cause count loss. The processing unit will adjust the En input time up or down based on the VS signal state to increase or decrease the dead time window of the single-photon avalanche diode SPAD2.

[0006] Furthermore, in the quenching unit, the inverting input of comparator U1 receives the quenching reference voltage Vref, and its non-inverting input is connected to the emitter of transistor Q1, one end of resistor R1, and the anode of single-photon avalanche diode SPAD1. Its output is connected to the base of transistor Q1 and pin 3 of D flip-flop U2. The anode of single-photon avalanche diode SPAD2 is connected to one end of resistor R2, the emitter of transistor Q2, and the non-inverting input of comparator U4, and feeds back the Vout signal to the subsequent logic circuit. The inverting input of comparator U4 is connected to the inverting input of comparator U1, and its output outputs the control signal PA. Its output is connected to pin 3 of D flip-flop U5. Pin 5 of D flip-flop U2 is connected to... One input of AND gate U6 is connected, and pin 6 is connected to one input of AND gate U3; the other input of AND gate U3 is connected to pin 6 of D flip-flop U5, and its output is connected to one input of XOR gate U7; the other input of AND gate U6 is connected to pin 5 of D flip-flop U5, and its output is connected to the other input of XOR gate U7; the output of XOR gate U7 outputs the adjustment signal VS; the cathodes of single-photon avalanche diode SPAD1 and SPAD2, the collectors of transistor Q1 and Q2, are connected to the power supply; the other ends of resistors R1 and R2 are connected to ground; the PA and VS signals are connected to the processing unit.

[0007] In one embodiment, the specific signal flow of the quenching unit is as follows: After the single-photon avalanche diode SPAD1 detects the first photon entering and an avalanche occurs, the current generated is first converted into a voltage by resistor R1 and then fed back to the non-inverting input of comparator U1. The output of comparator U1 outputs a high-level signal to the 1CLK pin of D flip-flop U2 and the base of transistor Q1, turning on transistor Q1. The power supply is fed back to the anode of the single-photon avalanche diode SPAD1 through the collector and emitter of transistor Q1. The bias voltage from the cathode to the anode of the single-photon avalanche diode SPAD1 decreases to the breakdown threshold, stopping avalanche and resetting. The voltage drop across resistor R1 causes comparator U1 to output a low level, and the inverting input of comparator U1 is set to Vre. The quenching reference voltage is less than the voltage applied to resistor R1 after the power supply circuit via transistor Q1 and resistor R1, and also less than the voltage applied to resistor R1 after the single-photon avalanche diode SPAD1 circuit via resistor R1. When the D flip-flop U2 receives a high-level output from comparator U1, pin 5 outputs a high level to AND gate U6, and pin 6 outputs a low level to AND gate U3. Simultaneously, the current generated after the first photon detected by the single-photon avalanche diode SPAD2 enters and causes an avalanche is fed back to the non-inverting input of comparator U4 via resistor R2. Comparator U4 outputs a high-level signal PA, completing the simultaneous high setting and misaligned pulse width release. Subsequently, PA is input to one path. The signal is fed back to the processing unit. Another path provides feedback to pin 3 of D flip-flop U5. When D flip-flop U5 receives a high-level input from comparator U4, pin 5 outputs a high level to AND gate U6, and pin 6 outputs a low level to AND gate U3. AND gate U3 outputs a low-level signal to XOR gate U7, AND gate U6 outputs a high-level signal to XOR gate U7, and XOR gate U7 outputs a low-level signal VS to the processing unit. At this time, pin 3 of D flip-flop U2 is low, and pin 3 of D flip-flop U5 is high. If no second photon enters the single-photon avalanche diode SPAD1 during this period, the processing unit starts timing after receiving the PA signal and inputs the En signal to the base of transistor Q2 after the timing ends. When transistor Q2 is turned on, the power supply is fed back to the anode of single-photon avalanche diode SPAD2 through the collector and emitter of transistor Q2. The bias voltage from the cathode to the anode of single-photon avalanche diode SPAD2 drops to the breakdown threshold and stops avalanche. The non-inverting input of comparator U4 samples resistor R2 and then outputs a low-level signal to pin 3 of D flip-flop U5. During this process, XOR gate U7 continuously outputs a low-level signal to ensure that single-photon avalanche diode SPAD2 does not receive a second photon within the dead window. The output levels of D flip-flop U2 and D flip-flop U5 are always synchronized, while the level state of pin 3 of D flip-flop U5 is always lagging behind pin 3 of D flip-flop U2, completing the different high-level time occupation.If the single-photon avalanche diode SPAD2 is still in its dead time, when the single-photon avalanche diode SPAD1 detects a second photon again, comparator U1 outputs a high-level signal to pin 3 of D flip-flop U2, pin 5 of D flip-flop U2 outputs a low-level signal to AND gate U3, and pin 6 outputs a high-level signal to AND gate U6. However, when the single-photon avalanche diode SPAD2 is in its dead time, pin 3 of D flip-flop U5 remains in a high-level positional state, and the pin output states remain unchanged. The asynchronous outputs of D flip-flops U2 and U5 cause AND gates U3 and U6 to output opposite values, and XOR gate U7 outputs a high-level signal VS to the processing unit.

[0008] Furthermore, in the processing unit, the input terminal of NOT gate U9 and pin 3 of digital potentiometer U8 receive the PA signal from the quenching unit; the output terminal of NOT gate U9 is connected to the base of transistor Q3; the collector of transistor Q3 is connected to one end of capacitor C1, the non-inverting input of operational amplifier U10, and pin 5 of digital potentiometer U8; pin 7 of digital potentiometer U8 is connected to the output terminal of NOT gate U11, pin 1 receives the clock signal CLK, and pin 2 is connected to one end of resistor R3 to receive the reset signal Res; the input terminal of NOT gate U11 receives the VS signal; the inverting input of operational amplifier U10 is connected to one end of resistor R3 and one end of resistor R4, and operational amplifier U10 outputs the En signal to the processing unit; the other end of resistor R3, the other end of resistor R4, the emitter of transistor Q3, the other end of capacitor C1, and the ground terminal are connected; the other end of resistor R3 is connected to the power supply.

[0009] The PA signal from the processing unit is fed back to pin 3 of NOT gate U9 and digital potentiometer U8. Pin 5 of digital potentiometer U8 and capacitor C1 form a delay circuit. When PA is low, transistor Q3 is turned on. Capacitor C1 is grounded through the collector, emitter, and ground loop of transistor Q3. The inverting input of operational amplifier U10 sets the delay reference signal. When the PA signal is high, NOT gate U9 outputs a low level, transistor Q3 is turned off, and the PA signal is fed back to capacitor C1 through digital potentiometer U8. The potential of capacitor C1 is pulled up to the voltage divider point of resistors R3 and R4, and then a high-level signal En is output. When transistor Q2 is turned on, the power supply is fed back to the anode of single-photon avalanche diode SPAD2 through the collector and emitter of transistor Q2. The bias voltage from the cathode to the anode of single-photon avalanche diode SPAD2 decreases to the breakdown threshold and stops avalanche. When VS is continuously at a low level, the NOT gate U11 outputs a high level to pin 7 of digital potentiometer U8. The NOT gate U11 remains in sleep mode and does not wake up. When the VS input is high, digital potentiometer U8 is woken up, and the current resistance value of digital potentiometer U8 is reduced. The time constant of digital potentiometer U8 and capacitor C1 is reduced, increasing or decreasing the delay time of En.

[0010] Furthermore, when the microprocessor in the processing unit detects a high level in Vs or when the photon counting input level in the digital logic circuit is not synchronized with a high level in a timing sequence with Vout, the delay time of En is increased; the initial delay time of Ec can be adjusted or modified by capacitor C1.

[0011] Furthermore, capacitor C1 in the processing unit is an adjustable capacitor, and adjusting the capacitance of capacitor C1 controls the initial delay time of En.

[0012] Furthermore, resistors R3 and R4 in the processing unit are adjustable resistors, and adjusting the voltage division ratio of resistors R3 and R4 controls the initial delay time of En. Attached Figure Description

[0013] Figure 1 and Figure 2 A schematic diagram of the existing quenching circuit principle provided for this invention.

[0014] Figure 3 This is a schematic diagram of the logic circuit processing flow after quenching provided by the present invention.

[0015] Figure 4 This is a schematic diagram of the quenching unit circuit provided by the present invention.

[0016] Figure 5 This is a schematic diagram of the processing unit circuit provided by the present invention. Detailed Implementation

[0017] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0018] The following disclosure provides numerous different embodiments or examples for implementing various structures of the invention. To simplify the disclosure, specific examples of components and arrangements are described below. These are merely examples and are not intended to limit the scope of the invention. Furthermore, reference numerals and / or letters may be repeated in different examples. Such repetition is for simplification and clarity and does not in itself indicate a relationship between the various embodiments and / or arrangements discussed.

[0019] In one embodiment, the goal is to achieve zero photon event omissions in the SPAD under different detection backgrounds in the insensitive state, see reference. Figure 4In this scheme, after the photonic avalanche diode SPAD1 and the single-photon avalanche diode SPAD2 in the quenching unit receive the same photon signal, the single-photon avalanche diode SPAD1 undergoes quenching and reset after avalanche, serving as a reference for the sensitive state of the single-photon avalanche diode SPAD2, and does not participate in the subsequent logic circuit processing. However, the feedback Vout signal from the single-photon avalanche diode SPAD2 participates normally in the subsequent logic circuit processing. During circuit power-up, comparators U1 and U4 sample the avalanche current of the single-photon avalanche diodes SPAD1 and SPAD2, and their output terminals are simultaneously set high or low, followed by a staggered release of the output level pulse width. In the initial state, the dead time width of the single-photon avalanche diode SPAD2 is set at the highest counting rate, that is, the input of En is input with the minimum delay time. The staggered release pulse width of comparators U1 and U4 ensures that the high-level input time of pin 3 of the corresponding D flip-flop U5 is always greater than the high-level input time of pin 3 of the D flip-flop U2. When the D flip-flop U2 and D flip-flop U4... When comparator U5 receives a simultaneous high or low output from comparator U1 and comparator U4, D flip-flops U2 and U5 will synchronize their outputs and continuously output a low-level signal to indicate that the maximum detectable count rate under the current background will not be missed due to the dead time of the single-photon avalanche diode SPAD2 being unable to respond in the insensitive state. When the En signal is input, the single-photon avalanche diode SPAD2 is quenched and reset, and pins 3 of both D flip-flops U2 and U5 are released from the high-level position, waiting for the second photon to enter before cycling again. If the second photon arrives again within the dead time window of the previous avalanche termination process of the single-photon avalanche diode SPAD2, D flip-flops U2, under the high-level position of D flip-flop U5, will asynchronously output with D flip-flop U5 and output a high-level signal to indicate that the current count rate will cause count loss. The processing unit adjusts the En input time up or down based on the VS signal state to increase or decrease the dead time window of the single-photon avalanche diode SPAD2.

[0020] In one embodiment, see Figure 4The specific signal flow of the quenching unit is as follows: When the single-photon avalanche diode SPAD1 detects the first photon entering the avalanche, the resulting current is first converted into a voltage by resistor R1 and then fed back to the non-inverting input of comparator U1. Comparator U1 outputs a high-level signal to the 1CLK pin of D flip-flop U2 and the base of transistor Q1, turning on transistor Q1. The power supply is then fed back to the anode of the single-photon avalanche diode SPAD1 through the collector and emitter of transistor Q1. The bias voltage from the cathode to the anode of the single-photon avalanche diode SPAD1 decreases to the breakdown threshold, stopping the avalanche and resetting. The voltage drop across resistor R1 causes comparator U1 to output a low level, and the Vref quenching parameter is set at the inverting input of comparator U1. Considering the voltage, the voltage amplitude is less than the voltage applied to resistor R1 after the power supply circuit via transistor Q1 and resistor R1, and also less than the voltage applied to resistor R1 after the single-photon avalanche diode SPAD1 circuit. When the D flip-flop U2 receives a high-level output from comparator U1, pin 5 outputs a high level to AND gate U6, and pin 6 outputs a low level to AND gate U3. Simultaneously, the current generated after the first photon detected by the single-photon avalanche diode SPAD2 enters and causes an avalanche is fed back to the non-inverting input of comparator U4 via resistor R2. Comparator U4 outputs a high-level signal PA, completing the simultaneous high setting and staggered pulse width release. Subsequently, PA is input to the processing circuit. The other path feeds back to pin 3 of D flip-flop U5. When D flip-flop U5 receives a high-level input from comparator U4, pin 5 outputs a high level to AND gate U6, and pin 6 outputs a low level to AND gate U3. AND gate U3 outputs a low-level signal to XOR gate U7, AND gate U6 outputs a high-level signal to XOR gate U7, and XOR gate U7 outputs a low-level signal VS to the processing unit. At this time, pin 3 of D flip-flop U2 is low, and pin 3 of D flip-flop U5 is high. If no second photon enters the single-photon avalanche diode SPAD1 during this period, the processing unit starts timing after receiving the PA signal and outputs the En signal to the base of transistor Q2 after the timing ends. When transistor Q2 is turned on, the power supply is fed back to the anode of single-photon avalanche diode SPAD2 through the collector and emitter of transistor Q2. The bias voltage from the cathode to the anode of single-photon avalanche diode SPAD2 drops to the breakdown threshold and stops avalanche. The non-inverting input of comparator U4 samples resistor R2 and then outputs a low-level signal to pin 3 of D flip-flop U5. During this process, XOR gate U7 continuously outputs a low-level signal to ensure that single-photon avalanche diode SPAD2 does not receive a second photon within the dead window. The output levels of D flip-flop U2 and D flip-flop U5 are always synchronized, while the level state of pin 3 of D flip-flop U5 is always lagging behind pin 3 of D flip-flop U2, completing the different high-level time occupation.If the single-photon avalanche diode SPAD2 is still in the dead zone, when the single-photon avalanche diode SPAD1 detects a second photon again, comparator U1 outputs a high-level signal to pin 3 of D flip-flop U2, pin 5 of D flip-flop U2 outputs a low-level signal to AND gate U3, and pin 6 outputs a high-level signal to AND gate U6. However, when the single-photon avalanche diode SPAD2 is in the dead zone, pin 3 of D flip-flop U5 is still in a high-level occupying state, and the pin output state remains unchanged. The asynchronous outputs of D flip-flop U2 and D flip-flop U5 cause AND gates U3 and U6 to have opposite outputs. XOR gate U7 outputs a high-level signal VS to the processing unit. In this embodiment, the processing unit adjusts the En delay time by the microprocessor when it detects a high level of Vs or when the photon counting input level in the digital logic circuit is not synchronized with Vout in a timing sequence.

[0021] For details, please refer to Figure 3 , Figure 3 This is a flowchart of the logic circuit processing after quenching. Taking the input pin judgment of the counting chip in photon counting as an example, assuming the counting chip model is 74HC4017, the input signal of pin 14 of the counting chip and the output signal of the processing unit Vout are sampled respectively and latched by the flip-flop. The AND gate samples the two latched signals. When the comparator U1 outputs again, if the true value of the AND gate is not 1, the delay time of En is increased and the output device is reset. The subsequent digital logic circuit is not shown in the attached figure. This only provides an embodiment of the judgment of whether there is metastability in signal establishment during logic circuit processing.

[0022] In one embodiment, see Figure 5 The PA signal from the processing unit is fed back to pin 3 of NOT gate U9 and digital potentiometer U8. Pin 5 of digital potentiometer U8 and capacitor C1 form a delay circuit. When PA is low, transistor Q3 is turned on. Capacitor C1 is connected to ground via the collector, emitter, and ground circuit of transistor Q3. The inverting input of operational amplifier U10 sets the delay reference signal. When the PA signal is high, NOT gate U9 outputs a low level, transistor Q3 is turned off, and the PA signal is fed back to capacitor C1 via digital potentiometer U8. The potential of capacitor C1 is pulled up to the voltage divider point of resistors R3 and R4, and then outputs a high-level signal En to transistor Q2. When 2 is turned on, the power supply is fed back to the anode of the single-photon avalanche diode SPAD2 through the collector and emitter of transistor Q2. The bias voltage from the cathode to the anode of the single-photon avalanche diode SPAD2 decreases to the breakdown threshold and stops avalanche. When VS is continuously at a low level, the output of NOT gate U11 is high to pin 7 of digital potentiometer U8. NOT gate U11 is in sleep mode and does not wake up. When the input of VS is high, digital potentiometer U8 is woken up and its current resistance value is reduced. The time constant of digital potentiometer U8 and capacitor C1 is reduced, increasing or shortening the delay time of En. The initial delay time of Ec can be adjusted or modified by capacitor C1.

Claims

1. A single photon detection quenching circuit for a quantum key distribution terminal, characterized by, The system includes a quenching unit and a processing unit. In the quenching unit, single-photon avalanche diodes SPAD1 and SPAD2 receive the same photon signal. After avalanche, SPAD1 is quenched and reset, while SPAD2 feeds back a Vout signal to the subsequent logic circuit for processing. Comparators U1 and U4 in the quenching unit sample the avalanche current of SPAD1 and SPAD2, and then simultaneously set their outputs high or low, subsequently releasing the output pulse width with a staggered timing. This ensures that the high-level input time at pin 3 of the corresponding D flip-flop U5 is always greater than that at pin 3 of the D flip-flop U2. When D flip-flops U2 and U5 receive simultaneous high or low outputs from comparators U1 and U4, they will output... The system synchronously and continuously outputs a low-level signal VS to indicate that the maximum detectable count rate under the current background will not be missed due to the dead time of the single-photon avalanche diode SPAD2 being unable to respond in the insensitive state. In the initial state, the input of En is input with the minimum delay time. When the En signal is input, the single-photon avalanche diode SPAD2 is quenched and reset, and the high-level preemption of pins 3 of D flip-flops U2 and U5 is released, waiting for the second photon to enter before cycling again. If the second photon arrives again within the dead time window of the previous avalanche termination process of the single-photon avalanche diode SPAD2, D flip-flop U2 will be asynchronous with the output of D flip-flop U5 under the high-level preemption of D flip-flop U5, and output a high-level signal VS to indicate that the current count rate will cause count loss. The processing unit adjusts the En input time up or down based on the VS signal state.

2. The single-photon-detection quenching circuit for a quantum-key-distribution terminal according to claim 1, wherein In the quenching unit, the inverting input of comparator U1 receives the quenching reference voltage Vref, and its non-inverting input is connected to the emitter of transistor Q1, one end of resistor R1, and the anode of single-photon avalanche diode SPAD1. Its output is connected to the base of transistor Q1 and pin 3 of D flip-flop U2. The anode of single-photon avalanche diode SPAD2 is connected to one end of resistor R2, the emitter of transistor Q2, and the non-inverting input of comparator U4, and feeds back the Vout signal to the subsequent logic circuit. The inverting input of comparator U4 is connected to the inverting input of comparator U1, and its output outputs the control signal PA. Its output is connected to pin 3 of D flip-flop U5. Pin 5 of D flip-flop U2 is connected to... One input of gate U6 is connected to pin 6 and one input of AND gate U3; the other input of AND gate U3 is connected to pin 6 of D flip-flop U5, and its output is connected to one input of XOR gate U7; the other input of AND gate U6 is connected to pin 5 of D flip-flop U5, and its output is connected to the other input of XOR gate U7; the output of XOR gate U7 outputs the adjustment signal VS; the cathodes of single-photon avalanche diode SPAD1 and SPAD2, the collectors of transistor Q1 and Q2, are connected to the power supply; the other ends of resistors R1 and R2 are connected to ground; the PA and VS signals are connected to the processing unit.

3. The single-photon-detection quenching circuit for a quantum-key-distribution terminal according to claim 1, wherein In the processing unit, the input of NOT gate U9 and pin 3 of digital potentiometer U8 receive the PA signal from the quenching unit; the output of NOT gate U9 is connected to the base of transistor Q3; the collector of transistor Q3 is connected to one end of capacitor C1, the non-inverting input of operational amplifier U10, and pin 5 of digital potentiometer U8; pin 7 of digital potentiometer U8 is connected to the output of NOT gate U11; pin 1 receives the clock signal CLK, and pin 2 is connected to one end of resistor R3 to receive the reset signal Res; the input of NOT gate U11 receives the VS signal; the inverting input of operational amplifier U10 is connected to one end of resistor R3 and one end of resistor R4, and operational amplifier U10 outputs the En signal to the processing unit; the other end of resistor R3, the other end of resistor R4, the emitter of transistor Q3, the other end of capacitor C1, and the ground terminal are connected; the other end of resistor R3 is connected to the power supply.

4. The single-photon detection quenching circuit for a quantum key distribution terminal according to claim 1, characterized in that, The microprocessor in the processing unit increases the En delay time when it detects a high level in Vs or when the photon counting input level in the digital logic circuit is not synchronized with a high level in a timing sequence with Vout.

5. The single-photon detection quenching circuit for a quantum key distribution terminal according to claim 2, characterized in that, In the processing unit, capacitor C1 is an adjustable capacitor. Adjusting the capacitance of capacitor C1 controls the initial delay time of En.

6. The single-photon detection quenching circuit for a quantum key distribution terminal according to claim 2, characterized in that, In the processing unit, resistors R3 and R4 are adjustable resistors. Adjusting the voltage division ratio of resistors R3 and R4 controls the initial delay time of En.

Images