A method for designing an isolation device for capacitive characteristic test of high voltage semiconductor switching devices

Abstract

This invention discloses a design method for an isolation device in the capacitive characteristic testing of high-voltage semiconductor switching devices. The method includes the following steps: designing a suitable PCB for the Coss isolation device; connecting the terminals of the LCR and MCU to the Coss test system; connecting the four terminals Hcur, Hpot, Lcur, and Lpot of the LCR, and the HI and LO terminals of the MCU to the Coss isolation device via coaxial cables; inserting the DUT into the test socket to prepare for the subsequent Coss test; and starting the Coss test. This invention's design method for an isolation device in the capacitive characteristic testing of high-voltage semiconductor switching devices ensures that a high-voltage DC signal can be applied to the D and S terminals of the device, while ensuring that the AC test circuit is not affected by the high-voltage signal. This ensures the accuracy and reliability of the measurement process and meets the requirements for accurate measurement of capacitive characteristics under high-voltage test conditions.

Description

Technical Field

[0001] This invention relates to the field of capacitive characteristic testing technology for high-voltage semiconductor switching devices, and particularly to a design method for an isolation device used in capacitive characteristic testing of high-voltage semiconductor switching devices. Background Technology

[0002] An isolation device is used for testing the capacitive characteristics of high-voltage semiconductor switching devices. Capacitive characteristic testing aims to evaluate the performance and response capability of the device under load conditions, especially verifying the stability and accuracy of voltage and current. Through capacitive characteristic testing, the performance of semiconductor switching devices can be comprehensively evaluated, ensuring their reliability and stability in circuit design and application. In capacitive characteristic testing, a DC high-voltage bias is typically applied to the drain (D) and source (S) terminals of the semiconductor switching device, while the capacitance value is measured using an AC signal with a frequency between 100kHz and 10MHz. With the continuous development of technology, the requirements for isolation devices are becoming increasingly stringent.

[0003] Existing isolation devices have certain drawbacks in use. Although current capacitive characteristic testing methods can achieve capacitive characteristic testing within a certain range, they impose limitations on the capacitive characteristic testing conditions of semiconductor devices under high voltage and high frequency conditions. Therefore, to improve the testing conditions for capacitive characteristics, this paper proposes a design method for an isolation device in the capacitive characteristic testing of high-voltage semiconductor switching devices. This method utilizes the characteristics of capacitance and inductance to achieve effective isolation between AC and DC signals, ensuring safety and accuracy of measurement results under high voltage testing conditions. Therefore, we propose a design method for an isolation device in the capacitive characteristic testing of high-voltage semiconductor switching devices. Summary of the Invention

[0004] Technical problem solved: In view of the shortcomings of the prior art, the present invention provides a design method for an isolation device in the capacitive characteristic test of high-voltage semiconductor switching devices, which ensures that the high-voltage DC signal can be applied to the D and S terminals of the device, while ensuring that the AC test circuit is not affected by the high-voltage signal, thus ensuring the accuracy and reliability of the measurement process and meeting the requirements for accurate measurement of capacitive characteristics under high-voltage test conditions. It can effectively solve the problems in the background art.

[0005] Technical Solution: To achieve the above objectives, the technical solution adopted by this invention is: a design method for an isolation device in the capacitive characteristic test of high-voltage semiconductor switching devices, specifically including the following operational steps:

[0006] S1: Design a reasonable PCB for the isolation device of Coss: Connect the series capacitor of the Hcur and Hpot terminals of LCR to the D terminal of DUT, connect the series capacitor of the Lcur and Lpot terminals of LCR to the S terminal of DUT, connect the HI terminal of MCU to the D terminal of DUT, connect the LO terminal of MCU to the S terminal of DUT, and short-circuit the G and S terminals.

[0007] S2: Connect the terminals of LCR and MCU to the Coss test system respectively: Connect the four terminals of LCR (Hcur, Hpot, Lcur, and Lpot) and the HI and LO terminals of MCU to the Coss isolation device via coaxial cable.

[0008] S3: Insert the DUT into the test socket: Insert the DUT into the test socket to prepare for the subsequent Coss test;

[0009] S4: Start Coss Test: The experimental environment required for leakage current testing has been set up. Perform Coss testing on the DUT. Before testing, short-circuit the G and S terminals of the DUT and perform open-circuit and short-circuit calibration on the LCR meter to eliminate the influence of parasitic parameters;

[0010] S5: Apply high voltage to the D terminal of the DUT and scan the Coss curve: With the LCR test frequency fixed, change the high voltage value output by the MCU to change the Crss test conditions, and perform Cgd test on the DUT under different Vds to generate the Coss test curve.

[0011] S6: The Coss test of the DUT is complete.

[0012] As a preferred technical solution of this application, the test system in step S2 includes an SMU, an LCR, an isolation device, and a DUT. The SMU is a high voltage source meter, the LCR is an inductance, capacitance, and resistance meter, and the DUT is the semiconductor switching device under test.

[0013] As a preferred technical solution of this application, the SMU provides a DC high voltage Vds to the DUT. The SMU interface includes a HI terminal and a LO terminal. The HI terminal is the positive terminal of the SMU and outputs a high voltage signal. The HI terminal is connected to the SMU through an isolation device. This isolation device prevents the high-frequency AC signal of the LCR meter from reaching the HI terminal of the MCU, thus preventing the high voltage signal of the SMU from affecting the LCR meter. The LO terminal is the negative terminal of the SMU and is connected to the S terminal of the DUT through an isolation device, providing a high voltage test circuit for the D terminal and S terminal of the DUT.

[0014] As a preferred technical solution of this application, the LCR measures Coss through a high-frequency AC signal, where Coss = Cgd + Cds. The LCR interface includes Hcur, Hpot, Lcur, and Lpot. After being isolated, Hcur, Hpot, Lcur, and Lpot are applied to the D and S terminals of the DUT to measure the Coss parameter. Hcur is a high-side current drive, Hpot is a high-side voltage detection, Lcur is a low-side current drive, and Lpot is a low-side voltage detection.

[0015] As a preferred technical solution of this application, the Hpot and Lpot ports apply high-frequency AC signals to the D and S terminals of the DUT and detect the actual voltages present at the D and S terminals as one of the important parameters for calculating Coss. The Hcur and Lcur ports are used to measure the AC current at the D and S terminals as one of the important parameters for calculating Coss.

[0016] As a preferred technical solution of this application, the input of the isolation device is the Hcur, Hpot, Lcur and Lpot terminals of the LCR meter, and the HI and LO terminals of the MCU meter, and the output is the high-frequency signal after Hcur and Hpot are combined and passed through a capacitor, the signal after Lcur and Lpot are combined, the high-voltage signal obtained after the HI terminal is passed through an inductor and a resistor, and the signal at the LO terminal.

[0017] As a preferred technical solution of this application, the three pins of the DUT are the D terminal, the G terminal and the S terminal, respectively. The D terminal is the drain, the G terminal is the gate, and the S terminal is the source. The D terminal is connected to the Hpot terminal and Hcur terminal of the LCR through an isolation device and a series capacitor, and is connected to the HI terminal of the SMU through a series inductor. The G terminal and the S terminal are shorted. At this time, the LCR meter measures the value of Cgd + Cds, that is, Coss. The S terminal is connected to the LO terminal of the SMU through an isolation device.

[0018] As a preferred technical solution of this application, the SMU applies a high voltage Vds between the D terminal and the S terminal of the DUT, the Hcur and Hpot of the LCR are connected to the D terminal of the DUT, the Lcur and Lpot are connected to the S terminal of the DUT, the S terminal and the G terminal are short-circuited, and the test current is divided into two parts, one part returns to the LCR through Cgd, and the other part returns to the LCR through Cds, which is the value of Coss.

[0019] Beneficial effects: Compared with the prior art, the present invention provides a design method for an isolation device in the capacitive characteristic test of high-voltage semiconductor switching devices, which has the following beneficial effects: This design method for an isolation device in the capacitive characteristic test of high-voltage semiconductor switching devices ensures that the high-voltage DC signal can be applied to the D and S terminals of the device, while ensuring that the AC test circuit is not affected by the high-voltage signal, thus ensuring the accuracy and reliability of the measurement process and meeting the requirements for accurate measurement of capacitive characteristics under high-voltage test conditions;

[0020] By connecting a capacitor and a TVS in series at the Hpot and Hcur terminals of the LCR meter, and connecting an inductor and a resistor in series at the HI terminal of the MCU, an AC / DC isolation device is formed, which effectively improves the capacitive characteristic test conditions and accuracy.

[0021] It is simple and easy to implement. With proper design of coaxial cable and PCB, high-precision capacitive characteristic testing can be achieved, which reduces the difficulty of operation, reduces additional equipment investment and maintenance costs, and improves the economy of testing.

[0022] It is not only applicable to the capacitive characteristic testing of semiconductor switching devices, but can also be extended to other electronic testing and measurement fields to improve the performance and reliability of electronic systems. The entire isolation device has a simple structure, is easy to operate, and performs better than traditional methods. Attached Figure Description

[0023] Figure 1 This is a flowchart illustrating a design method for an isolation device in the capacitive characteristic testing of high-voltage semiconductor switching devices according to the present invention.

[0024] Figure 2 This is a schematic diagram of the structure of an isolation device design method for capacitive characteristic testing of high-voltage semiconductor switching devices according to the present invention.

[0025] Figure 3 This is a schematic diagram of one of the principles of the isolation device design method for capacitive characteristic testing of high-voltage semiconductor switching devices according to the present invention.

[0026] Figure 4 This is a schematic diagram (2) of the principle of an isolation device design method for capacitive characteristic testing of high-voltage semiconductor switching devices according to the present invention. Detailed Implementation

[0027] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0028] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0029] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0030] like Figure 1-4 As shown, a design method for an isolation device used in capacitive characteristic testing of high-voltage semiconductor switching devices includes the following steps:

[0031] S1: Design a reasonable PCB for the isolation device of Coss: Connect the series capacitor of the Hcur and Hpot terminals of LCR to the D terminal of DUT, connect the series capacitor of the Lcur and Lpot terminals of LCR to the S terminal of DUT, connect the HI terminal of MCU to the D terminal of DUT, connect the LO terminal of MCU to the S terminal of DUT, and short-circuit the G and S terminals.

[0032] S2: Connect the terminals of LCR and MCU to the Coss test system respectively: Connect the four terminals of LCR (Hcur, Hpot, Lcur, and Lpot) and the HI and LO terminals of MCU to the Coss isolation device via coaxial cable.

[0033] S3: Insert the DUT into the test socket: Insert the DUT into the test socket to prepare for the subsequent Coss test;

[0034] S4: Start Coss Test: The experimental environment required for leakage current testing has been set up. Perform Coss testing on the DUT. Before testing, short-circuit the G and S terminals of the DUT and perform open-circuit and short-circuit calibration on the LCR meter to eliminate the influence of parasitic parameters;

[0035] S5: Apply high voltage to the D terminal of the DUT and scan the Coss curve: With the LCR test frequency fixed, change the high voltage value output by the MCU to change the Crss test conditions, and perform Cgd test on the DUT under different Vds to generate the Coss test curve.

[0036] S6: The Coss test of the DUT is complete.

[0037] The test system in step S2 includes an SMU, an LCR, an isolation device, and a DUT. The SMU is a high-voltage source meter, the LCR is an inductance, capacitance, and resistance meter, and the DUT is the semiconductor switching device under test.

[0038] The SMU provides a DC high voltage Vds to the DUT. The SMU interface includes a HI terminal and a LO terminal. The HI terminal is the positive terminal of the SMU and outputs a high voltage signal. The HI terminal is connected to the SMU through an isolation device. This isolation device prevents the high-frequency AC signal of the LCR meter from reaching the HI terminal of the MCU, thus preventing the high voltage signal of the SMU from affecting the LCR meter. The LO terminal is the negative terminal of the SMU and is connected to the S terminal of the DUT through an isolation device, providing a high voltage test circuit for the D and S terminals of the DUT.

[0039] The LCR (Liquid Crystal Array) measures Coss using a high-frequency AC signal, where Coss = Cgd + Cds. The LCR interface includes Hcur, Hpot, Lcur, Lpot, Hcur, Hpot, Lcur, and Lpot, which, after isolation, are applied to the D and S terminals of the DUT (Distributed Under Test) to measure the Coss parameter. Hcur is for high-side current drive, Hpot for high-side voltage detection, Lcur for low-side current drive, and Lpot for low-side voltage detection. The Hpot and Lpot ports apply a high-frequency AC signal to the D and S terminals of the DUT and detect the actual voltage at the D and S terminals, which is one of the important parameters for calculating Coss. The Hcur and Lcur ports are used to measure the AC current at the D and S terminals, which is also an important parameter for calculating Coss.

[0040] The inputs of the isolation device are the Hcur, Hpot, Lcur, and Lpot terminals of the LCR meter, and the HI and LO terminals of the MCU meter. The outputs are the high-frequency signal obtained by combining Hcur and Hpot and passing them through a capacitor, the signal obtained by combining Lcur and Lpot, the high-voltage signal obtained by passing the HI terminal through an inductor and a resistor, and the signal at the LO terminal.

[0041] The DUT has three pins: D, G, and S. D is the drain, G is the gate, and S is the source. D is connected to the Hpot and Hcur pins of the LCR through an isolation device and a series capacitor. The series inductor is connected to the HI pin of the SMU. G and S are shorted. At this time, the LCR meter measures the value of Cgd + Cds, i.e., Coss. S is connected to the LO pin of the SMU through an isolation device. The SMU applies a high voltage Vds between the D and S pins of the DUT. Hcur and Hpot of the LCR are connected to the D pin of the DUT, and Lcur and Lpot are connected to the S pin of the DUT. S and G are shorted. The test current is divided into two parts: one part returns to the LCR through Cgd, and the other part returns to the LCR through Cds, i.e., the value of Coss.

[0042] Figure 2 This is a structural diagram of an isolation device design method for capacitive characteristic testing of high-voltage semiconductor switching devices. Taking the measurement of Coss (output capacitance) parameter as an example, the test system includes SMU, LCR, isolation device, and DUT (semiconductor under test).

[0043] The SMU is a high voltage source meter that provides DC high voltage Vds to the DUT (semiconductor under test). The SMU interface includes the HI terminal and the LO terminal.

[0044] The HI terminal is the positive terminal of the SMU, outputting a high-voltage signal. The HI terminal is connected to the SMU through an isolation device. This isolation device not only effectively prevents the high-frequency AC signal from the LCR meter from reaching the HI terminal of the MCU, but also prevents the high-voltage signal from the SMU from affecting the LCR meter, ensuring the safety and validity of the test.

[0045] The LO terminal is the negative terminal of the SMU and is connected to the S terminal of the DUT (Semiconductor Under Test) through an isolation device, providing a high-voltage test circuit for the D and S terminals of the DUT.

[0046] LCR measures Coss using a high-frequency AC signal, where Coss = Cgd + Cds. The LCR interface includes Hcur (high-side current drive), Hpot (high-side voltage detection), Lcur (low-side current drive), and Lpot (low-side voltage detection). Hcur, Hpot, Lcur, and Lpot are isolated and then applied to the D and S terminals of the DUT (with the G and S terminals shorted) to measure the Coss parameter.

[0047] The Hpot and Lpot ports apply high-frequency AC signals to the D and S terminals of the DUT and detect the actual voltages present at the D and S terminals, which are used as one of the important parameters for calculating Coss.

[0048] The Hcur and Lcur ports are used to measure the AC current at the D and S terminals, which is one of the important parameters for calculating Coss.

[0049] The isolation device is crucial in Coss testing. The inputs are the Hcur, Hpot, Lcur, and Lpot terminals of the LCR meter, and the HI and LO terminals of the MCU meter. The outputs are the high-frequency signal obtained by combining Hcur and Hpot and passing them through a capacitor, the signal obtained by combining Lcur and Lpot, the high-voltage signal obtained by passing the HI terminal through an inductor and resistor, and the signal at the LO terminal.

[0050] Without a high-voltage isolation device, AC and high-voltage DC signals will act simultaneously on the DUT. The AC signal will be affected by the DC signal, leading to inaccurate measurement results. Furthermore, the high-voltage DC signal may be transmitted back to the LCR meter through the test circuitry, interfering with the LCR meter's internal circuitry, potentially damaging the equipment, and even endangering operator safety. Therefore, during Coss testing, the LCR meter and MCU meter require a high-voltage AC / DC isolation device to effectively physically isolate the high-frequency AC signal and the high-voltage DC signal, ensuring they do not interfere with each other. This allows the AC signal to be applied to the DUT independently of the DC signal, resulting in accurate capacitance measurements. This DC isolation device also provides electrical protection against damage to the LCR meter from the high-voltage DC signal, ensuring the safety and reliability of the test equipment.

[0051] Capacitors possess the characteristic of blocking DC and passing AC, effectively preventing the passage of high-voltage DC signals from the MCU output while allowing AC signals from the LCR meter to pass. This characteristic is based on the charging and discharging of capacitors. In a DC circuit, a capacitor initially charges; once fully charged, the current in the circuit stops due to charge accumulation, blocking the DC signal. However, due to the periodic nature of AC signals, the capacitor continuously charges and discharges, allowing AC signals to pass. The isolation device utilizes this DC-blocking and AC-passing characteristic by combining the Hcur and Hpot of the LCR meter with multiple capacitors in series. This improves the overall voltage withstand capability of the capacitor module, preventing the high-voltage DC signal from the MCU from reaching the LCR meter, thus protecting it from the influence of high-voltage DC signals. In this way, the LCR meter can safely measure the Coss value. The isolation device ensures that AC signals can pass while DC signals are blocked, so the LCR meter measures the AC component of Coss, guaranteeing the accuracy of the measurement results.

[0052] Inductors have the characteristic of low throughput and high resistance, allowing low-frequency alternating current to pass through while blocking high-frequency alternating current. Inductors significantly impede alternating current signals (inductive reactance) while offering relatively less resistance to direct current signals. This is because the self-induced electromotive force generated by the inductor always opposes changes in the current within the coil, thus impeding alternating current signals and approximating a short circuit for direct current signals. By connecting an inductor and a resistor in series at the HI terminal of the MCU, a high-voltage signal can be output from the MCU to the D terminal, while simultaneously blocking the AC signal from the LCR (Liquid Crystal Resonator).

[0053] The three pins of the DUT (Device Under Test) are D (drain), G (gate), and S (source).

[0054] The D terminal is connected to the H pot terminal and H cur terminal of the LCR through an isolation device and a series capacitor, and is connected to the HI terminal of the SMU through a series inductor;

[0055] When the G and S terminals are shorted, the LCR meter measures the value of Cgd + Cds, which is Coss.

[0056] The S terminal is connected to the LO terminal of the SMU via an isolation device;

[0057] The SMU applies a high voltage Vds between the D and S terminals of the DUT. The Hcur and Hpot of the LCR are connected to the D terminal of the DUT, and the Lcur and Lpot are connected to the S terminal of the DUT. The S terminal and the G terminal are shorted. The test current is divided into two parts: one part returns to the LCR through Cgd, and the other part returns to the LCR through Cds, which is the value of Coss(Cgd+Cds).

[0058] Figure 3 , 4 This is a design method for isolation devices used in capacitive characteristic testing of high-voltage semiconductor switching devices;

[0059] set up:

[0060] The LCR has four terminals: Hcur, Hpot, Lcur, and Lpot interfaces.

[0061] The capacitance of capacitors Hcur and Hpot connected in series can be increased by connecting them in parallel, and the overall withstand voltage of the capacitor can be increased by connecting them in series. This withstand voltage should be less than the maximum DC voltage to prevent the capacitor from being broken down.

[0062] A bidirectional TVS diode is connected in parallel across the capacitor. Multiple TVS diodes are connected in series to increase the withstand voltage. When the DC voltage exceeds the breakdown voltage of the TVS diode, the TVS diode will respond quickly and enter a low-resistance state, thus protecting the circuit.

[0063] The Hcur and Hpot of the LCR are connected to the D terminal of the DUT;

[0064] The LCR's Lcur and Lpot are connected to the S terminal of the DUT;

[0065] An inductor and a resistor are connected in series, with one end connected to the HI terminal of the MCU and the other end connected to the D terminal of the DUT.

[0066] The LO terminal of the MCU is connected to the S terminal of the DUT.

[0067] By connecting a capacitor and a TVS diode, an inductor and a resistor in series with the LCR meter and the MCU respectively, AC and DC signals can be effectively isolated, providing a safe high-voltage test environment for Coss testing, ensuring the accuracy of Coss measurement results and the safe operation of the equipment.

[0068] Figure 1 This is a flowchart of a design method for isolation devices used in capacitive characteristic testing of high-voltage semiconductor switching devices;

[0069] A reasonable PCB design for the isolation device of Coss refers to connecting the Hcur and Hpot terminals of the LCR in series with a capacitor connected to the D terminal of the DUT, the Lcur and Lpot terminals of the LCR in series with a capacitor connected to the S terminal of the DUT, the HI terminal of the MCU connected to the D terminal of the DUT, the LO terminal of the MCU connected to the S terminal of the DUT, and shorting the G and S terminals.

[0070] Connecting the terminals of the LCR and MCU to the Coss test system respectively means connecting the four terminals of the LCR (Hcur, Hpot, Lcur, and Lpot) and the HI and LO terminals of the MCU to the Coss isolation device via a coaxial cable.

[0071] Inserting the DUT into the Socket (test socket) prepares the DUT for the subsequent Coss test.

[0072] Starting Coss testing means that the experimental environment required for leakage current testing has been set up.

[0073] Perform Coss testing on the DUT. Before testing, the G and S terminals of the DUT need to be shorted, and the LCR meter needs to be calibrated with open and short circuits to eliminate the influence of parasitic parameters.

[0074] Applying high voltage to the D terminal of the DUT and scanning the Coss curve means that, with a fixed LCR test frequency, changing the high voltage value output by the MCU, i.e., changing the Crss test conditions, and performing Cgd tests on the DUT under different Vds, thereby generating the Coss test curve.

[0075] The Coss test of the DUT has ended.

[0076] The isolation device is crucial in Coss testing. The inputs are the Hcur, Hpot, Lcur, and Lpot terminals of the LCR meter, and the HI and LO terminals of the MCU meter. The outputs are the high-frequency signal obtained by combining Hcur and Hpot and passing them through a capacitor, the signal obtained by combining Lcur and Lpot, the high-voltage signal obtained by passing the HI terminal through an inductor and resistor, and the signal at the LO terminal.

[0077] Without a high-voltage isolation device, AC and high-voltage DC signals will act simultaneously on the DUT. The AC signal will be affected by the DC signal, leading to inaccurate measurement results. Furthermore, the high-voltage DC signal may be transmitted back to the LCR meter through the test circuitry, interfering with the LCR meter's internal circuitry, potentially damaging the equipment, and even endangering operator safety. Therefore, during Coss testing, the LCR meter and MCU meter require a high-voltage AC / DC isolation device to effectively physically isolate the high-frequency AC signal and the high-voltage DC signal, ensuring they do not interfere with each other. This allows the AC signal to be applied to the DUT independently of the DC signal, resulting in accurate capacitance measurements. This DC isolation device also provides electrical protection against damage to the LCR meter from the high-voltage DC signal, ensuring the safety and reliability of the test equipment.

[0078] Capacitors possess the characteristic of blocking DC and passing AC, effectively preventing the passage of high-voltage DC signals from the MCU output while allowing AC signals from the LCR meter to pass. This characteristic is based on the charging and discharging of capacitors. In a DC circuit, a capacitor initially charges; once fully charged, the current in the circuit stops due to charge accumulation, blocking the DC signal. However, due to the periodic nature of AC signals, the capacitor continuously charges and discharges, allowing AC signals to pass. The isolation device utilizes this DC-blocking and AC-passing characteristic by combining the Hcur and Hpot of the LCR meter with multiple capacitors in series. This improves the overall voltage withstand capability of the capacitor module, preventing the high-voltage DC signal from the MCU from reaching the LCR meter, thus protecting it from the influence of high-voltage DC signals. In this way, the LCR meter can safely measure the Coss value. The isolation device ensures that AC signals can pass while DC signals are blocked, so the LCR meter measures the AC component of Coss, guaranteeing the accuracy of the measurement results.

[0079] Inductors have the characteristic of low throughput and high resistance, allowing low-frequency alternating current to pass through while blocking high-frequency alternating current. Inductors significantly impede alternating current signals (inductive reactance) while offering relatively less resistance to direct current signals. This is because the self-induced electromotive force generated by the inductor always opposes changes in the current within the coil, thus impeding alternating current signals and approximating a short circuit for direct current signals. By connecting an inductor and a resistor in series at the HI terminal of the MCU, a high-voltage signal can be output from the MCU to the D terminal, while simultaneously blocking the AC signal from the LCR (Liquid Crystal Resonator).

[0080] It should be noted that, in this document, relational terms such as first and second (number one, number two), etc., are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0081] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A design method for an isolation device used in capacitive characteristic testing of high-voltage semiconductor switching devices, characterized in that: Specifically, the following steps are included: S1: Design a reasonable PCB for the isolation device of Coss: Connect the series capacitor of the Hcur and Hpot terminals of LCR to the D terminal of DUT, connect the series capacitor of the Lcur and Lpot terminals of LCR to the S terminal of DUT, connect the HI terminal of MCU to the D terminal of DUT, connect the LO terminal of MCU to the S terminal of DUT, and short-circuit the G and S terminals. S2: Connect the terminals of LCR and MCU to the Coss test system respectively: Connect the four terminals of LCR (Hcur, Hpot, Lcur, and Lpot) and the HI and LO terminals of MCU to the Coss isolation device via coaxial cable. S3: Insert the DUT into the test socket: Insert the DUT into the test socket to prepare for the subsequent Coss test; S4: Start Coss Test: The experimental environment required for leakage current testing has been set up. Perform Coss testing on the DUT. Before testing, short-circuit the G and S terminals of the DUT and perform open-circuit and short-circuit calibration on the LCR meter to eliminate the influence of parasitic parameters; S5: Apply high voltage to the D terminal of the DUT and scan the Coss curve: With the LCR test frequency fixed, change the high voltage value output by the MCU to change the Crss test conditions, and perform Cgd test on the DUT under different Vds to generate the Coss test curve. S6: The Coss test of the DUT is complete.

2. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 1, characterized in that: The test system in step S2 includes an SMU, an LCR, an isolation device, and a DUT. The SMU is a high-voltage source meter, the LCR is an inductance, capacitance, and resistance meter, and the DUT is the semiconductor switching device under test.

3. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 2, characterized in that: The SMU provides a DC high voltage Vds to the DUT. The SMU interface includes a HI terminal and a LO terminal. The HI terminal is the positive terminal of the SMU and outputs a high voltage signal. The HI terminal is connected to the SMU through an isolation device. This isolation device prevents the high-frequency AC signal of the LCR meter from reaching the HI terminal of the MCU, thus preventing the high voltage signal of the SMU from affecting the LCR meter. The LO terminal is the negative terminal of the SMU and is connected to the S terminal of the DUT through an isolation device, providing a high voltage test circuit for the D terminal and S terminal of the DUT.

4. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 2, characterized in that: The LCR measures Coss using a high-frequency AC signal, where Coss = Cgd + Cds. The LCR interface includes Hcur, Hpot, Lcur, and Lpot. After isolation, Hcur, Hpot, Lcur, and Lpot are applied to the D and S terminals of the DUT to measure the Coss parameter. Hcur is for high-side current drive, Hpot is for high-side voltage detection, Lcur is for low-side current drive, and Lpot is for low-side voltage detection.

5. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 2, characterized in that: The Hpot and Lpot ports apply high-frequency AC signals to the D and S terminals of the DUT and detect the actual voltage at the D and S terminals, which is one of the important parameters for calculating Coss. The Hcur and Lcur ports are used to measure the AC current at the D and S terminals, which is also one of the important parameters for calculating Coss.

6. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 1, characterized in that: The isolation device's inputs are the Hcur, Hpot, Lcur, and Lpot terminals of the LCR meter, and the HI and LO terminals of the MCU meter. Its outputs are the high-frequency signal obtained by combining Hcur and Hpot and passing them through a capacitor, the signal obtained by combining Lcur and Lpot, the high-voltage signal obtained by passing the HI terminal through an inductor and a resistor, and the signal obtained by the LO terminal.

7. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 2, characterized in that: The three pins of the DUT are D, G, and S. The D pin is the drain, the G pin is the gate, and the S pin is the source. The D pin is connected to the Hpot and Hcur pins of the LCR meter through an isolation device and a series capacitor. The D pin is connected to the HI pin of the SMU through a series inductor. The G and S pins are shorted. At this time, the LCR meter measures the value of Cgd + Cds, i.e., Coss. The S pin is connected to the LO pin of the SMU through an isolation device.

8. The method for designing an isolation device for capacitive characteristic testing of high-voltage semiconductor switching devices according to claim 7, characterized in that: The SMU applies a high voltage Vds between the D and S terminals of the DUT. The Hcur and Hpot of the LCR are connected to the D terminal of the DUT, and the Lcur and Lpot are connected to the S terminal of the DUT. The S terminal and G terminal are shorted. The test current is divided into two parts: one part returns to the LCR through Cgd, and the other part returns to the LCR through Cds, which is the value of Coss.

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