A multi-platform cooperative testing method and system for electronic device testing

Abstract

This application provides a multi-platform collaborative testing method and system for electronic device testing, belonging to the field of multi-platform collaborative testing technology. The method includes: responding to a test failure signal generated by an electrical testing platform, triggering an optical testing platform to identify a suspected defect feature region; locating the stress application period associated with the failure timing marker based on the failure timing marker recorded by the electrical testing platform and the imaging timing marker recorded by the optical testing platform; calculating the corresponding slip trajectory vector based on the probe pose data sequence within the stress application period; and identifying the effective defect region based on the slip trajectory vector and the morphological centerline of the suspected defect feature region; and determining the confidence level of the test failure signal based on the effective defect region and the failure pin indicated by the test failure signal. The technical solution provided by this application can perform accurate cross-platform collaborative testing of electronic devices despite interference artifacts introduced during the testing process itself.

Description

Technical Field

[0001] This application relates to the field of multi-platform collaborative testing technology, and more specifically, to a multi-platform collaborative testing method and system for testing electronic devices. Background Technology

[0002] In electronic device testing, as integrated circuits and microsystems evolve towards higher density and miniaturization, single testing platforms are no longer sufficient to meet the demands of comprehensive quality control. Automated optical inspection relies on surface morphology but cannot detect internal defects; X-ray inspection can see through packaging but is insensitive to electrical performance anomalies; and while electrical performance testing can accurately locate parameter drift, it lacks spatial positioning capabilities. Multi-platform collaborative testing technology has emerged to address this need. Through spatiotemporal registration and feature-level fusion of multi-source heterogeneous sensor information, it organically integrates multimodal data such as visual, X-ray, infrared thermal imaging, and electrical parameters, effectively breaking down the barriers of single-modal information and providing more complete criteria for fault tracing and lifespan prediction.

[0003] In existing multi-platform collaborative testing of electronic devices, the main approach is to decompose complex testing tasks according to functional or structural dimensions and execute them in parallel on heterogeneous platforms such as automated testing equipment, five-axis vision systems, and boundary scanning. Each platform achieves microsecond-level action synchronization through a high-precision master control clock and preset trigger signals. After independently acquiring heterogeneous data from multiple sources such as electrical signals and optical images, the host system performs spatiotemporal alignment and comprehensive correlation analysis, ultimately merging the data to form a comprehensive assessment of device performance and defects. However, in multi-platform collaborative testing of electronic devices, when the probe station applies electrical stress to the device under test for parameter testing, the contact between the probe and the pin under test is not ideal. At the moment the test excitation is applied, due to the probe's slight mechanical overshoot, the micro-vibration of the device stage, or the instantaneous expansion of the material caused by the electrothermal effect, the probe will produce micron-level dynamic slippage on the pin surface. This slippage often creates scratch marks on the pin plating along the slippage direction, exhibiting a gradually deformed shape with a darker head and a shallower tail. Since the morphology of such marks is highly similar to some real physical defects, when the optical inspection platform is subsequently triggered by the test failure signal to perform failure localization imaging, the optical inspection platform is very likely to mistakenly fuse these interference artifacts generated by the electrical testing process itself into real physical defects of the electronic device, thus leading to misjudgment of the cross-platform collaborative testing and diagnosis of electronic devices. Therefore, how to perform accurate cross-platform collaborative testing of electronic devices under the interference artifacts introduced by the testing process itself has become a difficult problem for the industry. Summary of the Invention

[0004] This application provides a multi-platform collaborative testing method and system for electronic device testing, which can perform accurate cross-platform collaborative testing of electronic devices under the interference artifacts introduced by the testing process itself.

[0005] In a first aspect, this application provides a multi-platform collaborative testing method for electronic device testing, comprising the following steps:

[0006] The test failure signal generated by the electrical test platform after testing the electronic parameters of the electronic device triggers the optical inspection platform to identify the suspected defect feature area of ​​the electronic device.

[0007] The stress application period associated with the failure timing mark is located based on the failure timing mark recorded by the electrical testing platform and the imaging timing mark recorded by the optical detection platform;

[0008] The probe pose data sequence during the stress application period is extracted to calculate the probe's sliding trajectory vector on the surface of the tested pin. Based on the sliding trajectory vector and the topographic centerline of the suspected defect feature area, the effective defect area to remove sliding artifact interference is identified.

[0009] The confidence level of the test failure signal is determined based on the effective defect area and the failure pin indicated by the test failure signal.

[0010] In some embodiments, the triggering of the optical inspection platform to identify suspected defect feature areas of the electronic device in response to a test failure signal generated after the electrical testing platform performs electronic parameter testing on the electronic device specifically includes:

[0011] The test failure signal generated after the electrical test platform performs electrical parameter tests on electronic devices is analyzed, and the failure trigger time and failure pin number when the electrical parameters exceed the limit are extracted.

[0012] Based on the failure triggering time, a preset stress response pre-time is traced back to generate a detection triggering window covering the entire stress loading process;

[0013] At the termination edge of the detection trigger window, the multi-axis light source and multi-angle image sensor of the optical detection platform are invoked, and the multi-angle image sequence of the electronic device is acquired with the spatial coordinate area corresponding to the failure pin number as the field of view center.

[0014] Suspected defect feature regions were identified from the multi-angle image sequence.

[0015] In some embodiments, identifying suspected defect feature regions from the multi-angle image sequence specifically includes:

[0016] Perform differential operations on each frame of the multi-angle image sequence to generate a set of differential images that highlight surface morphological anomalies;

[0017] Edge closure detection based on gray-level gradient is performed on the differential image set to extract contour clusters that meet the geometric closure conditions of defects, and the region enclosed by the contour clusters is marked as a suspected defect feature region.

[0018] In some embodiments, locating the stress application period associated with the failure timing marker based on the failure timing marker recorded by the electrical testing platform and the imaging timing marker recorded by the optical detection platform specifically includes:

[0019] The loading and release times of each test excitation signal during the testing of electronic devices are extracted from the test logs recorded by the electrical testing platform, and a stress loading timing diagram with the failure timing mark as the cutoff point is generated.

[0020] Based on the imaging time sequence markers recorded by the optical detection platform, the median exposure time for multi-angle imaging is calculated;

[0021] Using the median exposure time as the alignment reference, a time-synchronized rigid translation correction is applied to the stress loading time series map to obtain a corrected stress loading time series map that is aligned with the multi-angle imaging on the time axis.

[0022] In the corrected stress loading timing map, the failure timing mark is used as the starting point for backtracking. The moment when the test excitation signal is first applied is searched in reverse along the time axis. The continuous time period between this moment and the failure timing mark is determined as the stress application period associated with the failure timing mark.

[0023] In some embodiments, extracting the probe pose data sequence during the stress application period specifically includes:

[0024] Acquire the real-time probe pose data stream recorded by the probe motion controller of the electrical test platform throughout the entire electrical parameter test process;

[0025] Using the start and end times of the stress application period as index boundaries, the real-time pose data stream of the probe is clipped by a time window to extract the probe pose data sequence.

[0026] In some embodiments, calculating the sliding trajectory vector of the probe on the surface of the tested pin specifically includes:

[0027] The three-dimensional spatial coordinates of the probe tip in the probe stage coordinate system are extracted frame by frame from the probe pose data sequence to generate a set of probe tip trajectory points;

[0028] Obtain the nominal contact center coordinates of the tested pin in the probe station coordinate system, and use the nominal contact center coordinates as the reference origin to convert each trajectory point in the probe end trajectory point set into an offset vector sequence relative to the reference origin.

[0029] The slip trajectory vectors of the probe and the tested pin during the stress application period are determined based on the offset vector sequence.

[0030] In some embodiments, the multi-angle imaging includes... , , and .

[0031] Secondly, this application provides a multi-platform collaborative testing system for electronic device testing, used to execute a multi-platform collaborative testing method for electronic device testing. The system includes:

[0032] The response module is used to respond to the test failure signal generated by the electrical test platform after performing electronic parameter tests on the electronic device, and trigger the optical inspection platform to identify the suspected defect feature area of ​​the electronic device.

[0033] The processing module is used to locate the stress application period associated with the failure timing mark based on the failure timing mark recorded by the electrical testing platform and the imaging timing mark recorded by the optical detection platform;

[0034] The processing module is also used to extract the probe pose data sequence during the stress application period, so as to calculate the sliding trajectory vector of the probe on the surface of the tested pin, and identify the effective defect area to remove the interference of sliding artifacts based on the sliding trajectory vector and the topographic center line of the suspected defect feature area.

[0035] The execution module is used to determine the confidence level of the generation of the test failure signal based on the effective defect area and the failure pin indicated by the test failure signal.

[0036] Thirdly, this application provides a computer device, the computer device including a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the above-described multi-platform collaborative testing method for electronic device testing.

[0037] Fourthly, this application provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the aforementioned multi-platform collaborative testing method for electronic device testing.

[0038] The technical solutions provided by the embodiments disclosed in this application have the following beneficial effects:

[0039] First, the optical inspection platform is triggered by the response test failure signal to perform multi-angle imaging and identify suspected defect feature areas. The failure event of electrical testing and the triggering time of optical inspection can be synchronized at the hardware level. The detection trigger window is generated by retrospectively tracing back the preset stress response pre-time based on the failure triggering time. This allows the acquisition time of optical imaging to accurately cover the key time period of physical defect initiation and expansion caused by electrical stress. This avoids the missed detection and misjudgment caused by defect morphology evolution or contamination due to time delay in traditional post-event offline inspection.

[0040] Secondly, by tracing back the stress application period based on the failure time sequence mark and the imaging time sequence mark and extracting the probe pose data sequence, the method achieves precise alignment of the electrical domain stress loading process and the mechanical domain probe movement process on a unified time axis by performing time-synchronized rigid translation correction between the excitation loading time in the electrical test log and the exposure median time in the optical detection. This ensures that the extracted probe pose data sequence strictly corresponds to the entire stress application process that led to failure, providing a kinematic input with precise time boundaries and no redundant data for subsequent calculation of the sliding trajectory vector between the probe and the tested pin, and eliminating the time mismatch error caused by the asynchronous clocks of the two platforms.

[0041] Then, based on the probe pose data sequence, the slip trajectory vector is calculated and combined with the topographic centerline to identify the effective defect area to remove artifact interference. For the first time, a cross-modal correlation analysis channel between probe mechanical motion data and optical defect topographic data is established. By converting the three-dimensional offset trajectory of the probe end into a slip trajectory vector time series with the nominal contact center as a reference, and performing normalized cross-correlation comparison with the topographic centerline extracted from the differential image in terms of extension direction and following amplitude, the quantitative distinction between probe slip artifacts and electrical stress-induced solid defects is realized. Among them, probe slip artifacts are reliably identified and eliminated due to the high consistency between the topographic extension direction and the main direction of probe slip, as well as the linear following of the projection length and offset amplitude. This effectively solves the technical problem that traditional methods that rely solely on image grayscale or geometric features cannot distinguish between mechanical artifacts and real defects, and significantly improves the specificity of defect detection.

[0042] Finally, the confidence determination of the generation of test failure signals is based on the effective defect area and the failed pin. This involves mapping the effective defect area after removing artifacts to the device layout coordinate space, using the defect area and the spatial distance between the defect and the failed pin as quantitative inputs, and outputting a normalized failure correlation confidence score through a pre-constructed failure correlation confidence model. This is used to make a threshold determination, realizing a closed loop from defect existence detection to defect causation determination. This avoids the subjectivity and inconsistency introduced by manual judgment of the causal relationship between defects and failures based on experience in traditional methods.

[0043] In summary, the technical solution provided in this application can perform accurate cross-platform collaborative testing of electronic devices despite interference artifacts introduced during the testing process itself. Attached Figure Description

[0044] Figure 1 This is an exemplary flowchart of a multi-platform collaborative testing method for electronic device testing, as shown in some embodiments of this application.

[0045] Figure 2 This is a schematic diagram of a suspected defect feature area according to some embodiments of this application;

[0046] Figure 3 This is a schematic diagram of the structure of a multi-platform collaborative testing system for electronic device testing, as shown in some embodiments of this application;

[0047] Figure 4 This is a schematic diagram of the structure of a computer device that implements a multi-platform collaborative testing method for electronic device testing, according to some embodiments of this application. Detailed Implementation

[0048] To better understand the technical solution of this application, the technical solution of this application will be described in detail below with reference to the accompanying drawings and specific embodiments.

[0049] refer to Figure 1 This figure is an exemplary flowchart of a multi-platform collaborative testing method for electronic device testing according to some embodiments of this application. The figure mainly includes the following steps:

[0050] In step S101, in response to the test failure signal generated by the electrical test platform after performing electronic parameter tests on the electronic device, the optical inspection platform is triggered to identify the suspected defect feature area of ​​the electronic device.

[0051] It should be noted that, in this application, the electrical testing platform refers to a semiconductor parameter testing system equipped with a multi-channel probe station and a precision source measurement unit. This electrical testing platform can apply timed electrical stress excitation to the pins of electronic devices under preset temperature and bias conditions and simultaneously acquire electrical parameter test data including voltage and current, and record a six-degree-of-freedom pose data stream of the probe end with a timestamp. In this application, the optical inspection platform refers to an automatic optical inspection system integrating a multi-axis programmable light source and a multi-angle image sensor. This optical inspection platform can respond to external trigger signals to acquire multi-angle image sequences of the surface of electronic devices within a specified time window with a specified spatial coordinate area as the field of view center, and record an imaging time sequence mark including the median exposure time for each frame of image.

[0052] In some embodiments, the following steps are used to trigger the optical inspection platform to identify suspected defect feature areas of the electronic device in response to a test failure signal generated after the electrical testing platform performs electronic parameter testing on the electronic device:

[0053] The test failure signal generated after the electrical test platform performs electrical parameter tests on electronic devices is analyzed, and the failure trigger time and failure pin number when the electrical parameters exceed the limit are extracted.

[0054] Based on the failure triggering time, a preset stress response pre-time is traced back to generate a detection triggering window covering the entire stress loading process;

[0055] At the termination edge of the detection trigger window, the multi-axis light source and multi-angle image sensor of the optical detection platform are invoked, and the multi-angle image sequence of the electronic device is acquired with the spatial coordinate area corresponding to the failure pin number as the field of view center.

[0056] Suspected defect feature regions were identified from the multi-angle image sequence.

[0057] It should be noted that, in this application, the test failure signal refers to an abnormal state identification signal automatically generated by the electrical testing platform after the electrical testing platform applies a preset time-sequential electrical stress excitation to a designated pin of an electronic device and collects the corresponding electrical parameter response. When the measured value of any electrical parameter such as voltage, current or resistance of the tested pin exceeds the preset qualified threshold range, the signal includes at least the failure trigger time and the failure pin number. This will not be elaborated further here.

[0058] Specifically, firstly, the test failure signal output by the electrical test platform is parsed to extract the failure trigger time and the failure pin number where the electrical parameters exceed the limit. The failure trigger time is the timestamp recorded by the semiconductor parameter tester when the measured value of the voltage or current of the tested pin of the electronic device first exceeds the upper or lower boundary of the qualified threshold range. The failure pin number is the pin identification number specified in the datasheet of the tested electronic device. For example, for a TO-247 packaged device, this number corresponds to pin 3 of the drain pin. Secondly, based on the failure trigger time, a preset stress response pre-set time is traced back to generate a detection trigger window. The stress response pre-set time... The stress response pre-set time is set based on the typical response delay required from the application of electrical stress to induce physical deformation of the material. For example, for thermally induced damage to silicon-based power devices under overpressure stress, this stress response pre-set time can be set to 50ms. The start time of the detection trigger window is the difference between the failure trigger time and this 50ms, and the end time is the failure trigger time itself. The stress response pre-set time can be set according to actual conditions and is not limited here. Then, at the end edge of the detection trigger window, the multi-axis light source and multi-angle image sensor of the optical detection platform are invoked. The multi-angle imaging includes 0°, 45°, 90°, and 135°. The multi-axis light source is invoked according to... , , , The preset angle sequence is lit up sequentially, and the multi-angle image sensor is driven to perform synchronous exposure with the spatial coordinate area corresponding to the failure pin number as the field of view center, and a set of multi-angle image sequences imaging at four angles is acquired. The multi-angle image sequence refers to a set containing multiple frames of angle images, wherein each frame of angle image contains an imaging time sequence mark of the median exposure time of the failure pin; finally, the suspected defect feature area is identified from the multi-angle image sequence.

[0059] In some embodiments, identifying suspected defect feature regions from the multi-angle image sequence is achieved using the following steps:

[0060] Perform differential operations on each frame of the multi-angle image sequence to generate a set of differential images that highlight surface morphological anomalies;

[0061] Edge closure detection based on gray-level gradient is performed on the differential image set to extract contour clusters that meet the geometric closure conditions of defects, and the region enclosed by the contour clusters is marked as a suspected defect feature region.

[0062] Specifically, firstly, each frame of the multi-angle image sequence is compared pixel-by-pixel with a pre-acquired defect-free reference image to generate a set of difference images. The defect-free reference image is a field-of-view image acquired with the same imaging parameters before electrical stress is applied to a defect-free electronic device of the same type. The set of difference images refers to the collection of difference images corresponding to all angles. Then, for each frame of the difference image set, the Canny edge detection operator is used for processing. That is, a 3×3 Gaussian kernel is used to smooth and filter the difference image to suppress noise. Then, the gray-level gradient magnitude and direction of each pixel in the filtered image are calculated. Next, non-maximum suppression is performed on the gradient magnitude image to refine the edges. Finally, edge connection is performed using a double-threshold hysteresis connection method. The high threshold is set to 60 and the low threshold is set to 30. Pixels with a gradient magnitude higher than 60 are marked as strong edge points, and pixels with a gradient magnitude between 30 and 60 and connected to the 8-neighborhood of strong edge points are marked as weak edge points. The remaining pixels are suppressed to obtain the edge binary map corresponding to the difference image. Then, the Suzuki-Abe contour retrieval algorithm is used to extract all closed contours from the edge binary map, and the roundness, area and average difference gray value inside each closed contour are calculated one by one. Closed contours with a roundness greater than 0.5, an area greater than 100 pixels and an average difference gray value greater than 40 are judged as contour clusters that meet the geometric closure conditions of defects. Finally, the corresponding pixel set of the region enclosed by the contour clusters that meet the conditions on the original difference image is marked as the suspected defect feature region.

[0063] refer to Figure 2 This figure is a schematic diagram of a suspected defect feature area according to some embodiments of this application. The outer solid frame in the figure is the electronic device body, and the area enclosed by the dashed line above it is the original imaging area corresponding to the image acquired by the optical inspection platform. The grid texture filling part in the original imaging area is the artifact interference area composed of device substrate reflection, imaging noise, etc. The irregular block filled by the oblique section line is the suspected defect feature area obtained by contour extraction and identification. This figure intuitively shows that after optical multi-angle imaging, only suspicious defect blocks with mixed background interference can be distinguished, and the real failure defect cannot be directly determined. It is used to correspond to the step of triggering optical platform imaging and initially identifying suspected defect feature areas in this method.

[0064] It should be noted that, in this application, the suspected defect feature area refers to the area enclosed by the abnormal contour that differs from the defect-free reference state on the surface of the electronic device under multi-angle illumination imaging. Identifying the suspected defect feature area can provide a candidate space range for further eliminating false defects caused by interference factors such as probe slip artifacts from the area and identifying effective defect areas that are causally related to electrical failures.

[0065] In step S102, the stress application period associated with the failure timing mark is located based on the failure timing mark recorded by the electrical testing platform and the imaging timing mark recorded by the optical detection platform.

[0066] In some embodiments, the stress application period associated with the failure timing marker is located based on the failure timing marker recorded by the electrical testing platform and the imaging timing marker recorded by the optical detection platform using the following steps:

[0067] The loading and release times of each test excitation signal during the testing of electronic devices are extracted from the test logs recorded by the electrical testing platform, and a stress loading timing diagram with the failure timing mark as the cutoff point is generated.

[0068] Based on the imaging time sequence markers recorded by the optical detection platform, the median exposure time for multi-angle imaging is calculated;

[0069] Using the median exposure time as the alignment reference, a time-synchronized rigid translation correction is applied to the stress loading time series map to obtain a corrected stress loading time series map that is aligned with the multi-angle imaging on the time axis.

[0070] In the corrected stress loading timing map, the failure timing mark is used as the starting point for backtracking. The moment when the test excitation signal is first applied is searched in reverse along the time axis. The continuous time period between this moment and the failure timing mark is determined as the stress application period associated with the failure timing mark.

[0071] Specifically, firstly, the loading and releasing times of each test excitation signal during the testing of electronic devices are extracted from the test log recorded by the electrical test platform. This test log is a text-formatted data table recorded by the semiconductor parameter tester at fixed time intervals during the test. Each line contains at least a timestamp field, an excitation channel identifier field, and an excitation amplitude field. The loading time is the timestamp corresponding to the midpoint of the rising edge when the excitation amplitude jumps from zero to the set bias level, and the releasing time is the timestamp corresponding to the midpoint of the falling edge when the excitation amplitude falls back to zero from the set bias level. For example, in a certain gate... In the extreme bias stress test, the output voltage of channel 2 jumps from 0V to 10V at the 5000th sampling point of the system clock and falls back to 0V at the 15000th sampling point. The loading time is the timestamp corresponding to the 5000th sampling point, and the release time is the timestamp corresponding to the 15000th sampling point. All extracted loading and release times are arranged chronologically, and a square wave stress loading time sequence is plotted with the loading time as the starting point and the corresponding release time as the ending point. Only the square wave segment with the earliest starting point and an ending point no later than the failure time marker is retained, resulting in a stress loading time sequence with the failure time as the starting point. The stress loading time sequence map is marked with the cutoff point, where the failure time sequence mark refers to the failure trigger time parsed from the test failure signal. Next, based on the imaging time sequence mark recorded by the optical detection platform, the exposure start time of the first frame image and the exposure end time of the last frame image in the multi-angle image sequence are extracted, and their arithmetic mean is taken as the median exposure time of the multi-angle imaging. Then, using this median exposure time as the alignment reference, the median exposure time is uniformly subtracted from each loading and release time in the stress loading time sequence map to achieve rigid translational correction for time synchronization, making the correction... The zero point of the corrected time is aligned with the median exposure time to obtain the corrected stress loading time sequence map. The corrected stress loading time sequence map refers to the stress loading time sequence map after time synchronization. Finally, in the corrected stress loading time sequence map, the failure time sequence mark is used as the backtracking starting point, and the search is performed point by point along the time axis in the past direction. When a certain loading time is detected for the first time, the search stops, and the continuous time period between the loading time and the failure time sequence mark is determined as the stress application period associated with the failure time sequence mark. During the stress application period, the electronic device is continuously subjected to electrical stress.

[0072] It should be noted that, in this application, the stress application period refers to the continuous time interval from the moment when the electrical stress that ultimately leads to the test failure signal is first applied to the electronic device during the electrical parameter testing process, to the moment when the electrical parameter exceeds the limit as recorded by the failure timing mark. Determining the stress application period can provide an accurate time interception boundary for subsequently extracting the pose data sequence between the probe and the tested pin of the electronic device within this period, and then calculating the sliding trajectory vector between the two, so as to ensure that the analyzed probe motion trajectory strictly corresponds in time to the stress loading process that causes the failure.

[0073] In step S103, the probe pose data sequence during the stress application period is extracted to calculate the probe's sliding trajectory vector on the surface of the tested pin, and the effective defect area for removing sliding artifact interference is identified based on the sliding trajectory vector and the topographic center line of the suspected defect feature area.

[0074] In some embodiments, the following steps are used to extract the probe pose data sequence during the stress application period to calculate the probe's sliding trajectory vector on the surface of the tested pin:

[0075] Acquire the real-time probe pose data stream recorded by the probe motion controller of the electrical test platform throughout the entire electrical parameter test process;

[0076] Using the start and end times of the stress application period as index boundaries, the real-time pose data stream of the probe is clipped by a time window to extract the probe pose data sequence.

[0077] Specifically, firstly, the real-time probe pose data stream recorded by the probe motion controller of the electrical testing platform throughout the entire electrical parameter testing process is acquired. This real-time probe pose data stream is a time-series data of the spatial state of the probe tip, collected and stored by the probe motion controller at a fixed sampling frequency. The sampling frequency is typically set to 1000Hz. Each data record contains at least one timestamp field with microsecond precision generated by the controller system clock, and a six-degree-of-freedom pose field of the probe tip, consisting of six degrees of freedom components: X-axis displacement, Y-axis displacement, Z-axis displacement, pitch angle, yaw angle, and roll angle. For example, a record might contain the content "timestamp:1623456789123456,x:12.345,y:8.901,z:5.432,pitch:0.012,yaw:-0.008,roll:0.003", which respectively represent the position of the probe tip in the X-direction of the probe stage coordinate system at that sampling time. The probe's displacement is 12.345 micrometers in the Y direction, 8.901 micrometers in the Z direction, and 5.432 micrometers in the Z direction. The pitch, yaw, and roll angles are 0.012 radians, -0.008 radians, and 0.003 radians, respectively. Then, using the start and end times of the stress application period as index boundaries, the real-time pose data stream of the probe is clipped using a time window. Specifically, a binary search method is used to locate the first record with a timestamp equal to the start time and the last record with a timestamp equal to the end time in the real-time pose data stream. If no record with exactly equal timestamps exists, the first record with a timestamp greater than the start time and the last record with a timestamp less than the end time are taken as replacements, respectively. Then, the first record, the last record, and all records in between are arranged in ascending order of timestamp. The probe pose data sequence consisting of all probe pose sampling points during the stress application period is extracted. The time interval between adjacent sampling points in this sequence is equal to the reciprocal of the fixed sampling frequency.

[0078] It should be noted that the probe pose data sequence in this application refers to the time sequence of the displacement of the probe tip relative to the origin of the probe stage coordinate system and the changes of the six degrees of freedom components (pitch angle, yaw angle, roll angle) around each coordinate axis with the sampling time during the stress application period. Since the mechanical stress applied by the probe to the tested pin during the electrical parameter testing process may cause a small slip or offset of the probe tip relative to the pin surface, it is impossible to directly obtain the quantitative data of this dynamic process by relying solely on electrical parameters or optical images. The probe pose data sequence provides the only direct measurement basis for reconstructing the actual motion trajectory of the probe tip, and can provide a complete time-varying displacement input for subsequent calculation of the slip trajectory vector between the probe and the tested pin of the electronic device. This allows the slip trajectory vector to characterize the continuous offset process of the probe from the stress application start time to the failure trigger time with the accuracy of sampling point by sampling point.

[0079] In some embodiments, the following steps are used to calculate the sliding trajectory vector of the probe on the surface of the tested pin:

[0080] The three-dimensional spatial coordinates of the probe tip in the probe stage coordinate system are extracted frame by frame from the probe pose data sequence to generate a set of probe tip trajectory points;

[0081] Obtain the nominal contact center coordinates of the tested pin in the probe station coordinate system, and use the nominal contact center coordinates as the reference origin to convert each trajectory point in the probe end trajectory point set into an offset vector sequence relative to the reference origin.

[0082] The slip trajectory vectors of the probe and the tested pin during the stress application period are determined based on the offset vector sequence.

[0083] Specifically, firstly, the three-dimensional spatial coordinates of the probe tip in the probe stage coordinate system are extracted frame by frame from the probe pose data sequence to generate a probe tip trajectory point set. The specific operation of frame-by-frame extraction involves traversing each pose record in the probe pose data sequence, reading the values ​​of the X-axis displacement, Y-axis displacement, and Z-axis displacement fields, and combining these three values ​​into a three-dimensional spatial coordinate point. The three-dimensional spatial coordinate points corresponding to all sampling times within the stress application period are then arranged in ascending order of timestamps to form the probe tip trajectory point set. This probe tip trajectory point set represents the spatial motion path of the probe tip in the probe stage coordinate system during the stress application period. Secondly, the nominal contact center coordinates of the tested pin in the probe stage coordinate system are obtained. These nominal contact center coordinates are predetermined through a calibration process performed before the electrical parameter test begins. The calibration process specifically involves manipulating the probe stage to bring the probe tip close to the surface of the tested pin in 1-micron increments. When the contact resistance between the probe and the tested pin first drops to a preset threshold, such as 0.5 ohms... At the time of application, the spatial coordinates of the current probe tip are recorded as the nominal contact center coordinates. The nominal contact center coordinates refer to the ideal electrical contact spatial coordinates formed by the X, Y, and Z axis displacements of the probe tip in the probe stage coordinate system recorded by the probe motion controller. Using the nominal contact center coordinates as the reference origin, the coordinates of each trajectory point in the probe tip trajectory point set are subtracted from the reference origin coordinates one by one, and converted into an offset vector sequence relative to the reference origin. Finally, the tangential offset components of each trajectory point in the direction parallel to the surface of the tested pin are extracted from the offset vector sequence. The tangential offset components are obtained by projecting and decomposing the offset vectors on the local plane normal vector direction of the tested pin surface. Then, the magnitudes of the tangential offset components at each sampling time are arranged in the order of the timestamps recorded in the probe pose data sequence to form a time series with time as the independent variable and tangential offset magnitude as the dependent variable. This time series is determined as the sliding trajectory vector of the probe and the tested pin during the stress application period.

[0084] It should be noted that the slip trajectory vector in this application refers to the degree of deviation of the probe tip from the nominal contact position of the pin under test at each sampling moment between the stress application start time and the failure trigger time. Unlike the existing technology that relies on optical image post-processing for static offset measurement or single-direction displacement monitoring, this implementation constructs a relative offset vector sequence with the ideal contact point of the pin under test as the origin by associating the frame-by-frame spatial coordinate transformation of the probe pose data sequence with the nominal contact center coordinates based on the prior information of probe calibration. Instead of directly using the absolute coordinates of the probe for offset judgment, this eliminates the interference of the installation deviation between the probe station system coordinate system and the actual position of the device on the offset calculation.

[0085] In some embodiments, the morphological centerline of the suspected defect feature region is determined by the following steps:

[0086] The difference image corresponding to the suspected defect feature region is binarized and segmented to extract a binarized contour mask representing the boundary of the abnormal shape.

[0087] Morphological skeleton extraction is performed on the binarized contour mask to generate a connected skeleton curve with a single pixel width;

[0088] The continuous skeleton branches in the connected skeleton curve whose extension direction and the main offset direction of the sliding trajectory vector have an angle less than a preset angle threshold are determined as the topographic center line of the suspected defect feature region.

[0089] Specifically, firstly, the differential image corresponding to the suspected defect feature region is binarized and segmented. This differential image is the frame corresponding to the current suspected defect feature region from the differential image set generated from the multi-angle image sequence. The Otsu method is used to calculate the adaptive segmentation threshold of this differential image. Pixels with gray values ​​greater than this adaptive segmentation threshold are assigned a value of 255, and the remaining pixels are assigned a value of 0, resulting in a binary contour mask representing the boundary of the abnormal shape. This binary contour mask is the binary image obtained after binarizing the differential image corresponding to the suspected defect feature region. It is used to represent the spatial distribution boundary between pixels with gray-level abrupt changes caused by surface morphology abnormalities and normal background pixels in the differential image. White pixels correspond to the abnormal shape region, and black pixels correspond to the normal background region. Then, morphological skeleton extraction is performed on the binary contour mask. The Zhang-Suen thinning algorithm is used to iteratively strip the boundary pixels of the binary contour mask. Each iteration includes the binarization of the frame. In the contour mask, all white pixels are judged for pixel connectivity and marked as deletable according to the 8-neighborhood mode. Pixels that meet the topology preservation condition are retained and pixels marked as deletable are removed. After multiple iterations, the process stops when the remaining pixels no longer change, resulting in a binary image containing only a single-pixel-width connected skeleton curve. The single-pixel-width connected skeleton curve refers to the topological connectivity structure of the abnormal shape region in the original binary contour mask that is preserved. Finally, the shape center line is extracted from the connected skeleton curve. Specifically, the main offset direction of the slip trajectory vector is first determined as the direction angle of the offset vector projected in the XY plane at the sampling time when the slip trajectory vector reaches its peak during the stress application period. Then, the 8-neighborhood connected domain traversal algorithm is used to calculate the direction angle of the line connecting adjacent skeleton points in each skeleton branch. Continuous skeleton branches with an angle difference between the direction angle and the main offset direction less than a preset angle threshold of 30 degrees are selected. The selected continuous skeleton branches are combined into the shape center line of the suspected defect feature region.

[0090] It should be noted that, in this application, the morphology centerline refers to the morphological abnormality extension axis within the suspected defect feature area that tends to be consistent with the main direction of probe slippage. The reason for determining the morphology centerline is that the suspected defect feature areas identified in the multi-angle image sequence acquired by the optical inspection platform may present as material peeling or ablation marks caused by solid defects, or as linear drag artifacts generated during probe slippage. The two are difficult to distinguish directly in terms of image grayscale features. However, the morphological extension direction of solid defects is usually random, while the morphological extension direction of probe slippage artifacts is highly consistent with the probe movement direction. Therefore, it is necessary to extract the centerline feature representing the geometric extension direction from the suspected defect feature area to provide a geometric basis for subsequent comparison of the extension direction of the morphology centerline with the main offset direction of the slippage trajectory vector. This allows the system to determine whether the suspected defect feature area is caused by probe slippage artifacts based on directional correlation, and then remove it from the effective defect area, retaining only the real defect area composed of solid defects.

[0091] In some embodiments, identifying the effective defect region for removing slip artifact interference based on the slip trajectory vector and the topographic centerline of the suspected defect feature region is achieved through the following steps:

[0092] During the stress application period, the moment when the sliding trajectory vector reaches its peak value is taken as the alignment point. The peak offset vector corresponding to the moment is extracted from the trajectory point set at the end of the probe, and the direction of the peak offset vector is determined as the main sliding direction of the probe.

[0093] Project the topography centerline along the main sliding direction of the probe, calculate the projection length of the topography centerline along the main sliding direction of the probe, and simultaneously calculate the aspect ratio of the topography centerline;

[0094] The first time series of the projection length of the topographic center line on the main direction of probe sliding, which changes with the sampling time, is normalized and cross-correlated with the second time series of the sliding trajectory vector, which changes with the same time axis, to obtain the sliding follow correlation coefficient. When the sliding follow correlation coefficient exceeds a preset follow threshold and the aspect ratio exceeds a preset aspect ratio threshold, the local suspected defect feature area associated with the topographic center line is determined to be composed of probe sliding artifacts and is removed.

[0095] The regions retained after removing suspected defect features are identified as valid defect regions for removing slip artifact interference.

[0096] It should be noted that the slip artifact interference in this application refers to the micron-level dynamic slippage that occurs between the test probe and the device pin in a charged contact state during the stress application period of the electrical test. This charged micro-cutting process will cause secondary damage morphology on the pin surface. When the optical inspection platform subsequently images, these surface morphology anomalies introduced by the test process itself will be highly similar in image features to the actual physical defects such as inherent cracks and defects of the device, thus forming interfering artifacts and confusing the determination of the true source of the test failure signal.

[0097] Specifically, firstly, using the moment when the sliding trajectory vector reaches its peak value during the stress application period as the alignment point, the peak moment is located by searching the maximum value of the sliding trajectory vector time series. Then, the offset vector corresponding to this peak moment is extracted from the trajectory point set at the probe tip. The offset vector is the vector formed by the difference in displacement in the X, Y, and Z directions relative to the nominal contact center coordinates of the tested pin. The extracted offset vector is determined as the peak offset vector, and the two-dimensional direction angle projected onto the XY plane by this peak offset vector is taken as the main direction of probe sliding. The main direction of probe sliding refers to the direction at which the probe tip reaches its maximum offset value. The main sliding direction angle in the XY plane parallel to the surface of the probe pin is determined. Next, the topography centerline is projected along the main sliding direction of the probe. Specifically, the coordinates of each skeleton point on the topography centerline are sequentially projected onto a straight line along the main sliding direction of the probe. The difference between the maximum and minimum coordinates of the projected points on this straight line is taken as the projection length of the topography centerline along the main sliding direction of the probe. This projection length characterizes the extension span of the topography centerline along the probe sliding direction. Simultaneously, the aspect ratio of the topography centerline is calculated. The aspect ratio is defined as the ratio of the projection length of the topography centerline along the main sliding direction of the probe to the projection width perpendicular to the main sliding direction of the probe. The projection width in the direction is obtained by projecting each skeleton point on the topography centerline onto a straight line perpendicular to the main direction of probe sliding and taking the difference between the maximum and minimum projection coordinates. For example, if the vertical projection width is 2.1 micrometers, then the aspect ratio is 18.5 / 2.1≈8.81. A first time series showing the projection length of the topography centerline along the main direction of probe sliding changing with the sampling time is compared with a second time series showing the sliding trajectory vector changing with the same time axis. A normalized cross-correlation operation is then performed to calculate the sliding following correlation coefficient. The specific steps of the normalized cross-correlation operation are to first subtract the first time series and the second time series respectively... The mean of each sequence is removed to achieve zero-mean processing. Then, the values ​​of the first and second time series after zero-mean processing are multiplied point by point at the same sampling time and summed. The summation result is divided by the product of the standard deviations of the first and second time series to obtain the sliding follower correlation coefficient with a value between -1 and 1. The sliding follower correlation coefficient is used to quantify the linearity between the extension length of the topography centerline along the main sliding direction of the probe and the actual displacement amplitude of the probe, with a value between -1 and 1. Finally, when the sliding follower correlation coefficient exceeds the preset follower threshold of 0.8 and the aspect ratio exceeds the preset aspect ratio threshold of 5.At time 0, the local suspected defect feature area associated with the center line of the morphology is determined to be composed of probe slip artifacts and is removed from the suspected defect feature area. The preset following threshold and preset aspect ratio threshold are empirical values ​​determined through statistical analysis of historical test data or set based on expert knowledge; no specific limitations are imposed here. The preset following threshold refers to the lower limit of the correlation coefficient used to distinguish between probe slip artifacts and solid defects, and the preset aspect ratio threshold refers to the lower limit of the aspect ratio used to distinguish between linear slip artifacts and equiaxed solid defects. Probe slip artifacts refer to the elongated linear false defect traces formed in multi-angle optical images due to mechanical sliding of the probe tip relative to the surface of the tested pin during the application of electrical stress. Finally, the areas in the suspected defect feature area that are not marked as probe slip artifacts after the above removal operation are identified as valid defect areas.

[0098] It should be noted that the effective defect area in this application refers to the area excluding image artifacts caused by probe mechanical slippage, and only including the area corresponding to physical defects caused by electrical stress. This differs from the single-modal analysis path in existing technologies that relies solely on the geometric or grayscale features of the optical image itself to determine the authenticity of defects. This implementation establishes a cross-modal correlation determination mechanism between the probe pose data of the optical testing platform and the defect morphology features of the optical detection platform. It performs time-aligned and spatially normalized cross-correlation operations on the slip trajectory vector (mechanical domain data originating from the probe motion controller) and the morphology centerline (optical domain data originating from image processing), rather than relying solely on isolated determinations based on texture, shape, and other features within the image domain. This approach enables the causal chain between probe slippage (a mechanical behavior) and image artifacts to be quantified using the slippage-following correlation coefficient. Furthermore, this implementation introduces a dual-criteria joint decision-making logic using aspect ratio and slippage-following correlation coefficient. The aspect ratio is used to constrain the elongated linear morphological properties of artifacts, while the slippage-following correlation coefficient is used to constrain the linear following properties of artifact extension and probe offset. The two criteria jointly screen suspected defect feature regions from two orthogonal dimensions: morphological geometric stretching and cross-modal motion following. This avoids the risk of misjudging short solid defects as slippage artifacts or missing equiaxial slippage artifacts as solid defects in boundary cases using a single criterion, thus achieving a highly reliable distinction between probe slippage artifacts and solid defects.

[0099] In step S104, a confidence determination is made on the generation of the test failure signal based on the effective defect area and the failure pin indicated by the test failure signal.

[0100] In some embodiments, the confidence determination of the generation of the test failure signal based on the effective defect area and the failure pin indicated by the test failure signal is achieved by the following steps:

[0101] Map the effective defect region to the layout coordinate space of the electronic device, and calculate the spatial distance between the geometric center of the effective defect region and the nominal position of the failed pin in the layout coordinate space;

[0102] The area of ​​the effective defect region and the spatial distance are input into a pre-built failure association confidence model, and the failure association confidence level is output.

[0103] The failure association confidence level is compared with a preset confidence threshold. If the failure association confidence level exceeds the preset confidence threshold, the test failure signal is determined to be generated by the physical defect corresponding to the effective defect area; otherwise, the test failure signal is determined to be generated by a non-defect factor.

[0104] Specifically, firstly, the effective defect area is mapped to the layout coordinate space of the electronic device. The layout coordinate space refers to the two-dimensional Cartesian coordinate system defined in the electronic device design file with the chip origin as the reference. The mapping operation is achieved by applying a pre-calibrated affine transformation matrix between the pixel coordinate system acquired by the optical inspection platform and the layout coordinate space to the pixel coordinates of each pixel in the effective defect area. This affine transformation matrix is ​​a 2×3 matrix, and its six parameters are determined by placing a standard calibration board within the field of view of the optical inspection platform before electrical parameter testing and extracting at least three sets of non-collinear pixel coordinates and corresponding layout coordinate point pairs. Then, the minimum... Solving the overdetermined linear equations using the square method yields the following: For example, the coordinates of three marker points on the calibration board in the pixel coordinate system are (100, 200), (400, 200), and (250, 450), respectively, and their corresponding coordinates in the layout coordinate space are (0.5, 1.0), (2.0, 1.0), and (1.25, 2.25), respectively. Substituting these coordinates into the equations, we obtain the affine transformation matrix parameters. Multiplying the pixel coordinates within the effective defect area by the affine transformation matrix yields the corresponding coordinates of each pixel in the layout coordinate space. After mapping, we calculate the geometric center of the effective defect area and the nominal coordinates of the failed pin in the layout coordinate space. The spatial distance between locations is calculated by taking the average of the X and Y coordinates of all pixels in the effective defect area within the layout coordinate space. The nominal location of the failed pin is defined as the coordinates of the geometric center of the metal wire bonding area corresponding to the failed pin number in the electronic device layout design file within the layout coordinate space. The spatial distance is defined as the Euclidean distance between the geometric center and the nominal location. Then, the area of ​​the effective defect area and the aforementioned spatial distance are input into a pre-constructed failure association confidence model, which outputs the failure association confidence score. The area of ​​the effective defect area is calculated by statistically analyzing the effective defect area within the layout coordinate space. The failure association confidence model is obtained by multiplying the total number of pixels by the physical area corresponding to each pixel in the layout coordinate space. The model is a binary classification model trained using a logistic regression algorithm. The pre-construction process involves collecting multiple sets of sample data from historical tests, each containing the area of ​​a defect region, the spatial distance between the defect region and the corresponding failed pin, and a binary label indicating whether the defect is a cause of failure. The total number of sample data sets is no less than 500 sets, and the ratio of positive to negative samples is between 1:3 and 3:1. The area and spatial distance are used as two features input to the Sigmoid function of the logistic regression model. In, where z= ×Area+ × Spatial distance + , , , The model weight parameters are obtained by iteratively optimizing the maximum likelihood estimation method on the labeled sample set until the log loss function converges. For example, the model weight parameters are determined as follows after training. =-2.3、 =0.015、 =-0.08, where the Sigmoid function The output value is the failure association confidence score, which represents the probability estimate that the defect is the direct cause of the test failure given the known area and spatial distance of the valid defect region. Finally, the failure association confidence score is compared with a preset confidence threshold. The preset confidence threshold is the confidence threshold value that maximizes the F1 score, selected based on the precision-recall curve of the model on the validation set. For example, if the selected preset confidence threshold is 0.5, then when the failure association confidence score exceeds 0.5, the test failure signal is determined to be caused by the physical defect corresponding to the valid defect region. When the failure association confidence score is less than or equal to 0.5, the test failure signal is determined to be caused by non-defect factors, including factors unrelated to physical defects of electronic devices, such as poor contact of test probes, electromagnetic interference in the test environment, or measurement noise of the electrical test platform itself.

[0105] Furthermore, in another aspect of this application, in some embodiments, this application provides a multi-platform collaborative testing system for electronic device testing, referencing... Figure 3 The figure is a schematic diagram of the structure of a multi-platform collaborative testing system for electronic device testing according to some embodiments of this application. The multi-platform collaborative testing system for electronic device testing includes: a response module 201, a processing module 202, and an execution module 203, which are described below:

[0106] The response module 201 in this application is mainly used to respond to the test failure signal generated by the electrical test platform after performing electronic parameter tests on the electronic device, and trigger the optical detection platform to identify the suspected defect feature area of ​​the electronic device.

[0107] Processing module 202, in this application, is mainly used to locate the stress application period associated with the failure time sequence mark based on the failure time sequence mark recorded by the electrical testing platform and the imaging time sequence mark recorded by the optical detection platform;

[0108] The processing module 202 is also used to extract the probe pose data sequence during the stress application period, so as to calculate the sliding trajectory vector of the probe on the surface of the tested pin, and identify the effective defect area to remove the interference of sliding artifacts based on the sliding trajectory vector and the topographic center line of the suspected defect feature area.

[0109] The execution module 203 in this application is mainly used to determine the confidence of the generation of the test failure signal based on the effective defect area and the failure pin indicated by the test failure signal.

[0110] In addition, this application also provides a computer device, the computer device including a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the above-described multi-platform collaborative testing method for electronic device testing.

[0111] In some embodiments, reference Figure 4 The figure is a schematic diagram of the structure of a computer device implementing a multi-platform collaborative testing method for electronic device testing according to some embodiments of this application. The multi-platform collaborative testing method for electronic device testing in the above embodiments can... Figure 4 The computer device shown is used to implement this, and the computer device includes at least one processor 301, a communication bus 302, a memory 303, and at least one communication interface 304.

[0112] The processor 301 can be a general-purpose central processing unit (CPU), an application-specific integrated circuit (ASIC), or one or more multi-platform collaborative testing methods for controlling the execution of electronic device testing in this application.

[0113] The communication bus 302 can be used to transmit information between the aforementioned components.

[0114] The memory 303 may be a read-only memory (ROM) or other type of static storage device capable of storing static information and instructions, random access memory (RAM) or other type of dynamic storage device capable of storing information and instructions, or electrically erasable programmable read-only memory (EEPROM), compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disks or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto. The memory 303 may exist independently and be connected to the processor 301 via the communication bus 302. The memory 303 may also be integrated with the processor 301.

[0115] The memory 303 stores program code for executing the scheme of this application, and its execution is controlled by the processor 301. The processor 301 executes the program code stored in the memory 303. The program code may include one or more software modules. In the above embodiments, the determination of the multi-platform collaborative testing method for electronic device testing can be achieved by the processor 301 and one or more software modules in the program code in the memory 303.

[0116] Communication interface 304 uses any transceiver-like device for communicating with other devices or communication networks, such as Ethernet, radio access network (RAN), wireless local area networks (WLAN), etc.

[0117] In a specific implementation, as one example, a computer device may include multiple processors, each of which may be a single-core (single-CPU) processor or a multi-core (multi-CPU) processor. Here, a processor may refer to one or more devices, circuits, and / or processing cores used to process data (e.g., computer program instructions).

[0118] The aforementioned computer device can be a general-purpose computer device or a special-purpose computer device. In specific implementations, the computer device can be a desktop computer, a portable computer, a network server, a handheld digital assistant (PDA), a mobile phone, a tablet computer, a wireless terminal device, a communication device, or an embedded device. This application does not limit the type of computer device.

[0119] In addition, this application also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the above-described multi-platform collaborative testing method for electronic device testing.

[0120] Although preferred embodiments of this application have been described, those skilled in the art, once they have learned the basic inventive concept, can make other changes and modifications to these embodiments.

[0121] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application.

Claims

1. A multi-platform collaborative testing method for electronic device testing, characterized in that, Includes the following steps: The test failure signal generated by the electrical test platform after testing the electronic parameters of the electronic device triggers the optical inspection platform to identify the suspected defect feature area of ​​the electronic device. The stress application period associated with the failure timing mark is located based on the failure timing mark recorded by the electrical testing platform and the imaging timing mark recorded by the optical detection platform; The probe pose data sequence during the stress application period is extracted to calculate the probe's sliding trajectory vector on the surface of the tested pin. Based on the sliding trajectory vector and the topographic centerline of the suspected defect feature area, the effective defect area to remove sliding artifact interference is identified. The confidence level of the test failure signal is determined based on the effective defect area and the failure pin indicated by the test failure signal.

2. The method as described in claim 1, characterized in that, The test failure signal generated by the electrical testing platform after testing the electronic parameters of the electronic device triggers the optical inspection platform to identify the suspected defect feature areas of the electronic device, specifically including: The test failure signal generated after the electrical test platform performs electrical parameter tests on electronic devices is analyzed, and the failure trigger time and failure pin number when the electrical parameters exceed the limit are extracted. Based on the failure triggering time, a preset stress response pre-time is traced back to generate a detection triggering window covering the entire stress loading process; At the termination edge of the detection trigger window, the multi-axis light source and multi-angle image sensor of the optical detection platform are invoked, and the multi-angle image sequence of the electronic device is acquired with the spatial coordinate area corresponding to the failure pin number as the field of view center. Suspected defect feature regions were identified from the multi-angle image sequence.

3. The method as described in claim 2, characterized in that, Identifying suspected defect feature regions from the multi-angle image sequence specifically includes: Perform differential operations on each frame of the multi-angle image sequence to generate a set of differential images that highlight surface morphological anomalies; Edge closure detection based on gray-level gradient is performed on the differential image set to extract contour clusters that meet the geometric closure conditions of defects, and the region enclosed by the contour clusters is marked as a suspected defect feature region.

4. The method as described in claim 1, characterized in that, The stress application period associated with the failure time sequence marker is located based on the failure time sequence marker recorded by the electrical testing platform and the imaging time sequence marker recorded by the optical detection platform. Specifically, this includes: The loading and release times of each test excitation signal during the testing of electronic devices are extracted from the test logs recorded by the electrical testing platform, and a stress loading timing diagram with the failure timing mark as the cutoff point is generated. Based on the imaging time sequence markers recorded by the optical detection platform, the median exposure time for multi-angle imaging is calculated; Using the median exposure time as the alignment reference, a time-synchronized rigid translation correction is applied to the stress loading time series map to obtain a corrected stress loading time series map that is aligned with the multi-angle imaging on the time axis. In the corrected stress loading timing map, the failure timing mark is used as the starting point for backtracking. The moment when the test excitation signal is first applied is searched in reverse along the time axis. The continuous time period between this moment and the failure timing mark is determined as the stress application period associated with the failure timing mark.

5. The method as described in claim 1, characterized in that, Extracting the probe pose data sequence during the stress application period specifically includes: Acquire the real-time probe pose data stream recorded by the probe motion controller of the electrical test platform throughout the entire electrical parameter test process; Using the start and end times of the stress application period as index boundaries, the real-time pose data stream of the probe is clipped by a time window to extract the probe pose data sequence.

6. The method as described in claim 1, characterized in that, The calculation of the probe's sliding trajectory vector on the surface of the tested pin specifically includes: The three-dimensional spatial coordinates of the probe tip in the probe stage coordinate system are extracted frame by frame from the probe pose data sequence to generate a set of probe tip trajectory points; Obtain the nominal contact center coordinates of the tested pin in the probe station coordinate system, and use the nominal contact center coordinates as the reference origin to convert each trajectory point in the probe end trajectory point set into an offset vector sequence relative to the reference origin. The slip trajectory vectors of the probe and the tested pin during the stress application period are determined based on the offset vector sequence.

7. The method as described in claim 1, characterized in that, The multi-angle imaging includes multiple angles. , , and .

8. A multi-platform collaborative testing system for electronic device testing, used to execute the multi-platform collaborative testing method for electronic device testing as described in any one of claims 1 to 7, characterized in that, The system includes: The response module is used to respond to the test failure signal generated by the electrical test platform after performing electronic parameter tests on the electronic device, and trigger the optical inspection platform to identify the suspected defect feature area of ​​the electronic device. The processing module is used to locate the stress application period associated with the failure timing mark based on the failure timing mark recorded by the electrical testing platform and the imaging timing mark recorded by the optical detection platform; The processing module is also used to extract the probe pose data sequence during the stress application period, so as to calculate the sliding trajectory vector of the probe on the surface of the tested pin, and identify the effective defect area to remove the interference of sliding artifacts based on the sliding trajectory vector and the topographic center line of the suspected defect feature area. The execution module is used to determine the confidence level of the generation of the test failure signal based on the effective defect area and the failure pin indicated by the test failure signal.

9. A computer device, characterized in that, The computer device includes a memory and a processor, the memory storing code, and the processor being configured to acquire the code and execute the multi-platform collaborative testing method for electronic device testing as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by the processor, it implements the multi-platform collaborative testing method for electronic device testing as described in any one of claims 1 to 7.

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