A fault arc detection device and method based on voltage zero-crossing partitioning

Abstract

The application belongs to the technical field of low-voltage electrical apparatus, and specifically discloses a fault arc detection device and method based on voltage zero-crossing point partition. The device comprises: a voltage zero-crossing point detection circuit for detecting voltage zero-crossing points of a power supply signal at different time instants; a low-frequency sampling circuit for collecting a target low-frequency voltage signal in the power supply signal; a high-frequency sampling circuit for collecting a target high-frequency voltage signal in the power supply signal; and a signal processing unit for determining a corresponding power frequency cycle with each voltage zero-crossing point as a starting point, and dividing a phase range corresponding to each power frequency cycle into multiple phase intervals; and performing arc signal feature extraction and fusion analysis based on the target low-frequency voltage signal and the target high-frequency voltage signal in each phase interval to determine whether a fault arc exists in a target time period. The application can effectively improve the efficiency of fault arc detection and also improve the detection accuracy of fault arcs.

Description

Technical Field

[0001] This application belongs to the field of low-voltage electrical technology, specifically relating to the field of fault prediction and health management technology, and more specifically, relating to a fault arc detection device and method based on voltage zero-crossing point partitioning. Background Technology

[0002] With the continuous growth of electrical equipment and the proportion of new energy integration, fires caused by aging lines, poor contact, and arcing faults have become a prominent threat to public safety. Among these, arcing faults are the primary cause of high-frequency electrical fires, making their detection technology a key research direction for power distribution system safety, fault prediction, and health management.

[0003] Existing arc fault detection devices often employ a full-cycle statistical method that directly accumulates and analyzes all high-frequency pulses within the entire power frequency cycle when identifying arc faults. However, to reduce misjudgments caused by interference, this full-cycle statistical method requires smoothing filtering or averaging of statistical values ​​from a large number of consecutive cycles, leading to a delay in the arc fault determination result and ultimately resulting in low detection efficiency.

[0004] Therefore, how to better achieve fault arc detection has become a technical problem that the industry urgently needs to solve. Summary of the Invention

[0005] In view of the shortcomings of the existing technology, the purpose of this application is to better realize the detection of fault arcs, and to solve the problem that the existing full-cycle statistical methods have low detection efficiency due to the need to smooth and filter or average the statistical values ​​of a large number of consecutive cycles.

[0006] To achieve the above objectives, in a first aspect, this application provides a fault arc detection device based on voltage zero-crossing point partitioning, comprising: A signal processing unit, and a voltage zero-crossing detection circuit, a low-frequency sampling circuit, and a high-frequency sampling circuit respectively connected to the signal processing unit; The voltage zero-crossing detection circuit is used to detect the voltage zero-crossing point of the power supply signal at different times. The low-frequency sampling circuit is used to acquire the target low-frequency voltage signal in the power supply signal; The high-frequency sampling circuit is used to acquire the target high-frequency voltage signal in the power supply signal; The signal processing unit is used to determine the corresponding power frequency period starting from each of the voltage zero crossing points, and to divide the phase range corresponding to each power frequency period into multiple phase intervals; to perform arc signal feature extraction and fusion analysis based on the target low-frequency voltage signal and the target high-frequency voltage signal in each phase interval, and to determine whether there is a fault arc in the target time period; the target time period is determined based on a preset number of power frequency periods.

[0007] Optionally, the low-frequency sampling circuit includes a sampling resistor, a differential amplifier, and a low-pass filter connected in sequence; the low-pass filter is connected to the signal processing unit. The sampling resistor is used to sample the low-frequency current signal in the power supply signal and convert the low-frequency current signal into a low-frequency voltage signal. The differential amplifier is used to differentially amplify the low-frequency voltage signal and output a first amplified signal; The low-pass filter is used to filter and convert the first amplified signal to output the target low-frequency voltage signal.

[0008] Optionally, the high-frequency sampling circuit includes a high-frequency current sensor, a bandpass filter module, an amplification module, and a shaping module connected in sequence; the shaping module is connected to the signal processing unit. The high-frequency current sensor is used to couple the high-frequency current signal in the power supply signal and convert the high-frequency current signal into a high-frequency voltage signal. The bandpass filter module is used to extract the arc characteristic frequency band signal from the high-frequency voltage signal; The amplification module is used to amplify the amplitude of the arc characteristic frequency band signal and output a second amplified signal. The shaping module is used to convert the second amplified signal into a target high-frequency voltage signal.

[0009] Optionally, the voltage zero-crossing detection circuit includes a resistor divider network and a comparator connected in sequence, wherein the comparator is connected to the signal processing unit; The resistor divider network is used to divide the power supply signal and output a divided voltage signal; The comparator is used to output a square wave signal based on the voltage divider signal, so as to determine the zero-crossing point of the power supply signal at different times based on the square wave signal.

[0010] Secondly, this application provides a fault arc detection method applied to any of the aforementioned fault arc detection devices, comprising: S1, acquire the zero-crossing point of the power signal at different times, as well as the target low-frequency voltage signal and the target high-frequency voltage signal in the power signal; S2, using each of the voltage zero-crossing points as the starting point to determine the corresponding power frequency period, and dividing the phase range corresponding to each power frequency period into multiple phase intervals; S3, based on the target low-frequency voltage signal and target high-frequency voltage signal in each phase interval, perform arc signal feature extraction and fusion analysis to determine whether there is a fault arc in the target time period; the target time period is determined based on a preset number of power frequency cycles.

[0011] Optionally, S3 specifically includes: S31, based on the target low-frequency current signal corresponding to the target low-frequency voltage signal in each phase interval of each power frequency cycle, determine the load type corresponding to each power frequency cycle and the zero-sink depth corresponding to each phase interval, and based on the target high-frequency voltage signal in each phase interval, determine the comprehensive high-frequency characteristics corresponding to each phase interval. S32, determine the weight information corresponding to each phase interval according to the load type; S33, based on the zero-rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval of each power frequency cycle, perform fusion analysis to determine whether there is a fault arc in the target time period.

[0012] Optionally, the specific steps for determining the load type corresponding to each power frequency cycle include: Based on the target low-frequency current signal within each power frequency cycle, determine the power factor and total harmonic distortion rate; When it is determined that the power factor is not less than the power factor threshold and the total harmonic distortion rate is not greater than the first distortion threshold, the load type is determined to be a resistive load. or, When it is determined that the power factor is less than the power factor threshold, the total harmonic distortion rate is greater than the first distortion threshold but not greater than the second distortion threshold, and the current phase lags behind the voltage phase, the load type is determined to be an inductive load. or, When it is determined that the power factor is less than the power factor threshold, the total harmonic distortion rate is greater than the first distortion threshold but not greater than the second distortion threshold, and the current phase leads the voltage phase, the load type is determined to be a capacitive load. or, When the total harmonic distortion rate is determined to be greater than the second distortion threshold, the load type is determined to be a nonlinear load.

[0013] Optionally, the specific steps for determining the integrated high-frequency characteristics corresponding to each phase interval include: The total number of high-frequency pulses corresponding to each phase interval is determined based on the number of high-frequency pulse events that occur in the target high-frequency voltage signal within the corresponding time period of each phase interval. The number of high-frequency pulse clusters corresponding to each phase interval is determined based on the frequency of high-frequency pulse events that occur in the target high-frequency voltage signal within the corresponding time period of each phase interval. Based on the total number of high-frequency pulses and the number of high-frequency pulse clusters corresponding to each phase interval, the comprehensive high-frequency characteristics corresponding to each phase interval are determined.

[0014] Optionally, the specific steps for determining the zero-rest depth corresponding to each phase interval include: Based on the zero-crossing information of the target low-frequency current signal within each phase interval, multiple zero-crossing analysis windows corresponding to each phase interval are determined. Within each zero-current analysis window, the actual current deviation at each sampling point is calculated, and the maximum actual current deviation is selected as the zero-current depth corresponding to each zero-current analysis window. The zero-rest depth corresponding to each phase interval is obtained based on the maximum value in the zero-rest depth corresponding to each zero-rest analysis window.

[0015] Optionally, S33 specifically includes: For any power frequency cycle, the comprehensive score of the fault arc corresponding to any power frequency cycle is determined by weighted calculation using the zero rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval; Based on the load type and fault arc comprehensive score corresponding to any power frequency cycle, determine whether there is a suspected fault arc within any power frequency cycle; Determine the number of power frequency cycles in which a faulty arc is suspected within the target time period; If the number of power frequency cycles is determined to be not less than the target number threshold, then a fault arc is determined to exist within the target time period.

[0016] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: (1) The fault arc detection device and method based on voltage zero-crossing point partitioning provided in this application directly generates zero-crossing synchronization pulses by introducing a voltage zero-crossing point detection circuit to detect the voltage zero-crossing point of the power signal. Using the voltage zero-crossing point as a time-domain synchronization reference, the alignment of high and low frequency sampling data can be realized at the hardware end, eliminating the computational overhead and time drift caused by traditional software alignment methods. At the same time, by performing phase partitioning and weighted fusion on the power frequency cycle, a higher confidence judgment result can be obtained without long-period smoothing, and the response time is greatly compressed, which can effectively improve the efficiency of fault arc detection.

[0017] (2) By introducing the high and low frequency sampling channels with complete independence in physical structure, combined with the phase partitioning method, it can ensure the high extraction accuracy of low frequency current signals and the high sensitivity capture of high frequency arc signals, so that the arc features are concentrated in a few advantageous intervals, the signal differentiation is significantly improved, and the differentiated arc feature identification under the power frequency cycle phase partitioning is realized, which improves the detection accuracy of fault arcs.

[0018] (3) After phase partitioning, the dominant phase interval (such as the zero-crossing neighborhood of resistive load) that focuses on the characteristics of the arc is determined. The background noise is extremely low when the load is working normally in this interval, and even a small number of pulses generated by weak arc can significantly exceed the background level. At the same time, the weighting mechanism further compresses the noise contribution of non-dominant intervals, which is equivalent to obtaining a higher local signal-to-noise ratio in each dominant interval, thereby effectively improving the detection capability of low current arcs, effectively improving the detection sensitivity, and increasing the success rate of low current arc detection by 15% to 25%.

[0019] (4) After phase partitioning, the pulses generated by the interference load in its non-dominant region are given low weight, which effectively suppresses the interference contribution, while the pulses generated by the real arc in its dominant region are given high weight, maintaining high detection capability. Thus, the false judgment rate is greatly reduced without reducing the detection sensitivity, which can reduce the false action rate under typical interference load by 85% to 95%. Attached Figure Description

[0020] Figure 1 This is one of the structural schematic diagrams of the fault arc detection device based on voltage zero-crossing point partitioning provided in the embodiments of this application; Figure 2 This is a schematic diagram of the low-frequency sampling circuit in the fault arc detection device provided in this application embodiment; Figure 3 This is a schematic diagram of the high-frequency sampling circuit in the fault arc detection device provided in this application embodiment; Figure 4 This is a schematic diagram of the voltage zero-crossing detection circuit in the fault arc detection device provided in this application embodiment; Figure 5 This is the second schematic diagram of the fault arc detection device based on frequency band current acquisition provided in the embodiments of this application; Figure 6 This is a flowchart illustrating the fault arc detection method based on frequency band current acquisition provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the electronic device provided in the embodiments of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first amplified signal" and "second amplified signal," etc., are used to distinguish different amplified signals, not to describe a specific order of amplified signals.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] The embodiments of this application are described below with reference to the accompanying drawings.

[0025] Figure 1 This is one of the structural schematic diagrams of the fault arc detection device based on voltage zero-crossing point partitioning provided in the embodiments of this application, such as... Figure 1 As shown, the device includes: Signal processing unit 1, and low-frequency sampling circuit 2, high-frequency sampling circuit 3 and voltage zero-crossing detection circuit 4 respectively connected to signal processing unit 1; The voltage zero-crossing detection circuit 4 is used to detect the voltage zero-crossing point of the power supply signal at different times. Low-frequency sampling circuit 2 is used to acquire the target low-frequency voltage signal in the power supply signal; High-frequency sampling circuit 3 is used to acquire the target high-frequency voltage signal in the power supply signal; The signal processing unit 1 is used to determine the corresponding power frequency cycle with each voltage zero crossing point as the starting point, and divide the phase range corresponding to each power frequency cycle into multiple phase intervals; based on the target low-frequency voltage signal and the target high-frequency voltage signal in each phase interval, it performs arc signal feature extraction and fusion analysis to determine whether there is a fault arc in the target time period; the target time period is determined based on a preset number of power frequency cycles.

[0026] Specifically, the target low-frequency voltage signal described in the embodiments of this application refers to the low-frequency voltage signal obtained by acquisition and processing through a low-frequency sampling channel, which is used to capture the corresponding power frequency (50Hz) current waveform signal, i.e., the fundamental signal.

[0027] The target high-frequency voltage signal described in the embodiments of this application refers to the high-frequency arc signal captured by high-frequency sampling channel acquisition and processing, which may specifically be a high-frequency pulse digital signal.

[0028] The inventors discovered that a real electric arc simultaneously generates low-frequency current distortion (zero-wave phenomenon, with energy concentrated below 10kHz) and high-frequency radiation / conduction pulses (1-20MHz).

[0029] In the embodiments of this application, the fault arc detection device (AFDD) can consist of a signal processing unit, and a voltage zero-crossing detection circuit, a low-frequency sampling circuit, and a high-frequency sampling circuit respectively connected to the signal processing unit. The low-frequency sampling circuit constitutes a low-frequency sampling channel, and the high-frequency sampling circuit constitutes a high-frequency sampling channel. This introduces an asymmetric, frequency-segmented, and off-line deployed dual-channel current acquisition architecture for the low-frequency sampling circuit, which can separate and acquire the low-frequency and high-frequency signal characteristics of the arc signal on different physical channels.

[0030] It's important to note that a real electric arc simultaneously generates low-frequency current distortion and high-frequency radiated / conducted pulses. Therefore, by separately acquiring these two types of signal characteristics on different physical channels, the problem of low-frequency large signals suppressing high-frequency small signals can be avoided. Sampling resistors can be introduced into the low-frequency sampling channel, which possess excellent low-frequency linearity and phase characteristics, and are extremely low-cost. The high-frequency sampling channel is independently optimized, eliminating the need to handle large power frequency currents, and can utilize small magnetic cores, high-sensitivity sensors, and targeted signal conditioning circuits. By combining the low-frequency and high-frequency sampling circuits, high-precision power frequency information and highly sensitive high-frequency arc characteristics can be obtained simultaneously.

[0031] In the embodiments of this application, the introduced voltage zero-crossing detection circuit can convert the grid voltage signal into a hardware pulse signal V_zc aligned with the zero-crossing edge. This hardware pulse signal V_zc is connected to the signal processing unit and can be set to be triggered by both edges. It serves as a unified time-domain reference for the entire fault arc identification process, and is used to trigger subsequent phase interval division, time window reset, and timestamp alignment of multiple signals.

[0032] Based on the content of the above embodiments, as an optional embodiment, such as Figure 4 As shown, the voltage zero-crossing detection circuit 4 includes a resistor divider network 41 and a comparator 42 connected in sequence, and the comparator 42 is connected to the signal processing unit 1. The resistor divider network 41 is used to divide the power supply signal and output a divided voltage signal; Comparator 42 is used to output a square wave signal based on the voltage divider signal, so as to determine the zero-crossing point of the power supply signal at different times based on the square wave signal.

[0033] Specifically, in the embodiments of this application, the voltage zero-crossing detection circuit can be connected between the live wire (L line) and the neutral wire (N line) of the power grid to generate a hardware pulse signal V_zc synchronized with the voltage zero-crossing point of the power grid. The voltage zero-crossing detection circuit can be composed of a resistor divider network and a comparator connected in sequence. The resistor divider network can be composed of a high-voltage resistor R1 (e.g., 220kΩ / 1W) and a low-voltage resistor R2 (e.g., 1.1kΩ) connected in series between the L line and the N line; the voltage division ratio is approximately 200:1, which can be used to divide a 220V AC voltage to approximately 3.1V peak-to-peak value. This divided voltage signal can be adapted to the input range of the subsequent comparator. Here, the voltage division point is the connection node of R1 and R2.

[0034] The comparator's non-inverting input (+IN) can be connected to the aforementioned voltage divider point, while its inverting input (-IN) is connected to the reference voltage Vref (generated from VCC by a resistor divider, set to approximately 50mV, i.e., the zero-crossing threshold). Thus, after receiving the input voltage divider signal, the comparator outputs a square wave signal. The rising edge corresponds to the positive zero-crossing point (voltage changes from negative to positive), and the falling edge corresponds to the negative zero-crossing point (voltage changes from positive to negative). This allows the zero-crossing points of the power supply signal at different times to be determined, resulting in a simple and efficient circuit.

[0035] Here, the specific comparator model can be either TI TLV7031 (propagation delay 6μs) or LM393.

[0036] The voltage zero-crossing detection circuit in this embodiment is simple in structure and highly efficient in operation. When the AC signal crosses the 50mV threshold from negative to positive, the comparator output flips from low to high, generating a rising edge, corresponding to the positive zero-crossing of the voltage; when the AC signal crosses the 50mV threshold from positive to negative, the output flips to low, generating a falling edge, corresponding to the negative zero-crossing. This hardware pulse signal V_zc can be connected to the MCU's external interrupt pin EXT_INT0 as a unified time-domain reference for the entire identification process, used to trigger sampling, reset the time window, and align multiple signals.

[0037] Existing full-cycle statistical methods divide the cycle into fixed time windows. When the power grid frequency deviates from 50Hz, the actual length of the power frequency cycle changes (approximately 20.2ms at 49.5Hz and approximately 19.8ms at 50.5Hz). The fixed window cannot accurately align with the voltage zero-crossing point, resulting in the accumulation of phase drift and deviations in feature extraction.

[0038] The apparatus in this embodiment introduces a voltage zero-crossing detection circuit, which directly triggers cycle reset and interval division with a hardware zero-crossing pulse. Each cycle is realigned based on the actual zero-crossing point, and the interval boundaries automatically expand and contract with frequency changes, ensuring accurate phase reference. While voltage waveform distortion may cause local jitter near the zero-crossing point, the comparator's 50mV threshold and hysteresis effectively suppress glitches near the zero-crossing point. Combined with the interval division width (45° per interval), it provides tolerance for minor time jitter, thus maintaining stable judgment performance even in environments with poor power grid quality. The robustness of the judgment algorithm is improved, tolerating power grid frequency fluctuations of ±5% and voltage waveform distortion.

[0039] In the embodiments of this application, the signal processing unit can be a digital signal processing unit, specifically a microcontroller unit (MCU), used to receive the power signal voltage zero-crossing point detected by the voltage zero-crossing point detection circuit, and determine each power frequency cycle with each voltage zero-crossing point as the starting point, and divide the phase range corresponding to each power frequency cycle into multiple phase intervals according to the preset number of intervals.

[0040] Here, it is understandable that the time corresponding to one power frequency cycle depends on the power grid frequency. For example, it is 0.02 seconds (20ms) in a 50Hz system and approximately 0.0167 seconds (16.7ms) in a 60Hz system. The number of power frequency cycles contained in the target time period can be determined through experimental calibration.

[0041] Simultaneously, the signal processing unit can also receive ADC sampled values ​​from the low-frequency sampling channel and high-frequency pulse digital signals from the high-frequency sampling channel, and perform feature extraction within subdivided phase intervals under a unified time reference. This yields current waveform distortion characteristics and high-frequency pulse signal characteristics under different phase partitions. Furthermore, a fusion analysis is performed using a preset algorithm in the microcontroller unit. Specifically, during the fusion analysis, the MCU can identify the load type and current waveform distortion characteristics based on the current signal corresponding to the target low-frequency voltage signal acquired by the low-frequency sampling channel. Combined with the pulse density, amplitude, and other statistical quantities of the high-frequency pulse signal from the high-frequency sampling channel within a specific time window, it comprehensively determines whether a fault arc exists in the target time period consisting of multiple consecutive power frequency cycles of a preset number. If a fault arc is determined to exist in the target time period, a trip trigger signal is output to disconnect the power supply from the load, preventing the possibility of an electrical fire.

[0042] The fault arc detection device of this application introduces a voltage zero-crossing detection circuit to directly generate a zero-crossing synchronization pulse for power signal voltage zero-crossing detection. Using the voltage zero-crossing point as a time-domain synchronization reference, the alignment of high and low frequency sampling data can be achieved at the hardware level, eliminating the computational overhead and time drift caused by traditional software alignment methods. At the same time, by performing phase partitioning and weighted fusion on the power frequency cycle, a higher confidence judgment result can be obtained without long-period smoothing, and the response time is greatly compressed, which can effectively improve the efficiency of fault arc detection.

[0043] The fault arc detection device of this application, by introducing completely independent high and low frequency sampling channels in physical structure and combining them with phase partitioning, can ensure high extraction accuracy of low frequency current signals and high sensitivity capture of high frequency arc signals, so that arc features are concentrated in a few advantageous ranges, the signal differentiation is significantly improved, and differentiated arc feature identification under power frequency cycle phase partitioning is realized, thereby improving the detection accuracy of fault arcs.

[0044] Based on the content of the above embodiments, as an optional embodiment, such as Figure 2 As shown, the low-frequency sampling circuit 2 includes a sampling resistor 21, a differential amplifier 22, and a low-pass filter 23 connected in sequence; the low-pass filter 23 is connected to the signal processing unit 1. Sampling resistor 21 is used to sample the low-frequency current signal in the power supply signal and convert the low-frequency current signal into a low-frequency voltage signal; Differential amplifier 22 is used to differentially amplify low-frequency voltage signals and output the first amplified signal; The low-pass filter 23 is used to filter the first amplified signal and output the target low-frequency voltage signal.

[0045] Specifically, in the embodiments of this application, the low-frequency sampling circuit can be composed of a sampling resistor, a differential amplifier, and a low-pass filter connected in sequence. The sampling resistor is a two-terminal component; its first terminal can be connected in series to the incoming terminal of the power grid's neutral (N) or live (L) wire, and its second terminal is connected in series to the neutral loop on the load side. All the power frequency current flowing through the load flows through the sampling resistor, generating a weak voltage difference across it that is proportional to the instantaneous current value. Simultaneously, the first terminal (higher voltage side) of the sampling resistor can be connected to the non-inverting input (+IN) of the differential amplifier through a current-limiting resistor, and the second terminal (lower voltage side) can be connected to the inverting input (-IN) of the differential amplifier through an equivalent current-limiting resistor. Each of the two input terminals of the differential amplifier has a filter capacitor connected to ground, forming a common-mode filter; a capacitor can also be connected between the two input terminals to form a differential-mode filter. The reference voltage terminal (REF) of the differential amplifier is connected to a DC bias voltage generated by a resistor divider (such as the midpoint of a 3.3V power supply, approximately 1.65V), causing the output signal to oscillate around this bias level to match the input range of the subsequent unipolar ADC.

[0046] In the embodiments of this application, the output (OUT) of the differential amplifier circuit is directly connected to the input (Vin) of the low-pass filter. The low-pass filter can adopt a second-order active Sallen-Key topology, where the non-inverting input of its operational amplifier receives the Vin signal through a two-stage RC network. The output (Vout) of the operational amplifier is fed back to the first-stage RC node to form the filtering characteristics, and also serves as the filtered signal output. The output (Vout) of the low-pass filter is connected to the analog input pin (ADC_CH0) of the analog-to-digital converter (ADC) built into the signal processing unit (MCU). The input voltage range of this pin is 0 to 3.3V, which is matched with the front-end bias voltage and the amplifier output swing.

[0047] In the embodiments of this application, the sampling resistor can be used to convert the low-frequency current signal (DC to 10kHz frequency band component) in the current signal into a corresponding low-frequency voltage signal. A differential amplifier is connected across the sampling resistor, allowing the differential amplifier to differentially amplify the input low-frequency voltage signal and output the amplified low-frequency voltage signal, i.e., the first amplified signal. Then, its output is filtered by a low-pass filter to remove high-frequency noise and out-of-band signals, yielding the target low-frequency voltage signal. This signal is then fed into the built-in ADC of the signal processing unit, where it undergoes voltage-to-current conversion to provide the signal processing unit with the required power frequency current signal. This channel is primarily used to acquire the power frequency current waveform (50Hz), the time-varying characteristics of the load impedance, and the current zero-wave distortion signal. Placing the sampling resistor on the neutral (N) line reduces common-mode interference and simplifies the front-end protection circuitry.

[0048] In the embodiments of this application, the operation of the low-frequency sampling circuit is as follows: a sampling resistor is connected in series with the neutral (or live) wire. When current flows through the load, a small voltage proportional to the instantaneous current value is generated. This voltage is differentially amplified and low-pass filtered to remove high-frequency noise and out-of-band signals. Then, the ADC built into the MCU samples the voltage at a sampling rate suitable for the power frequency (e.g., 10kHz). The MCU directly reads these sampled values ​​to obtain a high-fidelity instantaneous power frequency current waveform (50Hz fundamental wave). This process utilizes the excellent linearity and zero phase distortion of the sampling resistor in the DC to several kHz frequency band, ensuring the accurate reproduction of the current waveform.

[0049] In this embodiment, the sampling resistor exhibits excellent linearity (nonlinearity less than 0.01%) and near-zero phase distortion in the DC to several kHz frequency range, without waveform distortion caused by hysteresis loops. In contrast, traditional high-current transformers suffer from proportional errors and phase deviations caused by excitation current in the low-frequency range, especially at low load currents, where the core operating point is at the lower end of the BH curve, and the low initial permeability results in a ratio error of 0.5% to 2%. This embodiment replaces electromagnetic conversion with resistive voltage division, directly extracting a voltage signal proportional to the instantaneous current from the current loop, bypassing the inherent problem of transformer nonlinearity, and significantly improving accuracy.

[0050] The apparatus of this application embodiment constructs a low-frequency sampling circuit by introducing a sampling resistor, a differential amplifier, and a low-pass filter. Through the coordinated processing between sampling, differential amplification, and filtering, it can ensure excellent linearity and zero phase distortion of the sampled signal in the DC to several kHz frequency band, ensure the true reproduction of the current waveform, effectively obtain a high-fidelity instantaneous waveform of the power frequency current, and improve the accuracy of subsequent low-frequency signal feature extraction.

[0051] Based on the content of the above embodiments, as an optional embodiment, such as Figure 3 As shown, the high-frequency sampling circuit 3 includes a high-frequency current sensor 31, a bandpass filter module 32, an amplification module 33, and a shaping module 34 connected in sequence; the shaping module 34 is connected to the signal processing unit 1. The high-frequency current sensor 31 is used to couple the high-frequency current signal in the power supply signal and convert the high-frequency current signal into a high-frequency voltage signal. Bandpass filter module 32 is used to extract arc characteristic frequency band signals from high-frequency voltage signals; Amplification module 33 is used to amplify the amplitude of the arc characteristic frequency band signal and output a second amplified signal; The shaping module 34 is used to convert the second amplified signal into a target high-frequency voltage signal.

[0052] Specifically, in the embodiments of this application, a high-frequency sampling circuit can be constructed by sequentially connecting a high-frequency current sensor, a bandpass filter module, an amplification module, and a shaping module to form a high-frequency arc signal acquisition channel. The bandpass filter module, the amplification module, and the shaping module together constitute a signal conditioning circuit.

[0053] The high-frequency current sensor is deployed on either the live wire (L-line) or the neutral wire (N-line) to couple the 1MHz to 30MHz high-frequency components of the power supply current signal, and outputs the corresponding high-frequency voltage signal after a resistor is connected in parallel on the secondary side. Here, the high-frequency current sensor can be a through-hole current transformer, with the L-line passing through the center hole of its magnetic core to form the primary side (equivalent to 1 turn). The two leads of the secondary winding of the high-frequency current sensor (wound on the magnetic core, 7 turns) are connected to the input terminals (In+ and GND) of the bandpass filter module, respectively.

[0054] Here, if the sampling resistor is deployed on the N line, the high-frequency current sensor is deployed on the L line; if the sampling resistor is deployed on the L line, the high-frequency current sensor is deployed on the N line.

[0055] The bandpass filter module, specifically configured with a center frequency of 10MHz and a bandwidth of 8-12MHz (arc characteristic frequency band), is used to extract the arc characteristic frequency band signal from the output signal of the high-frequency current sensor and suppress power frequency and low-frequency trailing and out-of-band radio frequency interference. Here, when the bandpass filter module adopts a passive LC structure, a 50Ω matching resistor is connected in parallel at its input, followed by an inductor L and a capacitor C in series, forming a series resonant bandpass filter. The signal is taken from the output terminal of the output capacitor and ground (GND).

[0056] In this embodiment, the output terminal (OUT+) of the bandpass filter module is connected to the base of the amplifier module. The amplifier module can be a discrete transistor amplifier, whose output terminal (OUT) is the collector terminal.

[0057] Here, the filtered arc characteristic frequency band signal is a weak high-frequency signal. The amplification module can amplify the arc characteristic frequency band signal to a detectable amplitude range, thereby obtaining a second amplified signal, which is then output to the shaping module.

[0058] Furthermore, the shaping module can convert the second amplified signal into a high-frequency pulse digital signal, thus obtaining the target high-frequency voltage signal.

[0059] Traditional single broadband current transformers, designed to handle large power frequency currents, have limited turns ratios (through-core primary side, hundreds of turns secondary side), resulting in low high-frequency signal coupling efficiency. Furthermore, the distributed capacitance and leakage inductance of the coils contribute to a low-pass effect, suppressing MHz-level signals. In this embodiment, by independently optimizing the high-frequency sampling channel, the sensor only needs to focus on the 1–30MHz frequency band. A low turns ratio (e.g., 1:7–1:50) small magnetic core can be used, reducing distributed capacitance and leakage inductance and significantly improving high-frequency coupling efficiency. Simultaneously, the subsequent signal conditioning circuit, consisting of a bandpass filter module, an amplification module, and a shaping module, can specifically perform low-noise amplification and band matching for weak signals, eliminating the need for attenuation compromises for large signals at the analog front end. This achieves an actual sensitivity gain of 10–20dB, greatly improving the sensitivity for capturing high-frequency arc signals.

[0060] In traditional architectures, a single current transformer needs to cover both high-frequency power current and MHz-level high-frequency signals. To prevent core saturation under low-frequency high current, a large-size high-permeability magnetic core must be used, resulting in high material costs and a large amount of material used.

[0061] In this embodiment, by independently acquiring data in different frequency bands, the low-frequency large current is processed by a sampling resistor at the mΩ level. The resistor does not have a magnetic saturation problem and does not require a large magnetic core. The high-frequency small signal is processed by a small high-frequency current sensor optimized for this frequency band. Only the uA-mA level high-frequency components need to be processed, and the cross-sectional area of ​​the magnetic core can be greatly reduced. The material and manufacturing complexity of both types of devices are significantly reduced, thereby achieving fundamental cost reduction at the bill of materials (BOM) level.

[0062] like Figure 5 As shown in a specific embodiment of this application, an AFDD product for use in a single-phase 220V / 50Hz power grid is provided. The signal processing unit 1 is an MCU, which can be an ARM Cortex-M0 core with a main frequency of 48MHz, such as the NXP LPC1114. Its peripheral resource configuration includes: an "EXT_INT0" pin for receiving the V_zc voltage zero-crossing pulse as a time domain reference; an "EXT_INT1" pin for receiving the high-frequency arc pulse sampled by the high-frequency sampling circuit 3; an "ADC_CH0" pin for receiving the current sample value sampled by the low-frequency sampling circuit 2; a "Timer0" pin for providing a global time reference with a 1μs resolution; and a "GPIO_OUT1" pin for outputting a trip trigger signal.

[0063] In the low-frequency sampling circuit 2, the sampling resistor 21 is a 2mΩ precision metal film resistor, connected in series in the N-line loop. Its first terminal is connected to the N-line input of the power grid, and its second terminal is connected to the N-line output of the load. When the load current flows through it, a weak voltage proportional to the instantaneous current value is generated across it. The non-inverting input (+IN) of the differential amplifier 22 is connected to the first terminal of the sampling resistor, and the inverting input (-IN) is connected to the second terminal of the sampling resistor 21. Its gain is set to 5.5 times, and its output voltage range is adapted to the subsequent ADC stage. The output of the low-pass filter 23 is connected to the ADC input pin (ADC_CH0) of the MCU. The MCU acquires current waveform data at a sampling rate of 10kHz.

[0064] In the high-frequency sampling circuit 3, the high-frequency current sensor 31 is a high-frequency current transformer wound with a ferrite core, and is installed through-wire to the live wire; the secondary winding outputs a high-frequency coupled signal. The bandpass filter module 32 has a passband range of 8MHz to 12MHz, performing 8MHz-12MHz bandpass filtering on the sensor output signal to filter out power frequency and low-frequency trailing and radio frequency interference. The amplification module has a gain of 23.5dB and uses a low-noise transistor amplifier for low-noise amplification. The shaping module can use a high-speed comparator to compare the filtered and amplified signal with a reference voltage Vref (e.g., 50mV) and convert it into a TTL level pulse signal; when the high-frequency signal amplitude exceeds the threshold, a high-level pulse is output. The output of the shaping module is connected to another external interrupt pin (EXT_INT1) of the MCU, triggered by a rising edge. The MCU records the pulse arrival timestamp and accumulates the pulse count in the interrupt service routine.

[0065] In the voltage zero-crossing detection circuit 4, this circuit is connected between the L and N lines of the power grid to generate a hardware pulse signal V_zc synchronized with the zero-crossing point of the power grid voltage. Its resistor divider network 41 consists of a high-voltage resistor R1 (e.g., 220kΩ / 1W) and a low-voltage resistor R2 (e.g., 1.1kΩ) connected in series between the L and N lines. The non-inverting input (+IN) of comparator 42 is connected to the voltage divider point of the resistor divider network 41, and the inverting input (-IN) is connected to the reference voltage Vref. The output generates a square wave signal, resulting in the hardware pulse signal V_zc. The output of comparator 42 is connected to the external interrupt pin (EXT_INT0) of the MCU, and the triggering mode is set to double-edge triggering. This pulse signal V_zc serves as the unified time-domain reference for the entire identification process.

[0066] Further, in this embodiment, the MCU uses the V_zc pulse as the synchronization reference and divides each power frequency cycle into several phase intervals (e.g., 8 intervals, each 45°). Within each phase interval, the target low-frequency voltage signal is sampled by an ADC, and low-frequency features (e.g., instantaneous current value, zero depth) are extracted from the ADC sampling data. High-frequency features such as the number and density of pulses within the interval are statistically analyzed from the high-frequency pulse signals recorded from the target high-frequency voltage signal. At the end of each power frequency cycle, based on the currently identified load type, the features of each interval are assigned normalized weights and weighted summed to obtain the comprehensive score for this cycle. When the score exceeds the single-cycle judgment threshold Th corresponding to the load type, this cycle is marked as a "suspected arc cycle" (denoted as 1); otherwise, it is marked as a normal cycle (denoted as 0). The MCU maintains a sliding window of length N to determine the target time period, such as N=8, and records the judgment results of the most recent 8 power frequency cycles. If the number of "suspected arc cycles" M ≥ N-2, i.e., 6, within the sliding window, it is determined to be a real fault arc, and a trip trigger signal is output; otherwise, monitoring continues.

[0067] The fault arc detection method provided in this application is described below. The fault arc detection method described below can be referred to in correspondence with the fault arc detection device described above.

[0068] Figure 6 This is a flowchart illustrating the arc fault detection method provided in this application. It can be understood that the execution entity of this method is a signal processing unit, which can be applied to any of the aforementioned arc fault detection devices, such as... Figure 6 As shown, the method includes: Step S1: Obtain the zero-crossing point of the power supply signal at different times, as well as the target low-frequency voltage signal and the target high-frequency voltage signal in the power supply signal; Step S2: Determine the corresponding power frequency cycle starting from each voltage zero-crossing point, and divide the phase range corresponding to each power frequency cycle into multiple phase intervals; Step S3: Based on the target low-frequency voltage signal and target high-frequency voltage signal in each phase interval, perform arc signal feature extraction and fusion analysis to determine whether there is a fault arc in the target time period; the target time period is determined based on a preset number of power frequency cycles.

[0069] It should be understood that the above method is applied to the fault arc detection device in the above embodiments. The implementation principle and technical effect of the corresponding steps in the method are similar to those described in the relevant modules / units in the above system. The implementation process of this method can refer to the corresponding working process in the above system, which will not be repeated here.

[0070] It should be noted that, in the embodiments of this application, taking each voltage zero-crossing point (rising edge or falling edge) as the starting point, one power frequency cycle T=20ms (corresponding to a 50Hz power grid) can be divided into N consecutive phase intervals. In this embodiment, N=8 can be set, and the width of each interval is 45° (corresponding to 2.5ms). The definitions of each phase interval are shown in Table 1.

[0071] Table 1

[0072] When the MCU receives the edge of the V_zc pulse, it resets the internal timer count to zero. The current interval number is obtained by dividing the timer count by 2.5ms (corresponding to 2500 timer clock cycles and a timer resolution of 1μs). Based on this, subsequent feature extraction can be assigned to the corresponding phase interval.

[0073] The fault arc detection method of this application introduces a voltage zero-crossing detection circuit to directly generate a zero-crossing synchronization pulse for power signal voltage zero-crossing detection. Using the voltage zero-crossing point as a time-domain synchronization reference, the alignment of high and low frequency sampling data can be achieved at the hardware level, eliminating the computational overhead and time drift caused by traditional software alignment methods. At the same time, by dividing the power frequency cycle into phases and combining the complete independence of the introduced high and low frequency sampling channels in terms of physical structure, high extraction accuracy of low frequency current signals and high sensitivity capture of high frequency arc signals can be ensured, so that arc features are concentrated in a few advantageous intervals, and the signal discrimination is significantly improved. Differentiated arc feature identification under the phase partitioning of the power frequency cycle can be achieved, and higher confidence judgment results can be obtained without long-period smoothing. The response time is greatly compressed, which can effectively improve the efficiency of fault arc detection and improve the detection accuracy of fault arc.

[0074] Based on the content of the above embodiments, as an optional embodiment, step S3 specifically includes: Step S31: Based on the target low-frequency current signal corresponding to the target low-frequency voltage signal in each phase interval of each power frequency cycle, determine the load type corresponding to each power frequency cycle and the zero-sink depth corresponding to each phase interval, and based on the target high-frequency voltage signal in each phase interval, determine the comprehensive high-frequency characteristics corresponding to each phase interval. Step S32: Determine the weight information corresponding to each phase interval according to the load type; Step S33: Based on the zero-rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval of each power frequency cycle, perform fusion analysis to determine whether there is a fault arc in the target time period.

[0075] Specifically, in the embodiments of this application, when performing arc signal feature extraction and fusion analysis, it is first necessary to determine the load type, the zero-suspension depth corresponding to each phase interval, and the comprehensive high-frequency characteristics. Specifically, in step S31, low-frequency feature extraction and analysis are performed using the target low-frequency current signal corresponding to the target low-frequency voltage signal in each phase interval of each power frequency cycle to determine the load type corresponding to each power frequency cycle and the zero-suspension depth corresponding to each phase interval. At the same time, high-frequency arc feature extraction and analysis are performed based on the target high-frequency voltage signal in each phase interval to determine the comprehensive high-frequency characteristics corresponding to each phase interval.

[0076] Based on the above embodiments, as an optional embodiment, the specific steps for determining the load type corresponding to each power frequency cycle include: Based on the target low-frequency current signal within each power frequency cycle, determine the power factor and total harmonic distortion rate; When the power factor is determined to be no less than the power factor threshold and the total harmonic distortion rate is no greater than the first distortion threshold, the load type is determined to be resistive load. or, When the power factor is determined to be less than the power factor threshold, the total harmonic distortion rate is greater than the first distortion threshold but not greater than the second distortion threshold, and the current phase lags behind the voltage phase, the load type is determined to be an inductive load. or, When the power factor is less than the power factor threshold, the total harmonic distortion rate is greater than the first distortion threshold but not greater than the second distortion threshold, and the current phase leads the voltage phase, the load type is determined to be a capacitive load. or, When the total harmonic distortion rate is determined to be greater than the second distortion threshold, the load type is determined to be a nonlinear load.

[0077] Specifically, in the embodiments of this application, the power factor threshold, the first distortion threshold, and the second distortion threshold are all preset calibration thresholds. The power factor threshold can range from 0.85 to 0.95, and can be specifically set to 0.9; the first distortion threshold can range from 8% to 12%, and can be specifically set to 10%; the second distortion threshold can range from 28% to 32%, and can be specifically set to 30%.

[0078] In the embodiment of the present application, after acquiring the target low-frequency voltage signal collected by the low-frequency acquisition circuit within the current power frequency cycle, after the MCU reads the voltage value through the ADC, it back-calculates the actual current waveform sampling value back in software according to the known sampling resistance value and amplification gain, so as to obtain the target low-frequency current signal. Then, the dot product operation can be performed by using the voltage waveform sampling value and the current waveform sampling value within the same power frequency cycle to obtain the ratio of active power to apparent power, and determine the power factor of the entire power distribution circuit.

[0079] Optionally, if no dedicated voltage sampling is introduced by the external circuit, the power factor can also be approximately estimated through the shape characteristics of the current waveform, such as the peak position of the waveform and the phase offset of the zero-crossing point.

[0080] Meanwhile, Fast Fourier Transform (FFT) can also be performed on the current waveform corresponding to the target low-frequency voltage signal sampled in the power frequency cycle, that is, the target low-frequency current signal, to obtain the fundamental amplitude and the third harmonic amplitude, and then the total harmonic distortion (THD) can be directly calculated. Specifically, 128-point FFT can be performed on 200 sampling points of the power frequency cycle to obtain the fundamental amplitude A1 and the amplitudes of each harmonic A2 to A7, and THD can be calculated by the following formula: THD=sqrt(A2 2 +A3 2 +…+A7 2 ) / A1×100%.

[0081] It should be noted that THD is used to characterize the deviation degree of the actual current waveform from the ideal sine waveform.

[0082] In a specific embodiment of the present application, if the power factor >= 0.9 and THD <= 10%, the load type can be determined as resistive load.

[0083] If the power factor < 0.9, the current phase lags the voltage phase (for example, the time difference between the current zero-crossing point and the voltage zero-crossing point ΔT_zc ≥ 1ms) and 10% < THD ≤ 30%, the load type can be determined as inductive load.

[0084] If the power factor < 0.9, the current phase leads the voltage phase (for example, the time difference between the current zero-crossing point and the voltage zero-crossing point ΔT_zc ≤ -1ms) and 10% < THD ≤ 30%, the load type can be determined as capacitive load.

[0085] If THD > 30%, the load type can be determined as non-linear load.

[0086] In addition, other situations can be classified as mixed loads.

[0087] Optionally, to further improve the calculation accuracy, the current waveform data of the current power frequency cycle and the previous multiple power frequency cycles can also be used. For example, the current waveform data of the previous 9 power frequency cycles can be selected, for a total of 10 cycles, with a total cycle time of 200ms.

[0088] The method in this application embodiment, by using a low-frequency sampling channel with an introduced sampling resistor to acquire low-frequency voltage signals, can effectively avoid the phase distortion and nonlinearity problems existing in the traditional low-frequency band, improve the extraction accuracy of subsequent low-frequency current signals, and comprehensively judge the load type from multiple dimensions such as power factor, total harmonic distortion rate and current phase, which can effectively determine the load type and improve the identification accuracy of load type.

[0089] Based on the above embodiments, as an optional embodiment, the specific steps for determining the zero rest depth corresponding to each phase interval include: Based on the zero-crossing information of the target low-frequency current signal within each phase interval, multiple zero-crossing analysis windows corresponding to each phase interval are determined. Within each zero-current analysis window, the actual current deviation at each sampling point is calculated, and the maximum actual current deviation is selected as the zero-current depth corresponding to each zero-current analysis window. The zero depth corresponding to each phase interval is obtained by using the maximum value in the zero depth corresponding to each zero-rest analysis window.

[0090] Specifically, the zero-crossing depth described in the embodiments of this application is used to characterize the maximum deviation of the measured current from the normal sine waveform near the current zero-crossing point, reflecting the severity of the arc current zero-crossing phenomenon.

[0091] In the embodiments of this application, when determining the zero-crossing depth corresponding to each phase interval, multiple zero-crossing analysis windows corresponding to each phase interval are first determined based on the zero-crossing information of the target low-frequency current signal within each phase interval. Specifically, the MCU locates the positive and negative zero-crossing points of the current by comparing the sign changes of adjacent sampling points. Taking the positive zero-crossing point as the center, a zero-crossing analysis window can be taken before and after it for 0.5ms. Symmetrically, taking the negative zero-crossing point as the center, a zero-crossing analysis window is also taken before and after it for 0.5ms. Thus, multiple zero-crossing analysis windows can be determined according to the number of voltage zero-crossing points within each phase interval.

[0092] Within each zero-wave analysis window, the deviation between the ideal sinusoidal current reference value I_ideal[n] and the measured value I[n] is calculated point by point, thus obtaining the actual current deviation amplitude ΔI[n]: ΔI[n] = |I_ideal[n] - I[n]|. Here, the ideal sinusoidal current reference value I_ideal[n] can be calculated based on the fundamental amplitude A1 of that period and the sinusoidal function; n represents the nth sampling point. For example, with a sampling rate of 10kHz, there are 200 sampling points per power frequency cycle, and the number of sampling points corresponding to interval 0 is n = 0 to 24 (10kHz × 2.5ms = 25 points).

[0093] Here, the maximum value of ΔI[n] within all zero-suspension analysis windows is taken as the zero-suspension depth, expressed as a percentage of peak current, and assigned to the phase interval corresponding to the maximum value.

[0094] Furthermore, the maximum actual current deviation is selected as the zero-crossing depth for each zero-crossing analysis window. In other words, the maximum value of ΔI[n] can be taken as the zero-crossing depth of that zero-crossing point, expressed as a percentage of the peak current. Then, based on the maximum value among the zero-crossing depths corresponding to each zero-crossing analysis window, the zero-crossing depth for each phase interval can be finally determined.

[0095] In this embodiment, the number of sampling points where ΔI[n] continuously exceeds the zero-rest depth threshold can be counted, and multiplied by the sampling period of 0.1ms to obtain the zero-rest duration. In this embodiment, the zero-rest depth threshold can be set to 5% of the peak current.

[0096] In the embodiments of this application, the extraction of low-frequency features requires data obtained from the current sampling channel. The current sampling channel can be a low-frequency sampling circuit consisting of a sampling resistor (2mΩ), a differential amplifier (5.5x gain), and a low-pass filter, as well as a 12-bit ADC built into the MCU. Here, the raw data output by the ADC is a digitized voltage sample value D_raw[n] (n=0,1,2,…,199), which needs to be converted into an actual current value according to the following formula: I[n]=(D_raw[n]×V_ref_ADC / 4096-V_bias) / (R_shunt×Gain), where V_ref_ADC=3.3V, V_bias=1.65V, R_shunt=2mΩ, and Gain=5.5. Furthermore, based on the I[n] sequence, the following low-frequency features can be calculated separately in each phase interval: (1) Instantaneous current value: that is, the real-time numerical sequence of the current waveform within the interval. It is extracted by directly taking the sampling point I[n] corresponding to the interval, without any additional calculation.

[0097] (2) Rate of change of current (di / dt): This is the first derivative of the current with respect to time, reflecting the steepness of the current waveform. It is extracted by calculating the difference between adjacent sampling points within the interval using the following formula: di / dt[n]=(I[n+1]-I[n]) / Δt, where Δt=0.1ms (corresponding to a 10kHz sampling period).

[0098] The maximum absolute value of di / dt within the interval is taken as the characteristic of the current change rate in that interval.

[0099] The rate of change of current can be used to characterize the sudden change in the slope of the current near the zero crossing point when an electric arc occurs; the peak value of di / dt can reach 2 to 5 times the normal value.

[0100] The method in this application embodiment performs zero-crossing neighborhood waveform analysis on the low-frequency current sampling signal in each phase interval of each power frequency cycle, extracts the current zero-crossing distortion signal features, provides key evaluation indicators for subsequent fault arc determination, and helps to improve the detection accuracy of fault arc.

[0101] Based on the above embodiments, as an optional embodiment, the specific steps for determining the comprehensive high-frequency characteristics corresponding to each phase interval include: The total number of high-frequency pulses corresponding to each phase interval is determined based on the number of high-frequency pulse events that occur in the target high-frequency voltage signal within the corresponding time period of each phase interval. The number of high-frequency pulse clusters corresponding to each phase interval is determined based on the frequency of high-frequency pulse events that occur in the target high-frequency voltage signal within the corresponding time period of each phase interval. Based on the total number of high-frequency pulses and the number of high-frequency pulse clusters corresponding to each phase interval, the comprehensive high-frequency characteristics corresponding to each phase interval are determined.

[0102] Specifically, in the embodiments of this application, after acquiring the target high-frequency voltage signal collected by the high-frequency acquisition circuit in each power frequency cycle, high-frequency channel features can be extracted in each phase interval. Here, during the detection of the high-frequency voltage signal, the occurrence of a pulse can be recorded as a pulse event. In the interrupt service routine, the MCU records the timer count value (timestamp) when each pulse arrives and increments it in the pulse count variable corresponding to the current phase interval. Taking the power frequency cycle as the unit, at the end of each cycle, the pulses in the interval are statistically processed to obtain the following high-frequency features: Total High-Frequency Pulses: This counts the number of high-frequency pulse events captured in the target high-frequency voltage signal within each phase interval. It is extracted by directly counting the number of external interrupt triggers within the phase interval. The MCU maintains a counter variable for each interval; when an interrupt is triggered, the corresponding counter is incremented by 1 based on the interval index of the current timestamp. At the end of the cycle, the count value of each interval is read.

[0103] High-frequency pulse clusters: This counts the frequency of high-frequency pulse clusters. A single pulse cluster is defined as multiple consecutive high-frequency pulse events occurring within a short period (e.g., within 100μs). The extraction method involves the MCU not only counting within an interrupt but also storing the timestamp of each pulse in a temporary array. At the end of the cycle, the time intervals between adjacent pulses in the array are scanned: if the time interval between adjacent pulses is less than the pulse cluster determination threshold T_cluster = 100μs, they are considered pulses within the same pulse cluster. The number of pulses within each pulse cluster (number of pulses within the cluster) and the duration of the cluster (time difference between the last pulse and the first pulse within the cluster) are counted. Pulse cluster density = number of pulse clusters in the interval / interval duration (e.g., 2.5ms). Average pulses within a cluster = sum of the number of pulses in all clusters / number of pulse clusters. If there are no pulse clusters in the interval (all pulse intervals > 100μs), the number of high-frequency pulse clusters is 0, and the high-frequency pulse cluster density is 0.

[0104] Therefore, through the above processing method, comprehensive high-frequency features, including the total number of high-frequency pulses and the number of high-frequency pulse clusters, can be extracted from the target high-frequency voltage signal in each phase interval.

[0105] The method in this application starts with high-frequency radiation pulses and extracts high-frequency arc signal features from the high-frequency current sampling signal in each power frequency cycle from multiple feature dimensions, providing key evaluation indicators for subsequent fault arc determination, which is beneficial to improving the detection accuracy of fault arcs.

[0106] Furthermore, in the embodiments of this application, in step S32, the weight information corresponding to each phase interval is further determined according to the aforementioned determined load type.

[0107] Specifically, in the embodiments of this application, it is necessary to pre-establish the mapping relationship between load type and phase interval, and determine the load-phase-weight mapping information. Based on experimental experience and the physical mechanism of electric arcs, the dominant phase intervals for the occurrence of high-frequency pulses and zero-rest characteristics of real electric arcs under different types of loads are shown in Table 2.

[0108] Table 2

[0109] Furthermore, the dynamic adjustment rules for the weighting coefficients are determined based on the above principles. The weighting coefficients are determined by the MCU in real time according to the previously identified load type, based on the following rules.

[0110] The inventors discovered that, for resistive loads, arc characteristics are highly concentrated near the zero-crossing point. High-frequency pulses and zero-crossing characteristics appearing in the zero-crossing region have extremely high arc indication value and are given the highest weight; if pulses appear in the peak region and the rising and falling regions, they are more likely to originate from external interference and are given lower weight, thus effectively distinguishing between real arcs and interference.

[0111] For example, in one specific embodiment of this application, a power frequency cycle T=20ms is divided into N=8 consecutive phase intervals. For resistive loads, the weight W[i] corresponding to the zero-crossing neighborhood (interval 0, interval 4) is 0.4 (high weight), the weight W[i] corresponding to the voltage peak region (interval 2, interval 6) is 0.05 (low weight), and the weight W[i] corresponding to the remaining intervals (intervals 1, 3, 5, 7) is 0.025 (suppression weight).

[0112] The inventors discovered that for inductive loads, the current lags behind the voltage, and arc reignition occurs at voltage peaks rather than at zero crossings. Therefore, they assigned higher weights to the voltage peak and valley regions, while significantly reducing the weight of the zero crossing region.

[0113] For example, in one specific embodiment of this application, for an inductive load, the weight W[i] corresponding to the zero-crossing neighborhood (interval 0, interval 4) is 0.08, the weight W[i] corresponding to the voltage peak region (interval 2, interval 6) is 0.35 (high weight), and the weight W[i] corresponding to the other intervals is 0.035.

[0114] In the embodiments of this application, for nonlinear loads and mixed loads, the weights of all intervals are uniformly distributed. For example, in a specific embodiment of this application, for nonlinear loads and mixed loads, the weights W[i] corresponding to intervals 0 to 7 are 0.125 (uniformly distributed), while a higher single-cycle judgment threshold Th=0.60 (compared to the resistive load threshold of 0.45) is used to compensate for the risk of misjudgment caused by uniform weights.

[0115] The inventors discovered that the arcing characteristics of capacitive loads are similar to those of resistive loads, but the mechanisms are different. The current phase of capacitive loads leads, and the zero-crossing characteristic may exist in the peak region. Therefore, weighting information can be designed separately. For example, in a specific embodiment of this application, for a capacitive load, the weight W[i] corresponding to its zero-crossing neighborhood (interval 0, interval 4) is 0.3, the weight W[i] corresponding to the voltage peak region (interval 2, interval 6) is 0.15, and the weight W[i] corresponding to the other intervals is 0.025.

[0116] It should be noted that, in the embodiments of this application, the mapping data between different load types and weight information can be dynamically adjusted according to specific working conditions such as phase interval division parameters and dominant phase interval distribution, thereby determining the weight information under different parameter working conditions. This application does not make specific limitations in this regard.

[0117] In this embodiment, load type (resistive, inductive, capacitive, nonlinear) is automatically identified through current waveform analysis, eliminating the need for manual load parameter setting during installation. Identification is based on multi-dimensional characteristics including power factor, current-voltage phase difference, and THD, and load type determination can be completed within 10 power frequency cycles (200ms). A differentiated weighted fusion method based on load type is proposed, where the identification result directly drives the weight selection, enabling the arc detection strategy to adaptively switch according to different load types. When the load changes (e.g., plugging or unplugging appliances), the system automatically updates the load type and adjusts the weight configuration within 200ms, requiring no manual intervention and exhibiting better adaptability than schemes with fixed thresholds or single judgment rules.

[0118] Furthermore, in the embodiments of this application, in step S33, a weighted fusion analysis is performed based on the zero-rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval of each power frequency cycle to determine whether there is a suspected fault arc in each power frequency cycle within the target time period, and then, based on the number of power frequency cycles in which a suspected fault arc exists, it is determined whether there is a fault arc in the entire target time period.

[0119] In existing technologies, the high-frequency pulse energy generated by low-current arcs (such as series arcs under a rated current of 2.5A) is weak and few in number. In full-cycle statistical methods, it is easily overwhelmed by the background high-frequency noise generated by the normal operation of the load, resulting in insufficient signal-to-noise ratio and low detection rate.

[0120] The method in this application, after phase partitioning, determines the dominant phase interval (such as the zero-crossing neighborhood of a resistive load) that focuses on the characteristics of the arc. The background noise in this interval is extremely low when the load is working normally, and even a small number of pulses generated by a weak arc can significantly exceed the background level. At the same time, the weighting mechanism further compresses the noise contribution of the non-dominant interval, which is equivalent to obtaining a higher local signal-to-noise ratio in each dominant interval, thereby effectively improving the detection capability of low-current arcs, effectively improving the detection sensitivity, and increasing the success rate of low-current arc detection by 15% to 25%.

[0121] Based on the content of the above embodiments, as an optional embodiment, step S33 specifically includes: For any power frequency cycle, the comprehensive score of the fault arc corresponding to any power frequency cycle is determined by weighted calculation using the zero rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval. Based on the load type and the comprehensive score of the fault arc corresponding to any power frequency cycle, determine whether there is a suspected fault arc in any power frequency cycle; Determine the number of power frequency cycles in which suspected faulty arcs may exist within the target time period; Given that the number of power frequency cycles is not less than the target number threshold, it is determined that there is a fault arc within the target time period.

[0122] Specifically, in the embodiments of this application, for any power frequency cycle, a weighted calculation is performed using the zero-rest depth, comprehensive high-frequency characteristics, and weight information corresponding to each phase interval to determine the comprehensive fault arc score corresponding to any power frequency cycle. Specifically, in order to enable the weighted fusion of features of different dimensions, the feature values ​​of each phase interval are first normalized to the range of 0 to 1.

[0123] The normalized zero-depth feature for the low-frequency band is calculated as follows: Normalized zero depth S_zero[i] = actual zero depth within phase interval i / reference threshold (the reference threshold can be set to 5% of peak current), with an upper limit cutoff of 1.0.

[0124] For the comprehensive high-frequency characteristics in the high-frequency band, the following procedure is performed: Normalized pulse count: S_pulse[i] = number of pulses in phase interval i / number of reference pulses (the reference pulse count is based on 30, corresponding to the normal interference level of resistive load), with an upper limit truncation of 1.0.

[0125] Normalized pulse cluster density: S_cluster[i] = number of pulse clusters in phase interval i / number of reference clusters (the baseline value of the number of reference clusters is 3), with an upper limit truncation of 1.0.

[0126] Normalized high-frequency characteristics: S_hf[i]=(S_pulse[i]+S_cluster[i]) / 2.

[0127] It should be noted that the normalized baseline values ​​are all reference values ​​obtained from statistical analysis of data collected under laboratory conditions when various loads are working normally.

[0128] Furthermore, in the embodiments of this application, a weighted calculation is performed to determine the comprehensive score of the fault arc corresponding to any power frequency cycle. This process can be expressed as: Score=Σ(W[i]×(α×S_zero[i]+β×S_hf[i])) (i=0~7 can be taken); Where: α=0.4 (weight of low-frequency zero-rest feature), β=0.6 (weight of high-frequency pulse feature), and the sum of the two is 1. Here, the slightly higher weight of high frequency reflects the discriminative advantage of the high-frequency pulse feature of the electric arc, and this ratio is determined by optimization through experimental data analysis.

[0129] Furthermore, in the embodiments of this application, it is determined whether a fault arc is suspected to exist within any power frequency cycle based on the load type and the comprehensive score of the fault arc corresponding to any power frequency cycle. Specifically, a pre-set judgment threshold is first determined according to the load type.

[0130] Specifically, the threshold value Th can be: Th=0.45 for resistive loads, Th=0.40 for inductive loads, Th=0.45 for capacitive loads, Th=0.60 for nonlinear loads, and Th=0.60 for mixed loads.

[0131] It should be noted that the above thresholds were determined based on standard laboratory test data. The optimal threshold was selected through ROC curve analysis, under the constraints of a detection rate >95% and a false alarm rate <0.1%. Furthermore, the score distribution range for each load type under the test conditions can be set as follows: Resistive load (1000W electric kettle) series arc: Score range is 0.55~0.85; Series arcing of inductive load (1.5HP motor): Score range 0.50 to 0.75; Nonlinear load is normal (1.5kW inverter air conditioner): Score range is 0.05~0.30; Nonlinear load is normal (induction cooker 2000W): Score range is 0.08~0.35; Nonlinear load series arc: Score range is 0.65 to 0.80; A 500W thyristor dimmer is functioning normally: the score range is 0.03 to 0.25.

[0132] When the score is greater than the threshold (Th), the current power frequency cycle can be marked as a "suspected arc cycle" (M=1); otherwise, it is marked as a normal cycle (M=0). This allows us to determine whether a suspected fault arc exists within any given power frequency cycle.

[0133] In the embodiments of this application, the MCU maintains a sliding window queue of length N (e.g., N=8) to record the M value of the most recent 8 power frequency cycles, and the target number threshold is set to N-2. At the end of each cycle, the queue is updated and the number of cycles with M=1 in the queue is counted, denoted as Cnt_arc.

[0134] If Cnt_arc≥N-2 (i.e. ≥6), it is determined that there is a real fault arc within the target time period, and a trip trigger signal is generated to drive the trip mechanism to act.

[0135] If Cnt_arc<N-2, the monitoring continues, and the process returns to the aforementioned initial detection step to enter the next cycle of cyclic judgment.

[0136] Here, regarding the design principle of the judgment mechanism: Score>Th in a single cycle (one power frequency cycle) ensures the phase synchronization of the low-frequency zero-current feature and the high-frequency pulse feature (both features appear in the dominant phase interval within the same cycle); the multi-cycle statistics require that at least 6 out of 8 cycles meet the condition, which confirms the persistence of the arc phenomenon, while allowing individual cycles to have unobvious features temporarily due to noise interference (tolerating 2 non-compliant cycles), achieving a balance between detection sensitivity and anti-interference performance.

[0137] It should be noted here that N=8 and the target quantity threshold N-2=6 are recommended parameters. In specific implementation, N can be selected within the range of 4 to 16, and the threshold can be adjusted between N-1 and N-3.

[0138] In a specific embodiment of the present application, with the above recommended parameters, the method according to the embodiment of the present application can achieve a detection success rate of 98.2% in a 2.5A arc test with a resistive load (1000W electric kettle); no false tripping occurred in the 24-hour normal operation test of a variable frequency air conditioner (1.5kW); under the normal operation of a thyristor dimmer (500W), the false action rate is lower than 1.2%.

[0139] It should be noted that, in the embodiments of the present application, the voltage zero-crossing synchronization reference can not only use the output of a hardware comparator, but also calculate the zero-crossing point by software after ADC sampling of the voltage waveform; the phase interval division is not limited to equal-angle division, and equal-time division or dynamic division based on the slope of the voltage waveform can also be adopted; the weight coefficient is not limited to a fixed value, and can be dynamically generated by fuzzy logic or a machine learning model; the number of phase intervals can be selected between 4 and 16.

[0140] In the prior art, the full-cycle statistics method accumulates all high-frequency pulses in the entire power frequency cycle without distinction, which loses the phase information of the occurrence of the pulses. The high-frequency pulses generated by the above-mentioned interfering loads during normal operation have a specific distribution in phase—for example, the pulses of a variable frequency air conditioner are concentrated at the moment of PWM switching (usually located in the voltage peak region), and the pulses of a thyristor dimmer are concentrated at the trigger conduction moment (voltage rising / falling region), which is essentially different from the zero-crossing / peak phase feature of a real arc.

[0141] The method according to the embodiments of the present application, after phase partitioning, assigns low weights to pulses generated by interfering loads in their non-dominant intervals, which effectively suppresses the contribution of interference, while assigns high weights to pulses generated by real arcs in their dominant intervals, maintaining high detection capability. Therefore, the false judgment rate is greatly reduced without reducing the detection sensitivity, and the false action rate under typical interfering loads can be reduced by 85% to 95%.

[0142] The method in this application embodiment considers that a real electric arc generates a current zero-crossing and reignition high-frequency pulse near the current zero-crossing point, and that the characteristic phase changes with the load type: resistive loads appear near the voltage zero-crossing point, while inductive loads move to the voltage peak area. Based on the hardware zero-crossing pulse, the power frequency cycle is divided into multiple phase intervals, and differentiating weights are assigned to each interval in combination with the load type. Differentiated arc feature identification is performed under different phase partitions, which effectively achieves accurate differentiation between real electric arcs and interference.

[0143] Based on the methods in the above embodiments, this application provides an electronic device, such as... Figure 7 As shown, the electronic device may include a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other via the communication bus 740. The processor 710 can call logical instructions in the memory 730 to execute the methods in the above embodiments.

[0144] Furthermore, the logical instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application.

[0145] Based on the methods in the above embodiments, this application provides a computer-readable storage medium storing a computer program that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0146] Based on the methods in the above embodiments, this application provides a computer program product that, when run on a processor, causes the processor to execute the methods in the above embodiments.

[0147] It is understood that the processor in the embodiments of this application can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. A general-purpose processor can be a microprocessor or any conventional processor.

[0148] The method steps in this application embodiment can be implemented in hardware or by a processor executing software instructions. The software instructions can consist of corresponding software modules, which can be stored in random access memory (RAM), flash memory, read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), registers, hard disks, portable hard disks, CD-ROMs, or any other form of storage medium known in the art. An exemplary storage medium is coupled to the processor, enabling the processor to read information from and write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can reside in an ASIC.

[0149] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially as a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted through the computer-readable storage medium. The computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state disk (SSD)).

[0150] It is understood that the various numerical designations used in the embodiments of this application are merely for the convenience of description and are not intended to limit the scope of the embodiments of this application.

[0151] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0152] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0153] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A fault arc detection device based on voltage zero-crossing point partitioning, characterized in that, include: A signal processing unit, and a voltage zero-crossing detection circuit, a low-frequency sampling circuit, and a high-frequency sampling circuit respectively connected to the signal processing unit; The voltage zero-crossing detection circuit is used to detect the voltage zero-crossing point of the power supply signal at different times. The low-frequency sampling circuit is used to acquire the target low-frequency voltage signal in the power supply signal; The high-frequency sampling circuit is used to acquire the target high-frequency voltage signal in the power supply signal; The signal processing unit is used to determine the corresponding power frequency period with each of the voltage zero crossings as the starting point, and to divide the phase range corresponding to each power frequency period into multiple phase intervals. Based on the target low-frequency voltage signal and target high-frequency voltage signal in each phase interval, arc signal feature extraction and fusion analysis are performed to determine whether there is a fault arc in the target time period. The target time period is determined based on a preset number of power frequency cycles.

2. The fault arc detection device according to claim 1, characterized in that, The low-frequency sampling circuit includes a sampling resistor, a differential amplifier, and a low-pass filter connected in sequence; the low-pass filter is connected to the signal processing unit. The sampling resistor is used to sample the low-frequency current signal in the power supply signal and convert the low-frequency current signal into a low-frequency voltage signal. The differential amplifier is used to differentially amplify the low-frequency voltage signal and output a first amplified signal; The low-pass filter is used to filter and convert the first amplified signal to output the target low-frequency voltage signal.

3. The fault arc detection device according to claim 1, characterized in that, The high-frequency sampling circuit includes a high-frequency current sensor, a bandpass filter module, an amplification module, and a shaping module connected in sequence; the shaping module is connected to the signal processing unit. The high-frequency current sensor is used to couple the high-frequency current signal in the power supply signal and convert the high-frequency current signal into a high-frequency voltage signal. The bandpass filter module is used to extract the arc characteristic frequency band signal from the high-frequency voltage signal; The amplification module is used to amplify the amplitude of the arc characteristic frequency band signal and output a second amplified signal. The shaping module is used to convert the second amplified signal into a target high-frequency voltage signal.

4. The fault arc detection device according to claim 1, characterized in that, The voltage zero-crossing detection circuit includes a resistor divider network and a comparator connected in sequence, and the comparator is connected to the signal processing unit. The resistor divider network is used to divide the power supply signal and output a divided voltage signal; The comparator is used to output a square wave signal based on the voltage divider signal, so as to determine the zero-crossing point of the power supply signal at different times based on the square wave signal.

5. A method for detecting fault arcs applied to the fault arc detection device as described in any one of claims 1-4, characterized in that, include: S1, acquire the zero-crossing point of the power signal at different times, as well as the target low-frequency voltage signal and the target high-frequency voltage signal in the power signal; S2, using each of the voltage zero-crossing points as the starting point to determine the corresponding power frequency period, and dividing the phase range corresponding to each power frequency period into multiple phase intervals; S3, based on the target low-frequency voltage signal and target high-frequency voltage signal in each phase interval, perform arc signal feature extraction and fusion analysis to determine whether there is a fault arc in the target time period; the target time period is determined based on a preset number of power frequency cycles.

6. The fault arc detection method according to claim 5, characterized in that, S3 specifically includes: S31, based on the target low-frequency current signal corresponding to the target low-frequency voltage signal in each phase interval of each power frequency cycle, determine the load type corresponding to each power frequency cycle and the zero-sink depth corresponding to each phase interval, and based on the target high-frequency voltage signal in each phase interval, determine the comprehensive high-frequency characteristics corresponding to each phase interval. S32, determine the weight information corresponding to each phase interval according to the load type; S33, based on the zero-rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval of each power frequency cycle, perform fusion analysis to determine whether there is a fault arc in the target time period.

7. The fault arc detection method according to claim 6, characterized in that, The specific steps for determining the load type corresponding to each power frequency cycle include: Based on the target low-frequency current signal within each power frequency cycle, determine the power factor and total harmonic distortion rate; When it is determined that the power factor is not less than the power factor threshold and the total harmonic distortion rate is not greater than the first distortion threshold, the load type is determined to be a resistive load. or, When it is determined that the power factor is less than the power factor threshold, the total harmonic distortion rate is greater than the first distortion threshold but not greater than the second distortion threshold, and the current phase lags behind the voltage phase, the load type is determined to be an inductive load. or, When it is determined that the power factor is less than the power factor threshold, the total harmonic distortion rate is greater than the first distortion threshold but not greater than the second distortion threshold, and the current phase leads the voltage phase, the load type is determined to be a capacitive load. or, When the total harmonic distortion rate is determined to be greater than the second distortion threshold, the load type is determined to be a nonlinear load.

8. The fault arc detection method according to claim 6, characterized in that, The specific steps for determining the comprehensive high-frequency characteristics corresponding to each phase interval include: The total number of high-frequency pulses corresponding to each phase interval is determined based on the number of high-frequency pulse events that occur in the target high-frequency voltage signal within the corresponding time period of each phase interval. The number of high-frequency pulse clusters corresponding to each phase interval is determined based on the frequency of high-frequency pulse events that occur in the target high-frequency voltage signal within the corresponding time period of each phase interval. Based on the total number of high-frequency pulses and the number of high-frequency pulse clusters corresponding to each phase interval, the comprehensive high-frequency characteristics corresponding to each phase interval are determined.

9. The fault arc detection method according to claim 6, characterized in that, The specific steps for determining the zero-rest depth corresponding to each phase interval include: Based on the zero-crossing information of the target low-frequency current signal within each phase interval, multiple zero-crossing analysis windows corresponding to each phase interval are determined. Within each zero-current analysis window, the actual current deviation at each sampling point is calculated, and the maximum actual current deviation is selected as the zero-current depth corresponding to each zero-current analysis window. The zero-rest depth corresponding to each phase interval is obtained based on the maximum value in the zero-rest depth corresponding to each zero-rest analysis window.

10. The fault arc detection method according to any one of claims 6-9, characterized in that, S33 specifically includes: For any power frequency cycle, the comprehensive score of the fault arc corresponding to any power frequency cycle is determined by weighted calculation using the zero rest depth, comprehensive high-frequency characteristics and weight information corresponding to each phase interval; Based on the load type and fault arc comprehensive score corresponding to any power frequency cycle, determine whether there is a suspected fault arc within any power frequency cycle; Determine the number of power frequency cycles in which a faulty arc is suspected within the target time period; If the number of power frequency cycles is determined to be not less than the target number threshold, then a fault arc is determined to exist within the target time period.

Images