A plastic package device failure detection method and system

Abstract

This invention provides a method and system for detecting failures in molded devices, relating to the field of molded device failure analysis technology. The invention removes a portion of the molding compound material above the chip in a molded device, obtaining a decapped molded device. A test voltage, not exceeding the normal operating voltage range of the chip, is applied to the decapped molded device. Under this test voltage, abnormal heating points on the top surface of the decapped molded device are located using infrared detection. The locations of these abnormal heating points distributed along the chip edge are identified as candidate short-circuit failure points. The decapped molded device is then sliced ​​at these suspected short-circuit failure points, and the distribution of conductive adhesive along the chip edge in the slice cross-section is used to determine whether the short-circuit failure is caused by conductive adhesive overflow. This method ensures the originality and integrity of the failure characteristics while simultaneously determining the location of short circuits caused by conductive adhesive overflow, identifying the location of short circuits without damaging the structure of the adhesive overflow anomaly points.

Description

Technical Field

[0001] This invention relates to the field of failure analysis technology for molded devices, and in particular to a method and system for detecting failures in molded devices. Background Technology

[0002] Molded form factor devices (MPPs) dominate the integrated circuit and semiconductor fields due to their extremely low production costs and strong scalability. MPPs are electronic devices in which a chip, substrate, and internal electrical interconnects are encapsulated and sealed using a molding compound. MPPs include a chip, substrate, conductive adhesive, and the molding compound encapsulating the chip, substrate, and conductive adhesive. The chip is fixed to the substrate using the conductive adhesive.

[0003] Conductive adhesive creep is a common and challenging process defect in molded devices. Conductive adhesive creep refers to the excessive climbing of conductive adhesive along the side of the chip during curing. Creeping conductive adhesive can contaminate the chip surface, causing short circuits; uneven adhesive distribution can generate localized stress, affecting the mechanical and thermal reliability of the chip, and consequently impacting the long-term reliability of the device.

[0004] Because of the plastic covering, abnormal structures cannot be directly observed during failure analysis, making it difficult to pinpoint the exact location of adhesive creep short circuits. Currently, conventional detection methods such as X-ray inspection and acoustic scanning microscopy lack sufficient resolution and contrast to clearly distinguish the interface between the conductive adhesive, the encapsulating material, and the chip, especially when the amount of conductive adhesive creep is small. This makes it difficult to accurately detect and locate the creep. Furthermore, when using chemical etching to open the package and observe the internal components, it is impossible to selectively remove the encapsulating material without damaging the conductive adhesive. It is also highly susceptible to accidentally corroding the conductive adhesive due to improper control of the acid dosage, thus obscuring the failure phenomenon. Summary of the Invention

[0005] This invention provides a method and system for detecting failures in molded devices, addressing the problem that existing methods struggle to accurately pinpoint the location of short circuits caused by adhesive creep without disrupting the conductive adhesive creep.

[0006] In a first aspect, embodiments of the present invention provide a method for detecting failures of a plastic-encapsulated device, wherein the chip of the plastic-encapsulated device is fixed to a ground electrode on a substrate by conductive adhesive; the method includes: removing a portion of the plastic-encapsulating material above the chip of the plastic-encapsulated device to obtain a plastic-encapsulated device after removing the cap; applying a test voltage not exceeding the normal operating voltage range of the chip to the plastic-encapsulated device after removing the cap, and locating the position of an abnormal heat point on the top surface of the plastic-encapsulated device after removing the cap by infrared detection under the test voltage condition; determining the positions of abnormal heat points distributed on the chip edge as candidate suspected short-circuit failure points; slicing the plastic-encapsulated device after removing the cap at the suspected short-circuit failure point position, and determining whether the short-circuit failure is caused by conductive adhesive overflow based on the distribution of conductive adhesive on the chip edge in the slice cross section.

[0007] In one possible implementation, the front side of the chip is electrically connected to the substrate via bonding wires; removing the plastic encapsulation material of a portion of the thickness above the chip to obtain the encapsulated device includes: using laser scanning to remove the plastic encapsulation material on top of the encapsulated device layer by layer; stopping the laser scanning when the top of the encapsulated device exposes the apex of the bonding wires, thus obtaining the encapsulated device.

[0008] In one possible implementation, removing the plastic encapsulation material on the chip top layer of the plastic-encapsulated device to obtain the plastic-encapsulated device after decapping includes: using laser scanning to remove the plastic encapsulation material on the top of the plastic-encapsulated device layer by layer; when the thickness of the plastic encapsulation material on the chip top layer of the plastic-encapsulated device is reduced to a preset value, the laser scanning is stopped to obtain the plastic-encapsulated device after decapping.

[0009] In one possible implementation, the preset value is 0.1 mm.

[0010] In one possible implementation, the molded device is a field-effect transistor, including a gate, a source, and a drain. Applying a test voltage not exceeding the normal operating voltage range of the chip to the molded device after removing the cap, and locating the position of an abnormal hot spot on the top surface of the molded device after removing the cap by infrared detection under the test voltage condition, includes: applying a gate-source test voltage to the gate and source of the molded device after removing the cap, without applying a test voltage to the drain, and determining whether there is an abnormal hot spot on the top surface of the molded device after removing the cap by infrared detection; applying a test voltage to the drain under the condition that the gate and source are in a non-conductive state, and determining whether there is an abnormal hot spot on the top surface of the molded device after removing the cap by infrared detection.

[0011] In one possible implementation, applying a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device after cap removal, and detecting and locating the location of an abnormal hot spot on the top surface of the encapsulated device under the test voltage condition by infrared detection includes: applying a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device according to a preset variation pattern; acquiring infrared variation signals of the top surface of the encapsulated device under the test voltage condition; and determining the abnormal hot spot when the infrared variation signal of a local area conforms to the preset variation pattern and the peak infrared intensity is greater than a preset threshold.

[0012] In one possible implementation, determining abnormal hot spots on the top surface of the encapsulated device after cap removal by infrared detection under the test voltage condition includes: determining the temperature distribution data of the top surface of the encapsulated device after cap removal by infrared detection under the test voltage condition; comparing the temperature data of the top surface of the encapsulated device after cap removal obtained by infrared detection with a preset temperature threshold; and determining that the local area is an abnormal hot spot when the temperature of a local area on the top surface is higher than the preset temperature threshold.

[0013] In one possible implementation, after determining the abnormal heat point on the top surface of the encapsulated device after removing the cover by infrared detection under the test voltage condition, the method further includes: if the abnormal heat point intersects with the chip edge or the distance to the chip edge is less than a preset value, then the abnormal heat point is determined as an abnormal heat point distributed on the chip edge.

[0014] In one possible implementation, determining whether a short circuit failure is caused by conductive adhesive overflow based on the distribution of conductive adhesive at the chip edge in the slice cross section includes: when conductive adhesive overflows from the slice cross section to the chip edge and the ground electrode, and the overflow overlaps the chip electrode and the ground electrode, it is determined to be a short circuit failure caused by conductive adhesive overflow.

[0015] Secondly, embodiments of the present invention provide a failure detection system for molded devices, including a control module for controlling a molding compound removal module to perform a partial cap removal operation; a power-on and detection module for applying a test voltage to the device after cap removal and simultaneously acquiring infrared thermographic data; a data analysis module for processing the infrared thermographic data to identify abnormal hot spots on the chip edge and generating a slicing position instruction; and a slicing module for slicing the device according to the slicing position instruction.

[0016] This invention provides a method and system for detecting failures in molded devices. By removing only a portion of the molding compound material above the chip during the cap removal process, while retaining a portion of the molding compound material in the corresponding area, damage to the chip and conductive adhesive structure can be avoided. This preserves the original abnormal morphology of conductive adhesive overflow and creep at the chip edge. Therefore, this opens a "window" for subsequent infrared detection and avoids the destruction of the original morphology of conductive adhesive creep caused by traditional methods such as complete cap removal or chemical etching, ensuring the integrity and authenticity of the failure characteristics and providing a basis for accurate analysis of the failure cause.

[0017] Based on this, by applying a test voltage within the chip's normal operating range, infrared detection is used to identify abnormal heating points on the top surface of the device, and abnormal heating points on the chip's edge are identified as short-circuit failure points, thus initially locating short-circuit locations that are obscured by plastic and cannot be directly observed. By applying a safe test voltage, microscopic leakage points (i.e., abnormal heating points) caused by abnormal conductive adhesive can be located non-destructively and visually. Compared to X-ray and acoustic scanning, this method significantly improves the accuracy and sensitivity of locating minute short-circuit defects.

[0018] Subsequently, the short-circuit failure point was sliced, and the cause of failure was determined based on the actual distribution of conductive adhesive in the slice cross section. The entire process did not require destroying the failure structure of the abnormal conductive adhesive creep, which not only ensured the originality and integrity of the failure characteristics, but also realized the determination of the short circuit location caused by the overflow of conductive adhesive. The location of the creep short circuit was determined without destroying the structure of the abnormal creep point.

[0019] Guided by infrared positioning, precise slicing is performed, narrowing the observation range from the entire chip to tiny suspected failure points. This avoids the inefficiency and waste of samples caused by blind slicing, significantly improving the efficiency and success rate of failure analysis, and ultimately revealing the cause of short circuits due to conductive adhesive overflow in a complete and reliable manner. Attached Figure Description

[0020] Figure 1 This is a schematic diagram of the structure of a plastic-encapsulated device provided in an embodiment of the present invention; Figure 2 This is a flowchart illustrating the implementation of a failure detection method for plastic-encapsulated devices provided in an embodiment of the present invention; Figure 3 This is a schematic diagram of the top surface structure of the encapsulated device after the cap has been removed, according to an embodiment of the present invention. Figure 4 This is a schematic diagram of infrared thermal imaging of a plastic-encapsulated device provided in an embodiment of the present invention; Figure 5 This is a schematic diagram of the slice cross-section structure provided in an embodiment of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand this solution, the technical solutions in the embodiments of this solution will be clearly described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this solution, not all of them. Based on the embodiments of this solution, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this solution.

[0022] The term "comprising" and any other variations thereof in the specification, claims, and accompanying drawings of this invention mean "including but not limited to," and are intended to cover a non-exclusive inclusion, not limited to the examples listed herein. Furthermore, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order.

[0023] The implementation of the present invention will be described in detail below with reference to the accompanying drawings: Failure analysis of molded devices refers to the technical process of determining the failure mode, failure location, failure mechanism, and cause of failure of molded devices that exhibit abnormal electrical performance, functional failure, or substandard reliability through failure detection and analysis methods.

[0024] The failure detection method of this invention can be widely applied to relevant testing scenarios for molded devices, specifically as follows: It can be applied to failed molded devices obtained after preliminary screening processes such as performance testing and aging testing, using this method to locate the failure location and determine whether the short circuit failure is caused by conductive adhesive overflow and creep; It can also be applied to verification molded devices used in the molding process verification process, using this method to detect the distribution state of conductive adhesive inside the device, thereby determining whether conductive adhesive creep occurs during the molding process, providing technical support for the optimization and reliability verification of the molding process.

[0025] In plastic-encapsulated devices, the conductive adhesive placed between the back of the chip and the substrate primarily serves three functions: electrical conductivity, chip fixation, and heat conduction. On one hand, it provides an electrical connection path between the chip and the substrate, enabling grounding; on the other hand, it securely bonds the chip to the substrate, ensuring the mechanical stability of the device's internal structure; simultaneously, it acts as a thermal conductive medium, efficiently transferring the heat generated during chip operation to the substrate, thus achieving heat dissipation and temperature control of the device.

[0026] In the failure analysis of conductive adhesive creep in molded devices, it is necessary not only to determine whether conductive adhesive creep exists, but also whether the creep has caused a short circuit failure. For example, when conductive adhesive creeps from the back of the chip to the front, connecting the back ground electrode to the front functional electrode, the current of the front functional electrode will be directly short-circuited to the ground terminal.

[0027] Since the molding compound encapsulates the chip, substrate, and conductive adhesive to form a sealed package structure, when the conductive adhesive overflows from the back of the chip and spreads to the front of the chip, it can easily cause an abnormal short circuit between the front electrode of the chip and the back electrode of the substrate. Furthermore, the encapsulation of the molding compound makes it impossible to observe the failure points and internal failure structures caused by the overflow of conductive adhesive through direct visual inspection.

[0028] In existing failure analysis techniques for plastic-encapsulated devices, conventional detection methods all have significant limitations: 1. When using X-ray inspection or acoustic scanning microscope inspection, it is impossible to directly observe the abnormal structure of conductive adhesive creep inside the device, and it is also difficult to accurately locate the specific location of the short circuit caused by the creep. Even if creep signs can be detected in some scenarios, it is impossible to determine whether the creep actually causes the device to fail due to a short circuit.

[0029] 2. Conventional electrical testing methods can only detect short circuits in devices, but cannot pinpoint the exact location of conductive adhesive creep.

[0030] 3. While chemical etching can expose the internal structure of the device and allow for visual observation of the adhesive creep location, it is very easy for the conductive adhesive to be corroded and damaged due to the difficulty in accurately controlling the amount of acid and the degree of corrosion, which directly destroys the original structure and failure characteristics of the adhesive creep failure point.

[0031] This presents a technical dilemma: without exposing the internal structure, failure points cannot be visually detected; however, directly exposing the internal structure easily damages the abnormal adhesive creep points. Therefore, it is difficult to determine the specific location of the short circuit while preserving the original morphology of the conductive adhesive creep failure point.

[0032] This invention removes a portion of the plastic material from the top of the encapsulated device to expose abnormal heat points when energized, thereby determining the location of short-circuit failure caused by excess conductive adhesive without disrupting the abnormal adhesive creep.

[0033] Figure 1 This is a schematic diagram of a plastic-encapsulated device provided in an embodiment of the present invention. (Refer to...) Figure 1 The chip 1 of the plastic-encapsulated device is fixed to the ground electrode of the substrate 3 by conductive adhesive 2.

[0034] For example, the inside of the plastic-encapsulated device is encapsulated with a chip and a packaging substrate by a plastic encapsulation material 4; the chip adopts a front-mounted bonding structure, with a source, drain and gate on the front side of the chip, and a ground electrode on the back side of the chip, which is fixed to the ground electrode of the packaging substrate by conductive adhesive; the front electrode of the chip can be electrically connected to the packaging substrate through bonding leads 5.

[0035] In a chip packaging structure, the conductive adhesive between the back of the chip and the packaging substrate is prone to overflow and spread: when the conductive adhesive overflows from the back of the chip and spreads to the front of the chip, it may cross the protection area of ​​the passivation layer on the front of the chip and directly connect the front electrode of the chip to the ground electrode on the back of the chip, or connect the front electrode of the chip to the ground electrode of the packaging substrate, so that the front electrode of the chip and the ground terminal form an abnormal electrical path, which ultimately directly causes the short circuit failure of the plastic packaged device.

[0036] Figure 2 This is a flowchart illustrating the implementation of a failure detection method for plastic-encapsulated devices according to an embodiment of the present invention. (Refer to...) Figure 2 The method includes: Step 201: Remove the plastic encapsulation material from the top portion of the chip of the plastic-encapsulated device to obtain the plastic-encapsulated device after removing the cap.

[0037] It should be noted that the molding compound of molded devices is typically an opaque insulating material with certain heat insulation and shielding properties. Without removing the cap, the molding compound on top of the chip will completely block internal heat signals. When a short circuit occurs, the infrared radiation generated by the abnormal heat source cannot penetrate the intact molding compound, preventing infrared detection equipment from detecting the heat signal and thus making it impossible to locate the short circuit failure point.

[0038] Meanwhile, this step uses a partial removal and partial retention method for removing the encapsulation material, rather than completely removing it. This avoids complete obstruction by the encapsulation material, allowing the infrared signal to penetrate the remaining encapsulation material and be captured by the detection equipment, thus enabling the identification of abnormal heat points. It also preserves the original structure of the chip periphery and conductive adhesive, preventing the conductive adhesive failure points from being destroyed due to the complete removal of the encapsulation material, and providing a complete structural basis for subsequent failure cause verification.

[0039] For example, in the vertical projection direction, only the encapsulation material within the vertical projection range of the chip can be removed, that is, only a window is opened within the chip range; another example is that the encapsulation material within the vertical projection range of the encapsulated device can also be removed.

[0040] In this step, the ideal state for preserving the encapsulating material is to just expose the top of the conductive adhesive overflow. This avoids the encapsulating material blocking the infrared heating signal while preserving the damaged structure intact. However, in practice, the location and thickness of the conductive adhesive overflow vary from person to person, making it difficult to precisely control the amount of encapsulating material removed. Removing too much can damage the conductive adhesive, while removing too little will fail to meet the testing requirements.

[0041] Based on the aforementioned practical operational difficulties, this application achieves reasonable removal of molding compound material through two different control methods in two embodiments: Embodiment 1 uses the bonding wire apex as the control benchmark, and stops removal when the laser scan exposes the bonding wire apex, indirectly ensuring that the molding compound material above the chip is removed as much as possible without damaging the conductive adhesive due to excessive removal; Embodiment 2 uses a preset thickness as the control standard, reducing the thickness of the molding compound material above the chip to a preset value, which reduces the obstruction of the molding compound material, and avoids damage to the conductive adhesive creeping structure by retaining a fixed thickness of molding compound material. From a practical operational perspective, it balances the molding compound material removal effect with the integrity of the conductive adhesive structure.

[0042] In one possible implementation, the front side of the chip is electrically connected to the substrate via bonding wires; removing the plastic encapsulation material of a portion of the thickness above the chip to obtain the encapsulated device includes: using laser scanning to remove the plastic encapsulation material on top of the encapsulated device layer by layer; stopping the laser scanning when the top of the encapsulated device exposes the apex of the bonding wires, thus obtaining the encapsulated device.

[0043] This implementation uses laser scanning to remove the molding compound on top of the chip layer by layer, with the exposure of the bonding wire apex serving as the stopping criterion. Using the exposure of the bonding wire apex as the stopping condition ensures maximum exposure of the chip surface, facilitating subsequent infrared detection, while avoiding damage to the bonding wire.

[0044] The top of the bonding wire is usually higher than the chip surface and close to the chip surface. Using this as a visual control benchmark, the depth of molding compound removal can be controlled. This can not only reduce the thickness of the molding compound layer on the chip to the greatest extent, but also reliably avoid laser damage to the chip surface, thus fully protecting the original failure structure of the chip and conductive adhesive.

[0045] After removing the cover, only a thin layer of encapsulating material remains on top of the chip. This thickness allows visible light to pass through to a certain extent, meeting the needs of initial visual observation. At the same time, it significantly reduces the obstruction of infrared thermal signals on the chip surface, ensuring that subsequent infrared detection can clearly capture the heat distribution.

[0046] In addition, this cap removal method only removes the molding compound, leaving the bonding wires intact and undamaged. Test voltage can be applied directly to the device from the outside, ensuring stable and feasible power-on testing.

[0047] This solution eliminates the need to predict the location of conductive adhesive overflow and achieves a simple and controllable cap removal operation based on the inherent structure of the lead wire. While simplifying the process, it also ensures the effectiveness of removing the plastic sealant and protecting the internal structure.

[0048] In one possible implementation, removing the plastic encapsulation material on the chip top layer of the plastic-encapsulated device to obtain the plastic-encapsulated device after decapping includes: using laser scanning to remove the plastic encapsulation material on the top of the plastic-encapsulated device layer by layer; when the thickness of the plastic encapsulation material on the chip top layer of the plastic-encapsulated device is reduced to a preset value, the laser scanning is stopped to obtain the plastic-encapsulated device after decapping.

[0049] This solution stops when the remaining molding compound thickness decreases to a preset value. It is suitable for molded devices without bonding wires or whose bonding wire layout does not obstruct the chip edge, and can precisely control the decapping depth.

[0050] For example, the preset value is 0.1 mm. It should be noted that the preset value can be determined based on simulation or experimentation of factors such as chip thickness and thermal conductivity of the molding compound.

[0051] This solution uses the reduction of the plastic encapsulation material thickness above the chip to a preset value as the criterion for stopping cap removal. At this point, the chip and conductive adhesive surface will be exposed, but not yet fully exposed. This approach replaces visual judgment of the internal structure with a quantified and controllable thickness threshold. Maintaining a thin layer of plastic encapsulation material above the chip minimizes the obstruction of infrared thermal signals by the encapsulation material, allowing abnormal heating on the chip surface to be clearly detected by infrared devices. Simultaneously, the thin plastic encapsulation layer allows visible light transmittance, meeting the needs of initial visual observation.

[0052] Meanwhile, the molding layer of this thickness can serve as a physical protective layer, preventing laser scanning or subsequent operations from directly contacting the chip surface, bonding wires, and conductive adhesive area. This fundamentally prevents the failure structure caused by conductive adhesive overflow from being destroyed, and completely preserves the original characteristics of short-circuit failure.

[0053] Compared to the cap removal method based on the internal structure, the fixed preset thickness is used as the control condition, which makes the process judgment simpler and the execution more stable, without relying on the exposed state of the internal structure.

[0054] Step 202: Apply a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device after removing the cap, and locate the abnormal hot spot on the top surface of the encapsulated device by infrared detection under the test voltage condition.

[0055] This step combines safe power-on with infrared detection to capture abnormal heating characteristics caused by short circuits in the conductive adhesive, thus pinpointing the location of the failure.

[0056] For example, this step applies DC power to the molded device, causing the chip to heat up or heat up only slightly, but the short-circuit point to heat up significantly. "No heat from the chip but heat from the short-circuit point" means the device is in a pinch-off state; applying a specific voltage to the chip results in no heat dissipation, and the chip does not heat up. "Slight heat but current flowing through the short-circuit point" means applying a voltage much lower than the normal operating voltage to the chip, putting it in a low-heat-dissipation state, and the chip heats up only slightly. "Significant heat from the short-circuit point" means controlling the short-circuit current by controlling the power supply's protective current, causing the short-circuit point to heat up significantly. The short-circuit heating point is the point whose temperature is significantly higher than the surrounding chip surface temperature.

[0057] Different chips have different electrode layouts and operating principles, resulting in varying normal operating voltages. This step limits the test voltage to within the chip's normal operating voltage range. If the device is not short-circuited, it will operate normally without generating excessive heat. If a short circuit exists, the short-circuit location will generate significant heat due to abnormal current conduction, which can preliminarily determine that the abnormal heat point is likely a short circuit. For example, applying the test at the lower limit of the normal operating voltage can minimize the chip's own normal operating heat generation, avoid interfering with the heat identification of short circuit points, and improve detection accuracy.

[0058] In the short-circuit scenario described in this application, the root cause of the short circuit is the abnormal path formed by the overflow of conductive adhesive. In this short-circuit path, the conductive adhesive, as the conductive medium, has relatively high resistance and is the most prone to abnormal heat generation. The heat generation location often corresponds to the chip edge (the core area of ​​conductive adhesive overflow), but may also appear at the bonding leads or the front electrode of the chip. If the conductive adhesive overflows and overlaps with the front electrode and the ground terminal, or overlaps with the bonding lead and the electrode, the corresponding location will generate heat due to short-circuit conduction. Infrared detection can capture this heat generation signal, thereby establishing a correlation between the conductive adhesive overflow and the short circuit.

[0059] In this embodiment, the infrared detection observes the front of the chip. The core principle is to distinguish between short-circuit abnormal heating and normal chip operating heat by using an infrared intensity threshold. When the chip is operating normally, devices such as power transistors generate basic heat, corresponding to a stable infrared intensity range. This infrared intensity is an inherent characteristic of normal device operation and falls within the reasonable range of heating. However, heating caused by a short circuit is excessive heat generated by abnormal current conduction, and its infrared intensity is much higher than that during normal operation. There is a significant difference between the two, which can be distinguished by setting a preset infrared intensity threshold.

[0060] The preset infrared intensity threshold is set based on the infrared intensity when the chip is working normally, and is usually higher than the maximum infrared intensity when the chip is working normally, so as to exclude interference from normal heat generation. When infrared detection observes that the infrared intensity at a certain point on the front of the chip is greater than the preset value, it indicates that the heat generation at that location is beyond the normal working range and is not heat generated by normal chip operation. It is most likely abnormal heat generation caused by short circuit of conductive adhesive creep.

[0061] It should be noted that applying a test voltage to the chip can either power each terminal individually or fully simulate the electrical conditions under which the chip actually works normally.

[0062] The core purpose of this power-on method is to establish a standardized current path consistent with actual operation between the packaging substrate (corresponding to the back ground plane of the chip) and the front electrodes of the chip (e.g., source, drain, gate). In normal device design, the front electrodes and the back ground plane are mutually insulated; direct electrical contact between them is strictly prohibited. This is a fundamental structural requirement for the device to function properly.

[0063] Under the aforementioned normal insulation conditions, a test voltage simulating operation is applied. If there is no internal failure in the chip, the current will only flow along the preset functional path. However, if the conductive adhesive overflows and creeps, an unexpected direct short circuit will be formed between the front electrode and the back ground layer of the chip. At this point, by capturing abnormal heating with infrared detection, it is possible to accurately determine whether a short circuit path exists between the front and back of the chip.

[0064] The following examples use field-effect transistors to illustrate the power-on test process.

[0065] In one possible implementation, the molded device is a field-effect transistor, including a gate, a source, and a drain. Applying a test voltage not exceeding the normal operating voltage range of the chip to the molded device after removing the cap, and locating the position of an abnormal hot spot on the top surface of the molded device after removing the cap by infrared detection under the test voltage condition, includes: applying a gate-source test voltage to the gate and source of the molded device after removing the cap, without applying a test voltage to the drain, and determining whether there is an abnormal hot spot on the top surface of the molded device after removing the cap by infrared detection; applying a test voltage to the drain under the condition that the gate and source are in a non-conductive state, and determining whether there is an abnormal hot spot on the top surface of the molded device after removing the cap by infrared detection.

[0066] The implementation method of this invention is to apply test voltage in different states to detect whether there are abnormal paths at the gate, drain and back of the chip, thereby locating short circuit failures caused by conductive adhesive creep.

[0067] To detect whether the gate is short-circuited, apply a test voltage to the gate source and leave the drain floating. If abnormal heating occurs at this time, it can be directly determined that there is an abnormal short circuit point in the gate.

[0068] To check if the drain is short-circuited, apply a pinch-off voltage to the gate and source to put the device in a pinch-off state, and apply a test voltage to the drain. If heat is generated at this time, it indicates that there is an abnormal short circuit point in the drain.

[0069] This state-based detection method can distinguish between different failure types such as gate short circuit and drain short circuit, and accurately determine the short circuit location and cause of failure without damaging the failed structure.

[0070] In one possible implementation, for a plastic-encapsulated device employing an off-plane electrode structure (e.g., a PN electrode structure), a functional electrode is located on the front side of the chip, and a ground electrode is located on the back side. The front and back sides are insulated from each other during normal operation, forming a controllable conductive path only through the internal PN junction. The power-on testing process of this invention is as follows: First, test conditions simulating normal operation are applied to the device after the cover is removed. A specified voltage is applied between the front functional electrode and the back ground electrode to construct an electric field and current path consistent with actual operation. If the device is not faulty, the current flows only along the designed PN junction direction, and no abnormal heating will occur.

[0071] If conductive adhesive overflows and creeps, it will create a direct short-circuit path between the front electrode and the back ground electrode, bypassing the normal PN junction structure. Under this voltage condition, infrared detection will show that the short-circuit path generates significant abnormal heat due to the large current, and the heat source typically appears at the chip edge, closely corresponding to the area of ​​conductive adhesive overflow.

[0072] To ensure accurate testing, the test voltage is controlled within the normal operating range to avoid overvoltage damage to the chip. By comparing the difference in infrared intensity between normal operating heat generation and abnormal short-circuit heat generation, it is possible to directly determine whether a short circuit caused by conductive adhesive creep exists between the front electrode and the back ground electrode, thereby locating the failure site.

[0073] The above describes the power-on testing method. It should be noted that during the power-on testing process, if the short-circuit point is energized for an extended period, excessive abnormal current can easily burn out the failure point and damage the original structure of the conductive adhesive, making subsequent accurate analysis of the failure cause impossible. Therefore, a short-time heating test method can be used to complete power-on and infrared acquisition within a short period, generating identifiable abnormal heat while avoiding secondary damage to the device.

[0074] After the cap is removed, only a thin layer of plastic encapsulation material remains on top of the chip, which greatly reduces the attenuation of the infrared signal and makes it easier to quickly capture the hot spots. Therefore, the power-on time can be further shortened, and the detection can be completed with less heat accumulation, thus better protecting the failed structure.

[0075] Meanwhile, this invention offers flexible options for power application: it can use a simple DC signal to quickly locate the heat source, or it can use a specifically coded alternating signal for testing. The specifically coded excitation signal can generate an infrared response at the short-circuit point that is significantly different from the normal operating area, improving the identification of abnormal heating and enhancing detection accuracy and anti-interference capabilities.

[0076] The following describes the power-on method for a specific encoded alternating signal.

[0077] In one possible implementation, applying a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device after cap removal, and detecting and locating the location of an abnormal hot spot on the top surface of the encapsulated device under the test voltage condition by infrared detection includes: applying a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device according to a preset variation pattern; acquiring infrared variation signals of the top surface of the encapsulated device under the test voltage condition; and determining the abnormal hot spot when the infrared variation signal of a local area conforms to the preset variation pattern and the peak infrared intensity is greater than a preset threshold.

[0078] In this embodiment of the invention, a specially coded alternating signal is used for power-on testing. By synchronously changing the voltage and infrared signal, normal heating and short-circuit heating can be distinguished, thereby improving the reliability of the detection.

[0079] This invention no longer uses a fixed DC voltage, but instead applies an alternating test voltage within the normal operating voltage range to the encapsulated device after the cap has been removed, according to a preset variation pattern. The short-circuit point forms a low-resistance path due to the conductive adhesive creeping through, and its heat generation strictly follows the voltage variation pattern, while the normal operating heat generation of the chip and environmental interference will not conform to this pattern.

[0080] While applying an alternating voltage, the infrared signal changes on the top surface of the chip are collected. When the infrared signal change in a certain local area closely matches the preset voltage pattern, and the peak infrared intensity exceeds a set threshold, that area can be identified as an abnormal heat source.

[0081] The essence of this method is to use the correlation of patterns as a criterion to significantly reduce the interference caused by environmental factors, background heating, and normal heating of the device itself. Even if the short circuit is weak and the heating is not obvious, it can be accurately identified through signal synchronization, achieving high sensitivity and high anti-interference positioning of short circuit points of conductive adhesive creep.

[0082] In one possible implementation, determining abnormal hot spots on the top surface of the encapsulated device after cap removal by infrared detection under the test voltage condition includes: determining the temperature distribution data of the top surface of the encapsulated device after cap removal by infrared detection under the test voltage condition; comparing the temperature data of the top surface of the encapsulated device after cap removal obtained by infrared detection with a preset temperature threshold; and determining that the local area is an abnormal hot spot when the temperature of a local area on the top surface is higher than the preset temperature threshold.

[0083] In this embodiment of the invention, under the applied test voltage, the complete temperature distribution data of the top surface of the encapsulated device after the cap is removed is first obtained by infrared detection, so as to obtain the real-time temperature information of each region on the chip surface.

[0084] The detected temperature data is compared with a preset temperature threshold. This preset temperature threshold is higher than the normal operating temperature of the chip under normal operating voltage, and is used to distinguish between normal operating heat and abnormal overheating caused by a short circuit. When the temperature of a local area on the top surface of the chip is significantly higher than this preset threshold, it indicates that there is concentrated heat exceeding the normal operating range, which is consistent with the heat generation characteristics of a short circuit failure, and this area can be identified as an abnormal heat point.

[0085] The essence of this determination method is to take advantage of the characteristics of concentrated current and significant temperature rise at the short circuit point, and use the absolute value of temperature as the basis for judgment, so as to quickly and intuitively locate the short circuit caused by conductive adhesive creep.

[0086] In one possible implementation, after determining the abnormal heat point on the top surface of the encapsulated device after removing the cover by infrared detection under the test voltage condition, the method further includes: if the abnormal heat point intersects with the chip edge or the distance to the chip edge is less than a preset value, then the abnormal heat point is determined as an abnormal heat point distributed on the chip edge.

[0087] In this embodiment of the invention, after identifying abnormal hot spots on the top surface of the device through infrared detection, the positional relationship between the hot spots and the chip edge is further combined to screen and determine abnormal hot spots on the chip edge.

[0088] In real-world failure scenarios, conductive adhesive creep does not necessarily lead to a short circuit, and short circuits can also be caused by other factors. To filter out the most likely short circuit caused by conductive adhesive creep from multiple suspected short circuit locations, this implementation utilizes the inherent correlation between the structure and the failure location: the conductive adhesive is located between the back of the chip and the substrate; once creep occurs, it can only spread from the chip edge to the front. Therefore, a short circuit caused by creep will inevitably have its heat source appearing in the chip edge area. By limiting the abnormal heat source to the vicinity of the chip edge, short circuit interference caused by other internal chip factors can be effectively eliminated, improving the accuracy of conductive adhesive creep failure determination.

[0089] Step 203: Identify the locations of abnormal heat points distributed on the edge of the chip as candidate locations of suspected short-circuit failure points; This step identifies abnormally hot spots distributed along the chip edge as potential short-circuit failure locations. It should be noted that once the conductive adhesive between the chip's back and the substrate overflows or creeps, it can only extend along the chip edge towards the front. Therefore, short circuits caused by conductive adhesive creep will inevitably result in hot spots appearing in the chip edge region.

[0090] Among the multiple abnormal heat points detected by infrared imaging, only those located at the chip edge closely matched the failure characteristics of conductive adhesive creep. This location-based screening eliminates heat generation and short-circuit interference caused by other internal chip factors, identifying areas that truly conform to the creep short-circuit mechanism as candidate potential failure points.

[0091] The essence of this step is to transform the heating anomaly detected by infrared into a structurally reliable failure location, providing a reliable target location for subsequent precise slicing and verification of the cause of failure without damaging the internal structure of the device.

[0092] Step 204: Slice the encapsulated device after removing the cover at the suspected short-circuit failure point, and determine whether the short-circuit failure is caused by excess conductive adhesive based on the distribution of conductive adhesive on the chip edge in the slice cross section.

[0093] This step verifies the root cause of short-circuit failure through slicing observation, from locating the failure site to clarifying the cause. It's important to note that slicing in this step refers to precisely cutting the encapsulated device at the identified suspected short-circuit failure location using a directional cutting method. This yields a cross-sectional sample containing the chip edge, conductive adhesive, and encapsulation material. Microscopic observation is then used to visually examine the distribution of various structures within the cross-section. The core function of slicing is to expose the internal microstructure of the short-circuit failure point, providing direct visual evidence for determining the cause of the failure.

[0094] It is important to note that the accuracy of the slicing position directly determines the effectiveness of the failure analysis: if the slicing position deviates from the identified suspected short-circuit failure point, the critical area of ​​conductive adhesive overflow and creep will not be reached, making it impossible to observe the creep phenomenon and thus impossible to accurately determine the cause of the failure. Therefore, the prerequisite for the slicing operation is the identification of the suspected short-circuit failure point on the chip edge as determined in step 203, ensuring that the cross-section can completely show the distribution of conductive adhesive on the chip edge.

[0095] After obtaining cross-sectional samples by slicing, failure analysis can be performed in various ways: professional technicians can use microscopic observation to visually determine whether there is excess or creeping of conductive adhesive in the cross-section, and whether the creeping adhesive overlaps the front electrode and the back ground electrode of the chip, forming a short circuit; or AI image analysis technology can be used to automatically identify the cross-sectional images of the slices, and the algorithm can capture the abnormal distribution characteristics of the conductive adhesive to help determine the cause of failure.

[0096] In one possible implementation, determining whether a short circuit failure is caused by conductive adhesive overflow based on the distribution of conductive adhesive at the chip edge in the slice cross section includes: when conductive adhesive overflows from the slice cross section to the chip edge and the ground electrode, and the overflow overlaps the chip electrode and the ground electrode, it is determined to be a short circuit failure caused by conductive adhesive overflow.

[0097] The core purpose of slicing is to expose the microscopic connections of the chip edges, conductive adhesive, electrodes, and ground electrode. The core mechanism by which conductive adhesive overflow causes short circuits is that the overflow creates an unintended conductive path between the chip electrodes and the ground electrode. Therefore, the key to determining this is to observe whether the distribution of conductive adhesive in the slice cross-section meets the short-circuit conditions for overlapping conduction.

[0098] When microscopic observation or AI image analysis reveals that conductive adhesive overflow occurs within the cross-section of a slice, and the overflow extends to the edge of the chip and between the ground electrode, and the overflow portion directly connects the front electrode of the chip (e.g., source, drain, gate, etc.) to the ground electrode on the back of the chip or the substrate, it can be clearly determined that the short circuit failure is caused by conductive adhesive overflow.

[0099] The essence of this determination method is to verify the short circuit mechanism through microstructural evidence: the conductive adhesive itself is conductive, and its normal distribution is limited to the back of the chip and the substrate. Once the adhesive overflows and overlaps the electrode and the ground terminal, it will form an abnormal conductive path. This corresponds to the suspected short circuit failure point on the edge of the chip located by infrared detection in the early stage. From macroscopic heat generation location to microstructural verification, the root cause of the failure is finally accurately confirmed.

[0100] This invention, in its embodiments, avoids damage to the chip and conductive adhesive structure by removing only a portion of the molding compound above the chip during the cap removal process of the molded device, while retaining a portion of the molding compound in the corresponding area. This preserves the original abnormal morphology of conductive adhesive overflow and creep at the chip edge. Based on this, by applying a test voltage within the chip's normal operating range, and simulating a safe operating condition, infrared detection is used to identify abnormal heat points on the top surface of the device. Abnormal heat points at the chip edge are identified as suspected short-circuit failure points, initially locating short-circuit locations that are obscured by plastic and cannot be directly observed. Subsequently, the suspected short-circuit failure point is sliced, and the cause of failure is determined based on the actual distribution of conductive adhesive in the slice cross-section. This entire process does not require damaging the abnormal structure of the conductive adhesive creep, ensuring both the originality and integrity of the failure characteristics and the determination of the short-circuit location caused by conductive adhesive overflow. The location of the creep short circuit is determined without damaging the structure of the creep abnormal point.

[0101] The following comprehensive embodiment illustrates the technical concept of the present invention. The detection method of this embodiment includes the following five steps: Step 1: Use a laser decapsulation machine to create a window on the surface of the molded device. The window will expose, but not completely expose, the chip and conductive adhesive. In this embodiment, the molded device is a molded GaN power amplifier. The chip surface area is 0.7mm*0.9mm, the conductive adhesive surface area is 0.84mm*1.08mm, and the window size is 1.5mm*2mm. During the decapsulation process, the decapsulation can be stopped when the bonding wire is exposed on the surface. At this point, the chip and conductive adhesive will be partially exposed. Figure 3 This is a schematic diagram of the top surface structure of the encapsulated device after the cap has been removed, according to an embodiment of the present invention; see reference. Figure 3 The black line in the diagram represents the exposed bonding wire 5.

[0102] Step 2: Apply DC power to the molded device so that the chip does not heat up, but the short-circuit point does. In this embodiment, the molded device needs to be supplied with specific gate and drain voltages so that the chip of the molded device has no heat dissipation and does not heat up. The leakage current protection current is set to 50mA, and the short-circuit heating point can be clearly observed.

[0103] Step 3: Locate the short-circuit heating point of the molded device using infrared thermal imaging technology. In this embodiment, an infrared thermal imager is used for infrared testing. During the test, the test fixture with the molded device soldered on is fixed on the heating platform, and thermal grease is evenly applied to the bottom of the test fixture to ensure good contact and heat transfer between it and the heating platform. After the current stabilizes, a true thermal distribution image is acquired. Figure 4 This is a schematic diagram of infrared thermal imaging of a plastic-encapsulated device provided in an embodiment of the present invention, as shown below. Figure 4As shown, a clear short-circuit heating point can be seen at the location of the dashed box, and the temperature at this point is significantly higher than the surrounding temperature.

[0104] Step 4: Prepare a cross-section sample of the short-circuit heating point. In this embodiment, the encapsulated device is cut at the short-circuit heating point, then embedded in resin, and subjected to a series of grinding, polishing, and cleaning processes to finally obtain a smooth, flat, deformation-free observation surface with a clear cross-section.

[0105] Step 5: Examine the prepared sample under a microscope to confirm whether the failure was caused by the conductive adhesive creeping. The results of the microscopic examination in this embodiment are as follows: Figure 5 As shown, Figure 5 This is a schematic diagram of a slice cross-sectional structure provided in an embodiment of the present invention. From... Figure 5 It can be clearly observed that the conductive adhesive has spread to the surface of the chip, thus confirming that the device failure was caused by the spread of the conductive adhesive.

[0106] This invention provides a failure detection system for molded devices, including a control module for controlling a molding compound removal module to perform partial cap removal; a power-on and detection module for applying a test voltage to the device after cap removal and simultaneously acquiring infrared thermographic data; a data analysis module for processing the infrared thermographic data to identify abnormal hot spots on the chip edge and generating a slicing position instruction; and a slicing module for slicing the device according to the slicing position instruction.

[0107] The molding material removal module is used to controllably thin the molding material on the top of the device, reducing infrared signal obstruction without damaging the chip and internal structure, and ensuring that subsequent heat distribution can be clearly observed.

[0108] The power-on and detection module simulates normal chip operating conditions, applying safe and standardized test voltages to each electrode of the device. This provides the electrical conditions for abnormal heating at short-circuit points. It also collects surface temperature and heat distribution information, identifies abnormal areas exceeding normal heating levels, and, based on location relationships, pinpoints failure points at the chip edges. The data analysis module processes infrared thermographic data to identify abnormal heating points at the chip edges and generates slice location instructions.

[0109] The slicing module is used to perform directional cutting at the located failure point to obtain a cross-section that can be visually observed, and finally confirm whether the conductive adhesive has overflowed or whether the electrodes have overlapped to form a short circuit.

[0110] The entire system integrates and streamlines four key steps: cap removal, power-on, infrared positioning, and slice verification. While preserving the original state of failure as much as possible, it achieves end-to-end detection from positioning to confirmation, and is compatible with the analysis of short-circuit failures of plastic-encapsulated devices caused by conductive adhesive overflow.

[0111] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for detecting failures of molded components, characterized in that, The chip of the plastic-encapsulated device is fixed to the ground electrode of the substrate using conductive adhesive; the method includes: Remove the top portion of the encapsulating material from the chip of the encapsulated device to obtain the encapsulated device after decapping. A test voltage not exceeding the normal operating voltage range of the chip is applied to the encapsulated device after the cap is removed, and the location of the abnormal hot spot on the top surface of the encapsulated device is located by infrared detection under the test voltage condition; The locations of abnormal heat points distributed at the edge of the chip are identified as candidate locations of suspected short-circuit failure points; The encapsulated device after removing the cover is sliced ​​at the suspected short-circuit failure point, and the distribution of conductive adhesive on the chip edge in the slice cross section is used to determine whether the short-circuit failure is caused by conductive adhesive overflow.

2. The failure detection method for molded devices as described in claim 1, characterized in that, The front side of the chip is electrically connected to the substrate via bonding leads; The process of removing the portion of the encapsulating material above the chip in the encapsulated device to obtain the encapsulated device after decapping includes: Laser scanning is used to remove the molding material from the top of the molded device layer by layer; When the top of the plastic-encapsulated device exposes the bonding wire apex, the laser scanning is stopped, and the plastic-encapsulated device after decapping is obtained.

3. The failure detection method for molded devices as described in claim 1, characterized in that, The process of removing the portion of the encapsulating material above the chip in the encapsulated device to obtain the encapsulated device after decapping includes: Laser scanning is used to remove the molding material from the top of the molded device layer by layer; When the thickness of the encapsulation material on the chip of the encapsulated device decreases to a preset value, the laser scanning stops, and the encapsulated device after the cap is removed is obtained.

4. The failure detection method for molded devices as described in claim 3, characterized in that, The preset value is 0.1 mm.

5. The failure detection method for molded devices as described in claim 1, characterized in that, The plastic-encapsulated device is a field-effect transistor, including a gate, a source, and a drain; Applying a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device after cap removal, and locating the abnormal hot spot on the top surface of the encapsulated device by infrared detection under the test voltage condition includes: A gate-source test voltage is applied to the gate and source of the plastic-encapsulated device after the cap is removed, while no test voltage is applied to the drain. Infrared detection is used to determine whether there are abnormal hot spots on the top surface of the plastic-encapsulated device after the cap is removed. Under the condition that the voltage applied to the gate source puts the source and drain in a non-conductive state, a test voltage is applied to the drain electrode, and infrared detection is used to determine whether there are abnormal hot spots on the top surface of the plastic-encapsulated device after the cover is removed.

6. The failure detection method for molded devices as described in claim 1, characterized in that, Applying a test voltage not exceeding the normal operating voltage range of the chip to the encapsulated device after cap removal, and locating the abnormal hot spot on the top surface of the encapsulated device by infrared detection under the test voltage condition includes: A test voltage not exceeding the normal operating voltage range of the chip is applied to the encapsulated device after the cap is removed, according to a preset variation pattern; Under the test voltage condition, the infrared change signal of the top surface of the plastic-encapsulated device after the cap was removed was collected; When the infrared change signal in a local area conforms to a preset change pattern and the peak infrared intensity is greater than a preset threshold, it is determined to be the abnormal heat point.

7. The method for detecting failure of molded devices as described in claim 1, characterized in that, Under the test voltage conditions, abnormal hot spots on the top surface of the encapsulated device after cap removal were identified by infrared detection, including: Under the test voltage conditions, infrared detection was used to determine the temperature distribution data on the top surface of the plastic-encapsulated device after the cap was removed. The temperature data of the top surface of the plastic-encapsulated device after the cap is removed, obtained by infrared detection, is compared with a preset temperature threshold. If the temperature of a local area on the top surface is higher than the preset temperature threshold, the local area is determined to be an abnormal heat point.

8. The method for detecting failure of molded devices as described in claim 1, characterized in that, After determining the abnormal hot spot on the top surface of the encapsulated device after cap removal using infrared detection under the test voltage condition, the method further includes: If an abnormal heat point intersects with the chip edge or the distance to the chip edge is less than a preset value, then the abnormal heat point is identified as an abnormal heat point distributed on the chip edge.

9. The failure detection method for molded devices as described in claim 1, characterized in that, Based on the distribution of conductive adhesive at the chip edge in the cross-section, determining whether the short circuit failure is caused by conductive adhesive overflow includes: When conductive adhesive overflows from the cross-section of the chip to the area between the chip edge and the ground electrode, and the overflow overlaps the chip electrode and the ground electrode, it is determined to be a short circuit failure caused by the overflow of conductive adhesive.

10. A failure detection system for molded components, characterized in that, include: The control module controls the molding material removal module to perform partial cap removal operations; The power-on and detection module is used to apply a test voltage to the device after the cover is removed and simultaneously acquire infrared thermal image data. The data analysis module is used to process infrared thermal image data to identify abnormal hot spots on the chip edge and generate slice location instructions; And a slicing module, used to slice the device according to the slicing position instruction.

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