A dual-pulse collaborative testing system and method applicable to micron-scale IGBT wafers

Abstract

This invention discloses a dual-pulse collaborative testing system applicable to micron-level IGBT wafers, comprising an automated wafer operation subsystem, a high-power testing subsystem, a synchronous measurement and control and isolation communication subsystem, and an intelligent management and control subsystem. These subsystems are interconnected via a standardized interface protocol. The dual-pulse collaborative testing system and method for micron-level IGBT wafers described in this invention employs a multimodal calibration method combined with micron-level vision-elastic probe card collaborative positioning technology. Through image magnification, servo fine-tuning, and elastic probe cards, it achieves high-precision, rapid alignment, and reliable high-current contact for wafer testing. Through innovative hardware architecture and deep integration of software algorithms, it realizes high-precision positioning, high-current testing, strong anti-interference, and fully automated wafer-level dynamic performance testing.

Description

Technical Field

[0001] This invention relates to the field of dual-pulse collaborative testing technology, and in particular to a dual-pulse collaborative testing system and method applicable to micron-scale IGBT wafers. Background Technology

[0002] The dual-pulse collaborative testing system is a supporting device for inspecting micron-sized IGBT wafers. Insulated-gate bipolar transistors (IGBTs), as core semiconductor devices in power electronics, directly determine the efficiency, reliability, and power density of power conversion systems. With the evolution of semiconductor manufacturing processes towards the micron and even nanometer scales, the research and mass production of micron-sized IGBT wafers has become crucial for achieving high-frequency and miniaturized devices, especially in high-end equipment such as new energy vehicles, photovoltaic inverters, and rail transportation. As technology continues to advance, the requirements for dual-pulse collaborative testing systems are also increasing.

[0003] Existing dual-pulse collaborative testing systems have certain drawbacks. Dual-pulse testing is a core method for evaluating the dynamic performance of IGBTs (such as turn-on loss Eon, turn-off loss Eoff, and reverse recovery characteristics), and its testing accuracy directly affects the screening efficiency and yield of wafer-level devices. However, existing dual-pulse testing systems face the following technical bottlenecks for micron-level IGBT wafers: Insufficient test coordination: In traditional systems, the pulse generation unit and signal acquisition unit are controlled independently. Pulse timing deviations (such as turn-on / turn-off pulse delay > 10ns) lead to increased dynamic parameter measurement errors, making it difficult to match the nanosecond-level switching speed of micron-level devices. Poor wafer-level compatibility: The gate drive voltage of micron-level IGBT wafers is sensitive (typical drive voltage ±15V, tolerance ≤ ±0.5V). Existing system drive modules have high output impedance, which easily introduces noise interference. Furthermore, the impedance matching between the probe station and the test circuit is poor, resulting in gate signal distortion. Weak multi-parameter synchronous acquisition capability: Dynamic testing requires the synchronous acquisition of multiple physical quantities such as voltage (Vce, Vge) and current (Ic), but the sampling rate (usually ≤1GS / s) and synchronization accuracy (>5ns) of existing systems are insufficient, making it impossible to fully capture the transient characteristics of micron-level device switching process; Low testing efficiency: There is a lack of parallel testing mechanisms for wafer arrays, and only a single chip can be tested at a time, which is difficult to meet the high-efficiency screening requirements in the mass production stage. To address this, we propose a dual-pulse collaborative testing system and method applicable to micron-level IGBT wafers. Summary of the Invention

[0004] Technical problem solved: To address the shortcomings of existing technologies, this invention provides a dual-pulse collaborative testing system and method applicable to micron-level IGBT wafers. It employs a multimodal calibration method combined with micron-level vision-elastic probe card collaborative positioning technology. Through image magnification, servo fine-tuning, and elastic probe cards, it achieves high-precision, rapid alignment, and reliable high-current contact for wafer testing. Through innovative hardware architecture and deep integration of software algorithms, it achieves high-precision positioning, high-current testing, strong anti-interference, and fully automated wafer-level dynamic performance testing, effectively solving the problems in the background technology.

[0005] Technical Solution: To achieve the above objectives, the technical solution adopted by this invention is as follows: a dual-pulse collaborative testing system applicable to micron-level IGBT wafers, comprising an automated wafer operation subsystem, a high-power testing subsystem, a synchronous measurement and control and isolation communication subsystem, and an intelligent management and control subsystem, and adopting a four-layer collaborative architecture of mechanical-circuit-measurement and control-software. The automated wafer operation subsystem, high-power testing subsystem, synchronous measurement and control and isolation communication subsystem, and intelligent management and control subsystem are linked through a standardized interface protocol. The automated wafer operation subsystem includes an automated wafer alignment and spring-loaded card testing operation subsystem, which is equipped with a spring-loaded card-type high-current testing interface and adopts a customized elastic probe card. The probe array spacing matches the wafer test points. The high-power testing subsystem includes a highly reliable high-current power testing circuit. The synchronous measurement and control and isolation communication subsystem includes a high-precision instrument combination and fiber optic isolated communication. The intelligent management and control subsystem includes a LabVIEW architecture.

[0006] As a preferred technical solution of this application, the vision of the automated wafer handling subsystem adopts a functional-mechanical collaborative alignment mechanism, integrating a 5-megapixel industrial camera and a 100x optical magnification module. Combined with image recognition algorithms, it uses SURF feature point matching, with a positioning error ≤0.5μm, to achieve sub-micron level recognition of wafer chip arrays. With a servo motor-driven X / Y / Z axis fine-tuning platform, the repeatability positioning accuracy is ±1μm and the response speed is ≤50ms. The software automatically completes the alignment process of image capture-feature matching-platform fine-tuning, compressing the alignment time to within 20s.

[0007] As a preferred technical solution of this application, the single probe contact resistance of the spring-loaded high-current test interface is ≤3mΩ, the rated current is ≥20A, and 10 probes in parallel support a continuous test current of more than 150A. The spring-loaded high-current test interface has a built-in buffer spring structure, and the contact pressure is adjustable from 50-200g to ensure low impedance contact under high current, avoid scratches on the wafer surface, and the damage rate is <0.1%.

[0008] As a preferred technical solution of this application, the high-reliability high-current power test circuit includes a pogopin inter-board interconnection circuit, a UCC21750 driver and protection integrated circuit, and an RCD anti-interference and EMC optimization circuit.

[0009] As a preferred technical solution of this application, the high-precision instrument combination includes an oscilloscope with a bandwidth of 2GHz and a sampling rate of 5GS / s, which simultaneously acquires Vce, Vge, and Ic waveforms. It is equipped with a high-voltage source to output 0-2000V with ripple ≤0.05%. A pulse generator is added with a pulse width adjustment accuracy of 1ns, which can completely capture nanosecond-level transient signals during switching and has a waveform sampling error of <3% with a rise time ≤10ns.

[0010] As a preferred technical solution of this application, the fiber optic isolated communication drive control signal is transmitted with the host computer using single-mode fiber with a transmission rate of 155Mbps and a delay of ≤5ns. It completely isolates common-mode interference on the high and low voltage sides, and the common-mode rejection ratio (CMRR) is ≥80dB. The pulse generator and oscilloscope are synchronized with a 10MHz clock to ensure that the timing deviation of the dual pulses is ≤3ns.

[0011] As a preferred technical solution of this application, the LabVIEW architecture in the intelligent control subsystem includes an automated testing structure, a status monitoring and alarm structure, and a data and remote management structure. The automated testing structure supports three modes: single-chip testing, multi-chip parallel testing, and wafer full array scanning. The status monitoring and alarm structure monitors 12 key parameters in real time, including test current, voltage, temperature, and probe contact resistance, and adopts a three-color LED + buzzer alarm mechanism.

[0012] A dual-pulse collaborative testing method applicable to micron-scale IGBT wafers specifically includes the following steps: S1: Micrometer-level 4- and 6-inch wafer placement, vacuum adsorption: The electrostatic chuck uses a kilovolt-level DC high voltage to generate Coulomb force to adsorb the wafer, and helium gas is introduced to regulate the back temperature to ensure that the wafer's thermal expansion coefficient is matched, so that submicrometer-level detection accuracy can still be maintained even under extreme temperatures. S2: Multimodal fusion alignment: Calibration can be directly recovered from stripe images through optical vision and a ResNet-based deep learning model; S3: Coordinated focusing by optical vision and laser interferometry: The equipment adopts a three-stage alignment strategy: First, coarse positioning is achieved by a robotic arm, then optical vision scans the global alignment marks for secondary calibration, and finally, nanometer-level fine adjustment is achieved by combining a dual-frequency laser interferometer and piezoelectric ceramic drive. S4: High-precision mechanical and environmental control testing: Combining Kalman filtering, real-time compensation is provided for interference such as mechanical vibration and air turbulence. The displacement of the lithography machine stage is monitored in real-time using a laser interferometer, controlling the positioning error to within ±0.3nm. S5: Temperature dynamic error compensation, test motherboard ready: debugging probe station integrates temperature control, vacuum environment and dynamic feedback test conditions; S6: Batch testing and test organization: Combining machine learning to analyze test data, the AI ​​model automatically identifies physical and electrical defects in the 28nm process, integrates new sensors and AI chips, and realizes real-time diagnosis and automatic compensation of the probe station, reducing manual intervention.

[0013] Beneficial effects: Compared with the prior art, the present invention provides a dual-pulse collaborative testing system and method applicable to micron-level IGBT wafers, which has the following beneficial effects: The dual-pulse collaborative testing system and method applicable to micron-level IGBT wafers adopts a multi-modal calibration method and combines micron-level vision-elastic card collaborative positioning technology: through image magnification + servo fine adjustment + elastic probe card, high-precision, fast alignment and reliable contact with high current are achieved in wafer testing, solving the problems of low positioning efficiency and wafer damage in traditional methods; The integrated power solution of pogopin + UCC21750 combines the high current interconnect of pogopin with the integrated drive-protection design of UCC21750, and achieves low noise drive and high reliability protection under 100A test current through RCD anti-interference network optimization. Fiber Optic Synchronous Measurement and Control System: It adopts fiber optic isolated communication and high-precision instrument clock synchronization to control the pulse timing deviation within 5ns, thus solving the bottleneck of poor coordination and severe interference in traditional systems; Optical force transmission and compensation: The force sensor signal is transmitted through an optical fiber bus after optical-to-electric conversion. Combined with the optical-to-electric phase compensation unit to dynamically correct the time delay, the transmission delay of the force feedback data is ensured to be ≤2ns, avoiding force measurement errors caused by electromagnetic interference. Multi-channel parallel intelligent test software: Supports 16-channel parallel testing and remote monitoring, combined with automatic alarm and data memory functions, greatly improving wafer-level testing efficiency and management convenience.

[0014] Employing a predictive-trigger linkage mechanism: The MCU control unit integrates image positioning deviation data and current sampling information. When a positioning deviation exceeding 10μm or a sudden increase in current is detected, a protection action is triggered synchronously, which improves the response speed by 5 times compared to traditional serial logic. Through hardware architecture innovation and deep integration of software algorithms, high-precision positioning, high-current testing, strong anti-interference, and fully automated wafer-level dynamic performance testing are achieved. The entire dual-pulse collaborative testing system has a simple structure, is easy to operate, and performs better than traditional methods. Attached Figure Description

[0015] Figure 1 This is a schematic diagram of a dual-pulse collaborative testing system for micron-scale IGBT wafers according to the present invention.

[0016] Figure 2 This invention provides a dual-pulse collaborative testing multimodal fusion alignment method applicable to micron-scale IGBT wafers.

[0017] Figure 3 This is a schematic diagram of the hardware time difference principle for dual-pulse collaborative testing of fiber optic synchronous test for micron-scale IGBT wafers according to the present invention.

[0018] Figure 4 This is a schematic diagram of a dual-pulse collaborative testing process applicable to micron-scale IGBT wafers according to the present invention. Detailed Implementation

[0019] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings and specific embodiments. However, those skilled in the art will understand that the embodiments described below are some embodiments of the present invention, but not all embodiments, and are only used to illustrate the present invention, and should not be regarded as limiting the scope of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention. Where specific conditions are not specified in the embodiments, conventional conditions or conditions recommended by the manufacturer shall be followed. Where the manufacturers of reagents or instruments are not specified, they are all conventional products that can be purchased commercially.

[0020] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0021] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0022] like Figure 1-4As shown, a dual-pulse collaborative testing system suitable for micron-scale IGBT wafers includes an automated wafer operation subsystem, a high-power testing subsystem, a synchronous measurement and control and isolation communication subsystem, and an intelligent management and control subsystem. It adopts a four-layer collaborative architecture of mechanical-circuit-measurement and control-software. The automated wafer operation subsystem, high-power testing subsystem, synchronous measurement and control and isolation communication subsystem, and intelligent management and control subsystem are linked through a standardized interface protocol. The automated wafer operation subsystem includes an automated wafer alignment and spring-loaded test operation subsystem. The spring-loaded test operation subsystem is equipped with a spring-loaded high-current test interface and uses a customized elastic probe card. The probe array spacing is matched with the wafer test points. The high-power test subsystem includes a highly reliable high-current power test circuit. The synchronous measurement and control and isolation communication subsystem includes a high-precision instrument combination and fiber optic isolated communication. The intelligent management and control subsystem includes a LabVIEW architecture, adopts a multimodal calibration method, and combines micron-level vision-elastic card collaborative positioning technology. Through image magnification, servo fine-tuning, and elastic probe cards, it achieves high-precision, rapid alignment, and reliable high-current contact for wafer testing. Through hardware architecture innovation and deep integration of software algorithms, it realizes high-precision positioning, high-current testing, strong anti-interference, and fully automated wafer-level dynamic performance testing.

[0023] The automated wafer handling subsystem employs a functional-mechanical collaborative alignment mechanism, integrating a 5-megapixel industrial camera and a 100x optical magnification module. Combined with image recognition algorithms and SURF feature point matching, the positioning error is ≤0.5μm, achieving sub-micron level recognition of wafer chip arrays. Paired with a servo motor-driven X / Y / Z axis fine-tuning platform, the repeatability is ±1μm, and the response speed is ≤50ms. The software automatically completes the alignment process of image capture, feature matching, and platform fine-tuning, compressing the alignment time to within 20 seconds.

[0024] The single probe contact resistance of the spring-loaded high-current test interface is ≤3mΩ, the rated current is ≥20A, and 10 probes in parallel support a continuous test current of over 150A. The spring-loaded high-current test interface has a built-in buffer spring structure, and the contact pressure is adjustable from 50-200g to ensure low impedance contact under high current, avoid scratches on the wafer surface, and the damage rate is <0.1%.

[0025] The high-reliability high-current power test circuit includes a pogopin board interconnect circuit, a UCC21750 driver and protection integrated circuit, and an RCD anti-interference and EMC optimization circuit.

[0026] The high-precision instrument combination includes an oscilloscope with a bandwidth of 2GHz and a sampling rate of 5GS / s, which simultaneously acquires Vce, Vge, and Ic waveforms. Paired with a high-voltage source, it outputs 0-2000V with ripple ≤0.05%. An additional pulse generator is added, with a pulse width adjustment accuracy of 1ns, which can completely capture nanosecond-level transient signals during switching. The waveform sampling error is <3% with a rise time ≤10ns.

[0027] The fiber optic isolated communication drive control signal is transmitted with the host computer using single-mode fiber optic cable, with a transmission rate of 155Mbps and a delay of ≤5ns. It completely isolates common-mode interference on the high and low voltage sides, and the common-mode rejection ratio (CMRR) is ≥80dB. The pulse generator and oscilloscope are synchronized with a 10MHz clock to ensure that the timing deviation of the dual pulses is ≤3ns.

[0028] The LabVIEW architecture in the intelligent control subsystem includes an automated testing structure, a status monitoring and alarm structure, and a data and remote management structure. The automated testing structure supports three modes: single-chip testing, multi-chip parallel testing, and wafer full array scanning. The status monitoring and alarm structure monitors 12 key parameters in real time, including test current, voltage, temperature, and probe contact resistance, and uses a three-color LED + buzzer alarm mechanism.

[0029] A dual-pulse collaborative testing method applicable to micron-scale IGBT wafers specifically includes the following steps: S1: Micrometer-level 4- and 6-inch wafer placement, vacuum adsorption: The electrostatic chuck uses a kilovolt-level DC high voltage to generate Coulomb force to adsorb the wafer, and helium gas is introduced to regulate the back temperature to ensure that the wafer's thermal expansion coefficient is matched, so that submicrometer-level detection accuracy can still be maintained even under extreme temperatures. S2: Multimodal fusion alignment: Calibration can be directly recovered from stripe images through optical vision and a ResNet-based deep learning model; S3: Coordinated focusing by optical vision and laser interferometry: The equipment adopts a three-stage alignment strategy: First, coarse positioning is achieved by a robotic arm, then optical vision scans the global alignment marks for secondary calibration, and finally, nanometer-level fine adjustment is achieved by combining a dual-frequency laser interferometer and piezoelectric ceramic drive. S4: High-precision mechanical and environmental control testing: Combining Kalman filtering, real-time compensation is provided for interference such as mechanical vibration and air turbulence. The displacement of the lithography machine stage is monitored in real-time using a laser interferometer, controlling the positioning error to within ±0.3nm. S5: Temperature dynamic error compensation, test motherboard ready: debugging probe station integrates temperature control, vacuum environment and dynamic feedback test conditions; S6: Batch testing and test organization: Combining machine learning to analyze test data, the AI ​​model automatically identifies physical and electrical defects in the 28nm process, integrates new sensors and AI chips, and realizes real-time diagnosis and automatic compensation of the probe station, reducing manual intervention.

[0030] Figure 1This is a submicron-level wafer manipulation subsystem, including the dual-pulse collaborative test system of this invention, which adopts a four-layer collaborative architecture of "mechanical-circuit-measurement and control-software". Specifically, it includes: an automated wafer manipulation subsystem, a high-power test subsystem, a synchronous measurement and control and isolated communication subsystem, and an intelligent management and control subsystem. Each subsystem is linked through a standardized interface protocol to achieve closed-loop control of the entire process from wafer upload to test report generation. The automated wafer handling subsystem is responsible for precise wafer positioning, wafer ejection docking, and non-destructive testing. The high-power test subsystem provides 100 ampere-level test current, low-noise drive, and multi-level protection. The synchronous measurement and control and isolation communication subsystem ensures nanosecond-level timing synchronization and high- and low-voltage safety isolation; The intelligent control subsystem enables automated testing processes, intelligent data management, and remote monitoring.

[0031] This includes an automated wafer alignment and card ejection testing subsystem, addressing the issues of low positioning accuracy and unreliable high-current contact in traditional wafer systems. The vision-mechanical collaborative alignment mechanism integrates a 5-megapixel industrial camera and a 100x optical magnification module, combined with an image recognition algorithm (using SURF feature point matching, positioning error ≤0.5μm) to achieve sub-micron level recognition of wafer chip arrays. Coupled with a servo motor-driven X / Y / Z axis fine-tuning platform (repeatability ±1μm, response speed ≤50ms), the software automatically completes the alignment process of "image capture - feature matching - platform fine-tuning," reducing alignment time to within 20 seconds, a 3-fold improvement in efficiency compared to traditional manual alignment. High-current test interface with spring-loaded card: It adopts a customized elastic probe card with probe array spacing matched to wafer test points (minimum spacing 50μm). The single probe contact resistance is ≤3mΩ and the rated current is ≥20A. 10 probes in parallel support a continuous test current of more than 150A. The spring-loaded card has a built-in buffer spring structure and the contact pressure is adjustable (50-200g), which ensures low impedance contact under high current and avoids scratches on the wafer surface (damage rate <0.1%).

[0032] High-reliability, high-current power test circuit design: To meet the driving characteristics of micron-level IGBTs and the testing requirements of hundreds of amperes, the circuit design achieves the following breakthroughs: Pogopin Inter-Board Interconnection Solution: A 2×8 array of pogopin connectors is used to connect the test motherboard and the power driver board. The rated current of a single pin is 50A, the contact resistance is ≤8mΩ, and the overall support is 200A peak current. The connector has a built-in guide and positioning structure and a mating life of ≥1000 cycles, solving the problems of heat generation and loosening of traditional ribbon cable connections under high current. UCC21750 Driver and Protection Integration: Utilizing the UCC21750 isolated gate driver, it features a 25ns fast switching response, ±20A peak drive current, and 5kVrms isolation withstand voltage. A 0.5Ω matching resistor is connected in series at the output, ensuring the drive voltage accuracy is controlled within ±15V±0.2V, perfectly suited to the gate sensitivity characteristics of micron-level IGBTs. It also integrates dual-channel protection: ① Overcurrent protection monitors Ic via a 0.01Ω sampling resistor, with a response time ≤80ns. The overcurrent threshold can be dynamically adjusted via a DAC. ② Desaturation protection detects Vce via a voltage divider circuit. When Vce > the set threshold, the gate is turned off within 100ns and the fault state is latched. RCD anti-interference and EMC optimization: A high-frequency RCD absorption network (R=10Ω, C=10nF, ultra-fast recovery diode) is designed between the power module and the drive circuit. Combined with the "power ground-signal ground" separation in the PCB layout and the drive line shielding layer (aluminum foil shielding, attenuation ≥40dB), the switching noise is effectively suppressed (noise suppression rate >85% in the 30MHz-1GHz band), ensuring that the drive signal distortion rate is <5%.

[0033] Nanosecond-level synchronous measurement and control and fiber optic isolated communication subsystem To address the requirements for test collaboration and anti-interference, the following test and control system is constructed: High-precision instrument combination: A Tektronix MDO3024 oscilloscope (2GHz bandwidth, 5GS / s sampling rate) is used to simultaneously acquire Vce, Vge, and Ic waveforms, paired with a Keithley 2657A high-voltage source (0-2000V output, ripple ≤0.05%) and an Agilent 81150A pulse generator (pulse width adjustment accuracy 1ns) to achieve complete capture of nanosecond-level transient signals during switching (waveform sampling error <3% for rise time ≤10ns). Fiber optic isolated communication: The drive control signal and the host computer are transmitted using single-mode fiber optic (transmission rate 155Mbps, delay ≤5ns), completely isolating common-mode interference on the high and low voltage sides (common-mode rejection ratio CMRR ≥80dB); the pulse generator and oscilloscope are synchronized with a 10MHz clock to ensure that the timing deviation of the dual pulses is ≤3ns, which is 4 times more accurate than the timing accuracy of traditional cable communication.

[0034] The testing software independently developed by the intelligent subsystem is based on the LabVIEW architecture and has integrated "control-test-storage-management" functions. Automated testing process: Supports three modes: "single chip testing - multi-chip parallel testing - wafer full array scanning", with a maximum of 16 parallel testing channels, a single chip testing cycle of ≤40ms, and wafer-level testing efficiency (UPH) increased to 300 wafers / hour, which is 3 times better than traditional single-channel testing; Status monitoring and alarm: Real-time monitoring of 12 key parameters (test current, voltage, temperature, probe contact resistance, etc.), using a "three-color LED + buzzer" alarm mechanism (green - normal, yellow - warning, red - fault), and automatically recording fault codes, waveform screenshots and timestamps; Data and Remote Management: Built-in SQLite database supports storage of 1 million sets of test data (including raw waveforms and calculation parameters), and data export formats are compatible with Excel / CSV / PDF; remote monitoring via Ethernet interface (supports PC / mobile access) is achieved, allowing remote configuration of test parameters, initiation of test tasks, and download of reports, meeting the centralized management needs of mass production scenarios.

[0035] Figure 2 For multimodal fusion alignment method The core stage of multimodal alignment is a gradient alignment process of "coarse → medium → fine," with each subsequent stage optimizing based on the results of the previous stage, while also integrating the advantages of different modalities. Coarse positioning: This involves using a mechanical structure for three-dimensional successive positioning, quickly narrowing down the position range, thus reducing the burden on subsequent high-precision alignment and avoiding inefficiency caused by excessively large search ranges in optical / laser equipment.

[0036] Intermediate alignment employs global optical alignment: leveraging the advantage of a large field of view (≥1mm² per shot) to solve the problem of local marker occlusion, outputting a global coordinate reference, and providing a "macroscopic anchor point" for fine alignment. High-precision positioning employs multimodal fine alignment: a laser interferometer is responsible for "dynamic monitoring," capturing in real time the thermal expansion errors caused by stage vibration and temperature; an electron beam is responsible for "microscopic positioning," compensating for the insufficient accuracy of the optical diffraction limit; The data fusion module uses the Kalman filter algorithm to weight and fuse real-time data from two modes, eliminating errors from a single mode.

[0037] The fusion accuracy verification and anomaly handling are as follows: Closed-loop verification: The "multi-modal fusion verification" adopts laser displacement measurement + electron beam mark position measurement to avoid the detection deviation of a single device and ensure the alignment accuracy is true and reliable.

[0038] Exception handling: Branches designed to address typical problems in multimodal scenarios: If optical mark recognition fails, such as due to scratches on the wafer surface, prioritize re-cleaning rather than directly switching the electron beam. If the laser interferometer detects high-frequency vibration, it activates the active vibration reduction module instead of re-executing the entire process.

[0039] Process Design Highlights Automation and unmanned operation: From wafer loading to alignment completion, human intervention is only triggered in the event of hardware malfunction, which meets the "high automation" requirements of semiconductor production lines.

[0040] Modal synergy rather than substitution: Instead of relying on a single technology, it balances "precision" and "efficiency" through gradient fusion of "mechanical → optical → laser / electron beam", with a total process time of ≤30s, meeting the mass production cycle.

[0041] Dynamic adaptability: Through real-time data fusion, including temperature and vibration compensation, it addresses the pain point of "large environmental fluctuations" in semiconductor workshops and ensures the stability of alignment accuracy (long-term repeatability positioning accuracy ≤ ±0.1μm).

[0042] The module parameters can be adjusted according to the specific application scenario, and the alignment accuracy threshold and modality can be selected, but the core logic gradient alignment and multimodal data fusion remain consistent.

[0043] Figure 3 Fiber Optic Synchronization Circuit: The schematic uses an ARM Cortex STM32F103 microprocessor to meet the needs of complex test logic and data processing. Peripheral Circuits: A switching power supply module (output 5V / 3A, 3.3V / 2A) provides stable power; a power-on reset + manual reset circuit ensures reliable system startup and guarantees clock accuracy. Filtering Module: An active low-pass filter circuit is used, with an adjustable cutoff frequency of 1MHz, to filter out high-frequency noise. Isolation Module: An opto-isolator (isolation voltage ≥5000V) is used to achieve electrical isolation between the test circuit and the control system, protecting the core chip from high-voltage surges. Data Acquisition Circuit This diagram illustrates the circuit module connection of a nanosecond-level time-frequency synchronization architecture based on a fiber optic bus. It is used to achieve zero-differential timing across modules (current acquisition module - protection module) in IGBT wafer testing. The core components include an MCU control unit, a fiber optic synchronization network unit, and related circuitry for optical-electrical phase compensation. The functions and collaborative logic of each part are as follows: MCU Control Unit: The microcontroller (MCU) in the center of the diagram serves as the core of the system control. It is responsible for configuring the master clock parameters (such as the initialization settings of the 10MHz clock reference and PPS synchronization pulse) and issuing working instructions to the "master clock-slave node" architecture, providing control layer logic support for the fiber optic synchronization network.

[0044] Fiber Optic Synchronization Network Unit: The master clock transmits optical time-frequency signals (including a 10MHz clock and PPS synchronization pulses) to the current acquisition module and protection module through the fiber optic transceiver circuit (including optical transmitting devices, optical receiving conditioning circuits, etc.) shown in the diagram. Taking advantage of the fiber optic transmission delay stability (within ±1ns), a low-latency synchronization network is constructed to provide hardware transmission guarantee for locking the local clock phase difference of the acquisition module and protection module within 5ns.

[0045] Optical-electric phase compensation unit: This unit consists of the signal processing and delay monitoring sub-circuits built into the acquisition module and the protection module (as shown in the timing comparison and feedback adjustment circuits). By monitoring the optical fiber transmission delay in real time (calculated based on the time difference between the round-trip optical signals), it dynamically corrects the local sampling trigger time to ensure that the timing deviation between the current sampling pulse and the protection trigger signal is ≤3ns, thus offsetting the impact of delay fluctuations on synchronization accuracy during transmission.

[0046] Through the collaborative work of the above modules, this architecture solves the synchronization drift problem caused by electromagnetic interference in high-power testing environments, improving the protection response speed by two orders of magnitude compared to traditional electrical signal synchronization methods. It meets the precise protection requirements of tens of nanosecond-level transient processes such as "avalanche breakdown" of IGBT wafers, and provides a hardware foundation for the test system's "prediction-trigger" linkage mechanism to break through the nanosecond-level response limit.

[0047] Figure 4 Functional testing flowchart: Multi-physics collaborative testing is adopted: the probe station integrates temperature control (-40°C to 150°C), vacuum environment, and dynamic force feedback. Probe pressure can be monitored in real time through piezoelectric sensors to ensure that pad damage is avoided in high-density package testing. Automotive-grade chip testing must meet the AEC-Q100 standard, and the probe card must pass the verification of high temperature (125°C), high pressure (100V+), and vibration environments.

[0048] Intelligent defect identification algorithm: By combining machine learning to analyze test data, the model can automatically identify physical and electrical defects in the micron process of power devices through intelligent algorithms.

[0049] The testing method includes the following steps: Wafer initialization: The micron-sized IGBT wafer is fixed on the automated platform, and the software starts the vision system to complete chip array identification and coordinate calibration; Alignment and Connection: The servo platform drives the spring-loaded probe to dock with the wafer test point, and the connection validity is confirmed by contact resistance detection (threshold ≤10mΩ); Parameter configuration: Test conditions (pulse width, Vce voltage, Ic current range, protection threshold, etc.) are set through software, and the system automatically completes instrument self-test and channel calibration; Dual-pulse test: The pulse generator outputs a dual-pulse signal, which is transmitted to the UCC21750 driver via optical fiber to drive the IGBT to complete the turn-on / turn-off process. The oscilloscope simultaneously acquires the waveforms of Vce, Vge, and Ic. Data processing and judgment: The software automatically calculates dynamic parameters such as Eon, Eoff, and Qrr, compares them with preset thresholds, and determines whether the chip is qualified; Batch testing and report generation: Repeat steps 4-5 to complete the full array testing of the wafer, automatically generate a test report containing a distribution map of qualified / unqualified chips and parameter statistics, and store it in the database.

[0050] This system, through the above-mentioned approach, can achieve high-precision and high-efficiency testing of the dynamic performance of micron-level IGBT wafers, with a testing error of ≤3%, meeting the screening requirements in mass production scenarios. It also has good scalability and can be adapted to the testing of IGBT wafers of different sizes (4-12 inches).

[0051] It should be noted that, in this document, relational terms such as first and second (number one, number two), etc., are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0052] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the claimed invention.

Claims

1. A dual-pulse collaborative testing system applicable to micron-scale IGBT wafers, comprising an automated wafer operation subsystem, a high-power testing subsystem, a synchronous measurement and control and isolation communication subsystem, and an intelligent management and control subsystem, and adopting a four-layer collaborative architecture of mechanical-circuit-measurement and control-software, characterized in that: The automated wafer handling subsystem, high-power testing subsystem, synchronous measurement and control and isolated communication subsystem, and intelligent management and control subsystem are linked through a standardized interface protocol. The automated wafer handling subsystem includes an automated wafer alignment and card ejection test operation subsystem. The card ejection test operation subsystem is equipped with a card ejection type high-current test interface and adopts a customized elastic probe card. The probe array spacing matches the wafer test points. The high-power testing subsystem includes a high-reliability high-current power test circuit. The synchronous measurement and control and isolated communication subsystem includes a high-precision instrument combination and fiber optic isolated communication. The intelligent management and control subsystem includes a LabVIEW architecture.

2. The dual-pulse collaborative testing system for micron-scale IGBT wafers according to claim 1, characterized in that: The automated wafer handling subsystem employs a functional-mechanical collaborative alignment mechanism, integrating a 5-megapixel industrial camera and a 100x optical magnification module. Combined with image recognition algorithms and SURF feature point matching, the positioning error is ≤0.5μm, achieving sub-micron level recognition of wafer chip arrays. Paired with a servo motor-driven X / Y / Z axis fine-tuning platform, the repeatability is ±1μm, and the response speed is ≤50ms. The software automatically completes the alignment process of image capture, feature matching, and platform fine-tuning, compressing the alignment time to within 20 seconds.

3. The dual-pulse collaborative testing system for micron-scale IGBT wafers according to claim 1, characterized in that: The single probe contact resistance of the spring-loaded high-current test interface is ≤3mΩ, the rated current is ≥20A, and 10 probes in parallel support a continuous test current of more than 150A. The spring-loaded high-current test interface has a built-in buffer spring structure, and the contact pressure is adjustable from 50-200g to ensure low impedance contact under high current, avoid scratches on the wafer surface, and the damage rate is <0.1%.

4. The dual-pulse collaborative testing system for micron-scale IGBT wafers according to claim 1, characterized in that: The high-reliability high-current power test circuit includes a pogopin inter-board interconnect circuit, a UCC21750 driver and protection integrated circuit, and an RCD anti-interference and EMC optimization circuit.

5. The dual-pulse collaborative testing system for micron-scale IGBT wafers according to claim 1, characterized in that: The high-precision instrument combination includes an oscilloscope with a bandwidth of 2GHz and a sampling rate of 5GS / s, which simultaneously acquires Vce, Vge, and Ic waveforms. Paired with a high-voltage source, it outputs 0-2000V with ripple ≤0.05%. An additional pulse generator is added, with a pulse width adjustment accuracy of 1ns, which can completely capture nanosecond-level transient signals during switching. The waveform sampling error is <3% with a rise time ≤10ns.

6. The dual-pulse collaborative testing system for micron-scale IGBT wafers according to claim 1, characterized in that: The fiber optic isolated communication drive control signal is transmitted to the host computer via single-mode fiber with a transmission rate of 155Mbps and a delay of ≤5ns. It completely isolates common-mode interference on the high and low voltage sides, and the common-mode rejection ratio (CMRR) is ≥80dB. The pulse generator and oscilloscope are synchronized via a 10MHz clock to ensure that the timing deviation of the dual pulses is ≤3ns.

7. The dual-pulse collaborative testing system for micron-scale IGBT wafers according to claim 1, characterized in that: The LabVIEW architecture in the intelligent control subsystem includes an automated testing structure, a status monitoring and alarm structure, and a data and remote management structure. The automated testing structure supports three modes: single-chip testing, multi-chip parallel testing, and wafer full array scanning. The status monitoring and alarm structure monitors 12 key parameters in real time, including test current, voltage, temperature, and probe contact resistance, and uses a three-color LED + buzzer alarm mechanism.

8. A dual-pulse coordinated testing method applicable to micron-scale IGBT wafers, characterized in that: Specifically, the following steps are included: S1: Micrometer-level 4- and 6-inch wafer placement, vacuum adsorption: The electrostatic chuck uses a kilovolt-level DC high voltage to generate Coulomb force to adsorb the wafer, and helium gas is introduced to regulate the back temperature to ensure that the wafer's thermal expansion coefficient is matched, so that submicrometer-level detection accuracy can still be maintained even under extreme temperatures. S2: Multimodal fusion alignment: Calibration can be directly recovered from stripe images through optical vision and a ResNet-based deep learning model; S3: Coordinated focusing by optical vision and laser interferometry: The equipment adopts a three-stage alignment strategy: First, coarse positioning is achieved by a robotic arm, then optical vision scans the global alignment marks for secondary calibration, and finally, nanometer-level fine adjustment is achieved by combining a dual-frequency laser interferometer and piezoelectric ceramic drive. S4: High-precision mechanical and environmental control testing: Combining Kalman filtering, real-time compensation is provided for interference such as mechanical vibration and air turbulence. The displacement of the lithography machine stage is monitored in real-time using a laser interferometer, controlling the positioning error to within ±0.3nm. S5: Temperature dynamic error compensation, test motherboard ready: debugging probe station integrates temperature control, vacuum environment and dynamic feedback test conditions; S6: Batch testing and test organization: Combining machine learning to analyze test data, the AI ​​model automatically identifies physical and electrical defects in the 28nm process, integrates new sensors and AI chips, and realizes real-time diagnosis and automatic compensation of the probe station, reducing manual intervention.

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