A method and system for detecting void defects in a chip gate oxide layer

Abstract

This application discloses a method and system for detecting void defects in the gate oxide layer of a chip, belonging to the field of semiconductor chip defect detection technology. The method involves: performing an volt-ampere characteristic test on the chip under test to determine whether there are voltage or current abnormalities in the gate oxide layer; grinding the chip with abnormalities until the polysilicon gate surface is uniformly exposed; then removing the polysilicon gate using wet selective etching to expose the gate oxide failure area; and finally, after cleaning and drying, performing a planar morphology scan on the gate oxide layer to determine the void defect detection result. Therefore, by implementing this application, the problem of existing technologies being unable to improve detection efficiency while ensuring the accuracy of void defect detection can be solved.

Description

Technical Field

[0001] This application relates to the field of void defect detection in chip gate oxide layers, and more particularly to a method and system for void defect detection in chip gate oxide layers. Background Technology

[0002] The gate oxide layer is the functional layer of a semiconductor device, serving as an electrical insulation layer between the gate and the channel, and regulating charge carriers via gate voltage. During wafer fabrication, factors such as abnormal growth environment, particulate contamination, and process stress can all lead to nanoscale void defects within the gate oxide layer. These defects cause a decrease in gate oxide breakdown voltage and an increase in leakage current, and in severe cases, can cause instantaneous breakdown or premature failure of the device, posing a significant threat to chip yield and reliability. Especially as semiconductor process nodes continue to advance and gate oxide layer thickness continues to decrease, the impact of tiny voids on device performance is further amplified. Therefore, there is an urgent need to develop efficient and accurate gate oxide layer void defect detection methods.

[0003] The current mainstream detection method for gate oxide layer void defects in the industry is focused ion beam (FIB) sample preparation combined with transmission electron microscopy (TEM) observation. This involves first using electrical testing to initially locate the failure area, then using a FIB to precisely cut the sample at the predetermined location to prepare a nanometer-thick gate oxide cross-section sample, and finally observing the cross-section using TEM to identify the morphology and size of the void defect. However, this method has the following technical drawbacks: the TEM cross-section hit rate is extremely low, often requiring sample duplication, resulting in very poor analysis efficiency and a long sample preparation and observation cycle; a complete process for a single sample can take several working days, leading to extremely low detection efficiency. Therefore, there is an urgent need for a technical solution that improves the detection efficiency of void defects while ensuring accuracy. Summary of the Invention

[0004] This application provides a method and system for detecting void defects in the gate oxide layer of a chip, which can solve the problem in the prior art that it is difficult to improve the detection efficiency of void defects while ensuring the accuracy of void defect detection.

[0005] In a first aspect, embodiments of the present invention provide a method for detecting void defects in a chip gate oxide layer, comprising:

[0006] Perform current-voltage characteristic tests on the chip under test to determine whether there are voltage or current abnormalities in the gate oxide layer of the chip under test;

[0007] If there is an abnormal voltage or current in the gate oxide layer, the chip under test is ground until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, thus obtaining the first intermediate chip under test.

[0008] The first intermediate chip under test is subjected to wet selective etching to expose the gate oxide failure points of the first intermediate chip under test, thereby obtaining the second intermediate chip under test.

[0009] The second intermediate chip under test is sequentially cleaned and dried to obtain the third intermediate chip under test;

[0010] A planar topography scan is performed on the gate oxide layer of the third intermediate chip under test to obtain a void defect scan image of the gate oxide layer, and the void defect detection result of the gate oxide layer of the chip under test is determined based on the void defect scan image.

[0011] This application pre-screens chips with abnormal voltage or current by conducting a preliminary volt-ampere characteristic test, ensuring that subsequent sample preparation and observation are carried out on suspected failed samples, avoiding aimless blind testing, and guaranteeing the targeting and accuracy of defect detection. Next, this application removes the chip's surface stacked structure through mechanical polishing, terminating at the polysilicon gate surface. This allows for rapid sample pretreatment in a parallel, whole-wafer manner, improving sample preparation efficiency compared to point-by-point cutting, and providing a uniform starting surface for subsequent wet etching, avoiding excessive polishing that damages the gate oxide layer and destroys the original morphology of void defects. Then, this application uses wet selective etching... The etching process utilizes the high etching selectivity of the etching system for polysilicon and gate oxide layers. This allows for the complete removal of the entire polysilicon gate and exposure of the complete gate oxide surface in a single operation, while preserving the original morphology of the gate oxide layer and void defects. This eliminates the need for preparing cross-sectional samples for each individual point, improving the efficiency and coverage of defect exposure. Cleaning and drying processes remove etching byproducts, polysilicon residue, and residual etching solution, preventing residue from obscuring defects or creating false defects that interfere with observation. This ensures the clarity of subsequent scanning imaging and the accuracy of defect identification. Finally, planar morphology scanning of the gate oxide layer and determination of the detection results enable comprehensive observation of a large area of ​​the gate oxide region in a single operation. Therefore, the embodiments of this application solve the problem in existing technologies of simultaneously improving the detection efficiency of void defects while maintaining accuracy.

[0012] As a preferred example of the first aspect, the grinding of the chip under test until the upper surface of the polysilicon gate of the chip under test is uniformly exposed to obtain a first intermediate chip under test includes:

[0013] The chip under test is polished using polishing media to remove the metal interconnect layer, interlayer dielectric layer and contact hole filling layer on the surface of the chip under test layer by layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, at which point polishing is stopped to obtain the first intermediate chip under test.

[0014] In this preferred embodiment, the metal interconnect layer, interlayer dielectric layer, and contact hole filling layer of the chip surface are removed layer by layer using a polishing medium. The surface structure can be quickly stripped by polishing the entire chip in parallel, which significantly improves the pre-processing efficiency compared to the point-by-point cutting method. At the same time, the polishing is precisely terminated on the upper surface of the polysilicon gate, which can avoid over-polishing and damage to the gate oxide layer and destroy the original morphology of void defects, ensuring the accuracy of subsequent defect identification. It can also provide a uniform working surface for subsequent wet etching, ensuring stable and controllable etching effect.

[0015] As a preferred example of the first aspect, the grinding media is alumina.

[0016] In this preferred example, alumina is used as the polishing medium. Its hardness is well-suited to the multi-layer structure of the chip surface, and the polishing rate is stable and controllable. It can efficiently complete the layer-by-layer peeling of structures such as metal interconnect layers and interlayer dielectric layers, effectively shortening the polishing sample preparation time and improving the sample pretreatment efficiency. At the same time, alumina particles have good uniformity, resulting in high surface flatness after polishing. It is not easy to cause over-polishing or surface scratch damage, and it can accurately terminate at the polysilicon gate surface, avoiding damage to the original morphology of the underlying gate oxide layer and void defects, thus ensuring the accuracy of subsequent defect identification.

[0017] As a preferred example of the first aspect, the step of performing wet selective etching on the first intermediate chip under test to expose the gate oxide failure points of the first intermediate chip under test to obtain the second intermediate chip under test includes:

[0018] The first intermediate chip under test is immersed in a preset solution for wet etching. By utilizing the etching selectivity ratio of the preset solution for polysilicon and gate oxide, all polysilicon gates are selectively removed, thereby exposing the gate oxide failure points of the first intermediate chip under test and obtaining the second intermediate chip under test.

[0019] In this preferred embodiment, the first intermediate chip under test is immersed in a preset solution for wet etching. The entire polysilicon gate can be removed in one go through parallel processing of the whole chip, eliminating the need to prepare cross-sectional samples point by point, thus shortening the sample preparation cycle. At the same time, by utilizing the etching selectivity ratio of the solution to polysilicon and gate oxide layer, polysilicon can be selectively etched without damaging the gate oxide layer, thus completely preserving the original morphology of void defects. This ensures the accuracy of defect identification and fully exposes the gate oxide failure area, avoiding the risk of missed detection due to local observation.

[0020] As a preferred example of the first aspect, the preset solution is a potassium hydroxide solution.

[0021] In this preferred embodiment, potassium hydroxide solution is used as the etching solution. It exhibits extremely high etching selectivity for both polysilicon and the gate oxide layer, removing the polysilicon gate while almost completely preserving the underlying gate oxide layer, thus ensuring the accuracy of defect identification. Furthermore, the potassium hydroxide etching process is mature and stable, with a uniform and controllable etching rate, enabling simultaneous processing of the entire chip. It also minimizes the introduction of additional impurities, reducing the interference of false defects on the detection results.

[0022] As a preferred example of the first aspect, the step of sequentially cleaning and drying the second intermediate chip under test to obtain the third intermediate chip under test includes:

[0023] The second intermediate test chip was placed in deionized water for ultrasonic cleaning to remove etching reaction byproducts, polysilicon etching residues and particulate contaminants from the surface of the second intermediate test chip, thus obtaining the fourth intermediate test chip.

[0024] The fourth intermediate test chip was statically rinsed with deionized water to remove the residual etching solution on the surface of the fourth intermediate test chip, thus obtaining the fifth intermediate test chip.

[0025] The fifth intermediate chip under test is dried to obtain the third intermediate chip under test.

[0026] In this preferred example, ultrasonic cleaning with deionized water can effectively remove etching reaction byproducts, polysilicon etching residues, and particulate contaminants from the chip surface, preventing impurities from obscuring void defects or forming pseudo-defects, and ensuring the clarity of subsequent scanning imaging and the accuracy of defect identification; then static rinsing with deionized water removes residual etching solution, preventing residual liquid from continuously corroding the gate oxide layer and destroying the original morphology of the defects.

[0027] As a preferred example of the first aspect, the step of performing an volt-ampere characteristic test on the chip under test to determine whether there is an abnormality in the voltage or current of the gate oxide layer of the chip under test includes:

[0028] A scanning voltage is applied to the gate of the chip under test to acquire the current-voltage characteristic curve corresponding to the gate, and the gate leakage current value and gate oxide breakdown voltage value of the chip under test are determined based on the current-voltage characteristic curve.

[0029] Based on the gate leakage current value and the gate oxide breakdown voltage value, it is determined whether there is an abnormal voltage or current in the gate oxide layer of the chip under test.

[0030] In this preferred example, by applying a scanning voltage to the gate of the chip under test and acquiring the current-voltage characteristic curve, two electrical parameters, namely the gate leakage current value and the gate oxide breakdown voltage value, can be quickly extracted. Based on the comprehensive determination of the two parameters, it is possible to determine whether there is an abnormality in the gate oxide layer. This allows for rapid batch screening, early exclusion of normal chips, avoidance of invalid sample preparation and observation processes, and improvement of overall detection efficiency from the source.

[0031] As a preferred example of the first aspect, determining whether there is a voltage or current abnormality in the gate oxide layer of the chip under test based on the gate leakage current value and the gate oxide breakdown voltage value includes:

[0032] Calculate the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard breakdown voltage value to obtain the breakdown voltage reduction magnitude;

[0033] If the breakdown voltage decrease is greater than or equal to a preset threshold value, or the gate leakage current exceeds a preset leakage current standard range, then it is determined that there is a voltage or current abnormality in the gate oxide layer of the chip under test.

[0034] In this preferred example, the degree of failure is defined quantitatively by calculating the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard value, thus avoiding subjective errors in qualitative judgment. The dual-condition judgment of breakdown voltage reduction threshold and leakage current standard range can cover different manifestations of gate oxide void failure, reducing the probability of missed and false judgments.

[0035] As a preferred example of the first aspect, the step of performing planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer includes:

[0036] The third intermediate chip under test is fixed to the sample stage of a scanning electron microscope so that the third intermediate chip under test is electrically connected to the sample stage and grounded.

[0037] The scanning electron microscope is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain the scanning image of the void defect in the gate oxide layer.

[0038] In this preferred embodiment, fixing the third intermediate chip under test to the scanning electron microscope sample stage and electrically connecting it to ground can eliminate the charging effect caused by the insulating properties of the gate oxide layer, avoid whitening and blurring of the scanned image, ensure the clarity and authenticity of the scanned image of void defects, and improve the accuracy of defect identification. By performing planar morphology scanning with a scanning electron microscope, a large area of ​​gate oxide can be covered at once, without the need to prepare cross-sectional samples point by point, which improves the efficiency of defect investigation, while fully presenting the morphology and distribution of defects and ensuring the accuracy of detection.

[0039] In a second aspect, the present invention provides a hole defect detection system for a chip gate oxide layer, comprising a first detection module, a second detection module, a third detection module, a fourth detection module and a fifth detection module;

[0040] The first detection module is used to perform current-voltage characteristic testing on the chip under test in order to determine whether there is any voltage or current abnormality in the gate oxide layer of the chip under test.

[0041] The second detection module is used to grind the chip under test if there is an abnormal voltage or current in the gate oxide layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, thereby obtaining the first intermediate chip under test.

[0042] The third detection module is used to perform wet selective etching on the first intermediate chip under test to expose the gate oxide failure points of the first intermediate chip under test, and obtain the second intermediate chip under test.

[0043] The fourth detection module is used to sequentially clean and dry the second intermediate chip under test to obtain the third intermediate chip under test.

[0044] The fifth detection module is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer, and to determine the void defect detection result of the gate oxide layer of the chip under test based on the void defect scanning image.

[0045] This application pre-screens chips with abnormal voltage or current by conducting a preliminary volt-ampere characteristic test, ensuring that subsequent sample preparation and observation are carried out on suspected failed samples, avoiding aimless blind testing, and guaranteeing the targeting and accuracy of defect detection. Next, this application removes the chip's surface stacked structure through mechanical polishing, terminating at the polysilicon gate surface. This allows for rapid sample pretreatment in a parallel, whole-wafer manner, improving sample preparation efficiency compared to point-by-point cutting, and providing a uniform starting surface for subsequent wet etching, avoiding excessive polishing that damages the gate oxide layer and destroys the original morphology of void defects. Then, this application uses wet selective etching... The etching process utilizes the high etching selectivity of the etching system for polysilicon and gate oxide layers. This allows for the complete removal of the entire polysilicon gate and exposure of the complete gate oxide surface in a single operation, while preserving the original morphology of the gate oxide layer and void defects. This eliminates the need for preparing cross-sectional samples for each individual point, improving the efficiency and coverage of defect exposure. Cleaning and drying processes remove etching byproducts, polysilicon residue, and residual etching solution, preventing residue from obscuring defects or creating false defects that interfere with observation. This ensures the clarity of subsequent scanning imaging and the accuracy of defect identification. Finally, planar morphology scanning of the gate oxide layer and determination of the detection results enable comprehensive observation of a large area of ​​the gate oxide region in a single operation. Therefore, the embodiments of this application solve the problem in existing technologies of simultaneously improving the detection efficiency of void defects while maintaining accuracy.

[0046] As a preferred example of the second aspect, the grinding of the chip under test until the upper surface of the polysilicon gate of the chip under test is uniformly exposed to obtain a first intermediate chip under test includes:

[0047] The chip under test is polished using polishing media to remove the metal interconnect layer, interlayer dielectric layer and contact hole filling layer on the surface of the chip under test layer by layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, at which point polishing is stopped to obtain the first intermediate chip under test.

[0048] In this preferred embodiment, the metal interconnect layer, interlayer dielectric layer, and contact hole filling layer of the chip surface are removed layer by layer using a polishing medium. The surface structure can be quickly stripped by polishing the entire chip in parallel, which significantly improves the pre-processing efficiency compared to the point-by-point cutting method. At the same time, the polishing is precisely terminated on the upper surface of the polysilicon gate, which can avoid over-polishing and damage to the gate oxide layer and destroy the original morphology of void defects, ensuring the accuracy of subsequent defect identification. It can also provide a uniform working surface for subsequent wet etching, ensuring stable and controllable etching effect.

[0049] As a preferred example of the second aspect, the grinding media is alumina.

[0050] In this preferred example, alumina is used as the polishing medium. Its hardness is well-suited to the multi-layer structure of the chip surface, and the polishing rate is stable and controllable. It can efficiently complete the layer-by-layer peeling of structures such as metal interconnect layers and interlayer dielectric layers, effectively shortening the polishing sample preparation time and improving the sample pretreatment efficiency. At the same time, alumina particles have good uniformity, resulting in high surface flatness after polishing. It is not easy to cause over-polishing or surface scratch damage, and it can accurately terminate at the polysilicon gate surface, avoiding damage to the original morphology of the underlying gate oxide layer and void defects, thus ensuring the accuracy of subsequent defect identification.

[0051] As a preferred example of the second aspect, the step of performing wet selective etching on the first intermediate chip under test to expose the gate oxide failure points of the first intermediate chip under test to obtain the second intermediate chip under test includes:

[0052] The first intermediate chip under test is immersed in a preset solution for wet etching. By utilizing the etching selectivity ratio of the preset solution for polysilicon and gate oxide, all polysilicon gates are selectively removed, thereby exposing the gate oxide failure points of the first intermediate chip under test and obtaining the second intermediate chip under test.

[0053] In this preferred embodiment, the first intermediate chip under test is immersed in a preset solution for wet etching. The entire polysilicon gate can be removed in one go through parallel processing of the whole chip, eliminating the need to prepare cross-sectional samples point by point, thus shortening the sample preparation cycle. At the same time, by utilizing the etching selectivity ratio of the solution to polysilicon and gate oxide layer, polysilicon can be selectively etched without damaging the gate oxide layer, thus completely preserving the original morphology of void defects. This ensures the accuracy of defect identification and fully exposes the gate oxide failure area, avoiding the risk of missed detection due to local observation.

[0054] As a preferred example of the second aspect, the preset solution is a potassium hydroxide solution.

[0055] In this preferred embodiment, potassium hydroxide solution is used as the etching solution. It exhibits extremely high etching selectivity for both polysilicon and the gate oxide layer, removing the polysilicon gate while almost completely preserving the underlying gate oxide layer, thus ensuring the accuracy of defect identification. Furthermore, the potassium hydroxide etching process is mature and stable, with a uniform and controllable etching rate, enabling simultaneous processing of the entire chip. It also minimizes the introduction of additional impurities, reducing the interference of false defects on the detection results.

[0056] As a preferred example of the second aspect, the step of sequentially cleaning and drying the second intermediate chip under test to obtain the third intermediate chip under test includes:

[0057] The second intermediate test chip was placed in deionized water for ultrasonic cleaning to remove etching reaction byproducts, polysilicon etching residues and particulate contaminants from the surface of the second intermediate test chip, thus obtaining the fourth intermediate test chip.

[0058] The fourth intermediate test chip was statically rinsed with deionized water to remove the residual etching solution on the surface of the fourth intermediate test chip, thus obtaining the fifth intermediate test chip.

[0059] The fifth intermediate chip under test is dried to obtain the third intermediate chip under test.

[0060] In this preferred example, ultrasonic cleaning with deionized water can effectively remove etching reaction byproducts, polysilicon etching residues, and particulate contaminants from the chip surface, preventing impurities from obscuring void defects or forming pseudo-defects, and ensuring the clarity of subsequent scanning imaging and the accuracy of defect identification; then static rinsing with deionized water removes residual etching solution, preventing residual liquid from continuously corroding the gate oxide layer and destroying the original morphology of the defects.

[0061] As a preferred example of the second aspect, the step of performing an volt-ampere characteristic test on the chip under test to determine whether there is an abnormality in the voltage or current of the gate oxide layer of the chip under test includes:

[0062] A scanning voltage is applied to the gate of the chip under test to acquire the current-voltage characteristic curve corresponding to the gate, and the gate leakage current value and gate oxide breakdown voltage value of the chip under test are determined based on the current-voltage characteristic curve.

[0063] Based on the gate leakage current value and the gate oxide breakdown voltage value, it is determined whether there is an abnormal voltage or current in the gate oxide layer of the chip under test.

[0064] In this preferred example, by applying a scanning voltage to the gate of the chip under test and acquiring the current-voltage characteristic curve, two electrical parameters, namely the gate leakage current value and the gate oxide breakdown voltage value, can be quickly extracted. Based on the comprehensive determination of the two parameters, it is possible to determine whether there is an abnormality in the gate oxide layer. This allows for rapid batch screening, early exclusion of normal chips, avoidance of invalid sample preparation and observation processes, and improvement of overall detection efficiency from the source.

[0065] As a preferred example of the second aspect, determining whether there is a voltage or current abnormality in the gate oxide layer of the chip under test based on the gate leakage current value and the gate oxide breakdown voltage value includes:

[0066] Calculate the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard breakdown voltage value to obtain the breakdown voltage reduction magnitude;

[0067] If the breakdown voltage decrease is greater than or equal to a preset threshold value, or the gate leakage current exceeds a preset leakage current standard range, then it is determined that there is a voltage or current abnormality in the gate oxide layer of the chip under test.

[0068] In this preferred example, the degree of failure is defined quantitatively by calculating the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard value, thus avoiding subjective errors in qualitative judgment. The dual-condition judgment of breakdown voltage reduction threshold and leakage current standard range can cover different manifestations of gate oxide void failure, reducing the probability of missed and false judgments.

[0069] As a preferred example of the second aspect, the step of performing planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer includes:

[0070] The third intermediate chip under test is fixed to the sample stage of a scanning electron microscope so that the third intermediate chip under test is electrically connected to the sample stage and grounded.

[0071] The scanning electron microscope is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain the scanning image of the void defect in the gate oxide layer.

[0072] In this preferred embodiment, fixing the third intermediate chip under test to the scanning electron microscope sample stage and electrically connecting it to ground can eliminate the charging effect caused by the insulating properties of the gate oxide layer, avoid whitening and blurring of the scanned image, ensure the clarity and authenticity of the scanned image of void defects, and improve the accuracy of defect identification. By performing planar morphology scanning with a scanning electron microscope, a large area of ​​gate oxide can be covered at once, without the need to prepare cross-sectional samples point by point, which improves the efficiency of defect investigation, while fully presenting the morphology and distribution of defects and ensuring the accuracy of detection.

[0073] Another embodiment of this application also provides a terminal device, including: a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the steps of the void defect detection method for the chip gate oxide layer of this application.

[0074] Another embodiment of this application also provides a computer-readable storage medium item, including: a stored computer program, which, when the computer program is running, controls the device where the computer-readable storage medium is located to perform the steps of the chip gate oxide void defect detection method of this application. Attached Figure Description

[0075] To more clearly illustrate the technical solution of this application, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0076] Figure 1A flowchart illustrating an embodiment of a method for detecting void defects in a chip gate oxide layer provided by the present invention;

[0077] Figure 2 A schematic diagram of the cross-sectional structure of a MOS device and the connection of the current-voltage characteristic test probe, which is an embodiment of the method for detecting void defects in the gate oxide layer of a chip provided by the present invention.

[0078] Figure 3 A schematic diagram of the chip surface structure grinding and sample preparation process in an embodiment of a chip gate oxide layer void defect detection method provided by the present invention;

[0079] Figure 4 A schematic diagram of a chip wet selective etching process, representing an embodiment of a chip gate oxide layer void defect detection method provided by the present invention.

[0080] Figure 5 A schematic diagram of a chip ultrasonic cleaning process, representing an embodiment of a method for detecting void defects in a chip gate oxide layer provided by the present invention;

[0081] Figure 6 A schematic diagram of a scanning electron microscope sample mounting for an embodiment of a method for detecting void defects in the gate oxide layer of a chip provided by the present invention;

[0082] Figure 7 A diagram illustrating the detection effect of a conventional cross-sectional observation scheme for gate oxide void defects, as an embodiment of the chip gate oxide layer void defect detection method provided by the present invention.

[0083] Figure 8 A diagram illustrating the detection effect of gate oxide void defects in a planar observation scheme according to an embodiment of a chip gate oxide void defect detection method provided by the present invention.

[0084] Figure 9 This is a module structure diagram of one embodiment of a chip gate oxide layer void defect detection device provided by the present invention. Detailed Implementation

[0085] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions of this application will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0086] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the application; the terms “comprising” and “having”, and any variations thereof, in the specification, claims, and foregoing description of the drawings are intended to cover non-exclusive inclusion.

[0087] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0088] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0089] In the description of the embodiments in this application, the term "and / or" is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, and B existing alone. Additionally, the character " / " in this document generally indicates that the preceding and following related objects have an "or" relationship.

[0090] In the description of the embodiments of this application, the term "multiple" refers to two or more (including two), similarly, "multiple sets" refers to two or more (including two sets), and "multiple pieces" refers to two or more (including two pieces).

[0091] In the description of the embodiments of this application, unless otherwise expressly specified and limited, technical terms such as "installation," "connection," "joining," and "fixing" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. For those skilled in the art, the specific meaning of the above terms in the embodiments of this application can be understood according to the specific circumstances.

[0092] Example 1

[0093] Please refer to Figure 1To address the problem in existing technologies of simultaneously improving the detection efficiency of void defects while maintaining accuracy, this application provides a method for detecting void defects in a chip gate oxide layer, comprising:

[0094] S1. Perform an volt-ampere characteristic test on the chip under test to determine whether there is any voltage or current abnormality in the gate oxide layer of the chip under test.

[0095] In some embodiments, performing an volt-ampere characteristic test on the chip under test to determine whether there is an abnormal voltage or current in the gate oxide layer of the chip under test includes:

[0096] A scanning voltage is applied to the gate of the chip under test to acquire the current-voltage characteristic curve corresponding to the gate, and the gate leakage current value and gate oxide breakdown voltage value of the chip under test are determined based on the current-voltage characteristic curve.

[0097] Based on the gate leakage current value and the gate oxide breakdown voltage value, it is determined whether there is an abnormal voltage or current in the gate oxide layer of the chip under test.

[0098] In some embodiments, determining whether there is a voltage or current abnormality in the gate oxide layer of the chip under test based on the gate leakage current value and the gate oxide breakdown voltage value includes:

[0099] Calculate the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard breakdown voltage value to obtain the breakdown voltage reduction magnitude;

[0100] If the breakdown voltage decrease is greater than or equal to a preset threshold value, or the gate leakage current exceeds a preset leakage current standard range, then it is determined that there is a voltage or current abnormality in the gate oxide layer of the chip under test.

[0101] Specifically, the current-voltage characteristic test of the chip under test to determine whether there are voltage or current abnormalities in the gate oxide layer of the chip under test can be implemented through the following scheme:

[0102] like Figure 2 The figure shows the cross-sectional structure of the chip (MOS device). The polysilicon gate, the source and drain doped regions on both sides, and the substrate stack structure of the device are all led out through contact holes. During testing, a nanoprobe station is used for point docking. The probes are reliably pressed to the gate contact hole, the source contact hole and the substrate lead-out end, respectively, to form a stable gate oxide electrical test circuit.

[0103] The test was performed at room temperature using a semiconductor parameter analyzer and a probe station. Before the test, the probes were pressed to the gate electrode and substrate electrode of the chip under test to form a reliable electrical contact. Then, a linear scan voltage starting from 0V was applied to the gate. The voltage scan range covered the rated operating voltage of the chip and was continuously increased to the range where the gate oxide would break down. The gate current data corresponding to different gate voltages were collected simultaneously, and the current-voltage characteristic curve of the gate was plotted.

[0104] From the obtained current-voltage characteristic curve, the gate leakage current value corresponding to the rated operating voltage point of the chip is extracted. At the same time, the position where the gate current suddenly increases is located, and the voltage value corresponding to the position is determined as the gate oxide breakdown voltage value. The two extracted parameters are compared with the preset standard values ​​corresponding to normal chips of the same process batch. When the gate oxide breakdown voltage decreases by 15% or more compared to the standard breakdown voltage, or the gate leakage current value exceeds the preset normal leakage current standard range, it can be determined that the gate oxide layer of the chip under test has voltage or current abnormalities and belongs to the sample to be analyzed with the risk of void defects.

[0105] S2. If there is an abnormal voltage or current in the gate oxide layer, the chip under test is ground until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, and the first intermediate chip under test is obtained.

[0106] In some embodiments, grinding the chip under test until the upper surface of the polysilicon gate of the chip under test is uniformly exposed to obtain a first intermediate chip under test includes:

[0107] The chip under test is polished using polishing media to remove the metal interconnect layer, interlayer dielectric layer and contact hole filling layer on the surface of the chip under test layer by layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, at which point polishing is stopped to obtain the first intermediate chip under test.

[0108] Specifically, such as Figure 3 As shown, the chip under test, after completing the electrical test, is first fixed on the sample fixture of the mechanical polishing equipment. Polishing slurry is used as the polishing medium. After setting the appropriate polishing pressure and turntable speed, the chip surface is polished. The polishing process proceeds layer by layer along the chip thickness direction, removing the outermost metal interconnect layer, the interlayer dielectric layer below it, and the contact hole filling layer in sequence. During the polishing process, the process can be paused at fixed intervals, and the sample is taken out and placed under a metallographic microscope to observe the surface condition to confirm the polishing progress. Polishing is terminated when the polysilicon gate surface is uniformly exposed throughout the entire chip area and there is no obvious surface metal and dielectric residue. Finally, a first intermediate chip under test with a flat surface is obtained.

[0109] In some embodiments, the grinding media is aluminum oxide.

[0110] Specifically, alumina is used as the polishing medium. In practice, it is usually prepared as an aqueous polishing slurry of a certain concentration. Different alumina abrasive particles of different sizes can be selected according to the polishing progress. In the coarse polishing stage, micron-sized alumina particles with a slightly larger particle size are used to ensure sufficient polishing efficiency and quickly remove the metal interconnect layer, interlayer dielectric layer, and contact hole filling layer of the chip surface layer layer by layer, reducing the overall polishing time. Near the end of the polishing, small-diameter alumina particles are used for fine polishing to reduce surface polishing scratches and improve the surface smoothness of the sample. The hardness of alumina is well compatible with various materials on the chip surface. It can efficiently remove the upper metal and dielectric stacked structure, and has good polishing controllability when reaching the polysilicon gate surface. It is not easy to cause over-polishing and damage to the underlying gate oxide layer. It can completely preserve the original morphology of the void defects inside the gate oxide, and the surface uniformity of the entire sample after polishing is high. It can provide a smooth and consistent foundation for subsequent wet selective etching, ensuring the uniformity and stability of the subsequent etching process.

[0111] S3. Perform wet selective etching on the first intermediate chip under test to expose the gate oxide failure points of the first intermediate chip under test, and obtain the second intermediate chip under test.

[0112] In some embodiments, performing wet selective etching on the first intermediate chip under test to expose gate oxide failure points of the first intermediate chip under test to obtain a second intermediate chip under test includes:

[0113] The first intermediate chip under test is immersed in a preset solution for wet etching. By utilizing the etching selectivity ratio of the preset solution for polysilicon and gate oxide, all polysilicon gates are selectively removed, thereby exposing the gate oxide failure points of the first intermediate chip under test and obtaining the second intermediate chip under test.

[0114] In some embodiments, the preset solution is a potassium hydroxide solution.

[0115] Specifically, the preset solution is a potassium hydroxide solution, also known as KOH etching solution, which is commonly used in the industry. This system has an extremely high etching selectivity for gate oxide layers made of polysilicon and silicon dioxide. Under the matched concentration and temperature conditions, it can quickly etch away the polysilicon gate while having a very weak etching effect on the underlying gate oxide layer. It can hardly damage the original structure of the gate oxide layer, and can completely preserve the original morphology and actual size of the void defects inside the gate oxide, avoiding the distortion of defect morphology caused by over-etching, thereby ensuring the accuracy of subsequent defect identification. The potassium hydroxide wet etching process is mature and stable, with flexible and convenient parameter adjustment. The solution concentration, reaction temperature, and etching time can be adjusted according to the process node and gate oxide thickness of the chip under test. For thick gate oxide processes, the concentration and temperature can be appropriately increased to accelerate the etching speed, while for thin gate oxide processes, the parameters can be lowered to ensure etching controllability. It is suitable for sample processing of various process nodes. At the same time, this process can simultaneously immerse the entire chip, eliminating the need for point-by-point processing of individual devices. This can significantly reduce sample preparation time, and the etched sample surface is less likely to introduce additional impurities and secondary damage, reducing the interference of false defects on subsequent scanning observations. This improves detection efficiency while ensuring the reliability of detection results.

[0116] Specifically, the operation method of wet etching is as follows: Figure 4 As shown, the first intermediate chip under test, after grinding, is immersed in an etching container containing KOH solution, so that the front side of the chip with the polysilicon gate is completely submerged in the solution. The polysilicon material is selectively removed by wet etching. This process utilizes the high etching selectivity of potassium hydroxide solution for polysilicon and gate oxide layer, which can completely remove all polysilicon gate while almost not damaging the underlying gate oxide layer, thereby fully exposing the surface of the gate oxide layer and preserving the original morphology of void defects, thus obtaining the second intermediate chip under test. The actual etching parameters need to be flexibly adjusted according to the process node and gate oxide thickness of the chip under test. Refer to the recommended parameters in Table 1 for matching: For devices with a 180nm process node and a gate oxide thickness of 8~12nm, a 20±1wt% KOH solution can be used, with the solution temperature controlled at 80±1℃ and the etching time set to 22~25s, corresponding to a polysilicon etching rate of approximately 18~22nm / s. As the process node advances and the gate oxide thickness gradually decreases, the etching solution concentration and reaction temperature need to be adjusted accordingly, and the etching time shortened. For example, for devices with a 40nm process node and a gate oxide thickness of 1.2~2nm, a 10±1wt% KOH solution can be used, etched at 65±1℃ for 12~15s, with an etching rate of approximately 5~8nm / s. This balances etching efficiency with the structural integrity of the gate oxide layer, avoiding over-etching of the thin gate oxide and damaging the internal void defect morphology, thus ensuring the accuracy of subsequent defect observation and identification.

[0117] Table 1 Recommended KOH wet etching parameters for different process nodes

[0118] S4. The second intermediate chip under test is cleaned and dried sequentially to obtain the third intermediate chip under test;

[0119] In some embodiments, the step of sequentially cleaning and drying the second intermediate chip under test to obtain the third intermediate chip under test includes:

[0120] The second intermediate test chip was placed in deionized water for ultrasonic cleaning to remove etching reaction byproducts, polysilicon etching residues and particulate contaminants from the surface of the second intermediate test chip, thus obtaining the fourth intermediate test chip.

[0121] The fourth intermediate test chip was statically rinsed with deionized water to remove the residual etching solution on the surface of the fourth intermediate test chip, thus obtaining the fifth intermediate test chip.

[0122] The fifth intermediate chip under test is dried to obtain the third intermediate chip under test.

[0123] Specifically, as shown in Figure 5, the second intermediate test chip, after wet etching, is first placed in a cleaning tank containing deionized water. The cleaning tank is then placed on an ultrasonic cleaning stage and ultrasonic oscillation is initiated. The cavitation effect of the ultrasonic waves is used to fully remove the etching reaction byproducts, polysilicon etching residues, and various particulate contaminants attached to the chip surface. This prevents impurities from obscuring voids or forming pseudo-defects on the gate oxide layer surface, which could interfere with subsequent observations. After ultrasonic cleaning, a preliminarily clean intermediate sample is obtained. Subsequently, the sample is removed, and the chip surface is statically rinsed with fresh deionized water to further remove the potassium hydroxide etching solution remaining on the chip surface and in the structural gaps. This prevents the residual solution from continuing to corrode the gate oxide layer, avoids destroying the original morphology of voids and defects, and ensures the accuracy of subsequent defect identification. After rinsing, the sample is dried. High-purity nitrogen can be used to slowly blow water stains off the chip surface to avoid watermarks from forming during natural drying, which could affect the clarity of the scanning image. Finally, a third intermediate test chip with a clean surface and a state that meets the requirements for planar morphology scanning is obtained.

[0124] S5. Perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer, and determine the void defect detection result of the gate oxide layer of the chip under test based on the void defect scanning image.

[0125] In some embodiments, performing planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer includes:

[0126] The third intermediate chip under test is fixed to the sample stage of a scanning electron microscope so that the third intermediate chip under test is electrically connected to the sample stage and grounded.

[0127] The scanning electron microscope is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain the scanning image of the void defect in the gate oxide layer.

[0128] Specifically, such as Figure 6 As shown, the planar morphology scanning of the gate oxide layer was performed using a scanning electron microscope (SEM). First, conductive adhesive was applied to the surface of the SEM stage. The back of the third intermediate chip under test was then smoothly mounted onto the conductive adhesive for fixation. The conductive adhesive provided a reliable electrical connection and grounding between the chip and the stage, thus dissipating the charge accumulated on the insulating gate oxide surface during electron beam irradiation. This prevented image whitening and drifting caused by the charging effect, ensuring the clarity and accuracy of subsequent imaging and the authenticity of the defect morphology. After mounting, the stage was placed into the vacuum chamber of the SEM. The appropriate accelerating voltage, beam current parameters, and working distance were set according to the chip manufacturing process. The focused electron beam was controlled to scan the gate oxide surface line by line, acquiring the secondary electron signals generated and converting them into surface morphology images. During observation, the magnification could be flexibly adjusted. A low-magnification mode was first used to complete a full-area scan of the large gate oxide region, quickly grasping the overall distribution of void defects. Then, the high-magnification mode was switched to perform detailed observation of individual defects, ultimately obtaining a scanned image of void defects in the gate oxide layer. This provides an intuitive and accurate basis for subsequent defect statistics and failure analysis.

[0129] Specifically, determining the void defect detection result of the gate oxide layer of the chip under test based on the void defect scanning image can be implemented through the following preferred scheme:

[0130] First, the dimensions are calibrated using the electron microscope scale attached to the scanned images of void defects. Then, void defects on the gate oxide layer are identified based on the differences in morphological contrast in the images. After identification, the total number of void defects, their planar distribution, the equivalent diameter and projected area of ​​each individual defect in the observation area are counted, and the void defect density in the observation area is calculated. Finally, the statistically obtained defect parameters are compared with the preset quality control thresholds of the corresponding process nodes. Combined with the electrical anomaly degree obtained from the previous volt-ampere characteristic test, the defect level and reliability risk of the gate oxide layer of the chip under test are comprehensively determined to form the final void defect detection result.

[0131] Furthermore, to fully illustrate the effectiveness of the embodiments of this application, it can be combined with... Figure 7 and Figure 8 A direct comparison was made between the actual measured observation results and those of the two institutions. Figure 7The results obtained from cross-sectional observation using existing testing methods can only present the local state of the gate oxide cross-section at a single cutting point, as shown in the area marked by the red box in the figure. The observation range is very limited, making it impossible to grasp the planar distribution pattern of void defects. It is also prone to missed detections due to the cutting position deviating from the defect. Furthermore, a single sample preparation can only complete a single-point observation, resulting in low detection efficiency. Figure 8 The planar morphology observation results obtained by the test scheme of this invention can fully present the surface state of the entire gate oxide layer, and can intuitively identify the void defects marked in the red box in the figure. Not only can the morphology and size of the defects be clearly observed, but the number and overall distribution of defects can also be comprehensively counted, effectively avoiding the problem of missed detection and ensuring the detection accuracy. At the same time, there is no need to perform fixed-point cutting and sample preparation. A single processing can complete the defect investigation of a large area, significantly improving the overall detection efficiency of void defects in the gate oxide layer.

[0132] Example 2

[0133] like Figure 9 As shown, based on the above method embodiments, corresponding device embodiments are provided;

[0134] An embodiment of the present invention provides a hole defect detection system for chip gate oxide layer, including a first detection module 91, a second detection module 92, a third detection module 93, a fourth detection module 94 and a fifth detection module 95;

[0135] The first detection module 91 is used to perform current-voltage characteristic testing on the chip under test in order to determine whether there is any voltage or current abnormality in the gate oxide layer of the chip under test.

[0136] The second detection module 92 is used to grind the chip under test if there is an abnormal voltage or current in the gate oxide layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, so as to obtain the first intermediate chip under test.

[0137] The third detection module 93 is used to perform wet selective etching on the first intermediate chip under test to expose the gate oxide failure points of the first intermediate chip under test and obtain the second intermediate chip under test.

[0138] The fourth detection module 94 is used to sequentially clean and dry the second intermediate chip under test to obtain the third intermediate chip under test;

[0139] The fifth detection module 95 is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test, obtain a void defect scanning image of the gate oxide layer, and determine the void defect detection result of the gate oxide layer of the chip under test based on the void defect scanning image.

[0140] This application pre-screens chips with abnormal voltage or current by conducting a preliminary volt-ampere characteristic test, ensuring that subsequent sample preparation and observation are carried out on suspected failed samples, avoiding aimless blind testing, and guaranteeing the targeting and accuracy of defect detection. Next, this application removes the chip's surface stacked structure through mechanical polishing, terminating at the polysilicon gate surface. This allows for rapid sample pretreatment in a parallel, whole-wafer manner, improving sample preparation efficiency compared to point-by-point cutting, and providing a uniform starting surface for subsequent wet etching, avoiding excessive polishing that damages the gate oxide layer and destroys the original morphology of void defects. Then, this application uses wet selective etching... The etching process utilizes the high etching selectivity of the etching system for polysilicon and gate oxide layers. This allows for the complete removal of the entire polysilicon gate and exposure of the complete gate oxide surface in a single operation, while preserving the original morphology of the gate oxide layer and void defects. This eliminates the need for preparing cross-sectional samples for each individual point, improving the efficiency and coverage of defect exposure. Cleaning and drying processes remove etching byproducts, polysilicon residue, and residual etching solution, preventing residue from obscuring defects or creating false defects that interfere with observation. This ensures the clarity of subsequent scanning imaging and the accuracy of defect identification. Finally, planar morphology scanning of the gate oxide layer and determination of the detection results enable comprehensive observation of a large area of ​​the gate oxide region in a single operation. Therefore, the embodiments of this application solve the problem in existing technologies of simultaneously improving the detection efficiency of void defects while maintaining accuracy.

[0141] In some embodiments, grinding the chip under test until the upper surface of the polysilicon gate of the chip under test is uniformly exposed to obtain a first intermediate chip under test includes:

[0142] The chip under test is polished using polishing media to remove the metal interconnect layer, interlayer dielectric layer and contact hole filling layer on the surface of the chip under test layer by layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, at which point polishing is stopped to obtain the first intermediate chip under test.

[0143] In this preferred embodiment, the metal interconnect layer, interlayer dielectric layer, and contact hole filling layer of the chip surface are removed layer by layer using a polishing medium. The surface structure can be quickly stripped by polishing the entire chip in parallel, which significantly improves the pre-processing efficiency compared to the point-by-point cutting method. At the same time, the polishing is precisely terminated on the upper surface of the polysilicon gate, which can avoid over-polishing and damage to the gate oxide layer and destroy the original morphology of void defects, ensuring the accuracy of subsequent defect identification. It can also provide a uniform working surface for subsequent wet etching, ensuring stable and controllable etching effect.

[0144] In some embodiments, the grinding media is aluminum oxide.

[0145] In this preferred example, alumina is used as the polishing medium. Its hardness is well-suited to the multi-layer structure of the chip surface, and the polishing rate is stable and controllable. It can efficiently complete the layer-by-layer peeling of structures such as metal interconnect layers and interlayer dielectric layers, effectively shortening the polishing sample preparation time and improving the sample pretreatment efficiency. At the same time, alumina particles have good uniformity, resulting in high surface flatness after polishing. It is not easy to cause over-polishing or surface scratch damage, and it can accurately terminate at the polysilicon gate surface, avoiding damage to the original morphology of the underlying gate oxide layer and void defects, thus ensuring the accuracy of subsequent defect identification.

[0146] In some embodiments, performing wet selective etching on the first intermediate chip under test to expose gate oxide failure points of the first intermediate chip under test to obtain a second intermediate chip under test includes:

[0147] The first intermediate chip under test is immersed in a preset solution for wet etching. By utilizing the etching selectivity ratio of the preset solution for polysilicon and gate oxide, all polysilicon gates are selectively removed, thereby exposing the gate oxide failure points of the first intermediate chip under test and obtaining the second intermediate chip under test.

[0148] In this preferred embodiment, the first intermediate chip under test is immersed in a preset solution for wet etching. The entire polysilicon gate can be removed in one go through parallel processing of the whole chip, eliminating the need to prepare cross-sectional samples point by point, thus shortening the sample preparation cycle. At the same time, by utilizing the etching selectivity ratio of the solution to polysilicon and gate oxide layer, polysilicon can be selectively etched without damaging the gate oxide layer, thus completely preserving the original morphology of void defects. This ensures the accuracy of defect identification and fully exposes the gate oxide failure area, avoiding the risk of missed detection due to local observation.

[0149] In some embodiments, the preset solution is a potassium hydroxide solution.

[0150] In this preferred embodiment, potassium hydroxide solution is used as the etching solution. It exhibits extremely high etching selectivity for both polysilicon and the gate oxide layer, removing the polysilicon gate while almost completely preserving the underlying gate oxide layer, thus ensuring the accuracy of defect identification. Furthermore, the potassium hydroxide etching process is mature and stable, with a uniform and controllable etching rate, enabling simultaneous processing of the entire chip. It also minimizes the introduction of additional impurities, reducing the interference of false defects on the detection results.

[0151] In some embodiments, the step of sequentially cleaning and drying the second intermediate chip under test to obtain the third intermediate chip under test includes:

[0152] The second intermediate test chip was placed in deionized water for ultrasonic cleaning to remove etching reaction byproducts, polysilicon etching residues and particulate contaminants from the surface of the second intermediate test chip, thus obtaining the fourth intermediate test chip.

[0153] The fourth intermediate test chip was statically rinsed with deionized water to remove the residual etching solution on the surface of the fourth intermediate test chip, thus obtaining the fifth intermediate test chip.

[0154] The fifth intermediate chip under test is dried to obtain the third intermediate chip under test.

[0155] In this preferred example, ultrasonic cleaning with deionized water can effectively remove etching reaction byproducts, polysilicon etching residues, and particulate contaminants from the chip surface, preventing impurities from obscuring void defects or forming pseudo-defects, and ensuring the clarity of subsequent scanning imaging and the accuracy of defect identification; then static rinsing with deionized water removes residual etching solution, preventing residual liquid from continuously corroding the gate oxide layer and destroying the original morphology of the defects.

[0156] In some embodiments, performing an volt-ampere characteristic test on the chip under test to determine whether there is an abnormal voltage or current in the gate oxide layer of the chip under test includes:

[0157] A scanning voltage is applied to the gate of the chip under test to acquire the current-voltage characteristic curve corresponding to the gate, and the gate leakage current value and gate oxide breakdown voltage value of the chip under test are determined based on the current-voltage characteristic curve.

[0158] Based on the gate leakage current value and the gate oxide breakdown voltage value, it is determined whether there is an abnormal voltage or current in the gate oxide layer of the chip under test.

[0159] In this preferred example, by applying a scanning voltage to the gate of the chip under test and acquiring the current-voltage characteristic curve, two electrical parameters, namely the gate leakage current value and the gate oxide breakdown voltage value, can be quickly extracted. Based on the comprehensive determination of the two parameters, it is possible to determine whether there is an abnormality in the gate oxide layer. This allows for rapid batch screening, early exclusion of normal chips, avoidance of invalid sample preparation and observation processes, and improvement of overall detection efficiency from the source.

[0160] In some embodiments, determining whether there is a voltage or current abnormality in the gate oxide layer of the chip under test based on the gate leakage current value and the gate oxide breakdown voltage value includes:

[0161] Calculate the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard breakdown voltage value to obtain the breakdown voltage reduction magnitude;

[0162] If the breakdown voltage decrease is greater than or equal to a preset threshold value, or the gate leakage current exceeds a preset leakage current standard range, then it is determined that there is a voltage or current abnormality in the gate oxide layer of the chip under test.

[0163] In this preferred example, the degree of failure is defined quantitatively by calculating the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard value, thus avoiding subjective errors in qualitative judgment. The dual-condition judgment of breakdown voltage reduction threshold and leakage current standard range can cover different manifestations of gate oxide void failure, reducing the probability of missed and false judgments.

[0164] In some embodiments, performing planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer includes:

[0165] The third intermediate chip under test is fixed to the sample stage of a scanning electron microscope so that the third intermediate chip under test is electrically connected to the sample stage and grounded.

[0166] The scanning electron microscope is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain the scanning image of the void defect in the gate oxide layer.

[0167] In this preferred embodiment, fixing the third intermediate chip under test to the scanning electron microscope sample stage and electrically connecting it to ground can eliminate the charging effect caused by the insulating properties of the gate oxide layer, avoid whitening and blurring of the scanned image, ensure the clarity and authenticity of the scanned image of void defects, and improve the accuracy of defect identification. By performing planar morphology scanning with a scanning electron microscope, a large area of ​​gate oxide can be covered at once, without the need to prepare cross-sectional samples point by point, which improves the efficiency of defect investigation, while fully presenting the morphology and distribution of defects and ensuring the accuracy of detection.

[0168] For more detailed steps and working principles of this embodiment, please refer to the relevant description in Embodiment 1, but not limited to these descriptions.

[0169] It should be noted that the device embodiments described above are merely illustrative, and some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided in this application, the connection relationships between modules indicate that they have communication connections, which can specifically be implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

[0170] Example 3

[0171] Based on the above embodiments of the chip gate oxide void defect detection method, another embodiment of this application provides a terminal device, which includes a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor. When the processor executes the computer program, it implements the chip gate oxide void defect detection method of any embodiment of this application.

[0172] For example, in this embodiment, the computer program can be divided into one or more modules, which are stored in the memory and executed by the processor to complete this application. The one or more module units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of the computer program in the terminal device.

[0173] The terminal device may be a desktop computer, laptop, handheld computer, or cloud server, etc. The terminal device may include, but is not limited to, a processor and a memory.

[0174] The processor can be a Central Processing Unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor can be a microprocessor or any conventional processor. The processor is the control center of the terminal device, connecting all parts of the terminal device via various interfaces and lines.

[0175] Example 4

[0176] Based on the above-described method embodiments, another embodiment of this application provides a computer-readable storage medium including a stored computer program, wherein, when the computer program is executed, it controls the device where the computer-readable storage medium is located to perform the chip gate oxide void defect detection method described in any of the above-described method embodiments of this application.

[0177] The modules / units integrated in the device / terminal equipment, if implemented as software functional units and sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

Claims

1. A method for detecting void defects in the gate oxide layer of a chip, characterized in that, include: Perform current-voltage characteristic tests on the chip under test to determine whether there are voltage or current abnormalities in the gate oxide layer of the chip under test; If there is an abnormal voltage or current in the gate oxide layer, the chip under test is ground until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, thus obtaining the first intermediate chip under test. The first intermediate chip under test is subjected to wet selective etching to expose the gate oxide layer of the first intermediate chip under test, thereby obtaining the second intermediate chip under test; The second intermediate chip under test is sequentially cleaned and dried to obtain the third intermediate chip under test; A planar topography scan is performed on the gate oxide layer of the third intermediate chip under test to obtain a void defect scan image of the gate oxide layer, and the void defect detection result of the gate oxide layer of the chip under test is determined based on the void defect scan image.

2. The method for detecting void defects in the gate oxide layer of a chip as described in claim 1, characterized in that, The process of grinding the chip under test until the upper surface of the polysilicon gate of the chip under test is uniformly exposed to obtain the first intermediate chip under test includes: The chip under test is polished using polishing media to remove the metal interconnect layer, interlayer dielectric layer and contact hole filling layer on the surface of the chip under test layer by layer until the upper surface of the polysilicon gate of the chip under test is uniformly exposed, at which point polishing is stopped to obtain the first intermediate chip under test.

3. The method for detecting void defects in the gate oxide layer of a chip as described in claim 2, characterized in that, The grinding medium is aluminum oxide.

4. The method for detecting void defects in the gate oxide layer of a chip as described in claim 1, characterized in that, The step of performing wet selective etching on the first intermediate chip under test to expose the gate oxide layer of the first intermediate chip under test to obtain the second intermediate chip under test includes: The first intermediate chip under test is immersed in a preset solution for wet etching. By utilizing the etching selectivity ratio of the preset solution for polysilicon and gate oxide layer, all polysilicon gates are selectively removed, thereby exposing the gate oxide layer of the first intermediate chip under test and obtaining the second intermediate chip under test.

5. The method for detecting void defects in the gate oxide layer of a chip as described in claim 4, characterized in that, The preset solution is a potassium hydroxide solution.

6. The method for detecting void defects in the gate oxide layer of a chip as described in claim 1, characterized in that, The process of sequentially cleaning and drying the second intermediate chip under test to obtain the third intermediate chip under test includes: The second intermediate test chip was placed in deionized water for ultrasonic cleaning to remove etching reaction byproducts, polysilicon etching residues and particulate contaminants from the surface of the second intermediate test chip, thus obtaining the fourth intermediate test chip. The fourth intermediate test chip was statically rinsed with deionized water to remove the residual etching solution on the surface of the fourth intermediate test chip, thus obtaining the fifth intermediate test chip. The fifth intermediate chip under test is dried to obtain the third intermediate chip under test.

7. The method for detecting void defects in the gate oxide layer of a chip as described in claim 1, characterized in that, The step of performing an volt-ampere characteristic test on the chip under test to determine whether there are voltage or current abnormalities in the gate oxide layer of the chip under test includes: A scanning voltage is applied to the gate of the chip under test to acquire the current-voltage characteristic curve corresponding to the gate, and the gate leakage current value and gate oxide breakdown voltage value of the chip under test are determined based on the current-voltage characteristic curve. Based on the gate leakage current value and the gate oxide breakdown voltage value, it is determined whether there is an abnormal voltage or current in the gate oxide layer of the chip under test.

8. The method for detecting void defects in the gate oxide layer of a chip as described in claim 7, characterized in that, The step of determining whether there is an abnormal voltage or current in the gate oxide layer of the chip under test based on the gate leakage current value and the gate oxide breakdown voltage value includes: Calculate the reduction ratio of the gate oxide breakdown voltage value relative to the preset standard breakdown voltage value to obtain the breakdown voltage reduction magnitude; If the breakdown voltage decrease is greater than or equal to a preset threshold value, or the gate leakage current exceeds a preset leakage current standard range, then it is determined that there is a voltage or current abnormality in the gate oxide layer of the chip under test.

9. The method for detecting void defects in the gate oxide layer of a chip as described in claim 1, characterized in that, The step of performing planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain a void defect scanning image of the gate oxide layer includes: The third intermediate chip under test is fixed to the sample stage of a scanning electron microscope so that the third intermediate chip under test is electrically connected to the sample stage and grounded. The scanning electron microscope is used to perform planar topography scanning on the gate oxide layer of the third intermediate chip under test to obtain the scanning image of the void defect in the gate oxide layer.

10. A system for detecting void defects in a chip gate oxide layer, characterized in that, The void defect detection system is used to perform the void defect detection method for the chip gate oxide layer as described in any one of claims 1-9.

Images