An on-line monitoring and cross-verification system and method for multi-site chip testing

Abstract

The application provides an online monitoring and cross verification system and method for multi-station chip testing. The system comprises: a main controller for resource scheduling of the whole system and monitoring of test data; an evaluation module for evaluating the comprehensive risk coefficient of each test station based on the yield, mean and variance of each test item in the measured data compared with the deviation rate of the benchmark; a scheduling module for automatically extracting the measured good chips from the test station with the lowest comprehensive risk coefficient and carrying them to the test station with the highest comprehensive risk coefficient for cross verification test when the comprehensive risk coefficient of any test station exceeds the threshold, so as to confirm whether there is false kill in the station and trigger a maintenance warning; and a diagnosis module for mapping the test data of the false kill chips to the underlying relevant physical test channels and outputting the failure probability ranking of each channel as the pointing information for accurate maintenance when it is confirmed that there is false kill. The application realizes early automatic warning of test abnormalities, zero interruption verification in mass production and accurate fault positioning at the channel level.

Description

Technical Field

[0001] This invention relates to the field of automated chip testing, specifically to an online monitoring and cross-validation system and method for multi-station chip testing. Background Technology

[0002] Automated Test Equipment (ATE) is a core piece of equipment used in the mass production of integrated circuits for verifying the electrical performance and functionality of wafers and chips. To improve the testing efficiency of large batches of chips, ATE platforms generally adopt a multi-site parallel testing architecture, which can simultaneously perform parallel tests on multiple chips, significantly reducing the testing time for a single chip.

[0003] For status monitoring and anomaly troubleshooting during multi-site testing, conventional techniques in this field typically involve: online monitoring of batch yield, real-time yield of approximately 100 chips, the number of consecutively failing chips, and the proportion of a certain type of failure to confirm whether there are anomalies in the testing environment; once an anomaly is confirmed, mass production testing is paused, and offline consistency calibration and troubleshooting are performed using a pre-fabricated Golden Unit. However, this approach suffers from three major insurmountable defects in actual mass production:

[0004] 1. The monitoring mode is singular and suffers from severe lag. Most ATE (Automatic Test Equipment) systems can only detect anomalies based on changes in yield. The single yield indicator monitoring mode has a slow response and a high false alarm rate. It is often not detected until the anomalies accumulate to the point of significant yield loss leading to downtime, which has a significant impact on production efficiency. Moreover, this mode cannot effectively distinguish between chip inherent performance problems and test environment problems.

[0005] 2. Fault verification relies on offline manual operation, interrupting the mass production process. Differences exist between different workstations, and existing solutions cannot confirm in real time whether a failed wafer or chip is due to an inherent anomaly or a machine malfunction. Fault verification heavily relies on manual stress testing of the Golden Unit offline, requiring system shutdown for offline calibration verification, making online fault confirmation impossible during mass production testing.

[0006] 3. Inaccurate anomaly localization, heavily reliant on manual experience. After confirming machine failure, current anomaly diagnosis often requires collaboration between product and equipment engineers, manually reviewing test data and equipment logs. Existing data can only identify which workstation is malfunctioning, lacking online, channel-level fault localization. This troubleshooting process can take anywhere from minutes to days, heavily depending on the operator's technical experience and teamwork, resulting in significant uncertainty in efficiency and consuming substantial production machine time, substantially increasing testing costs. Summary of the Invention

[0007] To address the shortcomings of existing automated test equipment (ATE) in multi-station testing, such as single monitoring indicators, delayed anomaly response, reliance on manual offline operation for cross-validation, and ambiguous fault location, this application provides an online monitoring and cross-validation system and method for multi-station chip testing, aiming to achieve early warning of test risks, automated online verification, and accurate fault diagnosis at the channel level.

[0008] This application provides the following technical solutions to achieve the above effects:

[0009] An online monitoring and cross-validation system for multi-station chip testing includes:

[0010] The main controller is used to monitor the test data of each test station, and for each test station, calculate the real-time pass rate, average value and variance of each test item.

[0011] The evaluation module is used to acquire test data for each test item at each test station, calculate the corresponding yield, mean, and variance; compare the yield, mean, and variance of each test station with the benchmark values ​​corresponding to all test stations to obtain the offset rate, and perform weighted calculation based on each offset rate to evaluate the risk coefficient of each test item at that test station; and obtain a comprehensive risk coefficient characterizing the risk coefficient of that test station based on the risk coefficient of each test item.

[0012] The scheduling module is used to automatically extract chips that have been tested as good from the test station with the lowest risk coefficient and move them to the test station with the highest overall risk coefficient for cross-verification testing when the overall risk coefficient of a certain test station exceeds a preset threshold.

[0013] If the test result is still qualified, the overall risk coefficient of the test station is reduced and normal testing is maintained; if the test result is unqualified, it is determined that there is an error in the high-risk station in classifying the product as non-defective and a maintenance warning is triggered.

[0014] The diagnostic module is used to extract the test data of the chip that was incorrectly identified as a defective product at a high-risk test station when an error occurs. It then maps the data to the physical test channel to determine which test channel is faulty, providing guidance for subsequent targeted repairs.

[0015] The evaluation module is used to: acquire test data for a certain test item from all current test stations; calculate the average value of the test data and set it as the benchmark value for that test item; compare the yield, mean, and variance of each test station under that test item with the corresponding yield benchmark, mean benchmark, and variance benchmark in the benchmark value to obtain the offset rate; perform a weighted calculation based on the offset rate to evaluate the risk coefficient of each test item for each test station. For the j-th test item on test station N, the specific formula is:

[0016] ;

[0017] in, This represents the yield offset of the j-th test item at test station N, and , This represents the yield of the j-th test item at test station N. This represents the yield baseline value of the j-th test item across all test stations;

[0018] This represents the mean offset of the j-th test item at test station N, and , This represents the mean of the j-th test item at test station N. The baseline value represents the mean of the j-th test item across all test stations;

[0019] This represents the variance offset of the j-th test item at test station N, and , Let represent the variance of the j-th test item at test station N. The baseline value represents the variance of the j-th test item across all test stations;

[0020] These are the weighting coefficients for yield, mean, and variance, respectively, and they satisfy... .

[0021] Furthermore, for any test station, the risk coefficient of each test item is calculated, and the risk coefficient with the largest value is selected as the comprehensive risk coefficient of the test station. The main controller is used to summarize the comprehensive risk coefficients of each test station and rank them in descending order. The test station that ranks first and exceeds the preset threshold is locked as a high-risk station, and the scheduling module is triggered to perform the action of moving the good chip to the high-risk station for cross-verification.

[0022] Furthermore, the test items include DC parameter test items or RF parameter test items; wherein, the DC parameter test items include at least one of open / short circuit, leakage current, and operating current; and the RF parameter test items include at least one of S-parameters and vector error amplitude.

[0023] Furthermore, the main controller can simultaneously control at least four test stations.

[0024] This application also provides an online monitoring and cross-validation method for multi-station chip testing, the method comprising the following steps:

[0025] For a specific test item, calculate the overall yield, global mean, and global variance of all test stations as a reference benchmark.

[0026] Calculate the yield, mean, and variance of the target test station for this test item, and compare them with the reference benchmark to obtain the yield deviation rate, mean deviation rate, and variance deviation rate.

[0027] The yield deviation rate, mean deviation rate and variance deviation rate are assigned preset weighting coefficients and normalized to obtain the risk coefficient of the target test station on a test item. Then, the risk coefficients of all test items on the test station are automatically calculated one by one, and the maximum value is used to represent the risk coefficient of the test station.

[0028] When the risk coefficient of a test station exceeds the preset threshold, the chip that has been tested as good is automatically extracted from the test station with the lowest overall risk coefficient and moved to the test station with the highest overall risk coefficient for cross-validation testing.

[0029] If the test result is still qualified, the risk factor of the test station is reduced and normal testing is maintained; if the test result is unqualified, it is determined that the high-risk station has erroneously identified the product as non-defective and a maintenance warning is triggered.

[0030] When a high-risk workstation is found to have a chip that was incorrectly identified as a defective product, the test data of the chip that was incorrectly identified as a defective product is extracted from that test workstation.

[0031] Based on the test plan and test procedures, iterate through all the test items performed by the chip and count the total number of times it is associated with the i-th physical test channel. Iterate through all failure items of a failed chip and count the total number of times it is associated with the i-th physical test channel. The probability of the physical test channel failing is... .

[0032] The failure probability of all physical test channels is ranked from high to low to provide guidance for targeted repairs.

[0033] Furthermore, the comprehensive risk coefficient is the one with the highest risk coefficient among all test items. The main server is used to calculate the comprehensive risk coefficient of each test station and rank each test station according to the comprehensive risk coefficient, and the station with the highest comprehensive risk coefficient is converted into a high-risk station.

[0034] Furthermore, the test items include DC parameter test items or RF parameter test items; wherein, the DC parameter test items include at least one of open / short circuit, leakage current, and operating current; and the RF parameter test items include at least one of S-parameters and vector error amplitude.

[0035] Furthermore, the main controller can control four test stations simultaneously.

[0036] This application has the following significant advantages over the prior art:

[0037] 1. Significantly improved the sensitivity and timeliness of anomaly warnings.

[0038] Traditional test monitoring often relies on a single yield metric, which can easily mask early physical degradation of equipment. This application introduces a multi-dimensional offset rate of yield, mean, and variance, and performs a weighted comprehensive evaluation. This enables the system to keenly detect subtle degradation of the test environment (such as measurement fluctuations caused by slight probe wear) before yield loss occurs. It successfully achieves a leap from traditional "post-event shutdown alarm" to "pre-event trend warning," effectively avoiding yield loss.

[0039] 2. Online automation of cross-validation and zero-disruption mass production have been achieved.

[0040] When the system triggers an anomaly warning, there is no need for manual intervention or interruption of the normal mass production feeding process to manually test standard samples (Golden Units). This application innovatively schedules known good products generated in real time at low-risk workstations within the system for cross-workstation retesting and verification. This mechanism not only perfectly eliminates interference from defective chips themselves, but also achieves true online closed-loop verification, greatly ensuring the continuous uptime of the testing equipment and significantly improving the overall equipment efficiency.

[0041] 3. It has achieved precise location of faults by tracing them back to the underlying physical links.

[0042] This application breaks away from the traditional reliance on engineers' experience for troubleshooting after an anomaly occurs. By constructing a failure probability algorithm, the system can map abstract test item failures to the physical path of failure. Specifically, it can accurately pinpoint a complete failure path, including the test socket, the probe (Pogo Pin), the PCB trace, and ultimately the internal board resources of the ATE test equipment. This feature eliminates the heavy reliance on individual engineer experience in traditional fault diagnosis, significantly shortens the mean time to repair (MTBT), and thus effectively reduces the maintenance and operating costs of the production line. Attached Figure Description

[0043] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0044] Figure 1 This is a system architecture diagram of online monitoring and cross-validation for multi-station chip testing in an embodiment of this application;

[0045] Figure 2 This is a flowchart of the online monitoring and cross-validation method in the embodiments of this application;

[0046] Figure 3 This is a schematic diagram of cross-station verification of the sorting machine in an embodiment of this application;

[0047] Figure 4 This is a schematic diagram of fault association probability and channel mapping in the embodiments of this application. Detailed Implementation

[0048] The present invention will be further described below with reference to the accompanying drawings and specific embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without inventive effort are within the scope of protection of the present invention.

[0049] Example 1:

[0050] like Figure 1 As shown, this embodiment provides an online monitoring and cross-validation system for multi-station chip testing. The system includes a main controller, which is the scheduling and computation core of the entire system and communicates with external test and sorting machines via a data interface. Specifically, the main controller integrates an evaluation unit, a scheduling unit, and a diagnostic unit. In this architecture, the main controller is responsible for overall data throughput and task distribution, while each unit performs specific logical operations.

[0051] 1. Evaluation Module: As the core of real-time monitoring and evaluation for the main controller, the evaluation unit is used to obtain the raw test data of each test item at each test station from the main controller. This unit calculates the risk coefficient based on the degree to which the yield, mean, and variance of each test item deviate from the global benchmark value.

[0052] Yield rate has the greatest impact on the risk factor. Failure of any test item will directly lead to the final judgment of the chip as a failure; therefore, yield loss generally has the greatest impact on the risk factor. For the j-th test item, after iterating through the Pass / Fail results of this test item across all test stations (from the 1st to the Mth), its average yield is obtained:

[0053]

[0054] in: This represents the yield offset of the j-th test item at workstation N, and , This represents the yield of the j-th test item on site N. This represents the yield baseline value for the j-th test item at all sites, i.e., the test station.

[0055] Moving on to the mean, sometimes the deviation doesn't cause serious yield consequences, but a continuous deviation can have a progressively more severe impact on yield. Therefore, deviations in the mean also pose a certain risk. For the j-th test item, after iterating through the test values ​​of this item across all test stations (from the 1st to the Mth), the mean of its test values ​​is obtained. :

[0056]

[0057] For station N, use yield offset. This represents the mean deviation of the j-th test item at this workstation. The larger the deviation relative to the mean of all workstations, the higher the risk of that workstation. The calculation method is as follows: , Let represent the mean of the j-th test item on site N. This represents the baseline value of the mean of the j-th test item across all sites.

[0058] Finally, there's the variance component. Variance indicates the degree of dispersion of the numerical values, which reflects the chip quality and the stability of the testing platform. Therefore, variance also has a certain impact on the risk coefficient, although it's relatively smaller compared to yield and mean. For the j-th test item, after iterating through the test values ​​of that item across all testing stations (from the 1st to the Mth), the variance of its test value is calculated. :

[0059]

[0060] For station N, use yield offset. This represents the variance offset of the j-th test item at this workstation. The larger the variance offset relative to all workstations, the higher the risk of this workstation. The calculation method is as follows:

[0061] This represents the variance offset of the j-th test item at workstation N, and , This represents the variance of the j-th test item on site N. This represents the baseline value of the variance of the j-th test item across all sites.

[0062] After weighting the three factors, a risk coefficient is derived:

[0063]

[0064] These are the weighting coefficients for yield, mean, and variance, respectively, and they satisfy... .

[0065] Automatically traverse all test items on the target test station and select the risk coefficient with the largest value as the comprehensive risk coefficient of that test station;

[0066] 2. Scheduling Module: As the core of the main controller's action control, the scheduling unit monitors the risk coefficient of each workstation. When the risk coefficient of a certain workstation triggers a preset threshold, the unit generates a handling control command, which is sent by the main controller to the sorting machine, driving it to perform the action of extracting good products from the low-risk workstation and transferring them to the high-risk workstation for retesting.

[0067] 3. Diagnostic Module: As the core of the main controller's failure analysis, the fault diagnosis unit is executed when retesting fails. This unit retrieves the test plan and test program mapping table stored in the main controller, analyzes the failure data of the mistakenly killed chip, and calculates the probability of physical channel failure. The specific calculation logic is as follows:

[0068] Count the total number of times the i-th physical test channel is called. And the number of times each failure item of the chip is associated with the i-th physical test channel. Calculate the failure probability of this physical channel. The fault diagnosis module is based on the failure probability. Rank them from highest to lowest and output repair guidance information.

[0069] The specific calculation method is given below:

[0070] set up Let the physical test channel be numbered. The test item number ( To express whether something is "relevant" and "ineffective," two binary variables (taking values ​​of 0 or 1) are introduced:

[0071] Channel-related indicator variables (Indicates the relationship between test items and channels):

[0072]

[0073] Test result indicator variable (This indicates the chip's performance on a specific test item):

[0074]

[0075] Based on the above definition, the first physical channel and It can be done on all Sum the total number of physical channel calls for each test item. :

[0076]

[0077] Iterate through all test items If the test item matches the channel If relevant, then Increment the counter by 1; if irrelevant, then... The counter increments by 0.

[0078] And the number of associated failures The definition is:

[0079]

[0080] This formula utilizes the properties of multiplication. It only applies when the test item... Both with the channel Related ( ), and the test item also triggered a failure ( )hour, The result is 1, which is included. In any other case (irrelevant, or relevant but the test passed), the product is 0.

[0081] Substituting the two summation formulas above into the basic formula in the original diagram, the final channel failure probability is obtained. It can be written as:

[0082] .

[0083] Example 2:

[0084] Please refer to the attached document. Figure 2 This embodiment provides an online monitoring and cross-validation method for multi-station chip testing. The method operates automatically based on the system architecture described in the previous embodiment, and its specific control flow includes the following steps:

[0085] Step 1, Test Start. The system initializes, and the test machine and sorting equipment start the mass production test of multi-station chips according to the standard procedure.

[0086] Step 2: Acquire test data and calculate the comprehensive risk coefficient R for each workstation. During the testing process, the main controller acquires the test data transmitted from each test workstation in real time. The evaluation module continuously calculates the risk of each workstation based on a preset statistical algorithm (combining the yield, mean, and variance deviation rates and weighting coefficients of each test item) and outputs the comprehensive risk coefficient R for each workstation.

[0087] Step 3: Determine if the overall risk coefficient R of any workstation exceeds the preset threshold. The system compares the highest overall risk coefficient R with the internally set safety threshold.

[0088] If the result is negative, it means that the current test environment is within a healthy or reasonable fluctuation range. The system will continue the normal test flow and return to step 2 to continue the cyclical monitoring.

[0089] If the judgment result is yes, that is, a risk of false testing is detected at a certain workstation, the system is triggered to enter the automated cross-validation stage and execute step 4.

[0090] Step 4: Automatically extract the tested good products from the lowest-risk workstation and move them to the highest-risk workstation for retesting. The scheduling module sends interrupt and grab commands to the sorting machine. The robotic arm of the sorting machine grabs the good chips in the current batch that have just passed the test at the workstation with the lowest overall risk coefficient and moves them to the highest-risk workstation where the risk coefficient exceeds the threshold to perform retesting.

[0091] Step 5: Determine whether the retest result is satisfactory and evaluate the retest result of the good chip at the high-risk workstation.

[0092] If the retest result is yes, it means that the highest-risk workstation has not suffered any substantial hardware damage and can still pass the test normally. The system reduces the risk factor of that workstation and returns to step 2 to resume normal mass production testing.

[0093] If the retest result is negative, it indicates that the test environment has become abnormal, and proceed to step 6.

[0094] Step 6: Determine if there are false positives at high-risk workstations and calculate the probability of physical channel failure. The system confirmed that the high-risk workstation was experiencing a false positive issue, misclassifying good products as defective. The fault diagnosis module was then activated, extracting test data from the high-risk workstation where the falsely identified chip was detected. Based on the underlying mapping relationship between the test plan and the test program, the system counted the total number of times the chip was associated with the i-th physical test channel. and the number of failure associations Based on this, the probability of each physical channel causing test failure was calculated. .

[0095] 4. The specific calculation logic is as follows:

[0096] Count the total number of times the i-th physical test channel is called. And the number of times each failure item of the chip is associated with the i-th physical test channel. Calculate the failure probability of this physical channel. The fault diagnosis module is based on the failure probability. Rank them from highest to lowest and output repair guidance information.

[0097] The specific calculation method is given below:

[0098] set up Let the physical test channel be numbered. The test item number ( To express whether something is "relevant" and "ineffective," two binary variables (taking values ​​of 0 or 1) are introduced:

[0099] Channel-related indicator variables (Indicates the relationship between test items and channels):

[0100]

[0101] Test result indicator variable (This indicates the chip's performance on a specific test item):

[0102]

[0103] Based on the above definition, the first physical channel and It can be done on all Sum the total number of physical channel calls for each test item. :

[0104]

[0105] Iterate through all test items If the test item matches the channel If relevant, then Increment the counter by 1; if irrelevant, then... The counter increments by 0.

[0106] And the number of associated failures The definition is:

[0107]

[0108] This formula utilizes the properties of multiplication. It only applies when the test item... Both with the channel Related ( ), and the test item also triggered a failure ( )hour, The result is 1, which is included. In any other case (irrelevant, or relevant but the test passed), the product is 0.

[0109] Substituting the two summation formulas above into the basic formula in the original diagram, the final channel failure probability is obtained. It can be written as:

[0110] .

[0111] Step 7: Shut down the system. The fault diagnosis module will calculate the failure probability of all physical test channels. The data is sorted from highest to lowest quality and output on the monitoring terminal to guide equipment engineers in performing precise and rapid targeted repairs.

[0112] Branch 1: When performing step 4 above, the specific process of the system controlling the sorting machine to perform cross-station scheduling is as follows: Figure 3 .like Figure 3 As shown, after the main controller generates the scheduling command, the robotic arm of the sorting equipment will interrupt the regular feeding process. The robotic arm moves to the station 1, which currently has the lowest overall risk, and picks up the chip that has just been judged to be qualified. Subsequently, the robotic arm translates along the trajectory shown by the dotted line, accurately placing the qualified chip into the test socket of the station 4, which has the highest overall risk, to perform a retest. This process realizes online, confirmed reverse verification of the qualified chip against the station.

[0113] Branch 2: When performing step 6 above, the specific fault association probability calculation and physical channel mapping logic are detailed below. Figure 4 .

[0114] like Figure 4As shown, the fault diagnosis unit maps abstract test items (such as leakage current Pass, gain Pass, operating current Fail, and vector error amplitude Pass) to the underlying physical network according to the test plan. The system counts the total number of times each physical channel i (as shown in the figure, a complete test physical channel starts from the chip pin, goes to the pogo pin of the test socket, passes through the channel of the test board, and then to the board channel of the test machine) is called in the entire test process. And the number of times it is called in the failure test item. Substituting into the failure probability formula Perform the calculations.

[0115] In a preferred embodiment of this application, the main controller is capable of controlling at least four workstations simultaneously.

[0116] In this embodiment, a 4-station parallel test of a domestically produced RF FEM chip is used as an example. The test equipment is an ATE platform based on a National Instruments PXI chassis, and the sorting machine is a domestically produced mainstream Pick and Place Handler. The 15th test item of this chip, the transmit power gain (Tx_Gain, RF signal path Tx-ANT) at 3.3V, is used as an analysis case. Since RF chips are sensitive to factors such as equipment nonlinearity, and based on historical test data analysis, the system preset weights are biased towards yield and mean; therefore, the yield weight for this test item is preset. Mean weight Variance weights The overall risk coefficient trigger threshold is set to 0.1.

[0117] 1. Real-time risk monitoring phase

[0118] After the system started parallel testing, the main controller acquired real-time data from each workstation. After a period of testing, the baseline yield of the four workstations for this test item was 97.2%, the baseline mean was 25.7dB, and the baseline variance was 0.151. At this point, site 4 triggered an over-threshold warning. Its yield was 95.5%, the mean was 23.5dB, and the variance was 0.311. Based on the weighted coefficient calculation, its risk coefficient was 0.10024, which indeed exceeded the threshold.

[0119] At this point, the yield rate had not yet reached the 95% alarm threshold. Traditional monitoring methods alone would not have detected the anomaly. However, risk factor monitoring had identified the anomaly because 52.8% of the risk factor was contributed by variance shift. Meanwhile, site 4 exhibited significant gain fluctuations, potentially due to severe pogo pin wear leading to fluctuations in high-power testing. In contrast, site 1, with the lowest risk, had a yield rate of 98.1%, a mean of 25.7 dB, a variance of 0.089, and a risk factor of only 0.03391, approximately one-third that of site 4. This demonstrates that the risk factor indicator is more sensitive to changes during the testing process than traditional methods, effectively distinguishing between stable, high-quality workstations and those with higher risks.

[0120] 2. Automated Cross-Validation Phase

[0121] When the main controller detects that the risk coefficient R of site 4 exceeds the preset threshold of 0.1, and the risk coefficient of site 1 is the lowest, the scheduling module automatically triggers the online cross-validation process. Specifically, the scheduling module controls the PickandPlace sorting machine to perform a grasping operation: the robotic arm continuously extracts ten good chips that have just passed the test at site 1 from the tested EQC good chips. Subsequently, the robotic arm transports the good chips one by one to the testing station at site 4 for retesting. The retest results show that nine of the chips that passed the test at site 1 still pass, but one chip has a transmit power gain (Tx_Gain) value of 9.1dB in the test at site 4, which is far below the lower limit of the specification. Since this chip has been confirmed as good by site 1, the main controller determines that there is a false positive at site 4 and immediately issues a shutdown and maintenance command.

[0122] 3. Accurate Fault Location Stage

[0123] After determining that a good chip was mistakenly rejected at site 4 and triggering a maintenance warning, the main controller's diagnostic module automatically starts. In this embodiment, the specific troubleshooting process for the chip that failed the retest at site 4 (Tx_Gain is 9.1dB) is as follows:

[0124] 1. Data Extraction and Path Traversal: The diagnostic module first extracts the complete original test records of the falsely identified chip at site 4. Based on the loaded test plan and test program mapping table, the system automatically identifies the physical test channels involved in the Tx_Gain test item, including: DC power supply channel VCC, Tx logic level PA_EN, RF input signal channel RFIN, and RF output signal channel ANT.

[0125] 2. Correlation Strength Statistics: The system iterates through all test items (including all items that passed and failed) that the chip underwent in site 4, and counts the call frequency of each physical channel. Subsequently, all failed test items were specifically traversed to count the number of failures associated with each physical channel. The physical channel where the ANT port of this chip is located. Based on program mapping analysis, the ANT port participated in the input / output test items such as Tx_Gain, Pout, Rx_Gain, and Harmonic during the full-process test. The total number of calls was counted. The chip's failure log shows that due to abnormal high-power output at the ANT port in Tx mode, all three associated Tx_Gain terminals at different voltages failed. The number of associated failures was recorded. Next. This applies to the physical channel where VCC resides. Because the VCC channel is frequently used throughout the entire process (except for the open / short circuit test), the total number of calls is [number missing]. However, the record for this failed chip also shows that the number of associated failures is also [number missing]. This refers to passive association only when Tx_Gain fails.

[0126] 3. Failure Probability Calculation and Ranking: The diagnostic module utilizes formulas... Calculate the probability of failure for each channel: The probability of failure for the ANT port is... The VCC failure probability is the highest among all physical channels. .

[0127] 4. Diagnostic Conclusion Output: The main controller ranks the failure probabilities of all physical test channels from highest to lowest. The results show that the port containing the ANT has the highest failure probability, far exceeding other channels. Since the system prompts engineers regarding diagnostic priority, the channel containing the ANT will be checked first. Furthermore, because it is not a complete failure, the Pogo pin corresponding to the ANT will be checked for poor contact first. After replacement, the fault was confirmed to be resolved.

[0128] The above embodiments are for illustrative purposes only and are not intended to limit the invention. Any modifications or variations made by those skilled in the art without departing from the spirit and scope of the invention are within the scope of the invention.

[0129] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope. The scope of protection of the present invention is defined by the appended claims, the specification, and their equivalents.

Claims

1. An online monitoring and cross-validation system for multi-station chip testing, characterized in that, The system includes: The main controller is used to monitor the test data of each test station, and for each test station, calculate the real-time pass rate, average value and variance of each test item. The evaluation module is used to acquire test data for each test item at each test station, calculate the corresponding yield, mean, and variance, compare the yield, mean, and variance of each test station with the benchmark values ​​corresponding to all test stations to obtain the offset rate, and perform weighted calculation based on each offset rate to evaluate the risk coefficient of each test item at that test station. And based on the risk coefficient of each test item, a comprehensive risk coefficient representing the risk coefficient of the test station is obtained; The scheduling module is used to automatically extract chips that have been tested as good from the test station with the lowest risk coefficient and move them to the test station with the highest overall risk coefficient for cross-verification testing when the overall risk coefficient of a certain test station exceeds a preset threshold. If the test result is still qualified, the overall risk coefficient of the test station will be reduced and normal testing will be maintained. If the test result is unqualified, it is determined that there is an error in the high-risk workstation in which the product is incorrectly identified as non-defective and a maintenance warning is triggered. The diagnostic module is used to extract the test data of the chip that was incorrectly identified as a defective product at a high-risk test station when an error occurs. It then maps the data to the physical test channel to determine which test channel is faulty, providing guidance for subsequent targeted repairs.

2. The online monitoring and cross-validation system for multi-station chip testing according to claim 1, characterized in that, The evaluation module is used to: acquire test data for a certain test item from all current test stations; calculate the average value of the test data and set it as the benchmark value for that test item; compare the yield, mean, and variance of each test station under that test item with the corresponding yield benchmark, mean benchmark, and variance benchmark in the benchmark value to obtain the offset rate; perform a weighted calculation based on the offset rate to evaluate the risk coefficient of each test item for each test station. For the j-th test item on test station N, the specific formula is: ； in, This represents the yield offset of the j-th test item at test station N, and , This represents the yield of the j-th test item at test station N. This represents the yield baseline value of the j-th test item across all test stations; This represents the mean offset of the j-th test item at test station N, and , This represents the mean of the j-th test item at test station N. The baseline value represents the mean of the j-th test item across all test stations; This represents the variance offset of the j-th test item at test station N, and , Let represent the variance of the j-th test item at test station N. The baseline value represents the variance of the j-th test item across all test stations; These are the weighting coefficients for yield, mean, and variance, respectively, and they satisfy... .

3. The online monitoring and cross-validation system for multi-station chip testing according to claim 1, characterized in that: For any test station, the risk coefficient of each test item is calculated, and the risk coefficient with the largest value is selected as the comprehensive risk coefficient of the test station. The main controller is used to summarize the comprehensive risk coefficients of each test station and rank them in descending order. The test station that ranks first and exceeds the preset threshold is locked as a high-risk station, and the scheduling module is triggered to move the good chip to the high-risk station for cross-verification.

4. The online monitoring and cross-validation system for multi-station chip testing according to any one of claims 1 to 3, characterized in that, The test items include DC parameter test items or RF parameter test items; wherein, the DC parameter test items include at least one of open / short circuit, leakage current and operating current; the RF parameter test items include at least one of S-parameters and vector error amplitude.

5. The online monitoring and cross-validation system for multi-station chip testing according to claim 1, characterized in that, The main controller can control at least four test stations simultaneously.

6. A method for online monitoring and cross-validation of multi-station chip testing, characterized in that, The method includes the following steps: For a specific test item, calculate the overall yield, global mean, and global variance of all test stations as a reference benchmark. Calculate the yield, mean, and variance of the target test station for this test item, and compare them with the reference benchmark to obtain the yield deviation rate, mean deviation rate, and variance deviation rate. The yield deviation rate, mean deviation rate and variance deviation rate are assigned preset weighting coefficients and normalized to obtain the risk coefficient of the target test station on a test item. Then, the risk coefficients of all test items on the test station are automatically calculated one by one, and the maximum value is used to represent the risk coefficient of the test station. When the risk coefficient of a test station exceeds the preset threshold, the chip that has been tested as good is automatically extracted from the test station with the lowest overall risk coefficient and moved to the test station with the highest overall risk coefficient for cross-validation testing. If the test result is still qualified, the risk factor of the test station will be reduced and normal testing will be maintained. If the test result is unqualified, it is determined that there is an error in the high-risk workstation in which the product was incorrectly identified as non-defective and a maintenance warning is triggered. When a high-risk workstation is found to have a chip that was incorrectly identified as a defective product, the test data of the chip that was incorrectly identified as a defective product is extracted from that test workstation. Based on the test plan and test procedures, iterate through all the test items performed by the chip and count the total number of times it is associated with the i-th physical test channel. Iterate through all failure items of a failed chip and count the total number of times it is associated with the i-th physical test channel. The probability of the physical test channel failing is... ; The failure probability of all physical test channels is ranked from high to low to provide guidance for targeted repairs.

7. The online monitoring and cross-validation system for multi-station chip testing according to claim 6, characterized in that, The comprehensive risk coefficient is the one with the highest risk coefficient among all test items. The main server is used to calculate the comprehensive risk coefficient of each test station and rank each test station according to the comprehensive risk coefficient, and the station with the highest comprehensive risk coefficient is converted into a high-risk station.

8. The online monitoring and cross-validation method for multi-station chip testing according to any one of claims 6 to 7, characterized in that, The test items include DC parameter test items or RF parameter test items; wherein, the DC parameter test items include at least one of open / short circuit, leakage current and operating current; the RF parameter test items include at least one of S-parameters and vector error amplitude.

9. The online monitoring and cross-validation system for multi-station chip testing according to claim 8, characterized in that, The main controller can control four test stations simultaneously.

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