Integrated circuit adjacent pin short test method, apparatus, and system

Abstract

The application discloses a kind of integrated circuit adjacent pin short circuit test method, device and system, belong to integrated circuit technical field, method includes, for any two adjacent functional pins on integrated circuit, adjacent functional pin includes the functional pin of being measured and reference functional pin, reference functional pin is directly connected with reference ground, test current is applied to the functional pin of being measured, and the diode voltage drop between the functional pin of being measured and ground pin in adjacent functional pin is acquired;Based on the diode voltage drop between the functional pin of being measured and ground pin, determine the short circuit condition between adjacent functional pin.The application realizes the effective exposure and accurate identification of short circuit defect to adjacent pin pair.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a method, apparatus and system for short-circuit testing of adjacent pins of integrated circuits. Background Technology

[0002] After the integrated circuit packaging process is completed, electrical performance testing is required to screen for good products. Among them, the open / short (OS) test is a basic and critical test item, used to detect whether there is an open circuit between the chip pins and the internal circuit, and whether there is a short circuit between the pins.

[0003] Conventional OS testing methods typically utilize integrated protection diodes between the chip's internal functional pins and ground pins. For example, the ground pin of the chip under test (DUT) is connected to the test equipment's reference ground, and each functional pin is connected to an independent test resource on the test equipment. During testing, a small negative test current is applied to each functional pin. This current flows through the protection diode to the ground pin, forming a forward conduction loop. By measuring the voltage drop across the functional pin, it can be determined whether there is an open circuit or short circuit between that pin and the reference ground.

[0004] However, in actual production, especially in the cutting and molding process, issues such as fixture positioning deviations or mold wear can cause lead frame or substrate cutting misalignment. This misalignment can lead to abnormal connections or solder wire residue between adjacent pins, resulting in physical short circuits between adjacent functional pins. The aforementioned conventional OS testing method has a significant drawback: when multiple adjacent functional pins are short-circuited, because each functional pin can connect to any other functional pin through the short-circuit path, and there is a protection diode path between any functional pin and the ground pin, applying a test current to any functional pin will still allow the current to flow to the reference ground through the short-circuit network—the protection diode—thus allowing a normal diode voltage drop to be measured. This results in a "pass" test result, even though the actual chip has a serious defect of adjacent pin short circuits, causing it to be missed and reducing the reliability of the test and product yield. Summary of the Invention

[0005] The main objective of this application is to provide a method, apparatus, and system for testing short circuits between adjacent pins of an integrated circuit, aiming to solve the technical problem in the related art of being unable to accurately determine the short circuit status of adjacent pins of an integrated circuit.

[0006] To achieve the above objectives, in a first aspect, this application provides a method for short-circuit testing of adjacent pins of an integrated circuit. The integrated circuit includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode in the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. The methods include: For any two adjacent functional pins on an integrated circuit, including the functional pin under test and the reference functional pin, the reference functional pin is directly connected to the reference ground, a test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin in the adjacent functional pins is obtained. Based on the diode voltage drop between the tested functional pin and the ground pin, the short circuit condition between adjacent functional pins is determined.

[0007] In one embodiment, the test current is a negative current, and the step of determining the short circuit between adjacent functional pins based on the diode voltage drop between the functional pin under test and the ground pin includes: If the diode voltage drop between the tested function pin and the ground pin is less than the short-circuit voltage drop threshold, then a short circuit is determined to be formed between the tested function pin and the reference function pin.

[0008] In one embodiment, for any two adjacent functional pins on an integrated circuit, the adjacent functional pins include a functional pin under test and a reference functional pin. The reference functional pin is directly connected to a reference ground. A test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin in the adjacent functional pins is obtained, including: In the first testing phase, all functional pins on the integrated circuit are defined as either the functional pin under test or the reference functional pin, and any two adjacent functional pins have different definitions. The reference functional pin is directly connected to the reference ground. Apply a test current to all the pins under test and obtain the diode voltage drop between each pin under test and the ground pin. In the second testing phase, the roles of the functional pin under test and the reference functional pin are interchanged, and the newly defined reference functional pin is directly connected to the reference ground. Apply a test current to all the redefined function pins under test and obtain the diode voltage drop between all the function pins under test and the ground pin.

[0009] In one embodiment, determining the short circuit condition between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin includes: The first functional pin under test is determined to have a diode voltage drop between it and the ground pin that does not exceed the short-circuit voltage drop threshold in the first test phase, and the second functional pin under test is determined to have a diode voltage drop between it and the ground pin that does not exceed the short-circuit voltage drop threshold in the second test phase. If the first function pin under test and the second function pin under test are adjacent function pins, then it is determined that there is a short circuit between the first function pin under test and the second function pin under test.

[0010] In one embodiment, the step of determining the short circuit condition between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin includes: Collect the diode voltage drop corresponding to each of all the functional pins under test, and filter out the target functional pins under test whose diode voltage drop is less than the short-circuit voltage drop threshold; wherein, all functional pins on the integrated circuit are defined as functional pins under test or reference functional pins, and any two adjacent functional pins have different definitions, and the reference functional pins are directly connected to the reference ground; Disconnect each reference function pin from the reference ground in turn. When disconnecting a single reference function pin, all other reference function pins remain directly connected to the reference ground. After disconnecting each reference function pin, reapply the test current to the target function pin under test and measure the diode voltage drop between the target function pin under test and the ground pin. If, after disconnecting a certain reference function pin, the diode voltage drop corresponding to the target function pin being tested rises from below the short-circuit voltage drop threshold to the normal diode voltage drop range, then it is determined that there is a pin short-circuit defect between the reference function pin and the target function pin being tested.

[0011] In one embodiment, the method further includes: If, after performing disconnection tests on all reference function pins, the diode voltage drop of the target function pin under test is always less than the short-circuit voltage drop threshold, then it is determined that the target function pin under test is short-circuited with at least two reference function pins at the same time, and a second round of testing is performed. The second round of testing includes: Disconnect all direct connections between the reference function pins and the reference ground, and connect all reference function pins to the reference ground through their corresponding diodes; Each reference function pin is connected directly to the reference ground in turn. When a single reference function pin is closed, all other reference function pins are connected to the reference ground through their corresponding diodes. After each reference function pin is closed, a test current is applied to the target function pin under test, and the diode voltage drop between the target function pin under test and the ground pin is collected. If, after closing a certain reference function pin, the diode voltage drop corresponding to the target function pin being tested drops from the normal diode voltage drop range to less than the short-circuit voltage drop threshold, then it is determined that there is a pin short-circuit defect between the reference function pin and the target function pin being tested.

[0012] In one embodiment, one end of the reference function pin is selectively and directly connected to the reference ground via a controllable switch; for any two adjacent function pins on the integrated circuit, obtaining the diode voltage drop between the measured function pin and the ground pin in the adjacent function pins includes: The controllable switch is closed to connect the reference function pin directly to the reference ground. After waiting for a preset time period, a test current is applied to the function pin under test. Obtain the diode voltage drop between the tested functional pin and the ground pin; the preset time period is determined as follows: T=k×( C total × R eq ) Where T is a preset time period. C total This is the sum of the parasitic capacitances to ground of all reference function pins. R eq The equivalent on-resistance is the resistance of all controllable switches connected in parallel, and k is the safety factor.

[0013] In one embodiment, after determining the short circuit between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin, the method further includes the step of: Based on the short-circuit test results of multiple chips under test, the short-circuit locations of the chips and the number of short circuits at each short-circuit location are summarized and statistically analyzed, and a short-circuit reference heat map is drawn. Retrieve the standard mold coordinate drawing of the tendon cutting forming machine, and compare the short circuit reference heat map with the mold coordinate drawing to determine whether the short circuit defects are concentrated in a certain fixed area of ​​the mold. Based on the location of the short circuit faults, determine the mold positioning offset or mold wear condition; Based on the mold positioning offset or mold wear, generate and output equipment calibration prompts.

[0014] Secondly, to achieve the above objectives, this application further provides an integrated circuit adjacent pin short-circuit testing device. The integrated circuit includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode within the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. The integrated circuit adjacent pin short-circuit testing device includes: The voltage measurement module is used to measure any two adjacent functional pins on an integrated circuit, including the functional pin under test and the reference functional pin. The reference functional pin is directly connected to the reference ground, a test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin is obtained. The short-circuit result determination module is used to determine the short-circuit condition between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin.

[0015] Thirdly, to achieve the above objectives, this application further provides an integrated circuit adjacent pin short-circuit test system, which includes: The chip under test includes a ground pin and multiple functional pins. The ground pin is connected to the reference ground. Each functional pin is connected to the ground pin through a diode in the integrated circuit that has a one-to-one relationship with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. A number of controllable switches, in any two adjacent functional pins, one of the functional pins can be selectively and directly connected to the reference ground through its corresponding controllable switch; The tester includes several pin parameter measurement units. When any functional pin is used as the functional pin under test, one end of the functional pin is also connected to an independent pin parameter measurement unit. The pin parameter measurement unit is used to apply test current to the functional pin. The test machine also includes: a memory, a processor, and a computer program stored in the memory and executable on the processor. The computer program is configured to control the controllable switch and the pin parameter measurement unit to implement the steps of the above-described integrated circuit adjacent pin short-circuit test method.

[0016] One or more technical solutions proposed in this application have at least the following technical effects: This application sets one of adjacent functional pins as the pin under test and the other as the reference pin, and combines the diode voltage drop change and the voltage drop response after the reference pin is disconnected for judgment. This allows short-circuit defects of adjacent pins that are easily masked by short-circuit networks in conventional OS testing to be effectively exposed and accurately identified. Compared with the traditional detection method that only relies on the diode path to ground of the functional pin, this solution can significantly improve the detection rate of short circuits of adjacent pins, reduce the risk of missed screening, and enhance the reliability and specificity of electrical performance testing after packaging. At the same time, it can also improve the stability of test judgment through staged testing and controllable switching timing design, reduce misjudgments caused by parasitic capacitance and transient interference, thereby helping to improve product yield and factory screening quality. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the pin connection for traditional OS testing in related technologies.

[0018] Figure 2 This is a schematic diagram of the short-circuit test system for adjacent pins of the integrated circuit in this application.

[0019] Figure 3 This is a flowchart illustrating the short-circuit test method for adjacent pins of the integrated circuit in this application.

[0020] Figure 4This is a schematic diagram of the structure of the short-circuit test device for adjacent pins of the integrated circuit in this application.

[0021] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0022] It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0023] The embodiments of this application will be described below, including the integrated circuit adjacent pin short-circuit testing method, apparatus, system, and storage medium used in the technical implementation of this application: Reference Figure 1 , Figure 1 This is a schematic diagram of the pin connections for traditional OS testing in related technologies. In related technologies, such as... Figure 1 As shown, testing typically utilizes integrated protection diodes between the chip's internal functional pins PIN2-PINn and the ground pin PIN1. For example, the ground pin PIN1 of the chip under test is connected to the tester's reference ground GND. Each functional pin is connected to the ground pin PIN1 via a reverse-connected diode; that is, the anode of each diode is connected to the ground pin, and the cathode is connected to the functional pin. During testing, each functional pin is connected to the tester's independent pin parameter measurement units OVI1-OVIm. The tester applies a small negative test current, such as -100μA, to each functional pin PIN2-PINn. This current flows through the diode and the ground pin PIN1 to the reference ground GND, forming a conductive loop. By measuring the voltage drop across the functional pin, it can be determined whether there is an open circuit or a short circuit between the pin and the reference ground GND. This method is simple to operate and fast.

[0024] However, in actual production, especially in the chip forming process, issues such as fixture positioning deviation or mold wear can cause lead frame or substrate cutting misalignment. This misalignment can lead to abnormal connections or solder wire residue between adjacent pins, resulting in physical short circuits between adjacent functional pins. The conventional OS testing method has a significant drawback: when multiple adjacent functional pins are short-circuited, each functional pin can connect to any other functional pin through the short-circuit path, and a protection diode path exists between any functional pin and the ground pin PIN1. Therefore, according to the conventional OS testing method, applying a test current to any functional pin, regardless of whether adjacent pins are short-circuited, will still allow the current to flow through the short-circuit network—the protection diode—to the reference ground GND, thus measuring a normal diode voltage drop. This results in a "pass" test result, even though the actual chip has a serious defect of adjacent pin short circuits, causing it to be missed and reducing the reliability of the test and product yield.

[0025] Based on this, this embodiment provides a short-circuit test system for adjacent pins of an integrated circuit, the system may include: The chip under test includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode in the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin.

[0026] A plurality of controllable switches, wherein one of any two adjacent functional pins can be selectively and directly connected to a reference ground through its corresponding controllable switch.

[0027] The tester includes several pin parameter measurement units. When any functional pin is used as the functional pin under test, one end of the functional pin is also connected to an independent pin parameter measurement unit. The pin parameter measurement unit is used to apply test current to the functional pin.

[0028] The test machine also includes: a memory, a processor, and a computer program stored in the memory and capable of running on the processor. The computer program is configured to control the controllable switch and the pin parameter measurement unit to implement the steps of the short-circuit test method for adjacent pins of the integrated circuit.

[0029] For example, such as Figure 2 As shown, compared to traditional OS testing methods, this system uses controllable switches connected to some functional pins. These controllable switches are controlled by the testing machine, which, based on a running computer program, executes a short-circuit test method for adjacent pins of the integrated circuit. This controllable machine controls the controllable switches to achieve open-circuit / ground connections for each functional pin and controls the pin parameter measurement units OVI1~OVIm to apply test current to the corresponding functional pins. In actual testing... Figure 2 In any two adjacent functional pins, one functional pin can be selectively connected directly to the reference ground through its corresponding controllable switch. That is, in two adjacent functional pins, such as pin PIN2 and pin PIN3, one pin is connected to an independent pin parameter measurement unit, which is used to apply test current to the functional pin, while the other pin can be set to float or directly connected to the reference ground by controlling the on and off of the controllable switch according to actual needs.

[0030] It is understandable that the core purpose of setting up a controllable switch in this embodiment is to achieve the controllability of directly grounding the relevant functional pins. The number, selection, and connection method of the controllable switches can be adjusted adaptively according to the actual situation while ensuring that the above purpose is achieved.

[0031] Furthermore, refer to Figure 3To address the technical problem of this application, this application embodiment further provides a corresponding method for short-circuit testing of adjacent pins of an integrated circuit, the method including steps S10 to S20: Step S10: For any two adjacent functional pins on the integrated circuit, the adjacent functional pins include the functional pin under test and the reference functional pin. The reference functional pin is directly connected to the reference ground. A test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin in the adjacent functional pins is obtained.

[0032] Step S20: Based on the diode voltage drop between the tested functional pin and the ground pin, determine the short circuit condition between adjacent functional pins.

[0033] The integrated circuit includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode within the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin.

[0034] It should be noted that among two adjacent function pins, the function pin under test refers to the function pin currently used to apply test current and perform voltage drop detection, while the reference function pin refers to the function pin that can be directly connected to the reference ground.

[0035] Specifically, in this embodiment, adjacent functional pins include a functional pin under test and a reference functional pin. A test current is applied to one end of the functional pin under test, and the other end is connected to a ground pin via a first diode. The cathode of the first diode is connected to the other end of the functional pin under test, and the anode of the first diode is connected to the ground pin. One end of the reference functional pin is directly connected to a reference ground, and the other end is connected to a ground pin via a second diode. The cathode of the second diode is connected to the other end of the reference functional pin, and the anode of the second diode is connected to the ground pin.

[0036] Both the first and second diodes are inherent ESD protection diodes within the input / output ports of the integrated circuit. Their cathodes are connected to the corresponding functional pins, and their anodes are connected to the ground pins. By grounding the reference functional pins, test boundary conditions different from traditional OS tests can be constructed, thereby enhancing the observability of short-circuit defects between adjacent pins.

[0037] Understandably, for two adjacent functional pins, one end of the reference functional pin is directly connected to the reference ground. Then, the pin parameter measurement unit applies a preset test current to the functional pin under test. Thus, if a short circuit exists between the functional pin under test and the reference functional pin, the test current will not pass through the first diode, but will flow directly to the reference ground through the short circuit path between the functional pin under test and the reference functional pin. Conversely, if there is no short circuit, the test current will pass through the first diode. Based on this characteristic, the short circuit status between the functional pin under test and the reference functional pin can be determined.

[0038] In one feasible implementation, the test current is a negative current, and step S20 includes: Step S21: If the voltage drop of the diode between the tested function pin and the ground pin does not exceed the short-circuit voltage drop threshold, then it is determined that a short circuit is formed between the tested function pin and the reference function pin.

[0039] Specifically, in this embodiment, the test current is a negative current, and the short-circuit voltage drop threshold is a judgment threshold used to distinguish between the normal diode conduction state and the short-circuit state. Its value can be preset according to the chip process, the characteristics of the protection diode, and the magnitude of the test current. For example, under normal circumstances, the protection diode usually generates a certain voltage drop when it is conducting, while when the functional pin is directly grounded through a short-circuit path, the corresponding voltage drop will be significantly reduced and close to zero. Therefore, when the diode voltage drop between a tested functional pin and the ground pin does not exceed the short-circuit voltage drop threshold, it can be identified as an abnormal pin. If the tested functional pin is not short-circuited with the reference functional pin, the test current will form a conduction loop through the first diode corresponding to the tested functional pin. At this time, a normal diode voltage drop can be measured between the tested functional pin and the ground pin. By obtaining this voltage drop value, the actual flow path of the test current and the conduction state of the corresponding protection diode can be reflected.

[0040] When a physical short circuit exists between the tested functional pin and the reference functional pin, caused by bridging, solder residue, or other manufacturing defects, the tested functional pin will form an approximately zero-impedance connection with ground through this physical short circuit path, since the reference functional pin is directly grounded. In this case, the test current preferentially flows to ground via the short circuit path, without needing to pass through the first diode. Therefore, the voltage drop measured between the tested functional pin and the ground pin is significantly reduced, approaching zero (the short-circuit voltage drop threshold). In other words, the forward voltage drop that should appear across the protection diode is bypassed by the short circuit path, thus creating a detection characteristic significantly different from the normal state.

[0041] In summary, the presence of a short circuit between adjacent functional pins is determined based on the obtained diode voltage drop results. When a normal diode voltage drop is detected between the functional pin under test and the ground pin, it indicates that the test current is still conducting through the first diode, and there is no short circuit connection between the reference functional pin and the functional pin under test that would affect the test results. However, when the diode voltage drop between the functional pin under test and the ground pin does not exceed the short circuit voltage drop threshold or is lower than the preset threshold, it indicates that the test current has flowed directly to the ground through the short circuit path between the functional pin under test and the reference functional pin, thus determining that a short circuit has formed between them.

[0042] Understandably, compared to traditional OS testing that relies solely on the conduction of the protection diode between the functional pin and the ground pin for detection, this embodiment introduces a reference functional pin grounding mechanism to convert short-circuit defects between adjacent pins into directly observable voltage drop anomalies. Even if a short-circuit network is formed between multiple functional pins, the test current will preferentially flow through the short-circuit path corresponding to the grounded reference functional pin, preventing short-circuit defects from being masked by the conduction of the protection diode. This effectively improves the detection capability of short-circuit defects between adjacent pins and enhances the accuracy and reliability of post-package electrical performance testing.

[0043] Furthermore, this embodiment continues to provide a feasible implementation method A to realize diode voltage drop detection between the tested functional pin and the ground pin in adjacent functional pins. Specifically, the method further includes steps A10 to A60: Step A10: In the first test phase, all functional pins on the integrated circuit are defined as functional pins under test or reference functional pins, and any two adjacent functional pins are defined differently. The reference functional pins are directly connected to the reference ground.

[0044] Step A20: Apply test current to all the function pins under test and obtain the diode voltage drop between all the function pins under test and the ground pin.

[0045] In step A30, during the second test phase, the roles of the function pin under test and the reference function pin are interchanged, and the newly defined reference function pin is directly connected to the reference ground.

[0046] Step A40: Apply test current to all redefined function pins under test and obtain the diode voltage drop between all function pins under test and the ground pin.

[0047] Step A50: Determine the first functional pin under test whose diode voltage drop between it and the ground pin does not exceed the short-circuit voltage drop threshold in the first test phase, and the second functional pin under test whose diode voltage drop between it and the ground pin does not exceed the short-circuit voltage drop threshold in the second test phase.

[0048] Step A60: If the first function pin under test and the second function pin under test are adjacent function pins, then a short circuit is formed between the first function pin under test and the second function pin under test.

[0049] Specifically, the functional pins on an integrated circuit can be alternately defined as functional pins under test and reference functional pins, for example, in... Figure 2 In this method, the first functional pin PIN2 is defined as the functional pin under test, the second functional pin PIN3 is defined as the reference functional pin, the third functional pin PIN4 is defined as the functional pin under test, the fourth functional pin PIN5 is defined as the reference functional pin, and so on. By using this alternating definition method, each functional pin can play the role of either the functional pin under test or the reference in different test stages, thereby expanding the short circuit detection coverage.

[0050] Subsequently, a test current is applied to all pins defined as functional pins under test in the first test phase, and the diode voltage drop between each functional pin under test and the ground pin is obtained. The test current is preferably a negative current to form a forward conduction path through the protection diode corresponding to the functional pin under test. If a short circuit exists between a functional pin under test and its adjacent reference functional pin, the short circuit path will change the return path of the test current because the reference functional pin is grounded, causing a significant anomaly in the voltage drop at the corresponding functional pin under test, thus providing a basis for subsequent short circuit determination.

[0051] In the second testing phase, the roles of the tested and reference functional pins from the first testing phase are swapped, and all functional pins on the integrated circuit are reconfigured. Specifically, pins that were previously tested are reassigned as reference functional pins in the second testing phase, and vice versa. From the test results of the first phase, the first tested functional pin whose diode voltage drop to ground does not exceed the short-circuit voltage drop threshold is selected; similarly, from the test results of the second phase, the second tested functional pin whose diode voltage drop to ground does not exceed the short-circuit voltage drop threshold is selected. Because the first and second testing phases employ a test strategy that swaps the roles of tested and reference functional pins, the first and second tested functional pins effectively reflect the response results of the same adjacent pin pair under two opposite test directions.

[0052] It is understandable that if only unidirectional testing is performed (such as testing only pin PIN3), there may be certain special short circuit structures (such as only pin PIN2 and pin PIN3 are shorted, but pin PIN3 and pin PIN4 are normal), which may cause test blind spots or make it impossible to locate the problem accurately.

[0053] By switching roles between the first and second testing phases, it's equivalent to performing two independent tests on the same group of pins. For example, if an abnormal voltage is detected at pin PIN3 in the first phase, a short circuit involving pin PIN3 can be identified. In the second phase, the voltage at pin PIN2 (now a reference pin) is tested. If its voltage is normal, it can be inferred that the short circuit is likely between pins PIN3 and PIN4, rather than between pins PIN2 and PIN3. This bidirectional testing strategy not only enables batch detection of short circuits, improving testing efficiency, but also enhances the resolution of fault location.

[0054] In summary, this implementation method constructs a test mechanism that features alternating definitions, phased application, and bidirectional verification, enabling each adjacent functional pin pair to undergo voltage drop detection under different role conditions.

[0055] Furthermore, unlike the above implementation method, this embodiment provides another feasible implementation method B to realize diode voltage drop detection between the tested functional pin and the ground pin in adjacent functional pins. Specifically, the method further includes steps B10 to B50: Step B10: Collect the diode voltage drop corresponding to each of all the functional pins under test, and filter out the target functional pins under test whose diode voltage drop is less than the short-circuit voltage drop threshold; wherein, all functional pins on the integrated circuit are defined as functional pins under test or reference functional pins and any two adjacent functional pins have different definitions, and the reference functional pins are directly connected to the reference ground.

[0056] Step B20: Disconnect each individual reference function pin from the reference ground in turn. When disconnecting a single reference function pin, all other reference function pins remain directly connected to the reference ground.

[0057] In step B30, after disconnecting each reference function pin, reapply the test current to the target function pin under test and collect the diode voltage drop between the target function pin under test and the ground pin.

[0058] If, after disconnecting a certain reference function pin, the diode voltage drop corresponding to the target function pin being tested rises from below the short-circuit voltage drop threshold to the normal diode voltage drop range, then it is determined that there is a pin short-circuit defect between the reference function pin and the target function pin being tested.

[0059] Step B50: If, after performing disconnection tests on all reference function pins, the diode voltage drop of the target function pin under test is always less than the short-circuit voltage drop threshold, then it is determined that the target function pin under test is simultaneously short-circuited with at least two reference function pins, and a second round of testing is performed.

[0060] The second round of testing includes steps B51 to B54: Step B51: Disconnect all reference function pins from the reference ground directly, and connect all reference function pins to the reference ground through their corresponding diodes. Step B52: Connect each individual reference function pin directly to the reference ground. When a single reference function pin is closed, all other reference function pins are connected to the reference ground through their corresponding diodes. Step B53: After closing each reference function pin, apply a test current to the target function pin under test and collect the diode voltage drop between the target function pin under test and the ground pin. Step B54: If, after closing a certain reference function pin, the diode voltage drop corresponding to the target function pin being tested drops from the normal diode voltage drop range to less than the short-circuit voltage drop threshold, then it is determined that there is a pin short-circuit defect between the reference function pin and the target function pin being tested.

[0061] Specifically, in the first round of testing (steps B10 to B40), this implementation method can initially determine whether there is a reference function pin that is short-circuited to the function pin under test. First, while keeping all reference function pins directly connected to the reference ground, test current is applied to each function pin under test, and the diode voltage drop between each function pin under test and the ground pin is obtained.

[0062] Under normal circumstances, the test current flows through the corresponding protection diode to the ground pin, thus allowing the measurement of the normal diode voltage drop. However, if there is a physical short circuit between a function pin under test and any reference function pin, the test current will preferentially flow directly to the reference ground through the short circuit path, significantly reducing the diode voltage drop corresponding to that function pin under test. Therefore, function pins with diode voltage drops less than the short-circuit voltage drop threshold can be selected as target function pins under test and used for subsequent location testing.

[0063] Subsequently, a disconnection verification was performed on each of the reference function pins. Specifically, only one reference function pin was disconnected from the reference ground at a time, while the remaining reference function pins remained directly grounded. A test current was then reapplied to the target function pin under test, and the diode voltage drop corresponding to the target function pin was measured. Since only the grounding state of one reference function pin was changed at a time, the change in diode voltage drop uniquely corresponds to the currently disconnected reference function pin. When a reference function pin was disconnected, if the diode voltage drop corresponding to the target function pin recovered from below the short-circuit voltage drop threshold to the normal diode voltage drop range, it indicates that the original test current formed a short-circuit loop through that reference function pin. When the reference function pin lost its direct grounding condition, the short-circuit path failed, and the test current re-circulated through the protection diode corresponding to the target function pin, thus restoring the normal diode voltage drop. Based on this, it can be determined that there is a pin short-circuit defect between the currently disconnected reference function pin and the target function pin under test.

[0064] It should be noted that the first round of testing described above can effectively locate situations where the target function pin under test (DUT) is short-circuited with only a single reference function pin. However, in actual packaging processes, it is also possible for the same DUT pin to simultaneously form a multi-point short-circuit network with two or more reference function pins due to solder bridging or residual solder wire. In this case, even if any one of the reference function pins is disconnected, the remaining reference function pins remain directly grounded, and the test current can still flow to the reference ground through the remaining short-circuit path. Therefore, the diode voltage drop corresponding to the DUT pin will not return to the normal diode voltage drop range, but will always remain below the short-circuit voltage drop threshold.

[0065] Therefore, after completing the traversal disconnection test of all reference function pins, if the diode voltage drop corresponding to the target function pin under test does not recover to the normal diode voltage drop range, it can be determined that the target function pin under test is short-circuited with at least two reference function pins at the same time. At this time, a second round of testing is performed to further determine all reference function pins that have actually been short-circuited.

[0066] Specifically, firstly, disconnect all direct connections between the reference function pins and the reference ground, leaving the external pins of all reference function pins floating and connecting them only to the ground pins through their respective corresponding protection diodes. At this point, since there are no directly grounded reference function pins, even if the target function pin under test forms a short circuit with multiple reference function pins, its test current still needs to form a conduction path through the corresponding protection diodes. Therefore, the normal diode voltage drop can be measured again, thus establishing a unified initial test state.

[0067] Subsequently, a step-by-step closed-loop verification method was used to restore the direct ground connection of the reference function pins. Specifically, only one reference function pin was directly connected to the reference ground at a time, while all other reference function pins remained floating. A test current was then reapplied to the target function pin under test, and the diode voltage drop corresponding to the target function pin was simultaneously measured. Since only one reference function pin was directly grounded at a time, if there was no short circuit between the currently closed reference function pin and the target function pin under test, the test current would still conduct through the protection diode corresponding to the target function pin under test, and the diode voltage drop would remain within the normal diode voltage drop range. Conversely, if there was a short circuit between the currently closed reference function pin and the target function pin under test, the target function pin under test would immediately connect directly to the reference ground through this short circuit path. The test current would bypass the protection diode and flow to the reference ground, causing the diode voltage drop corresponding to the target function pin under test to drop again from the normal diode voltage drop range to below the short-circuit voltage drop threshold. Based on this, it could be determined that there was a pin short circuit defect between the currently closed reference function pin and the target function pin under test.

[0068] Understandably, the first round of testing uses a pin-by-pin disconnection method to determine whether a reference functional pin is the only short-circuit path, while the second round of testing verifies the reference functional pin by restoring it pin-by-pin. These two rounds of testing correspond to two opposite verification processes: eliminating short-circuit paths and establishing short-circuit paths. They corroborate each other, accurately identifying not only single-point short circuits but also fully recognizing multi-point short-circuit networks formed by multiple reference functional pins simultaneously connecting to the same target functional pin under test, thus avoiding missed detections or misjudgments.

[0069] For example, refer to Figure 2 When both reference function pins PIN2 and PIN4 are directly connected to the reference ground, and a test current of -100uA is applied to the function pin under test PIN3, there will be a short circuit between the function pin under test PIN3 and the reference function pin PIN2, as well as between the function pin under test PIN3 and the reference function pin PIN4.

[0070] In the actual testing process, the initial test result should be that the voltage drop of the diode between the tested function pin PIN3 and the ground pin PIN1 should be lower than the short-circuit voltage drop threshold. This only indicates that there is a short circuit between the tested function pin PIN3 and at least one tested function pin, and the first test disconnection procedure is initiated. Disconnect the direct connection between the reference function pin PIN2 and the reference ground GND, while keeping the reference function pin PIN4 connected to the reference ground GND. In reality, the tested function pin PIN3 and the reference function pin PIN4 are short-circuited, and the short-circuit discharge path still exists. The voltage drop of the diode between the tested function pin PIN3 and the ground pin PIN1 is still lower than the short-circuit voltage drop threshold.

[0071] Restore the direct connection between the reference function pin PIN2 and the reference ground GND, and disconnect the direct connection between the reference function pin PIN4 and the reference ground GND. At this time, the tested function pin PIN3 and the reference function pin PIN2 are short-circuited, and the voltage drop of the diode between the tested function pin PIN3 and the ground pin PIN1 is still lower than the short-circuit voltage drop threshold.

[0072] After traversing all reference pins, the voltage drop of the diode between the tested function pin PIN3 and the ground pin PIN1 never returned to the normal range. At this point, it can be determined that the tested function pin PIN3 is short-circuited with more than one reference function pin, which meets the trigger condition and starts the second round of reverse positioning test.

[0073] Pre-operation of the second round of reverse positioning test: Float one end of the reference function pins PIN2 and PIN4, apply -100uA to the function pin under test PIN3, with no external short-circuit discharge path, the current can only flow through the internal diode of the function pin under test PIN3, and the voltage drop is stable within the normal range.

[0074] Connect one end of the reference function pin PIN2 directly to the reference ground, keep one end of the reference function pin PIN4 floating, and after the reference function pin PIN2 is grounded, there is a short circuit between the function pin under test PIN3 and the reference function pin PIN2. The current bypasses the internal diode of the function pin under test PIN3 and flows directly to the reference ground GND through the short circuit. When the voltage drop of the diode corresponding to the function pin under test PIN3 drops to less than the short circuit voltage drop threshold, it is determined that there is a pin short circuit between the reference function pin PIN2 and the function pin under test PIN3.

[0075] One end of the reference function pin PIN2 is returned to floating, and one end of the reference function pin PIN4 is directly connected to the reference ground. At this time, a short circuit is formed between the function pin under test PIN3 and the reference function pin PIN4, and a low-impedance discharge path is formed again. The diode voltage drop corresponding to the function pin under test PIN3 drops to less than the short circuit voltage drop threshold again, and it is determined that there is a pin short circuit between the reference function pin PIN4 and the function pin under test PIN3.

[0076] The second round of testing completely detected two short-circuit pairs: PIN3-PIN2 and PIN3-PIN4, which solves the defect of a single-round disconnect test that can only find faults but cannot locate all short-circuited pins.

[0077] Traditional testing only records the failure of a single chip, making it impossible to distinguish whether a pin short circuit is a random, sporadic defect or a systemic defect in a batch caused by mold misalignment or localized edge wear. Therefore, this embodiment further proposes the following solution: Based on implementation method A or implementation method B, the specific location of the pin pair experiencing the short circuit can be accurately determined. Based on this, after obtaining the short circuit test results, the following steps C10 to C40 can be performed: Step C10: Based on the short-circuit test results of multiple chips under test, summarize and statistically analyze the short-circuit locations of the chips and the number of short circuits at each short-circuit location, and draw a short-circuit reference heat map.

[0078] Step C20: Retrieve the standard mold coordinate drawing of the rebar forming machine, and compare the short circuit reference heat map with the mold coordinate drawing to determine whether the short circuit defects are concentrated in a certain fixed area of ​​the mold.

[0079] Step C30: Determine the mold positioning offset or mold wear condition based on the location of the short circuit faults.

[0080] Step C40: Based on the mold positioning offset or mold wear, generate and output equipment calibration prompt information.

[0081] Specifically, after the packaged chips are assembled, they are sent to a stamping machine. The mold is used to cut the connecting ribs between the pins and separate the individual chips. Most pin short circuit defects are caused by residual metal wires due to incomplete cutting in this process.

[0082] The standard mold coordinate drawing is a reference file pre-stored in the integrated circuit automatic test program. It records the XY coordinates of all cutting edges and chip placement cavities when the mold is free of offset and the cutting edges are intact. Each group of adjacent pins of the chip (e.g., PIN2-PIN3, PIN3-PIN4) corresponds to a fixed cutting edge coordinate on the drawing, which serves as a reference standard for comparing defect distribution.

[0083] Based on this, in this embodiment, for chips with pin short circuits in the test results, the test program records a unique failure signature for each chip under test, that is, accurately records the specific adjacent pin pairs where the short circuit occurred, such as PIN2-PIN3 short circuit, PIN3-PIN4 short circuit, and stores the short circuit pin pair positions in the test log. After completing the batch testing of dozens, hundreds, or even thousands of chips, the test program extracts the short circuit position data from all logs, performs frequency statistics on the short circuit positions of each group of adjacent pins, and counts the total number of times the same pin pair short circuits. Using the two-dimensional coordinates of the cutting and forming mold as a reference, a planar coordinate system is established, and each group of short circuit pin pairs is mapped to the corresponding cutting edge coordinate points on the mold. The corresponding light and dark color values ​​are filled according to the number of short circuits at each coordinate point, and finally a short circuit reference heat map is generated. The color depth of each coordinate region in the heatmap is positively correlated with the frequency of short circuits in the corresponding pin pairs. That is, the darker the color of the coordinate region in the heatmap, the higher the frequency of short circuits and the more concentrated the defects are in the corresponding pin pairs; the lighter the color, the fewer or no short circuits there are in that location.

[0084] Next, the test program retrieves the pre-stored standard mold coordinate drawings of the rebar forming machine inside the equipment, perfectly aligns and overlays the thermal map with the coordinates on the drawings, and matches the color depth of the defective blocks corresponding to each cutting edge one by one. The program automatically judges the distribution characteristics of short-circuit defects, distinguishing whether the defects are scattered and evenly distributed, or a large number of them are clustered on one side of the mold or in a localized fixed area. Only when the defects are determined to be clustered together is it considered that there is a systemic abnormality in the mold, and the subsequent mold fault judgment steps are initiated.

[0085] Based on the morphology of the defective accumulation area, there are generally two types of mold failures: One type is an overall offset fault, which indicates that the entire mold has shifted in a certain direction.

[0086] For example: The left-side pin pairs (PIN2-PIN3) of all chips in the entire mold are frequently short-circuited, while the right-side pin pairs (PIN4-PIN5) are almost flawless. This indicates that the mold as a whole is shifted in the negative X direction, the cutter is completely deviated to the left, and the left-side pins are cut off-center during rib cutting, leaving residual ribs. If the overall mold positioning is determined to be off-center, the machine adjustment prompt is output based on the calculated offset amount and direction, for example, the prompt: "Adjust the rib cutting mold in the positive X-axis direction by 2μm".

[0087] Another type is localized wear failure, which indicates that the cutting edge in a certain area of ​​the mold has problems such as wear, chipping, or pitting.

[0088] For example: Only the pins in the fixed coordinate area at the lower left corner of the mold are short-circuited at high frequency, while the middle and right sides of the mold are normal. This indicates that the cutting edge at the lower left corner of the mold is worn, chipped, or has a pit, and metal wires or connecting ribs will remain there during cutting. If it is determined that the cutting edge of the mold is locally worn, a prompt containing information such as the XY coordinates of the worn cutting edge will be output to prompt the staff to inspect the cutting edge at that location. For example, the prompt will be: "Please check whether the cutting edge at coordinates (X,Y) of the mold is worn or chipped."

[0089] Furthermore, in a feasible implementation, one end of the reference function pin is selectively and directly connected to the reference ground via a controllable switch; for any two adjacent function pins on the integrated circuit, obtaining the diode voltage drop between the measured function pin and the ground pin in the adjacent function pins includes: The controllable switch is closed to connect the reference function pin directly to the reference ground. After waiting for a preset time period, a test current is applied to the function pin under test. Obtain the diode voltage drop between the tested functional pin and the ground pin; the preset time period is determined as follows: T=k×( C total × R eq ), formula (1) Where T is a preset time period. C total This is the sum of the parasitic capacitances to ground of all reference function pins. R eq The equivalent on-resistance is the resistance of all controllable switches connected in parallel, and k is the safety factor.

[0090] Specifically, before applying current, this implementation requires a pre-charge balancing step: after connecting the reference function pin to the reference ground, wait for a preset time period T before applying current to the function pin under test; the preset time period is dynamically calculated using formula (1), and k is usually set to 2 to 5.

[0091] In the test circuit, each reference function pin is connected to the reference ground via a corresponding controllable switch (such as a relay, analog switch, or MOSFET). R on This refers to the on-resistance of each switch itself. Since the controllable switches in all reference function pins are connected to ground in parallel, from an electrical perspective, R eq Calculated using formula (2): R eq = R on / N, formula (2) Where N is the number of reference function pins.

[0092] It is understandable that immediately measuring after direct grounding may result in unstable voltage due to the charging and discharging of parasitic capacitance, leading to erroneous measurements. Conventional methods use a fixed delay, but excessively long delays reduce testing efficiency. This implementation proposes dynamically calculating the minimum settling time based on the actual parasitic capacitance, maximizing testing speed while ensuring accuracy.

[0093] For example, assume: N = 10; parasitic capacitance to ground for each pin. C pin =50pF, on-resistance of each switch R on =50Ω (e.g., low-resistance analog switch), safety factor k = 3.

[0094] but C total =N× C pin =10 × 50 pF = 500 pF = 5 × 10 10 F; R eq = R on / N=50Ω / 10=5Ω; T=3×(5×10 10F)×5 Ω=3×2.5×10 9s = 7.5ns.

[0095] That is, the waiting time is only 7.5 nanoseconds, which is far lower than the minimum time resolution of conventional testing equipment (mostly at the microsecond level), so it can be completely ignored.

[0096] Analyze special cases, if: the number of pins is very small (N is small), i.e. R eq Large, and the parasitic capacitance per pin is also large (if the pin is connected to a large external capacitor for decoupling). C pin = 10 nF The switching resistance is also relatively large (such as that of a common relay). R on =100Ω). For example: N=2, C pin =10nF, R on =100Ω, k=3, then: C total =20 nF , R eq=50Ω, T=3×(20×10) 9 )×50=3×1×10 6 = 3μs. 3 microseconds is still very short and will not cause a testing bottleneck.

[0097] This embodiment further provides a computer-readable storage medium storing an integrated circuit adjacent pin short-circuit test program. When the integrated circuit adjacent pin short-circuit test program is executed by a processor, it implements the steps of the above-described integrated circuit adjacent pin short-circuit test method.

[0098] Specifically, those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0099] Furthermore, refer to Figure 4 Based on the same inventive concept, this application also provides an integrated circuit adjacent pin short-circuit test device. The integrated circuit includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode within the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. The integrated circuit adjacent pin short-circuit test device includes: The voltage measurement module is used to measure any two adjacent functional pins on an integrated circuit, including the functional pin under test and the reference functional pin. The reference functional pin is directly connected to the reference ground, a test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin is obtained. The short-circuit result determination module is used to determine the short-circuit condition between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin.

[0100] It should be noted that the various embodiments of the short-circuit test device for adjacent pins of integrated circuits in this embodiment and the technical effects they achieve can be referred to the various implementation methods of the short-circuit test method for adjacent pins of integrated circuits in the foregoing embodiments, and will not be repeated here.

[0101] It should also be noted that the device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Furthermore, in the accompanying drawings of the device embodiments provided in this application, the connection relationships between modules indicate that they have communication connections, which can be specifically implemented as one or more communication buses or signal lines. Those skilled in the art can understand and implement this without any creative effort.

Claims

1. An integrated circuit adjacent pin short test method, comprising: The integrated circuit includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode in the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. The method includes: For any two adjacent functional pins on an integrated circuit, the adjacent functional pins include a functional pin under test and a reference functional pin. The reference functional pin is directly connected to a reference ground. A test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin in the adjacent functional pins is obtained. Based on the diode voltage drop between the tested functional pin and the ground pin, the short circuit condition between adjacent functional pins is determined.

2. The integrated circuit adjacent pin short test method of claim 1, wherein, The test current is a negative current, and the step of determining the short circuit between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin includes: If the diode voltage drop between the tested functional pin and the ground pin is less than the short-circuit voltage drop threshold, then a short circuit is determined to be formed between the tested functional pin and the reference functional pin.

3. The method for short-circuit testing of adjacent pins of an integrated circuit according to claim 1, characterized in that, The method involves targeting any two adjacent functional pins on an integrated circuit, where the adjacent functional pins include a functional pin under test and a reference functional pin. The reference functional pin is directly connected to a reference ground. A test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin is obtained. In the first testing phase, all functional pins on the integrated circuit are defined as either the functional pin under test or the reference functional pin, and any two adjacent functional pins have different definitions. The reference functional pin is directly connected to the reference ground. Apply a test current to all the pins under test and obtain the diode voltage drop between each pin under test and the ground pin. In the second testing phase, the roles of the functional pin under test and the reference functional pin are interchanged, and the newly defined reference functional pin is directly connected to the reference ground. Apply a test current to all the redefined function pins under test and obtain the diode voltage drop between all the function pins under test and the ground pin.

4. The method for short-circuit testing of adjacent pins of an integrated circuit according to claim 3, characterized in that, The method of determining the short circuit status between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin includes: The first functional pin under test is determined to have a diode voltage drop between it and the ground pin that does not exceed the short-circuit voltage drop threshold in the first test phase, and the second functional pin under test is determined to have a diode voltage drop between it and the ground pin that does not exceed the short-circuit voltage drop threshold in the second test phase. If the first function pin under test and the second function pin under test are adjacent function pins, then it is determined that there is a short circuit between the first function pin under test and the second function pin under test.

5. The method for short-circuit testing of adjacent pins of an integrated circuit according to claim 1, characterized in that, The step of determining the short circuit condition between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin includes: Collect the diode voltage drop corresponding to each of all the functional pins under test, and filter out the target functional pins under test whose diode voltage drop is less than the short-circuit voltage drop threshold; wherein, all functional pins on the integrated circuit are defined as functional pins under test or reference functional pins, and any two adjacent functional pins have different definitions, and the reference functional pins are directly connected to the reference ground; Disconnect each reference function pin from the reference ground in turn. When disconnecting a single reference function pin, all other reference function pins remain directly connected to the reference ground. After disconnecting each reference function pin, a test current is reapplied to the target function pin under test, and the diode voltage drop between the target function pin under test and the ground pin is measured. If, after disconnecting a certain reference function pin, the diode voltage drop corresponding to the target function pin under test rises from below the short-circuit voltage drop threshold to the normal diode voltage drop range, then it is determined that there is a pin short-circuit defect between the reference function pin and the target function pin under test.

6. The method for short-circuit testing of adjacent pins of an integrated circuit according to claim 5, characterized in that, The method further includes: If, after performing a disconnection test on all reference function pins, the diode voltage drop of the target function pin under test is always less than the short-circuit voltage drop threshold, then it is determined that the target function pin under test is simultaneously short-circuited with at least two reference function pins, and a second round of testing is performed. The second round of testing includes: Disconnect all direct connections between the reference function pins and the reference ground, and connect all reference function pins to the reference ground through their corresponding diodes; Each reference function pin is connected directly to the reference ground in turn. When a single reference function pin is closed, all other reference function pins are connected to the reference ground through their corresponding diodes. After each reference function pin is closed, a test current is applied to the target function pin under test, and the diode voltage drop between the target function pin under test and the ground pin is collected. If, after closing a certain reference function pin, the diode voltage drop corresponding to the target function pin being tested drops from the normal diode voltage drop range to less than the short-circuit voltage drop threshold, then it is determined that there is a pin short-circuit defect between the reference function pin and the target function pin being tested.

7. The method for short-circuit testing of adjacent pins of an integrated circuit according to claim 3 or 5, characterized in that, One end of the reference function pin can be selectively connected directly to reference ground via a controllable switch; the step of obtaining the diode voltage drop between the measured function pin and the ground pin for any two adjacent function pins on the integrated circuit includes: The controllable switch is closed so that the reference function pin is directly connected to the reference ground. After waiting for a preset time period, a test current is applied to the function pin under test. Obtain the diode voltage drop between the tested functional pin and the ground pin; wherein the preset time period is determined as follows: T=k×( C total × R eq ) Where T is a preset time period. C total This is the sum of the parasitic capacitances to ground of all reference function pins. R eq The equivalent on-resistance is the resistance of all controllable switches connected in parallel, and k is the safety factor.

8. The method for short-circuit testing of adjacent pins of an integrated circuit according to claim 1, characterized in that, After determining the short circuit between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin, the method further includes the following step: Based on the short-circuit test results of multiple chips under test, the short-circuit locations of the chips and the number of short circuits at each short-circuit location are summarized and statistically analyzed, and a short-circuit reference heat map is drawn. Retrieve the standard mold coordinate drawing of the rebar forming machine, and compare the short circuit reference heat map with the mold coordinate drawing to determine whether the short circuit defects are concentrated in a certain fixed area of ​​the mold. Based on the location of the short circuit faults, determine the mold positioning offset or mold wear condition; Based on the mold positioning offset or mold wear, generate and output equipment calibration prompts.

9. A short-circuit testing device for adjacent pins of an integrated circuit, characterized in that, The integrated circuit includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode within the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. The short-circuit test device for adjacent pins of the integrated circuit includes: A voltage measurement module is used to measure any two adjacent functional pins on an integrated circuit, the adjacent functional pins including the functional pin under test and a reference functional pin, the reference functional pin is directly connected to a reference ground, a test current is applied to the functional pin under test, and the diode voltage drop between the functional pin under test and the ground pin is obtained. The short-circuit result determination module is used to determine the short-circuit condition between adjacent functional pins based on the diode voltage drop between the tested functional pin and the ground pin.

10. A short-circuit test system for adjacent pins of an integrated circuit, characterized in that, The short-circuit test system for adjacent pins of the integrated circuit includes: The chip under test includes a ground pin and multiple functional pins. The ground pin is connected to a reference ground. Each functional pin is connected to the ground pin through a diode in the integrated circuit that has a one-to-one correspondence with it. The anode of the diode is connected to the ground pin, and the cathode of the diode is connected to the functional pin. A plurality of controllable switches, wherein in any two adjacent functional pins, one of the functional pins can be selectively and directly connected to a reference ground through its corresponding controllable switch; The tester includes several pin parameter measurement units. When any one of the functional pins is used as the functional pin under test, one end of the functional pin is also connected to an independent pin parameter measurement unit. The pin parameter measurement unit is used to apply a test current to the functional pin. The test machine further includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to control the controllable switch and the pin parameter measurement unit to implement the steps of the integrated circuit adjacent pin short-circuit test method as described in any one of claims 1 to 8.

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