Method and system for optimizing power consumption of memory chips of integrated computing units
Patent Information
- Application Number
- CN202610905057.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-06-23
- Publication Date
- 2026-09-11
Smart Images
Figure CN122733084A_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of power management technology for memory chips, specifically a method and system for optimizing the power consumption of memory chips with integrated computing units. Background Technology
[0002] With the widespread deployment of compute-intensive applications in terminal devices and data centers, memory chips with integrated computing units have gradually become one of the mainstream architectures. These memory chips are no longer just responsible for data storage; they also integrate a certain amount of computing resources on-chip to handle some data preprocessing, matrix operations, or feature extraction tasks. Because the computing unit and storage medium are located within the same chip, their operating states are coupled, and power consumption exhibits dynamic characteristics strongly correlated with the task load. This places more stringent requirements on on-chip power management.
[0003] In related technologies, power consumption control for memory chips mainly adopts a fixed-level dynamic voltage and frequency adjustment scheme. This involves switching between several pre-defined operating states based on time or utilization thresholds. While this approach is suitable for scenarios with relatively stable loads, it often struggles to handle the complex operating conditions caused by rapid load changes in memory chips with integrated computing units. In particular, when the peak intensity of computing tasks increases significantly in a short period, the fixed-level adjustment cannot promptly match the instantaneous resource demands, easily leading to problems such as untimely frequency reduction or excessive voltage boosting.
[0004] Furthermore, the aforementioned solutions lack a tight linkage mechanism between voltage level and operating frequency. When the voltage level is adjusted, the operating frequency often fails to adapt synchronously, resulting in mismatched ranges such as "high voltage, low frequency" or "low voltage, high frequency" in the chip. This not only wastes the energy-saving margin provided by the voltage level itself but may also cause timing violations and reliability issues at high frequency and low voltage. At the same time, existing solutions generally lack continuous feedback correction capabilities after the adjustment takes effect. Whether an adjustment has truly fallen into the expected power consumption range is often not detected and corrected in a timely manner.
[0005] In addition, existing technologies mostly still use strategies that are relatively independent of energy consumption adjustment at the task scheduling level. The number of activated computing units and the task assignment method do not update with the adjustment of voltage and frequency, making it difficult to translate the optimization of power parameters into effective collaborative energy saving. Overall, it is difficult to achieve a complete closed loop from "scenario identification - decision parameters - collaborative execution - feedback correction".
[0006] Therefore, it is evident that a key technical problem in this field is how to establish a power consumption optimization scheme that can closely integrate scene recognition, voltage and frequency adjustment, and feedback correction in response to the dynamic changes in the workload of computing units during the operation of memory chips, so as to achieve fine-grained and convergent strategy optimization. Summary of the Invention
[0007] This application aims to provide a method and system for optimizing the power consumption of a memory chip with integrated computing units, in order to overcome the shortcomings of the prior art. The technical problem to be solved by this application is achieved through the following technical solution.
[0008] To achieve the above objectives, the technical solution adopted in this application is as follows: According to a first aspect of this application, a method for optimizing the power consumption of a memory chip with an integrated computing unit is provided, the method comprising: S1. Collect the task load data of the computing unit within the monitoring window, extract the load peak and the rate of change from it, and output a high load scenario identifier when both the load peak and the rate of change meet the preset high load triggering conditions. S2. Based on the high-load scenario identifier, read the resource allocation requirements from the preset scenario-resource mapping table, combine the load duration and resource occupancy ratio in the monitoring window, determine the voltage adjustment range, and output the voltage level configuration to be adjusted; S3. Obtain the current frequency parameter of the memory chip. When the current frequency parameter does not match the voltage level configuration to be adjusted, iteratively adjust the current frequency parameter according to a preset frequency optimization step size until it matches the voltage level configuration to be adjusted, thereby obtaining a coordinated configuration. S4. Select a suitable collaboration mode from the preset collaboration mode rule base according to the collaboration configuration, allocate the tasks to be executed by the computing unit according to the collaboration mode, and obtain the final running configuration; S5. Run the memory chip according to the final running configuration, collect power consumption data according to the preset power consumption monitoring cycle, and when the power consumption data exceeds the preset power consumption limit threshold, adjust the voltage and frequency in the collaborative configuration according to the preset parameter fine-tuning granularity until the power consumption data falls back below the power consumption limit threshold to obtain a stable power consumption control configuration.
[0009] Preferably, in step S1, the step of collecting the task load data of the computing unit within a preset monitoring window and extracting the load peak and rate of change from the task load data includes: The task load data is collected according to a preset sampling frequency, and the task load data includes at least the number of tasks, processor utilization, and memory utilization at each sampling time. The task load data is segmented according to the length of the monitoring window to obtain multiple window segments; The maximum number of tasks within each window segment is taken as the load peak, and the difference between the average number of tasks in adjacent window segments is calculated. The difference is then divided by the length of the monitoring window to obtain the rate of change.
[0010] Preferably, in step S1, the output of the high-load scenario identifier includes: Maintain a high-load scenario feature library, which contains feature vectors corresponding to various high-load scenarios. The current feature vector, composed of the load peak, the rate of change, the processor utilization, and the memory utilization, is compared with the feature vectors in the high-load scenario feature library for similarity calculation. The high-load scene corresponding to the feature vector with the highest similarity is selected as the hit scene, and the number of the hit scene is output as the high-load scene identifier.
[0011] Preferably, in step S2, determining the voltage adjustment range and outputting the voltage level configuration to be adjusted includes: The load pressure value is calculated based on the load duration and the resource utilization ratio. The longer the load duration and the higher the resource utilization ratio, the greater the load pressure value. According to the preset pressure value and voltage adjustment range segmentation table, find the voltage adjustment range corresponding to the segment to which the load pressure value belongs; The voltage adjustment range is superimposed on the current voltage of the memory chip, and then rounded down to the nearest integer value of the preset voltage level. The rounded-down value is then used as the output of the voltage level to be adjusted.
[0012] Preferably, in step S3, the iterative adjustment of the current frequency parameter according to a preset frequency optimization step size includes: Obtain the allowed frequency range corresponding to the voltage level configuration to be adjusted and the upper limit constraint of the power consumption of the memory chip; In each iteration, the current frequency parameter is decreased according to the frequency optimization step size to obtain candidate frequencies; When the candidate frequency falls within the allowed frequency range and the estimated power consumption corresponding to the candidate frequency does not exceed the upper limit of the power consumption constraint, the candidate frequency is selected as the frequency that matches the voltage level configuration to be adjusted, and the iteration is terminated.
[0013] Preferably, in step S4, selecting a collaboration mode adapted to the collaboration configuration from a preset collaboration mode rule base and allocating tasks to be executed by the computing unit according to the collaboration mode includes: Under the voltage level and frequency indicated by the collaborative configuration, the collaborative mode rule base is queried to obtain the number of activated computing units and the division of responsibilities for each activated computing unit; Based on the division of responsibilities and the real-time load of each activated computing unit, the task to be executed is assigned to the activated computing unit with the lowest real-time load, so that the load difference between each activated computing unit does not exceed the preset load balancing threshold.
[0014] Preferably, in step S5, the step of correcting the voltage and frequency in the coordinated configuration according to the preset parameter fine-tuning granularity includes: Based on the amount by which the power consumption data exceeds the power consumption limit threshold, the direction and magnitude of this round of fine-tuning are determined, wherein the fine-tuning magnitude does not exceed the parameter fine-tuning granularity; The voltage and frequency in the coordinated configuration are simultaneously reduced according to the fine-tuning direction and the fine-tuning amplitude to obtain the corrected coordinated configuration, and the power consumption data is collected again in the next energy consumption monitoring cycle based on the corrected coordinated configuration.
[0015] Preferably, the method further includes: The system monitors the task load data at the current moment. When the peak load and the rate of change are both below a preset standby trigger threshold for multiple consecutive monitoring windows, the system determines that the storage chip has entered standby mode. Under the standby condition, the voltage level and frequency in the stable energy consumption control configuration are synchronously reduced to the preset standby voltage level and standby frequency level to obtain a low power consumption configuration; When the collected task load data re-meets the high load triggering condition, the system reverts from the low power consumption configuration to the stable energy consumption control configuration and returns to step S1.
[0016] According to a second aspect of this application, a memory chip power optimization system for an integrated computing unit employing the above-described integrated computing unit power optimization method is provided, comprising: The scene recognition module is used to collect the task load data of the computing unit within the monitoring window, extract the load peak and the rate of change from it, and output a high load scene identifier when both the load peak and the rate of change meet the preset high load triggering conditions. The voltage decision module is used to read resource allocation requirements from a preset scenario-resource mapping table based on the high-load scenario identifier, combine the load duration and resource occupancy ratio in the monitoring window to determine the voltage adjustment range, and output the voltage level configuration to be adjusted. A frequency coordination module is used to obtain the current frequency parameters of the memory chip. When the current frequency parameters do not match the voltage level configuration to be adjusted, the current frequency parameters are iteratively adjusted according to a preset frequency optimization step size until they match the voltage level configuration to be adjusted, thus obtaining a coordinated configuration. The task scheduling module is used to select an appropriate collaboration mode from a preset collaboration mode rule base according to the collaboration configuration, allocate the tasks to be executed by the computing unit according to the collaboration mode, and obtain the final running configuration; The feedback correction module is used to run the memory chip according to the final running configuration, collect power consumption data according to a preset power consumption monitoring cycle, and when the power consumption data exceeds the preset power consumption limit threshold, correct the voltage and frequency in the collaborative configuration according to the preset parameter fine-tuning granularity until the power consumption data falls back below the power consumption limit threshold, thereby obtaining a stable power consumption control configuration.
[0017] Preferably, it further includes a monitoring configuration module, used to monitor the task load data at the current moment, determine whether the storage chip enters standby mode; under the standby mode, obtain a low-power configuration, and when the task load data is collected and the high load triggering condition is met again, restore from the low-power configuration to the stable energy consumption control configuration.
[0018] The embodiments of this application have the following advantages: This application uses two indicators, peak load and rate of change, to jointly determine high load scenarios. The high load scenario identifier is used to guide subsequent steps, so that voltage level, frequency parameters, cooperation mode and task allocation are all based on the same scenario identifier. This avoids configuration conflicts caused by isolated adjustments and improves the consistency and stability of strategy optimization. This application uses voltage level configuration as a constraint input for frequency adjustment. It iterates the frequency optimization step size to approximate the current frequency parameters step by step until they match the voltage level. This fundamentally eliminates the mismatch range of "high voltage and low frequency" or "low voltage and high frequency" and allows the energy-saving margin of the power supply parameters to be fully released. After obtaining the collaborative configuration, this application further drives the update of the collaboration mode and task allocation, so that the number of activated computing units, the division of responsibilities and the task scheduling strategy evolve synchronously with the change of voltage-frequency, thereby coordinating the parameter optimization at the power supply level with the resource optimization at the task scheduling level, and achieving a higher overall energy efficiency ratio. After the final operational configuration takes effect, this application continuously collects power consumption data in cycles based on the power consumption monitoring period, and fine-tunes the voltage and frequency when the power consumption limit threshold is exceeded, forming a convergent closed-loop feedback to ensure that the power consumption control effect remains stable during long-term operation, significantly reducing the risk of energy consumption rebound caused by factors such as temperature drift and load fluctuation. Attached Figure Description
[0019] Figure 1 A flowchart illustrating a method for optimizing the power consumption of a memory chip in an integrated computing unit, as provided in an embodiment of this application; Figure 2 This is a structural block diagram of a memory chip power consumption optimization system for an integrated computing unit provided in an embodiment of this application. Detailed Implementation
[0020] To enable those skilled in the art to better understand the technical solution, the present application will be described in detail below with reference to the embodiments. The description in this section is only exemplary and explanatory, and should not be used to limit the scope of protection of the present application in any way.
[0021] See Figure 1 This embodiment provides a power consumption optimization method for a memory chip with integrated computing units. The method is applied to a controller of a memory chip with integrated computing units. The controller can be a sub-module for power management inside the memory chip, or an off-chip management controller that communicates with the memory chip; this application does not impose any particular limitation on this. The memory chip with integrated computing units refers to a chip architecture that simultaneously sets up several memory arrays and several computing units within the same chip package. The computing units can perform lightweight computing tasks such as data preprocessing, matrix multiplication and addition, and feature extraction locally, thereby reducing the overhead of data transfer between the storage side and the main processor.
[0022] The method specifically includes the following steps: Step S1: Collect the task load data of the computing unit within the preset monitoring window, extract the load peak and change rate from the task load data, compare the load peak and change rate with the preset high load triggering conditions, and output a high load scenario identifier when both the load peak and change rate meet the high load triggering conditions.
[0023] The purpose of this step is to identify from the raw operational data whether the current scenario is a high-load situation requiring strategy optimization, in order to provide a triggering basis for subsequent voltage, frequency, and scheduling decisions. See also Figure 2 In a typical implementation, step S1 may further include four sub-steps, S11 to S14.
[0024] In S11, the controller collects the task load data of the computing unit in real time according to a preset sampling frequency. The task load data includes at least the number of tasks, processor utilization, and memory utilization at each sampling moment. As an example, the sampling frequency can be between once per second and ten times per second. When the granularity of power consumption control is high, the sampling frequency can be appropriately increased; when the controller's own power consumption is sensitive, the sampling frequency can be appropriately decreased. The length of the monitoring window can be flexibly set according to the application scenario. For example, in a scenario oriented towards real-time inference, the monitoring window can be set to several seconds to tens of seconds; in a scenario oriented towards batch processing tasks, the monitoring window can be extended to tens of seconds to several minutes.
[0025] In S12, the controller segments the task load data collected in S11 according to the length of the monitoring window, resulting in several window segments arranged in chronological order. Each window segment corresponds to a statistically significant fragment of raw data, facilitating subsequent calculation of load characteristics on a window-by-window basis.
[0026] In S13, the controller takes the maximum number of tasks within each window segment as the peak load for that window segment. Simultaneously, it selects the average number of tasks in the current window segment and the previous window segment, calculates the difference between the two, and divides this difference by the length of the monitoring window to obtain the rate of change. This simultaneously reflects both the absolute intensity and relative trend of the load, avoiding false triggers caused by relying solely on peak loads.
[0027] In S14, the controller compares the load peak value and rate of change obtained in S13 with preset high-load trigger conditions. The high-load trigger conditions include at least a load peak value threshold and a rate of change threshold. Only when the load peak value is not lower than its corresponding threshold and the rate of change is not lower than its corresponding threshold is the high-load trigger condition determined to be met. When the high-load trigger condition is met, the controller further calls the high-load scenario feature library, selects the high-load scenario with the highest similarity to the current feature vector as the hit scenario, and outputs its number as the high-load scenario identifier. The high-load scenario feature library can be established offline in advance by collecting historical operating data of the chip under different typical operating conditions and extracting feature vectors under each operating condition as priors.
[0028] The preset high-load trigger conditions are based on the maximum bandwidth and average access latency of the memory chip under specific programming conditions. When the throughput within a continuous monitoring window exceeds 80% of the typical value, or when the average latency experiences a non-linear transition of 2-3 times, the preset high-load trigger conditions are determined to be met.
[0029] In this step, the similarity between the current feature vector and the feature vectors in the high-load scene feature library is calculated, and the high-load scene with the highest similarity to the current feature vector is selected as the hit scene. The specific method for calculating similarity typically uses the logic of Euclidean distance or cosine similarity. For example, in spatial distance determination, the current feature vector is treated as a point in a multi-dimensional space, and the physical distance between this point and each "prior point" in the feature library is calculated. The closer the distance, the closer the current working condition is to the historical scenario. Alternatively, a directional dimension can be used for judgment, which involves calculating the cosine of the angle between vectors to assess whether the trends of fluctuations in each indicator are consistent. Even if the numerical values differ, as long as the proportional relationship of each indicator matches a certain pattern in the database, it can be judged as similar.
[0030] As a specific numerical example, assuming a sampling frequency of twice per second and a monitoring window length of thirty seconds, each window segment contains sixty sampling points. Let the maximum number of tasks in the current window be 4.2 tasks per second, the average number of tasks in the previous window be 2.5 tasks per second, and the average number of tasks in the current window be 3.3 tasks per second. Then, the load peak can be calculated as 4.2 tasks per second, and the rate of change is (3.3 minus 2.5) divided by thirty, which is approximately 0.027 tasks per second squared. If the preset load peak threshold is four tasks per second and the rate of change threshold is 0.02 tasks per second squared, then both indicators meet the triggering conditions, determining that a high-load scenario has been entered. Combining indicators such as processor utilization and memory utilization, the high-load scenario numbered "HL-03" is selected from the high-load scenario feature library and output as the high-load scenario identifier to step S2.
[0031] It should be noted that the above values are merely examples for ease of understanding. In actual engineering applications, the thresholds, window lengths, and number of feature library entries can be calibrated according to specific chips and specific business scenarios, and should not be regarded as limitations on the scope of protection of this application.
[0032] Step S2: Based on the high-load scenario identifier, read the corresponding resource allocation requirements from the preset scenario-resource mapping table, combine the load duration and resource occupancy ratio in the monitoring window, determine the voltage adjustment range, and output the voltage level configuration to be adjusted.
[0033] This step follows the output of step S1. The high-load scenario identifier, once generated, is sent to this step and used as the key-value pair in the scenario-resource mapping table. The scenario-resource mapping table can be established offline, recording the computing resource allocation requirements corresponding to each high-load scenario, such as the number of computing units to be activated, the required reserved storage bandwidth, and the baseline task priority.
[0034] In one alternative implementation, step S2 specifically includes: First, the controller queries a preset scenario-resource mapping table using the high-load scenario identifier as the key, and reads the registered resource allocation requirements. These resource allocation requirements will be used as input for subsequent collaboration mode queries and also as a reference for calculating voltage adjustment ranges, since the level of resource demand directly affects the required voltage margin.
[0035] The pre-defined scenario-resource mapping table is the core logical index table in the storage controller used to implement on-demand allocation. It establishes a quantitative correspondence between specific business scenarios and underlying physical resources. By benchmarking typical high-load scenarios, the minimum resource thresholds required to maintain system stability in each scenario are recorded, and resource allocation is refined into specific parameters, such as CPU core count requirements, DMA bandwidth weight, or specific voltage levels, thereby completing the preparation of the scenario-resource mapping table.
[0036] Secondly, the controller extracts the load duration and resource utilization ratio within the monitoring window. The load duration refers to the cumulative length of time within the current monitoring window where the number of tasks exceeds a preset activity threshold; the resource utilization ratio considers both the average processor utilization and the average memory utilization. The controller uses the load duration and resource utilization ratio as inputs to calculate the load pressure value. The load pressure value increases with increasing load duration and increases with increasing resource utilization ratio. The contributions of both to the pressure value can be synthesized using a weighted summation method, and the specific weights can be calibrated offline according to the application scenario.
[0037] The steps for calculating the load stress value are as follows: The controller counts the duration of the load within a monitoring window, i.e., the cumulative length of time the number of tasks exceeds a preset activity threshold; simultaneously, it calculates the resource utilization ratio, which is derived from the average processor utilization and the average memory utilization. Two weighting coefficients are calibrated offline according to the application scenario, representing the contribution of load duration and resource utilization ratio to the stress value, respectively. The collected load duration is multiplied by its corresponding weight, and the resource utilization ratio is multiplied by its corresponding weight. Finally, the two products are added together to obtain a comprehensive value. This value is the load stress value, which monotonically increases with increasing load duration or resource utilization ratio, reasonably reflecting the overall stress level within the current monitoring window.
[0038] Next, the controller searches for the voltage adjustment range corresponding to the segment to which the load pressure value belongs, according to a preset pressure value and voltage adjustment range segmentation table. The segmentation table can pre-divide the pressure value range into several levels, each level corresponding to a specific direction and magnitude of voltage adjustment range. For example, the pressure value can be divided into four levels: "low," "medium," "high," and "very high," corresponding to adjustment strategies of no voltage adjustment, voltage increase by one level, voltage increase by two levels, and voltage increase by three levels, respectively. This pressure value and voltage adjustment range segmentation table divides the continuous range of load pressure values into several discrete segments, each segment uniquely corresponding to a voltage adjustment range. Its calibration method involves collecting power consumption, performance, and stability data of the chip under different workload combinations. Using the load pressure value as the horizontal axis and the optimal voltage offset that enables stable system operation and minimizes power consumption as the vertical axis, non-linear inflection points are found through curve fitting. Based on the reference voltage, a hill-climbing search is performed on each pressure value interval to find the lowest feasible voltage that satisfies the task's real-time constraints without causing timing violations. The difference between this voltage and the current voltage is the adjustment range for that segment. The boundary of the pressure value interval is set at the critical point where adjacent adjustment ranges change.
[0039] Finally, the controller adds the voltage adjustment magnitude to the current voltage of the memory chip and rounds it down to the nearest preset voltage level. The voltage level refers to a set of discrete voltage values that the memory chip hardware can physically support. The controller compares the adjusted voltage value with each of these discrete levels, selects the closest one as the voltage level to be adjusted, and outputs it. Thus, step S2 delivers a specific configuration carrying the voltage-level optimization result to step S3, for step S3 to use as a matching benchmark.
[0040] The preset voltage level settings are mainly based on: first, the electrical specifications of the memory chip, which stipulate the upper and lower voltage limits and recommended step sizes for safe operation, ensuring that the physical tolerance range is not exceeded; second, the actual configurable granularity of the chip's internal power management unit or external voltage regulator, as only discrete fixed voltage points can be directly executed by the hardware; and third, balancing performance and power consumption, typically setting the voltage level near common frequency inflection points to cover typical load scenarios. For example, suppose a calculated load pressure value is 51 points, falling into the "high" segment, corresponding to a voltage adjustment of one level. The current memory chip voltage is 1.2 volts, and the target voltage value after adding one level is 1.32 volts. This is then rounded down to the nearest integer among the supported hardware voltage levels (1.1 volt, 1.2 volt, 1.3 volt, 1.4 volt), selecting 1.3 volts as the output voltage level to be adjusted.
[0041] Step S3: Obtain the current frequency parameter of the memory chip, determine the matching status between the current frequency parameter and the voltage level configuration to be adjusted, and if it is determined to be mismatched, iteratively adjust the current frequency parameter according to the preset frequency optimization step size until it matches the voltage level configuration to be adjusted, and obtain a coordinated configuration.
[0042] This step follows the voltage level configuration to be adjusted output in step S2, using it as a constraint for its own operation. The purpose is to eliminate any potential mismatch between voltage and frequency. In one optional implementation, step S3 specifically includes: First, the controller reads the current frequency parameter from the status register of the memory chip and queries a preset voltage-frequency matching rule to obtain the frequency allowable range corresponding to the voltage level configuration to be adjusted. The voltage-frequency matching rule can be pre-characterized by the chip's device characteristics and reflects the upper and lower bounds of the frequency at which the chip can operate safely and stably under different voltages. Simultaneously, the controller also reads the upper limit constraint of the memory chip's power consumption from external sensors or monitoring interfaces. The frequency allowable range corresponding to the voltage level configuration to be adjusted is indexed by voltage level (discrete increments), providing the frequency allowable range that ensures stable operation of the memory chip and computing unit at that voltage, along with the corresponding estimated upper limit reference value of power consumption, which is obtained through voltage-frequency characteristic testing of the chip.
[0043] Secondly, the controller determines whether the current frequency parameter falls within the allowed frequency range. If the current frequency parameter exceeds the upper limit of the allowed frequency range, it indicates that there is a timing violation or stability risk when operating at the current frequency under the target voltage level, and the frequency needs to be reduced; if the current frequency parameter is below the lower limit of the allowed frequency range, it indicates that the current voltage has a margin of safety, and it can be adjusted down in the next feedback correction phase.
[0044] Furthermore, when frequency reduction is required, the controller iteratively adjusts the current frequency parameter according to a preset frequency optimization step size. In each iteration, the current frequency parameter is subtracted from the frequency optimization step size to obtain a candidate frequency, and it is further determined whether the estimated power consumption corresponding to the candidate frequency does not exceed the power consumption upper limit constraint. Only when the candidate frequency falls within the allowed frequency range and meets the power consumption upper limit constraint is it adopted as the frequency matching the voltage level configuration to be adjusted, and the iteration ends. Otherwise, the candidate frequency is used as the new current frequency parameter, and the next iteration continues until the conditions are met or the iteration count limit is reached.
[0045] Finally, the controller encapsulates the successfully matched frequency value and the voltage level configuration output in step S2 together into a cooperative configuration and outputs it to step S4. This cooperative configuration serves as both the input for selecting the cooperative mode in step S4 and the initial basis for parameter fine-tuning in step S5, playing a crucial role in bridging the preceding and following steps.
[0046] As an example, suppose the frequency range corresponding to the voltage level configuration to be adjusted output in step S2 is 700 MHz to 850 MHz, and the power consumption limit is 5 watts; the current frequency parameter is 860 MHz, which exceeds the frequency range. Assuming the frequency optimization step size is 10 MHz, the candidate frequency after the first iteration is 850 MHz, and the estimated power consumption calculated by the model is 5.2 watts, still exceeding the power consumption limit; entering the second iteration, the candidate frequency drops to 840 MHz, corresponding to an estimated power consumption of 4.9 watts, satisfying both constraints, and the iteration exits. The final frequency parameter is locked at 840 MHz, forming a coordinated configuration with the 1.3 volt voltage level.
[0047] Step S4: Based on the collaborative configuration, select a collaborative mode that matches the collaborative configuration from the preset collaborative mode rule base, and allocate the tasks to be executed by the computing unit according to the collaborative mode to obtain the final running configuration.
[0048] The input to this step is the collaborative configuration output from step S3. Its purpose is to extend the strategy optimization at the voltage-frequency level to the collaborative mode and task allocation of computing units, so that the internal operating resources of the chip can be adjusted again around the collaborative configuration.
[0049] Each record in the preset collaboration mode rule base is uniquely determined by the collaboration configuration, providing the optimal collaboration mode for the computing units under that configuration, including the number of activated computing units, the division of responsibilities among the units, and the task scheduling strategy preference. The calibration method includes the following steps: In a laboratory environment, a typical benchmark task set is run for each set of discrete voltage-frequency cooperative configurations. Different combinations of active cell counts and responsibility partitioning are traversed, and performance per watt is measured. The combination with the highest energy efficiency is selected as the standard cooperative mode for that configuration and recorded in the rule base. If multiple configurations correspond to the same cooperative mode, they are merged to reduce storage overhead. For intermediate configurations that are not explicitly calibrated, approximations can be made through interpolation or by using neighboring high-efficiency configurations.
[0050] In this step, the collaborative configuration output in step S3 is used as a query key to match within a preset collaborative mode rule base, returning a list of corresponding active units and a division of responsibilities. The task scheduling module then initializes the computing units and assigns tasks accordingly.
[0051] In one alternative implementation, step S4 specifically includes: First, the controller queries a preset cooperation mode rule base under the voltage level and frequency indicated by the cooperation configuration. The cooperation mode rule base pre-records suggested cooperation modes corresponding to different cooperation configurations. Each cooperation mode describes at least two aspects: the number of activated computing units and the division of responsibilities among the activated computing units. For example, under a higher voltage-higher frequency cooperation configuration, the cooperation mode might instruct the activation of all computing units and their cooperation in a pipelined manner; while under a lower voltage-lower frequency cooperation configuration, the cooperation mode might only instruct the activation of half of the computing units, with the remaining units entering gating.
[0052] Secondly, the controller, based on the task queue retained from the previous round of task execution and the division of responsibilities indicated by the collaboration mode, allocates the tasks to be executed one by one to each activated computing unit. In terms of allocation strategy, the controller prioritizes the activated computing unit with the lowest real-time load as the target, and uses a load balancing threshold as a constraint during allocation, ensuring that the load difference between any two activated computing units does not exceed this threshold. This load difference refers to the maximum difference in real-time load among multiple activated computing units.
[0053] Finally, the controller summarizes the voltage, frequency, list of activated computing units, division of responsibilities, and task allocation results into the final runtime configuration and sends it to the hardware execution layer of the memory chip. At this point, the main strategy optimization process of the entire power optimization scheme is completed, resulting in the final runtime configuration adapted to the current high-load scenario.
[0054] Step S5: Run the memory chip according to the final running configuration, collect power consumption data according to the preset power consumption monitoring cycle, compare the power consumption data with the preset power consumption limit threshold, and when the power consumption data exceeds the power consumption limit threshold, correct the voltage and frequency in the collaborative configuration according to the preset parameter fine-tuning granularity until the power consumption data falls back below the power consumption limit threshold to obtain a stable power consumption control configuration.
[0055] This step addresses the continuous feedback loop during operation, with the final operational configuration output from step S4 as its input. Considering that factors such as on-chip temperature, power supply noise, and task bursts may cause power consumption drift during operation, step S5 forms a correction loop for the configuration obtained in step S4 through periodic sampling and online fine-tuning.
[0056] The power consumption limit threshold is mainly determined by the power limit corresponding to the highest safe junction temperature (Tjunction) of the memory chip under specific operating conditions, as well as the peak power supply capability of the power management module (PMIC).
[0057] In one alternative implementation, step S5 specifically includes: First, the controller continuously acquires power consumption data through a power consumption sampling path deployed on the chip's power supply link, using a preset power consumption monitoring cycle as the tick. The power consumption monitoring cycle can be set to between several seconds and several minutes. The shorter the power consumption monitoring cycle, the higher the real-time feedback, but it also correspondingly increases the energy consumption overhead of the sampling itself.
[0058] Secondly, the controller compares the collected power consumption data with a preset power consumption limit threshold. If the power consumption data remains stable below the power consumption limit threshold, it is considered that the current final operating configuration has converged to a stable state, and no correction action is triggered.
[0059] Furthermore, if the power consumption data exceeds the power consumption limit threshold within a certain energy consumption monitoring cycle, the controller determines the fine-tuning direction and magnitude for this round based on the excess amount. The fine-tuning magnitude does not exceed the parameter fine-tuning granularity to avoid excessive adjustment at once, which could cause system oscillation. When the excess amount is small, the controller only adjusts the voltage and frequency at a single-level parameter fine-tuning granularity; when the excess amount is large, continuous adjustment is allowed in several iterations until the power consumption data falls back below the power consumption limit threshold. The parameter fine-tuning granularity refers to the minimum step size that the controller is allowed to adjust the voltage or frequency in each round. Its tuning basis mainly includes: according to the minimum configurable resolution of the power management unit or phase-locked loop, which is the minimum step size supported by the physical layer; or according to the system stability margin, typically taking 50% to 80% of the maximum safe step size that does not cause performance jitter in chip characteristic testing.
[0060] Finally, the fine-tuned configuration is used as the corrected collaborative configuration and continues to be used as the basis for sampling in the next energy consumption monitoring cycle. If the power consumption data collected in several consecutive energy consumption monitoring cycles remains below the power consumption limit threshold, the current configuration is used as the stable energy consumption control configuration, completing this round of strategy optimization.
[0061] As an example, assume the preset power consumption limit threshold is 4.0W, and the parameter fine-tuning granularity corresponds to a voltage of 0.05V and a frequency of 50MHz. In a certain monitoring cycle, the power consumption data collected is 4.2W, exceeding the limit by 0.2W. Based on this, the controller lowers the voltage in the collaborative configuration from 1.3V to 1.25V and the frequency from 840MHz to 790MHz, resulting in the corrected collaborative configuration. In the next monitoring cycle, the power consumption data collected is 3.8W, falling back below the power consumption limit threshold. After remaining stable for three consecutive monitoring cycles, this configuration is recorded as the stable energy consumption control configuration.
[0062] This embodiment further describes the extended behavior of the method in standby scenarios.
[0063] The controller continuously monitors the current task load data. When the peak load and the rate of change are both below a preset standby trigger threshold for multiple consecutive monitoring windows, the controller determines that the storage chip has entered standby mode. The standby trigger threshold includes both an upper limit for the peak load and an upper limit for the rate of change. Only when both are met is the controller determined to enter standby mode, thus avoiding false triggering of standby due to a brief load dip.
[0064] The standby trigger threshold is determined based on the following: the upper limit of peak load is usually set to 5%-10% of the system's lowest operating energy efficiency point to ensure that the current task is extremely light; the upper limit of the rate of change is determined based on the second derivative to ensure that the load is at a stable low level rather than a sudden drop. The core is to ensure that the power saving in standby is far greater than the latency loss caused by frequent wake-ups.
[0065] Once in standby mode, the controller synchronously reduces the voltage and frequency levels in the stable power consumption control configuration described in Example 1 to preset standby voltage and frequency levels, resulting in a low-power configuration. The standby voltage and frequency levels are typically specified in the chip datasheet, and they meet the device-level stable matching requirements. Since the standby voltage and frequency levels are significantly lower than the normal operating levels, both static and dynamic power consumption are significantly suppressed. The preset standby voltage and frequency levels are determined based on: data retention voltage (for memory chips such as DRAM, SRAM, and Flash, ensuring no data loss during standby, the voltage must not fall below the data retention voltage (typically 50%–70% of normal operating voltage), a value specified by the chip's process and design specifications); and a minimum operating frequency (the standby frequency must ensure the internal state machine (such as refresh circuitry and wake-up logic) functions correctly, typically the lowest frequency that the PLL can stably output or the minimum division value of the clock controller).
[0066] When the task load data again meets the high load triggering condition of step S1, the controller reverts from the low power configuration to the stable energy consumption control configuration and returns to step S1 to restart a complete round of strategy optimization. This extension expands the applicability of the method from simple high load optimization to full operating condition coverage, forming a closed loop of "standby—identification—decision—coordination—feedback", providing a complete power management framework for memory chips with integrated computing units.
[0067] This embodiment corresponds to the memory chip power consumption optimization system of the integrated computing unit, see [link / reference]. Figure 2 The system includes a scene recognition module, a voltage decision module, a frequency coordination module, a task scheduling module, and a feedback correction module.
[0068] The scene recognition module is used to execute step S1 in Embodiment 1, and further includes a data acquisition subunit, a feature extraction subunit, and a scene determination subunit. The data acquisition subunit is responsible for acquiring task load data according to a preset sampling frequency, the feature extraction subunit is responsible for generating load peaks and change rates from the task load data, and the scene determination subunit is responsible for outputting high-load scene identifiers based on a high-load scene feature library.
[0069] The voltage decision module is used to execute step S2 in Embodiment 1, receive the high load scene identifier output by the scene recognition module, and generate and output the voltage level configuration to be adjusted based on the preset scene-resource mapping table and the pressure value and voltage adjustment range segmentation table.
[0070] The frequency coordination module is used to execute step S3 in Embodiment 1, using the voltage level configuration to be adjusted output by the voltage decision module as a constraint, to iteratively adjust the current frequency parameters and output a coordinated configuration.
[0071] The task scheduling module is used to execute step S4 in Embodiment 1, taking the collaborative configuration output by the frequency collaboration module as input, querying the collaboration mode rule base and performing task allocation, and outputting the final running configuration.
[0072] The feedback correction module is used to execute step S5 in Embodiment 1, continuously collect power consumption data during operation, and fine-tune the voltage and frequency in the collaborative configuration when necessary, and finally output a stable power consumption control configuration.
[0073] The signal flow between the above modules is consistent with the execution order of steps S1 to S5. That is, each module forms a unidirectional main chain in the order of "scene recognition - voltage decision - frequency coordination - task scheduling - feedback correction". At the same time, there is a backtracking branch between the feedback correction module and the scene recognition module, which is used to trigger a new round of strategy optimization process when the load changes significantly, thus forming a closed loop.
[0074] It should be noted that, in this document, the terms "comprising," "including," and any other variations are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Specific examples have been used in this document to illustrate the principles and implementation methods of the technical solutions of this application. The above examples are only for the purpose of helping to understand the methods and core ideas of this application. The above descriptions are merely preferred embodiments of this application. It should be pointed out that, due to the limitations of written expression and the objective existence of infinite specific structures, those skilled in the art can make several improvements, modifications, or changes without departing from the principles of this application, and can also combine the above technical features in an appropriate manner; these improvements, modifications, changes, or combinations, or the direct application of the concept and technical solutions of this application to other situations without modification, should all be considered within the scope of protection of this application.
Claims
1. A method for power consumption optimization of a memory chip integrated with a computing unit, the method comprising: The method includes: S1. Collect the task load data of the computing unit within the monitoring window, extract the load peak and the rate of change from it, and output a high load scenario identifier when both the load peak and the rate of change meet the preset high load triggering conditions. S2. Based on the high-load scenario identifier, read the resource allocation requirements from the preset scenario-resource mapping table, combine the load duration and resource occupancy ratio in the monitoring window, determine the voltage adjustment range, and output the voltage level configuration to be adjusted; S3. Obtain the current frequency parameter of the memory chip. When the current frequency parameter does not match the voltage level configuration to be adjusted, iteratively adjust the current frequency parameter according to a preset frequency optimization step size until it matches the voltage level configuration to be adjusted, thereby obtaining a coordinated configuration. S4. Select an appropriate collaboration mode from the preset collaboration mode rule base according to the collaboration configuration, and allocate the tasks to be executed by the computing unit according to the appropriate collaboration mode to obtain the final running configuration; S5. Run the memory chip according to the final running configuration, collect power consumption data according to the preset power consumption monitoring cycle, and when the power consumption data exceeds the preset power consumption limit threshold, adjust the voltage and frequency in the collaborative configuration according to the preset parameter fine-tuning granularity until the power consumption data falls back to below the preset power consumption limit threshold, and obtain a stable power consumption control configuration.
2. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 1, characterized in that... In step S1, the step of collecting the task load data of the computing unit within the monitoring window and extracting the load peak and rate of change from the task load data includes: The task load data is collected according to a preset sampling frequency, and the task load data includes at least the number of tasks, processor utilization, and memory utilization at each sampling time. The task load data is segmented according to the length of the monitoring window to obtain multiple window segments; The maximum number of tasks within each window segment is taken as the load peak, and the difference between the average number of tasks in adjacent window segments is calculated. The difference is then divided by the length of the monitoring window to obtain the rate of change.
3. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 2, characterized in that... In step S1, when both the load peak and the rate of change meet the preset high load triggering condition, a high load scenario identifier is output, including: Maintain a high-load scenario feature library, which contains feature vectors corresponding to various high-load scenarios. The current feature vector, composed of the load peak, the rate of change, the processor utilization, and the memory utilization, is compared with the feature vectors in the high-load scenario feature library for similarity calculation. The high-load scene corresponding to the feature vector with the highest similarity is selected as the hit scene, and the number of the hit scene is output as the high-load scene identifier.
4. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 1, characterized in that... In step S2, determining the voltage adjustment range and outputting the voltage level configuration to be adjusted includes: The load pressure value is calculated based on the load duration and the resource utilization ratio. The longer the load duration or the higher the resource utilization ratio, the greater the load pressure value. According to the preset pressure value and voltage adjustment range segmentation table, find the voltage adjustment range corresponding to the segment to which the load pressure value belongs; The voltage adjustment range is superimposed on the current voltage of the memory chip, and then rounded down to the nearest integer value of the preset voltage level. The rounded-down value is then used as the output of the voltage level to be adjusted.
5. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 1, characterized in that... In step S3, the iterative adjustment of the current frequency parameter according to a preset frequency optimization step size until it matches the voltage level configuration to be adjusted, thus obtaining a coordinated configuration, includes: Obtain the allowed frequency range corresponding to the voltage level configuration to be adjusted and the upper limit constraint of the power consumption of the memory chip; In each iteration, the current frequency parameter is decreased according to the frequency optimization step size to obtain candidate frequencies; When the candidate frequency falls within the allowed frequency range and the estimated power consumption corresponding to the candidate frequency does not exceed the upper limit of the power consumption constraint, the candidate frequency is selected as the frequency that matches the voltage level configuration to be adjusted, and the iteration is terminated.
6. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 1, characterized in that... In step S4, selecting a collaboration mode adapted to the collaboration configuration from a preset collaboration mode rule base and allocating the tasks to be executed by the computing unit according to the adapted collaboration mode includes: Under the voltage level and frequency indicated by the collaborative configuration, the preset collaborative mode rule base is queried to obtain the number of activated computing units and the division of responsibilities for each activated computing unit; Based on the division of responsibilities and the real-time load of each activated computing unit, the task to be executed is assigned to the activated computing unit with the lowest real-time load, so that the load difference between each activated computing unit does not exceed the preset load balancing threshold.
7. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 1, characterized in that... In step S5, the step of fine-tuning the voltage and frequency in the coordinated configuration according to preset parameters includes: Based on the amount by which the power consumption data exceeds the power consumption limit threshold, the direction and magnitude of this round of fine-tuning are determined, and the fine-tuning magnitude does not exceed the preset parameter fine-tuning granularity; The voltage and frequency in the coordinated configuration are simultaneously reduced according to the fine-tuning direction and the fine-tuning amplitude to obtain the corrected coordinated configuration, and the power consumption data is collected again in the next energy consumption monitoring cycle based on the corrected coordinated configuration.
8. The method for optimizing the power consumption of a memory chip in an integrated computing unit according to claim 1, characterized in that... The method further includes: The system monitors the task load data at the current moment. When the peak load and the rate of change are both below a preset standby trigger threshold for multiple consecutive monitoring windows, the system determines that the storage chip has entered standby mode. Under the standby condition, the voltage level and frequency in the stable energy consumption control configuration are synchronously reduced to the preset standby voltage level and standby frequency level to obtain a low power consumption configuration; When the collected task load data re-meets the high load triggering condition, the system reverts from the low power consumption configuration to the stable energy consumption control configuration.
9. A memory chip power optimization system for an integrated computing unit employing the memory chip power optimization method of any one of claims 1 to 8, characterized in that... ,include: The scene recognition module is used to collect the task load data of the computing unit within the monitoring window, extract the load peak and the rate of change from it, and output a high load scene identifier when both the load peak and the rate of change meet the preset high load triggering conditions. The voltage decision module is used to read resource allocation requirements from a preset scenario-resource mapping table based on the high-load scenario identifier, combine the load duration and resource occupancy ratio in the monitoring window to determine the voltage adjustment range, and output the voltage level configuration to be adjusted. A frequency coordination module is used to obtain the current frequency parameters of the memory chip. When the current frequency parameters do not match the voltage level configuration to be adjusted, the current frequency parameters are iteratively adjusted according to a preset frequency optimization step size until they match the voltage level configuration to be adjusted, thus obtaining a coordinated configuration. The task scheduling module is used to select an appropriate collaboration mode from a preset collaboration mode rule base according to the collaboration configuration, allocate the tasks to be executed by the computing unit according to the collaboration mode, and obtain the final running configuration; The feedback correction module is used to run the memory chip according to the final running configuration, collect power consumption data according to a preset power consumption monitoring cycle, and when the power consumption data exceeds the preset power consumption limit threshold, correct the voltage and frequency in the collaborative configuration according to the preset parameter fine-tuning granularity until the power consumption data falls back below the power consumption limit threshold, thereby obtaining a stable power consumption control configuration.
10. The memory chip power consumption optimization system for the integrated computing unit according to claim 9, characterized in that... It also includes a monitoring configuration module, used to monitor the task load data at the current moment, determine whether the storage chip has entered standby condition; under the standby condition, obtain a low power configuration, and when the task load data is collected and the high load trigger condition is met again, restore from the low power configuration to the stable energy consumption control configuration.