Data error correction method of flash memory device, flash memory device, and electronic device

Abstract

This invention discloses a data error correction method for flash memory devices, a flash memory device, and an electronic device. During operation, this invention collects wear parameters of the flash memory device online. It utilizes a pre-trained flash memory performance prediction model that can predict performance parameters based on wear parameters and error correction code encoding / decoding parameters. An optimization algorithm is used to find error correction code encoding / decoding parameters that significantly optimize performance parameters under the current wear parameters. These parameters include at least a degree parameter for constructing the LDPC parity-check matrix. The degree parameter of the LDPC parity-check matrix is ​​dynamically adjusted based on the collected wear parameters, thereby adjusting the LDPC parity-check matrix used in the error correction code encoding / decoding process and precisely optimizing the performance and lifespan of the flash memory device.

Description

Technical Field

[0001] This invention relates to the field of memory error correction code technology, and more specifically to a data error correction method for flash memory devices, flash memory devices, and electronic devices. Background Technology

[0002] Flash memory has gradually become the mainstream storage product due to its advantages of low cost and high bandwidth. With the continuous increase in storage density, in order to ensure storage quality and reduce the bit error rate during read and write operations, LDPC (Low-Density Parity-Check) codes are introduced into the storage controller of flash memory devices as error correction codes. These codes are used to correct errors during data encoding and decoding during read and write operations to ensure storage performance. However, as the usage time of flash memory devices increases, the performance of the memory within them will continuously decline, leading to a continuous increase in the bit error rate. Most current flash memory devices adopt a static LDPC code structure design, which results in the devices becoming unusable after a long period of use due to excessively high bit error rates, thus shortening their lifespan.

[0003] Some existing technologies use different LDPC parity matrix specifications for different media in the hope of extending their service life. However, they cannot solve the problems of shortened lifespan and continuous performance degradation of flash memory devices after long-term use.

[0004] Another part of the existing technology pre-configures multiple different LDPC parity matrices and selects them by looking up a table during use. Although this can improve the performance of flash memory devices to some extent, it cannot accurately optimize the performance and lifespan of flash memory devices during use. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a data error correction method, a flash memory device, and an electronic device, with the aim of dynamically adjusting the LDPC check matrix used for data error correction to precisely optimize the performance and lifespan of the flash memory device.

[0006] In a first aspect, embodiments of the present invention provide a data error correction method for a flash memory device, the method comprising: Obtain wear parameters of the flash memory device, the wear parameters including one or more of read / write cycle count, number of failed bits, or read retry rate; Based on the wear parameters and the pre-trained flash memory performance prediction model, an optimization algorithm is used to determine the adjusted error correction code encoding and decoding parameters. The pre-trained flash memory performance prediction model is used to predict the corresponding performance parameters based on the wear parameters and the error correction code encoding and decoding parameters. The performance parameters include one or more of the following: unrepairable error parameters, bandwidth, or power consumption. The error correction code encoding and decoding parameters include the degree parameter of the LDPC parity-check matrix. An adjusted LDPC parity-check matrix is ​​constructed based on the adjusted error correction code encoding and decoding parameters. The adjusted LDPC parity-check matrix has a different degree parameter than the LDPC parity-check matrix used for current data error correction. Data error correction for flash memory devices based on the adjusted LDPC parity matrix.

[0007] In some implementations, based on the wear parameters and a pre-trained flash memory performance prediction model, an optimization algorithm is used to determine the adjusted error correction code encoding / decoding parameters, including: In response to the LDPC parity-check matrix adjustment condition being triggered, the adjusted error correction code encoding and decoding parameters are determined by an optimization algorithm based on the wear parameters and the pre-trained flash memory performance prediction model.

[0008] In some implementations, the flash memory performance prediction model is trained and determined as follows: Record wear parameters, performance parameters, and corresponding error correction code encoding / decoding parameters of multiple flash memory devices to determine the recording dataset; Adjust the error correction code encoding and decoding parameters, and based on error correction codes with different error correction code encoding and decoding parameters and wear parameters, simulate and calculate the corresponding performance parameters to determine the simulation dataset; Using the recorded dataset and the simulation dataset as sample sets, the wear parameters and error correction code encoding / decoding parameters as sample inputs, and the performance parameters as outputs, regression training is performed on the initialized flash memory performance prediction model to determine the pre-trained flash memory performance prediction model.

[0009] In some implementations, the initialized flash memory performance prediction model is a support vector regression model or a neural network model.

[0010] In some implementations, the degree parameter is the variable node degree distribution of the LDPC parity-check matrix; Constructing the adjusted LDPC parity-check matrix based on the adjusted error-correcting code encoding / decoding parameters includes: Based on the adjusted variable node degree parameters and the current bitrate, determine the adjusted check node degree distribution; The adjusted LDPC verification matrix is ​​constructed based on the adjusted variable node degree distribution and the adjusted verification node degree distribution.

[0011] In some implementations, the adjusted check node degree distribution is determined based on the adjusted variable node degree distribution and the current bitrate, including: Based on the relationship formula between variable node degree distribution, current code rate and check node degree distribution, and assuming that all check nodes have the same degree, the adjusted check node degree distribution is solved.

[0012] In some implementations, the degree parameter is the variable node degree distribution and the check node degree distribution of the LDPC check matrix; Constructing the adjusted LDPC check matrix based on the adjusted degree parameters includes: The adjusted LDPC verification matrix is ​​constructed based on the adjusted variable node degree distribution and the adjusted verification node degree distribution.

[0013] In some implementations, the error correction code encoding / decoding parameters further include at least one of the code rate or the decision log-likelihood ratio.

[0014] In a second aspect, embodiments of the present invention provide a flash memory device, the flash memory device comprising: Flash memory; and, A controller, coupled to the flash memory, performs operations as described in the first aspect.

[0015] In some implementations, the flash memory is NOR flash memory or NAND flash memory.

[0016] Thirdly, an electronic device is provided, including a flash memory device as described in the second aspect.

[0017] This invention, through online acquisition of flash memory device wear parameters during operation, utilizes a pre-trained flash memory performance prediction model that can predict performance parameters based on wear parameters and error correction code encoding / decoding parameters. An optimization algorithm is then used to find error correction code encoding / decoding parameters that significantly optimize performance parameters under the current wear conditions. These parameters include at least the degree parameter used to construct the LDPC parity-check matrix. Furthermore, the degree parameter of the LDPC parity-check matrix can be dynamically adjusted based on the acquired wear parameters, thereby adjusting the LDPC parity-check matrix used in the error correction code encoding / decoding process and precisely optimizing the performance and lifespan of the flash memory device.

[0018] In some implementations, flash memory performance prediction models can use online-recorded wear parameters to simulate and calculate performance parameters based on different error correction encoding and decoding parameters, determine the simulation dataset, and combine it with the online-recorded dataset for regression training, thereby determining a model that can predict the corresponding performance parameters based on wear parameters and error correction encoding and decoding parameters. Attached Figure Description

[0019] The above and other objects, features and advantages of the present invention will become more apparent from the following description of embodiments of the invention with reference to the accompanying drawings, in which: Figure 1 This is a schematic diagram of a flash memory device according to an embodiment of the present invention; Figure 2 This is a flowchart of a data error correction method for a flash memory device according to an embodiment of the present invention; Figure 3 This is a flowchart of training a flash memory performance prediction model according to an embodiment of the present invention; Figure 4 This is a schematic diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0020] The present application is described below based on embodiments, but it is not limited to these embodiments. In the detailed description of the present application below, certain specific details are described in detail. Those skilled in the art can fully understand the present application without these details. To avoid obscuring the substance of the present application, well-known methods, processes, flows, elements, and circuits are not described in detail.

[0021] Furthermore, those skilled in the art should understand that the accompanying drawings provided herein are for illustrative purposes only and are not necessarily drawn to scale.

[0022] Unless the context explicitly requires it, words such as "including" or "contains" throughout the application should be interpreted as including rather than exclusive or exhaustive; that is, meaning "including but not limited to".

[0023] In the description of this application, it should be understood that the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance. Furthermore, in the description of this application, unless otherwise stated, "a plurality of" means two or more.

[0024] Figure 1 This is a schematic diagram of a flash memory device according to an embodiment of the present invention. Figure 1As shown, the flash memory device 1 in this embodiment includes a flash memory 11 and a controller 12. The flash memory 11 can be a NAND flash memory or a NOR flash memory. Both NAND flash memory and NOR flash memory are non-volatile memories. NAND flash memory is based on a floating-gate transistor structure, storing binary information (0 or 1) by capturing or releasing charge. NAND flash memory is read and written in pages and erased in blocks; the target area must be erased before writing. Its storage cells are classified by the number of bits per cell: SLC (1 bit), MLC (2 bits), TLC (3 bits), QLC (4 bits), and PLC (5 bits). More bits result in higher capacity but lower speed and durability. To overcome the density limitations of 2D planar structures, 3D NAND technology vertically stacks storage cells, significantly improving capacity, performance, and reducing cost. Similar to other types of flash memory, the lifespan of NAND flash memory is limited by the number of program / erase (P / E) cycles. Wear leveling and error correction mechanisms implemented by the controller extend its lifespan.

[0025] In this embodiment, the controller 12 is an application-specific integrated circuit (ASIC), a programmable general-purpose integrated circuit, or a hybrid of both. As the core bridge between the host and the flash memory 11, the controller 12 manages all data read / write operations and device maintenance. It communicates with the host via interface protocols (such as SATA, PCIe / NVMe, eMMC, UFS) to translate the host's logical read / write requests into physical operations of the flash memory. The controller 12 integrates a data processing unit 121, a cache management module 122, and an error correction engine 123 (such as an LDPC error correction engine) to ensure data integrity. It maintains a mapping table from logical addresses to physical addresses through the flash translation layer (FTL) and performs bad block management, isolating factory defects or damaged cells generated later. To extend the flash memory's lifespan, the controller uses a wear leveling algorithm to evenly distribute write operations across all storage cells. Simultaneously, a garbage collection mechanism cleans up invalid data and releases available space.

[0026] In the flash memory device of this embodiment, the controller 12 performs error correction code encoding and decoding during read and write operations through the error correction engine 123, thereby realizing data error correction operations for stored data. Specifically, the error correction process of the error correction engine 123 is based on the iterative belief propagation algorithm, and achieves accurate repair of bit errors in high-density flash memory through soft / hard decision decoding. When the controller 12 reads data from the flash memory, it first starts hard decision decoding. This process directly determines the read voltage signal as 0 or 1, and performs parity check operation with the pre-stored LDPC parity check matrix. If the check passes, the data is correct; otherwise, it enters the soft decision decoding process. Soft decision decoding uses the analog voltage information of the flash memory cell to calculate the log-likelihood ratio (LLR) of each bit, reflecting the probability confidence of its value being 0 or 1. The error correction engine 123 performs multiple rounds of iterative message passing on the Tanner graph composed of variable nodes and check nodes, continuously updating the confidence of each bit until the convergence condition is met or the maximum number of iterations is reached. To improve efficiency, the engine prioritizes processing low-information-volume nodes located in voltage overlap regions and optimizes the allocation of computing resources.

[0027] LDPC codes are linear block error-correcting codes with a sparse parity-check matrix (also known as an LDPC check matrix). LDPC codes use the LDPC check matrix to verify the presence of errors in the read codeword. The performance of LDPC codes approaches the Shannon limit, making them an important coding technique in modern communication and storage systems. The core characteristic of LDPC codes is the extremely small number of non-zero elements in the check matrix; this "low-density" characteristic allows encoding to be implemented using a generator matrix G. The generator matrix G is a tool in the LDPC encoding process used to convert the original information bit sequence into a complete codeword containing check bits. Using the generator matrix G, an LDPC code appends a check sequence p to the uncoded bit sequence u, forming the encoded codeword c = [u, p]. The check sequence p ensures that the encoded codeword c satisfies... Where H is the LDPC parity-check matrix. The generator matrix G is a... The matrix is ​​given by: k is the length of the information bits (size of the input data), and n is the total length of the encoded codewords (size of the output data). The generator matrix G and the LDPC parity-check matrix are set to correspond and satisfy the following conditions: .

[0028] The structure of LDPC codes can typically be represented using a Tanner graph, and decoding relies on an iterative belief propagation (BP) algorithm based on the Tanner graph. The Tanner graph contains two types of nodes: variable nodes (VNs) and check nodes (CNs). Variable nodes correspond to the individual bits of the codeword. Check nodes correspond to the check equation. If the element in the i-th row and j-th column of the check matrix H is 1, then an edge is connected between variable node j and check node i, indicating that the bit participates in the modulo-2 addition operation of the check equation. There are no direct connections between nodes of the same type in the Tanner graph. Since the check matrix of an LDPC code is a sparse matrix, each node in the Tanner graph is connected to only a small number of other nodes. During decoding, the controller 12 first initializes a confidence value (e.g., log-likelihood ratio LLR) for each bit based on channel information (e.g., flash memory cell voltage), and then executes the belief propagation (BP) algorithm according to the Tanner graph. Variable nodes and check nodes repeatedly exchange external information; check nodes update messages according to XOR constraints; and variable nodes iteratively correct their own confidence by fusing prior information and external messages. This process continues until all verification equations are satisfied or the maximum number of iterations is reached.

[0029] In LDPC error correction, the degree parameter describes the statistical characteristics of the number of connections between nodes in the Tanner graph and is a key parameter determining the LDPC parity-check matrix. The "degree" of a node refers to the number of edges connected to that node. Therefore, to accurately describe the degree distribution throughout the graph, two degree distribution multinomials, λ(x) and ρ(x), are typically used. Here, λ(x) represents the variable node degree distribution. λ(x) can be expressed as:

[0030] Where the coefficient λ i dv represents the proportion of all edges connected to the variable node of degree i, and dv represents the maximum column degree.

[0031] ρ(x) represents the degree distribution of the check nodes, which can be expressed as:

[0032] Where the coefficient ρ j dh represents the proportion of all edges connected to the check node of degree j, and dh represents the maximum row degree.

[0033] Based on the degree parameter constrained by the degree distribution multinomial, a Tanner graph can be constructed using an algorithm. One implementation uses the Progressive Edge-Growth (PEG) algorithm. In fact, the Tanner graph and the LDPC parity-check matrix have a corresponding relationship. The number of variable nodes in the Tanner graph corresponds to the number of columns in the LDPC parity-check matrix, and the number of check nodes corresponds to the number of rows in the LDPC parity-check matrix. That is, each row of the LDPC parity-check matrix represents a check node, and each column represents a variable node. By traversing each position (i, j) in the matrix, if there is an edge connecting check node ci and variable node Cj, then the matrix element H... ij =1 otherwise, 0. Once the Tanner graph is constructed, the LDPC check matrix is ​​also constructed. Based on the Tanner graph or the LDPC check matrix, data error correction operations can be performed.

[0034] In existing flash memory devices, the controller typically uses a static LDPC parity-check matrix. This leads to a continuous decline in the performance of the flash memory device and an increase in the bit error rate after prolonged use, while the controller's error correction capability cannot be adjusted accordingly. The controller 12 in this embodiment can predict performance parameters under different degree parameters based on wear parameters during flash memory device operation using a pre-trained performance prediction model. This allows for the use of an optimization algorithm to obtain the optimal degree parameters, thereby dynamically adjusting the LDPC parity-check matrix. The adjusted matrix, with stronger error correction capabilities, is then used for data error correction to adapt to actual usage conditions and dynamically adjust and improve the performance of flash memory devices after prolonged use.

[0035] In this embodiment, the controller 12 is configured to perform the operations described below to perform data error correction on the flash memory device.

[0036] Figure 2 This is a flowchart of a data error correction method for a flash memory device according to an embodiment of the present invention. Figure 2 As shown, the data error correction process in this embodiment of the invention includes: Step S210: Obtain the wear parameters of the flash memory device.

[0037] In this embodiment, the wear parameters of the flash memory device are used to characterize the overall or partial (e.g., specific memory block of a specific memory chip) wear condition of the flash memory device. In this embodiment, the wear parameters include one or more of the following: read / write cycle count, Fail Bit Count (FBC), or Retry Rate. These parameters do not change due to variations in the LDPC parity-check matrix or other error correction code parameters.

[0038] The read / write cycle count, also known as the Program / Erase (PE) cycle, refers to the number of times a memory block completes one full write (programming) and one full erase process. For flash memory, the target area must be erased before data is written; therefore, one PE cycle represents one basic wear and tear on a memory cell. Each PE cycle causes minor damage to the oxide layer within the memory cell. As the number of cycles accumulates, the damage worsens, eventually causing the cell to fail and become unable to reliably store charge. The number of PE cycles is not measured in bits but rather in blocks.

[0039] The number of failed bits refers to the number of bits that do not match the original data, detected by the error correction code (ECC) mechanism during read or program verification of flash memory. This value is a key indicator for flash memory controllers to assess the health of memory cells, manage bad blocks, and predict lifespan.

[0040] The read retry rate refers to the frequency or number of read retries performed to successfully read data. When flash memory cells experience charge drift due to prolonged use (increased PE cycle count), long-term data storage, or read interference, reading data using the default reference voltage may fail. In this case, the memory controller initiates a read retry mechanism, automatically attempting to reread the data using a series of preset, finely tuned reference voltages until the read is successful or all retry options are exhausted. Therefore, the retry rate reflects the health of the flash memory and the difficulty of the read operation.

[0041] The wear parameters described above can reflect the usage and wear status of flash memory to a certain extent. Therefore, subsequent optimization methods for the LDPC parity-check matrix (i.e., error correction coding method) can be sought based on the wear status characterized by the wear parameters.

[0042] Step S220: Based on the wear parameters and the pre-trained flash memory performance prediction model, an optimization algorithm is used to determine the adjusted error correction code encoding and decoding parameters.

[0043] This step can be triggered under different circumstances.

[0044] In one implementation, step S220 can be triggered periodically, that is, a predetermined periodic interval is used as the trigger condition for adjusting the LDPC check matrix.

[0045] In another implementation, step S220 can specifically involve determining the adjusted error correction code encoding / decoding parameters based on the wear parameters and / or the online recorded performance parameters, according to an optimization algorithm, in response to at least one of the wear parameters and / or online recorded performance parameters satisfying the LDPC parity-check matrix adjustment condition, using the wear parameters and the pre-trained flash memory performance prediction model. That is, when the wear parameters or performance parameters indicate a performance degradation to a certain extent, the LDPC parity-check matrix adjustment begins. The adjustment condition can be that the number of parameters among the wear parameters and performance parameters reaching the corresponding parameter threshold reaches a predetermined value. In one example, the wear parameters include read / write cycle count, failure bits, and read retry rate. If the number of PE cycles is higher than the PE threshold, or the number of failure bits is higher than the failure threshold, or the read retry rate is higher than the retry threshold, then one of the parameters is considered to have reached the corresponding parameter threshold. If two or more parameters reach the threshold, the adjustment condition is determined to be satisfied.

[0046] Alternatively, the adjustment condition can be triggered by inputting multiple parameters into an evaluation function to calculate a score. If the score reaches a threshold, the adjustment condition is triggered. For example, wear parameters include read / write cycle count, failure bits, and read retry rate; performance parameters include unrepairable error parameters, bandwidth, and power consumption. The score can be calculated by weighted summing of the read / write cycle count, failure bits, read retry rate, unrepairable error parameters, power consumption, and the reciprocal of bandwidth. Based on a pre-set score threshold, it can be determined whether the wear level has reached the set level, and then whether step S220 should be triggered.

[0047] In this embodiment, a pre-trained flash memory performance prediction model can be used to predict corresponding performance parameters using wear parameters and error correction code encoding / decoding parameters, including degree parameters, that describe the error correction performance of the LDPC parity-check matrix. That is, the pre-trained flash memory performance prediction model is used to predict corresponding performance parameters based on wear parameters and error correction code encoding / decoding parameters including degree parameters. In this embodiment, performance parameters are parameters used to characterize the current operating performance of the flash memory device, including one or more of uncorrectable error parameters, bandwidth, or power consumption. The error correction code encoding / decoding parameters include the degree parameters of the LDPC parity-check matrix. These parameters can characterize the data read / write performance, rate, and efficiency after error correction under a specific LDPC parity-check matrix-correlation processing load.

[0048] The unrepairable error parameter specifically refers to the UECC (Uncorrectable Error Correction Code) error rate. UECC is a crucial indicator for measuring data integrity risk in flash memory. This error occurs when data bits flip due to aging, wear, or interference in a storage cell, and the number of erroneous bits exceeds the error correction engine's capability limit. In this case, the controller cannot recover the original data, and the read operation fails. In flash memory device controllers, unrepairable error parameters are typically presented as an error rate. Once UECC occurs, the controller usually marks the physical block containing the data as a bad block and attempts to recover the data using redundancy mechanisms such as RAID, while simultaneously logging the event. By adjusting the degree parameter of the LDPC parity-check matrix, the LDPC error correction engine can have different error correction capabilities and exhibit different UECC error rates under the same wear conditions.

[0049] Bandwidth, also known as data transfer rate, refers to the amount of data that can be read or written per unit of time, usually measured in MB / s or GB / s. Using LDPC parity-check matrices with different error correction capabilities for data error correction will also lead to changes in bandwidth.

[0050] Power consumption refers to the electrical energy consumed by a flash memory device per unit time during operation. Typically, for flash memory devices, power consumption includes active power consumption and idle power consumption, with active power consumption representing the electrical energy consumed during read and write operations. Power consumption effectively characterizes the performance of a flash memory device. Power consumption increases significantly as the flash memory device ages. Furthermore, using LDPC parity-check matrices with different error correction capabilities for data error correction also leads to changes in power consumption.

[0051] Since the wear parameter is not affected by the error correction code performance, while the performance parameter, although related to the degree of wear, is affected by changes in the degree parameter of the LDPC parity-check matrix or other error correction code encoding / decoding parameters (such as code rate or LLR), a regression model that can predict the corresponding performance parameter based on the wear parameter and degree parameter can be pre-trained. Based on this model, an optimization algorithm can be used to optimize the current degree parameter, thereby adjusting the LDPC parity-check matrix.

[0052] Let the wear parameter be denoted as ms, the performance parameter as x, the flash memory performance prediction model as the nonlinear function F(), and the degree parameter of the LDPC parity-check matrix as d. Then the relationship between the four can be expressed by the following formula: x=F(ms, d) It should be understood that wear parameters and performance parameters can be vectors or matrices containing multiple data items. In this step, given the wear parameter ms and the flash memory performance prediction model F(), we aim to find the optimal degree parameter d that optimizes the performance parameter x.

[0053] Figure 3 This is a flowchart illustrating the training of a flash memory performance prediction model according to an embodiment of the present invention. Figure 3 As shown, the process of training the flash memory performance prediction model includes the following steps: In step S310, wear parameters, performance parameters, and corresponding error correction code encoding / decoding parameters of multiple flash memory devices are recorded to determine the recording dataset.

[0054] In this step, wear parameters, performance parameters, and error correction encoding / decoding parameters of the same model or the same flash memory chip at different wear stages can be recorded experimentally beforehand. The error correction encoding / decoding parameters must include at least the aforementioned degree parameters, thereby determining a recording dataset. Each recorded data item in the dataset includes a set of wear parameters, the corresponding performance parameters, and the error correction encoding / decoding parameters used.

[0055] In step S320, the error correction code encoding and decoding parameters are adjusted. Based on error correction codes with different error correction code encoding and decoding parameters and wear parameters, the corresponding performance parameters are simulated and calculated to determine the simulation dataset.

[0056] Since it is difficult to obtain a large amount of data to construct a training dataset through experimental recordings, in this step, after adjusting the error correction code encoding and decoding parameters and constructing the corresponding LDPC parity-check matrix, the corresponding performance parameters are calculated offline using simulation software to determine the simulation dataset. The simulation data items in the simulation dataset also include a set of wear parameters, the corresponding performance parameters, and the error correction encoding and decoding parameters used. Unlike the recorded dataset, the performance parameters in the simulation dataset are obtained through simulation calculations.

[0057] Therefore, the sample set for training the flash memory performance prediction model can be obtained through steps S310 and S320.

[0058] In step S330, the initial flash memory performance prediction model is subjected to regression training using the recorded dataset and the simulation dataset as sample sets, the wear parameters and degree parameters as sample inputs, and the performance parameters as outputs, to determine the pre-trained flash memory performance prediction model.

[0059] In this step, the initial flash memory performance prediction model is trained using regression training, so that the model can use wear parameters and degree parameters as inputs to predict performance parameters.

[0060] In one implementation, the initial flash memory performance prediction model can employ a Support Vector Regression (SVR) model. SVR is an extension of Support Vector Machines (SVM) for regression problems, used to predict continuous values. Unlike traditional regression methods that minimize the prediction error across all samples, SVR aims to construct a function such that the absolute difference between the predicted and true values ​​for most training samples does not exceed a preset tolerance threshold ε. This model focuses only on samples falling outside the ε-tube, which are the support vectors. SVR also utilizes kernel tricks to handle non-linear relationships and improves the model's generalization performance through structural risk minimization.

[0061] The final prediction model of SVR is a combination of linear functions. After mapping to a high-dimensional feature space using the kernel trick, its decision function takes the form:

[0062] Where K(x) i (x) is the kernel function. and b is a Lagrange multiplier, and b is a bias term.

[0063] For SVR, the training objective is to minimize Among them, ||w|| 2 This represents the complexity of the model (aiming for a flat function), while This is a penalty for the total error. The penalty parameter C is used to balance model flatness with tolerance for error. This is achieved by introducing Lagrange multipliers α and β. The original problem is transformed into a convex quadratic programming problem involving these multipliers. Solving this dual problem using corresponding optimization algorithms (such as Sequential Minimum Optimization (SMO) or a general quadratic programming solver) yields the optimal Lagrange multipliers. The sample points corresponding to non-zero Lagrange multipliers are the support vectors. These are the key points determining the shape of the final regression function, while most other sample points have no impact on the model, reflecting the sparsity of the SVR model. Using the obtained support vectors and Lagrange multipliers, the final regression function can be constructed. After training, the model's performance needs to be evaluated using an independent test set. Common metrics include mean squared error and mean absolute error. If the performance is unsatisfactory, hyperparameters (such as C, ε, and kernel parameters) need to be adjusted using methods such as grid search, and the training process repeated until a satisfactory model is obtained.

[0064] Therefore, the regression function can be used as a flash memory performance prediction model to predict the corresponding performance parameters based on the input wear parameters and the degree parameter of the LDPC parity-check matrix.

[0065] After determining the flash memory prediction model, the target degree parameter is calculated from the available degree parameters using an optimization algorithm, so that the performance parameters are optimized given a fixed wear parameter.

[0066] In one alternative implementation, a grid search method can be used to search for the target degree parameter that optimizes the performance parameters.

[0067] In another alternative implementation, intelligent optimization algorithms such as particle swarm optimization, genetic algorithm, or ant colony optimization can be used to search for the target degree parameter that makes the performance parameters optimal, using the flash memory performance prediction model as the fitness function.

[0068] Specifically, an evaluation function g() can be constructed based on multiple performance parameters, and the value of the evaluation function can be used as a performance score to evaluate whether the error correction code encoding and decoding parameters have optimized the performance parameters during the optimization process.

[0069] It should be understood that, as an alternative, flash memory performance prediction models are not limited to the relatively simple SVR model, but can also employ more complex, but more accurate, neural network models.

[0070] As an alternative, existing technologies also include lifetime prediction models that can predict performance parameters based on wear parameters and degree parameters. Alternatively, third-party-provided models of this type can be used as flash memory performance prediction models.

[0071] Step S230: Construct an adjusted LDPC check matrix based on the adjusted error correction code encoding and decoding parameters. The adjusted LDPC check matrix has a different degree parameter than the LDPC check matrix used for current data error correction.

[0072] In one optional implementation, the degree parameter in the error-correcting code encoding parameters is the variable node degree distribution of the LDPC parity-check matrix. Since the parity-check node degree distribution, the variable node degree distribution, and the code rate satisfy the following constraint relationship in the LDPC parity-check matrix:

[0073] Where R is the code rate, and the code rate of the error correction code is the ratio of the number of information bits to the total number of bits after encoding. λ(x) represents the variable node degree distribution. ρ(x) represents the check node degree distribution. Since the code rate is usually predetermined, the integral value of the check node degree distribution can be obtained based on the adjusted variable node degree distribution. If we increase the coefficients ρ in ρ(x)... j With essentially the same assumptions, all ρ values ​​can be calculated from the integral values. j .

[0074] Therefore, step S230 may include the following steps: Step S231: Determine the adjusted check node degree distribution based on the adjusted variable node degree parameters and the current bit rate.

[0075] Specifically, as described above, the adjusted check node degree distribution is solved based on the relationship formula between the variable node degree distribution, the current code rate, and the check node degree distribution, and assuming that all check node degrees are basically the same.

[0076] In step S232, the adjusted LDPC check matrix is ​​constructed based on the adjusted variable node degree distribution and the adjusted check node degree distribution. Since the degree must be an integer, if they are all exactly the same, the integer constraint cannot be satisfied, so the degree of some nodes needs to be adjusted to make the degree distribution conform to the above constraint.

[0077] Specifically, an asymptotic edge-growth algorithm can be used to construct the Tanner graph corresponding to the LDPC parity-check matrix. If the LDPC error correction code used is a QC-LDPC error correction code, a quasi-rule-based approach can be used to construct the LDPC parity-check matrix.

[0078] After the LDPC check matrix is ​​constructed, the controller 12 can store the corresponding data object through its own memory or a memory shared with external components, and call the adjusted LDPC check matrix to perform data error correction operations.

[0079] In another optional implementation, step S220 can involve adding a code rate constraint through an optimization algorithm, while simultaneously performing optimization calculations on the variable node degree distribution and the check node degree distribution. This allows the variable node degree distribution and the check node degree distribution to be calculated during the optimization process. This method can obtain more accurate and optimized degree parameters; however, it increases the computational resources required for adjustment to some extent.

[0080] In another alternative implementation, the error-correcting code encoding and decoding parameters are not limited to the degree parameter alone, but may further include one or more of the code rate and decision log-likelihood ratio (LLR). Since the above parameters, together with the degree parameter, affect the encoding and decoding error-correcting capability and decoding convergence speed of the LDPC error-correcting code, the data error-correcting capability can also be adjusted by adding adjustments to the above parameters, thereby dynamically improving performance.

[0081] In one implementation, a corresponding generator matrix can be generated for the adjusted LDPC matrix to perform the corresponding error correction coding operation, so that the two satisfy the constraint relationship described above.

[0082] Step S240: Perform data error correction on the flash memory device based on the adjusted LDPC check matrix.

[0083] Specifically, the adjusted LDPC parity-check matrix has a different degree parameter than the original configuration, thus providing enhanced error correction capabilities. Since the degree parameter is a core factor determining LDPC code performance, it directly influences the error correction capability and decoding convergence speed by affecting the structure of the parity-check matrix. Therefore, for performance degradation caused by wear, dynamically adjusting the LDPC parity-check matrix can effectively improve performance and extend the lifespan of the flash memory device.

[0084] Specifically, in this step, a corresponding generator matrix for encoding can be generated based on the adjusted LDPC parity check matrix. The new generator matrix is ​​used for error correction encoding, and the adjusted LDPC parity check matrix is ​​used for error correction decoding, thereby improving performance while ensuring the normal operation of the flash memory device.

[0085] This invention, through online acquisition of flash memory device wear parameters during operation, utilizes a pre-trained flash memory performance prediction model that can predict performance parameters based on wear parameters and error correction code encoding / decoding parameters. An optimization algorithm is then used to find error correction code encoding / decoding parameters that significantly optimize performance parameters under the current wear conditions. These parameters include at least the degree parameter used to construct the LDPC parity-check matrix. This allows for dynamic adjustment of the degree parameter of the LDPC parity-check matrix based on the acquired wear parameters, thereby adjusting the LDPC parity-check matrix used in the error correction code encoding / decoding process and precisely optimizing the performance and lifespan of the flash memory device.

[0086] In some implementations, flash memory performance prediction models can use online recorded wear parameters to simulate and calculate performance parameters based on different error correction codec parameters, determine the simulation dataset, and combine it with the online recorded dataset for regression training, thereby determining a model that can predict the corresponding performance parameters based on wear parameters and error correction codec parameters.

[0087] Figure 4 This is a schematic diagram of an electronic device according to an embodiment of the present invention. In this embodiment, electronic device 4 is an electronic device using the flash memory device of an embodiment of the present invention. Figure 4 As shown, the electronic device 4 includes at least one processor 41; a flash memory device 42 communicatively connected to at least one processor 41; and a communication component 43, which receives and transmits data under the control of the processor 41; wherein the flash memory device 42 stores instructions executable by at least one processor 41, which are read and written by at least one processor 41 to perform the set functions.

[0088] Specifically, the electronic device includes: one or more processors 41 and a flash memory device 42. Figure 4 Taking a processor 41 as an example, the processor 41 and the flash memory device 42 can be connected via a bus or other means. Figure 4 Taking a bus connection as an example, the flash memory device 42, as a non-volatile computer-readable storage medium, can be used to store non-volatile software programs, non-volatile computer-executable programs, and modules. The processor 41 executes various functional applications and data processing of the device by running the non-volatile software programs, instructions, and modules stored in the flash memory device 42.

[0089] The flash memory device 42 collects wear parameters online during operation and uses a pre-trained flash memory performance prediction model that can predict performance parameters based on wear parameters and error correction code encoding / decoding parameters. An optimization algorithm is then used to find error correction code encoding / decoding parameters that significantly optimize performance parameters under the current wear conditions. These parameters include at least the degree parameter used to construct the LDPC parity-check matrix. This allows for dynamic adjustment of the degree parameter of the LDPC parity-check matrix based on the collected wear parameters, thereby adjusting the LDPC parity-check matrix used in the error correction code encoding / decoding process and precisely optimizing the performance and lifespan of the flash memory device.

[0090] The above description is merely a preferred embodiment of this application and is not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A data error correction method for a flash memory device, characterized in that, The method includes: Obtain wear parameters of the flash memory device, the wear parameters including one or more of read / write cycle count, number of failed bits, or read retry rate; Based on the wear parameters and the pre-trained flash memory performance prediction model, an optimization algorithm is used to determine the adjusted error correction code encoding and decoding parameters. The pre-trained flash memory performance prediction model is used to predict the corresponding performance parameters based on the wear parameters and the error correction code encoding and decoding parameters. The performance parameters include one or more of the following: unrepairable error parameters, bandwidth, or power consumption. The error correction code encoding and decoding parameters include the degree parameter of the LDPC parity-check matrix. An adjusted LDPC parity-check matrix is ​​constructed based on the adjusted error correction code encoding and decoding parameters. The adjusted LDPC parity-check matrix has a different degree parameter than the LDPC parity-check matrix used for current data error correction. Data error correction for flash memory devices based on the adjusted LDPC parity matrix.

2. The method according to claim 1, characterized in that, Based on the wear parameters and the pre-trained flash memory performance prediction model, an optimization algorithm is used to determine the adjusted error correction code encoding and decoding parameters, including: In response to the LDPC parity-check matrix adjustment condition being triggered, the adjusted error correction code encoding and decoding parameters are determined by an optimization algorithm based on the wear parameters and the pre-trained flash memory performance prediction model.

3. The method according to claim 1, characterized in that, The flash memory performance prediction model is trained and determined in the following manner: Record wear parameters, performance parameters, and corresponding error correction code encoding / decoding parameters of multiple flash memory devices to determine the recording dataset; Adjust the error correction code encoding and decoding parameters, and based on error correction codes with different error correction code encoding and decoding parameters and wear parameters, simulate and calculate the corresponding performance parameters to determine the simulation dataset; Using the recorded dataset and the simulation dataset as sample sets, the wear parameters and error correction code encoding / decoding parameters as sample inputs, and the performance parameters as outputs, regression training is performed on the initialized flash memory performance prediction model to determine the pre-trained flash memory performance prediction model.

4. The method according to claim 3, characterized in that, The initialized flash memory performance prediction model is a support vector regression model or a neural network model.

5. The method according to claim 1, characterized in that, The degree parameter is the variable node degree distribution of the LDPC parity-check matrix; Constructing the adjusted LDPC parity-check matrix based on the adjusted error-correcting code encoding / decoding parameters includes: Based on the adjusted variable node degree parameters and the current bitrate, determine the adjusted check node degree distribution; The adjusted LDPC verification matrix is ​​constructed based on the adjusted variable node degree distribution and the adjusted verification node degree distribution.

6. The method according to claim 5, characterized in that, Based on the adjusted variable node degree distribution and the current bitrate, the adjusted check node degree distribution is determined as follows: Based on the relationship formula between variable node degree distribution, current code rate and check node degree distribution, and assuming that all check nodes have the same degree, the adjusted check node degree distribution is solved.

7. The method according to claim 1, characterized in that, The degree parameter is the variable node degree distribution and the check node degree distribution of the LDPC check matrix; Constructing the adjusted LDPC check matrix based on the adjusted degree parameters includes: The adjusted LDPC verification matrix is ​​constructed based on the adjusted variable node degree distribution and the adjusted verification node degree distribution.

8. The method according to claim 1, characterized in that, The error correction code encoding / decoding parameters also include at least one of the following: code rate or decision log-likelihood ratio.

9. A flash memory device, characterized in that, The flash memory device includes: Flash memory; and, A controller, coupled to the flash memory, performs the operations described in any one of claims 1-8.

10. The flash memory device according to claim 9, characterized in that, The flash memory is either NOR flash or NAND flash.

11. An electronic device, characterized in that, Includes the flash memory device as described in any one of claims 9-10.

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