Retry method for atomic operations, atomic operation module, and graphics processor

Abstract

The application provides an atomic operation retry method, an atomic operation module and a graphics processor. The method is applied to an atomic operation module in a graphics processor (GPU). The atomic operation module comprises a response detection unit, a retry control unit, a main state machine and an atomic operation execution unit. The method comprises the following steps: after the response detection unit receives an atomic operation response, triggering the main state machine according to a response result of the atomic operation response; the main state machine is used for synchronizing the response result to the retry control unit; if the response result is a failure response, triggering the main state machine after the retry control unit waits for a preset retry interval; the main state machine is used for triggering the atomic operation execution unit after being triggered by the retry control unit; and the atomic operation execution unit is used for retransmitting execution data to a network on chip (NOC) after being triggered by the main state machine. By using the atomic operation retry method, the atomic operation module and the graphics processor, the atomic operation retry timeliness and operation reliability can be considered.

Description

Technical Field

[0001] This application belongs to the field of chip technology, specifically relating to a retry method for atomic operations, an atomic operation module, and a graphics processor. Background Technology

[0002] In high-performance computing chips such as Graphics Processing Units (GPUs), the Atomic module in the Command Processor (CP) system is responsible for executing atomic operations. Atomic operations are core operations for implementing data synchronization and locking mechanisms, and are widely used in multi-threaded and multi-process data consistency control scenarios. Currently, the Atomic module supports the normal execution of atomic operations and basic exception handling, but it lacks reasonable control over retry methods after operation failures. Uncontrolled retries may cause bus congestion, reducing the overall system throughput and operational reliability.

[0003] Therefore, how to provide a retry method for atomic operations that balances retry timeliness and operational reliability is an urgent problem to be solved in this field. Summary of the Invention

[0004] To address the problems existing in the prior art, a retry method, atomic operation module, and graphics processor for atomic operations are proposed. By utilizing this retry method, atomic operation module, and graphics processor, both the timeliness of retrying atomic operations and the reliability of operation can be ensured.

[0005] This application provides the following solutions.

[0006] In a first aspect, this application provides a retry method for atomic operations. This method is applied to an atomic operation module in a graphics processing unit (GPU). The atomic operation module includes a response detection unit, a retry control unit, a main state machine, and an atomic operation execution unit. The method includes:

[0007] After receiving the atomic operation response, the response detection unit triggers the main state machine based on the response result of the atomic operation. The main state machine is used to synchronize the response result to the retry control unit. If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine. The main state machine is used to trigger the atomic operation execution unit after being triggered by the retry control unit. The atomic operation execution unit is used to resend execution data to the on-chip network NOC after being triggered by the master state machine.

[0008] In some possible embodiments, the master state machine includes a write state, a write success state, and a write failure state; The master state machine is used to transition from the execution failure state to the write state after being triggered by the retry control unit, and to trigger the atomic operation execution unit after transitioning to the write state; If the response result is a failure response, the response detection unit triggers the main state machine, causing the main state machine to transition from the write state to the write failure state; If the response result is a successful response, the response detection unit triggers the main state machine, causing the main state machine to transition from the write state to the write success state.

[0009] In some possible embodiments, the retry control unit further includes a timing detection subunit. If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine, including: If the response result is a failure response, the retry control unit controls the timing detection subunit to wait for the preset retry interval before triggering the main state machine.

[0010] In some possible embodiments, the retry control unit further includes a timing detection subunit and a retry counter. If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine, including: If the response result is a failure response, the retry control unit determines whether the count of the retry counter is less than the preset number of retries; If the retry counter count is less than the preset number of retries, the retry control unit will trigger the main state machine after waiting for the preset retry interval through the timing detection subunit. If the retry counter count is greater than or equal to the preset number of retries, the retry control unit stops retrying.

[0011] In some possible embodiments, the method further includes: The master state machine is used to trigger the retry counter after transitioning from the write state to the write failure state, thus incrementing the retry counter by 1.

[0012] In some possible embodiments, the retry control unit further includes a status management unit, and the method further includes: If the retry counter count is greater than or equal to the preset number of retries, the status management unit receives the retry failure signal sent by the retry calculator and sends the retry failure information to the calculation processing unit (CPE).

[0013] In some possible embodiments, the atomic operation module further includes a configuration unit, and the method further includes: The configuration unit receives the atomic operation command sent by the computing and processing unit and triggers the main state machine, causing the main state machine to switch from the idle state to the write state. The configuration unit sends operation data to the operation unit according to the atomic operation command; The operation unit sends execution data to the on-chip network (NOC) based on the operation data.

[0014] In some possible embodiments, the retry control unit further includes a status management unit, and the configuration unit receives atomic operation commands sent by the computation processing unit and sends operation data to the operation unit, including: The configuration unit receives atomic operation commands sent by the computing and processing unit, and performs address validity checks on the target address in the atomic operation command; If the detection passes, the configuration unit sends operation data to the operation unit; If the detection fails, the configuration unit sends an address error message to the status management unit; The status management unit sends error information back to the computing and processing unit based on the address error information.

[0015] Secondly, this application provides an atomic operation module applied to a graphics processor. The atomic operation module includes a response detection unit, a retry control unit, a main state machine, and an atomic operation execution unit. The response detection unit is used to trigger the main state machine based on the response result of the atomic operation response after receiving the atomic operation response. The main state machine is used to synchronize the response result to the retry control unit. If the response result is a failure response, the retry control unit is used to wait for a preset retry interval and then trigger the main state machine. The main state machine is used to trigger the atomic operation execution unit after being triggered by the retry control unit. The atomic operation execution unit is used to resend execution data to the on-chip network NOC after being triggered by the master state machine.

[0016] In some possible embodiments, the master state machine includes a write state, a write success state, and a write failure state; the master state machine is used to transition from the execution failure state to the write state after being triggered by the retry control unit, and to trigger the atomic operation execution unit after transitioning to the write state; if the response result is a failure response, the response detection unit is used to trigger the master state machine to transition from the write state to the write failure state; if the response result is a success response, the response detection unit is used to trigger the master state machine to transition from the write state to the write success state.

[0017] In some possible embodiments, the retry control unit further includes a timing detection subunit. If the response result is a failure response, the retry control unit is used to control the main state machine to be triggered after waiting for a preset retry interval through the timing detection subunit.

[0018] In some possible embodiments, the retry control unit further includes a timing detection subunit and a retry counter. If the response result is a failure response, the retry control unit is used to determine whether the count of the retry counter is less than the preset number of retries. If the count of the retry counter is less than the preset number of retries, the retry control unit is used to control the main state machine to be triggered after waiting for a preset retry interval through the timing detection subunit. If the count of the retry counter is greater than or equal to the preset number of retries, the retry control unit is used to stop retries.

[0019] In some possible embodiments, the master state machine is used to trigger a retry counter after transitioning from a write state to a write failure state, thereby incrementing the retry counter by 1.

[0020] In some possible embodiments, the retry control unit further includes a status management unit. If the count of the retry counter is greater than or equal to a preset number of retries, the status management unit is used to receive a retry failure signal sent by the retry calculator and send retry failure information to the calculation processing unit CPE.

[0021] In some possible embodiments, the atomic operation module further includes a configuration unit, which receives atomic operation commands sent by the computing processing unit and triggers the main state machine to transition from an idle state to a write state; the configuration unit is used to send operation data to the operation unit according to the atomic operation commands; the operation unit sends execution data to the on-chip network (NOC) according to the operation data.

[0022] In some possible embodiments, the retry control unit further includes a status management unit. The configuration unit is used to receive atomic operation commands sent by the computing processing unit and to perform address validity checks on the target address in the atomic operation commands. If the check passes, the configuration unit is used to send operation data to the operation unit. If the check fails, the configuration unit is used to send address error information to the status management unit. The status management unit feeds back abnormal information to the computing processing unit based on the address error information.

[0023] Thirdly, this application provides a graphics processor that includes the aforementioned atomic operation module.

[0024] The atomic operation retry method provided in this application, through the retry control unit and the main state machine, can precisely control the retry interval and automatically trigger the retry operation, effectively avoiding bus congestion caused by frequent retries, while ensuring the timeliness of retry and improving the overall system throughput and operational reliability.

[0025] Other advantages of this application will be explained in more detail with reference to the following description and figures.

[0026] It should be understood that the above description is merely an overview of the technical solution of this application, so as to enable a clearer understanding of the technical means of this application and thus allow for its implementation in accordance with the contents of the specification. To make the above and other objects, features, and advantages of this application more apparent and understandable, specific embodiments of this application are illustrated below. Attached Figure Description

[0027] By reading the detailed description of the exemplary embodiments below, those skilled in the art will understand the advantages and benefits described herein, as well as other advantages and benefits. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. In the drawings: Figure 1 A flowchart illustrating a retry method for atomic operations provided in an embodiment of this application; Figure 2 A hardware schematic diagram illustrating the application of a retry method for atomic operations provided in an embodiment of this application; Figure 3 This is a schematic diagram of an atomic operation module for atomic operations provided in an embodiment of this application.

[0028] In the accompanying drawings, the same or corresponding reference numerals indicate the same or corresponding parts. Detailed Implementation

[0029] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0030] In the description of embodiments of this application, it should be understood that terms such as “comprising” or “having” are intended to indicate the presence of the disclosed features, figures, steps, behaviors, components, portions or combinations thereof in this specification, and do not exclude the possibility of the presence of one or more other features, figures, steps, behaviors, components, portions or combinations thereof.

[0031] Unless otherwise stated, " / " means "or". For example, A / B can mean A or B. In this article, "and / or" is merely a way of describing the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can mean: A alone, A and B at the same time, and B alone.

[0032] The terms "first," "second," etc., are used only for ease of description to distinguish identical or similar technical features and should not be construed as indicating or implying the relative importance or number of these technical features. Therefore, a feature defined by "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of embodiments of this application, unless otherwise stated, the term "multiple" means two or more.

[0033] It should also be noted that, unless otherwise specified, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0034] like Figure 1 and Figure 2 As shown in the embodiments of this application, the atomic operation retry method is applied to the atomic operation module in a graphics processing unit (GPU). The atomic operation module includes a response detection unit, a retry control unit, a main state machine, and an atomic operation execution unit. The method includes: S101: The response detection unit receives the atomic operation response and triggers the main state machine based on the response result of the atomic operation response. The main state machine is used to synchronize the response result to the retry control unit.

[0035] S102: If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine. The main state machine is used to trigger the atomic operation execution unit after being triggered by the retry control unit.

[0036] S103: The atomic operation execution unit is used to resend execution data to the on-chip network NOC after being triggered by the master state machine.

[0037] It should be noted that the atomic operation provided in this application embodiment can specifically be a timeout retry of the atomic compare and swap (CAS) operation, which is applicable to the optimization of atomic CAS operation of the atomic operation module in the CP system based on the CASAXI5 protocol.

[0038] The response detection unit in this embodiment can capture the atomic operation responses returned by the bus in real time. Normally, all atomic operations will receive a response, and there is no scenario where no response is received. Responses include two types: success responses and failure responses. Failure responses may also include bus response errors. If a success response is detected, it indicates that the atomic operation has been completed and a success status can be returned to the computation processing unit (CPE). If a failure response is detected, it indicates that the atomic operation has not been completed, which may be due to a discrepancy between the comparison value and the current value of the target address, or a bus malfunction, in which case a retry process is initiated.

[0039] The master state machine in this application may include an idle state, a write state, a write success state, and a write failure state. The master state machine is used to transition from the execution failure state to the write state after being triggered by the retry control unit, and to trigger the atomic operation execution unit after transitioning to the write state. If the response result is a failure response, the response detection unit triggers the master state machine, causing it to transition from the write state to the write failure state; if the response result is a success response, the response detection unit triggers the master state machine, causing it to transition from the write state to the write success state.

[0040] As one possible implementation, the retry control unit in this embodiment can be in an infinite retry mode. In this embodiment, the retry control unit includes a timing detection subunit. If the response result is a failure, the retry control unit, through the timing detection subunit, controls the waiting period after a preset retry interval before triggering the main state machine. Further, the retry control unit in this embodiment may also include a retry counter. The retry counter is used to record the number of retries performed by the retry control unit.

[0041] As another possible implementation, the retry control unit in this embodiment can be a limited retry mode. The retry control unit also includes a timing detection subunit and a retry counter. The main state machine is used to trigger the retry counter after transitioning from the write state to the write failure state, incrementing the retry counter by 1. If the response result is a failure response, the retry control unit determines whether the retry counter count is less than the preset number of retries; if the retry counter count is less than the preset number of retries, the retry control unit controls the waiting period after the preset retry interval through the timing detection subunit before triggering the main state machine; if the retry counter count is greater than or equal to the preset number of retries, the retry control unit stops retrying. If the retry counter count is greater than or equal to the preset number of retries, the state management unit receives the retry failure signal sent by the retry calculator and sends the retry failure information to the computation processing unit (CPE).

[0042] In this embodiment, the atomic operation module further includes a configuration unit. The configuration unit receives atomic operation commands sent by the computing processing unit and sends operation data to the operation unit. The operation unit sends execution data to the Network-on-Chip (NOC) according to the operation data. The operation unit triggers the main state machine, causing the main state machine to switch from an idle state to a write state.

[0043] In this embodiment, the configuration unit can confirm the state of the master state machine through a corresponding port. If the master state machine is in a write-success state, the configuration unit sends an execution completion message to the computation processing unit (CPE). After the execution completion message is sent, the configuration unit triggers the master state machine, causing it to transition from the write-success state to the idle state. If the master state machine is not in the idle state, the configuration unit can pressure the upstream CPE to prevent it from receiving new atomic operation commands.

[0044] As one possible implementation, in this embodiment, both the preset retry count and preset retry interval can be set through the initialization configuration of the atomic operation module. The preset retry count is the maximum number of retries allowed after a single atomic operation fails, and the retry interval is the time interval between two retry operations (in system clock cycles). The configuration information including the preset retry interval and preset retry count can be written to a dedicated configuration register in the register group, read by the configuration unit of the atomic operation module, and synchronized to the retry control unit. In this embodiment, the dedicated configuration register can be dynamically modified by software to adapt to the needs of different application scenarios. Thus, the atomic operation retry method provided in this embodiment can match the needs of different application scenarios, offering high flexibility and allowing adjustment of the retry strategy without modifying the hardware logic.

[0045] In this embodiment, the retry control unit may further include a state management unit. If the retry counter count is greater than or equal to a preset number of retries, the state management unit receives a retry failure signal from the retry counter and sends retry failure information to the computation processing unit (CPE). The computation processing unit triggers subsequent exception handling procedures based on the retry failure information. For example, it may temporarily adjust the scheduling priority of the task to low and schedule other high-priority tasks. Thus, the atomic operation retry method provided in this embodiment can effectively improve the debuggability and maintainability of the system.

[0046] As one possible implementation, the response detection unit can also send a response result to the state management unit after receiving the atomic operation response. In this embodiment, the state management unit can update the internally stored abnormal state data based on the response result when the main state machine transitions from the write state to the write failure state.

[0047] In this embodiment, the configuration unit can receive atomic operation commands sent by the computing processing unit and perform address validity checks on the target address in the atomic operation command. If the check passes, the configuration unit sends operation data to the operation unit; if the check fails, the configuration unit sends address error information to the status management unit. The status management unit then feeds back exception information to the computing processing unit based on the address error information. The address validity check in this embodiment can be a 64-bit alignment check on the target address to check whether the target address format conforms to preset regulations. Thus, the atomic operation retry method provided in this embodiment can avoid retries caused by address format issues, improving the overall system throughput and operational reliability.

[0048] In summary, the atomic operation retry method provided in this application addresses the deficiency of existing atomic operations lacking a standardized retry interval after failure. By precisely controlling the retry interval and automatically triggering retry operations, it effectively avoids bus congestion caused by frequent retries while ensuring timely retries, thereby improving overall system throughput and operational reliability. The atomic operation retry method provided in this application also supports dynamic software configuration of preset retries and preset retry intervals to adapt to the needs of different application scenarios, allowing adjustment of the retry strategy without modifying hardware logic. Furthermore, the atomic operation retry method provided in this application also features retry failure exception reporting, status recording, and address validity detection functions, facilitating software troubleshooting and effectively improving system debuggability and maintainability.

[0049] In the description of this specification, references to terms such as "some possible implementations," "some implementations," "example," "specific example," or "some examples" indicate that a specific feature, structure, material, or characteristic described in connection with that implementation or example is included in at least one implementation or example of this application, and the aforementioned terms do not necessarily refer to the same implementation or example. Furthermore, the described specific features, structures, materials, or characteristics can be combined in any suitable manner in one or more implementations or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different implementations or examples described in this specification, as well as the features of different implementations or examples.

[0050] The method flowcharts for embodiments of this application describe certain operations as different steps performed in a certain order. Such flowcharts are illustrative and not restrictive. Some steps described herein may be grouped together and performed in a single operation, or some steps may be divided into multiple sub-steps, and some steps may be performed in an order different from that shown herein. The various steps shown in the flowcharts may be implemented in any way by any circuit structure and / or tangible mechanism (e.g., by software running on a computer device, hardware (e.g., logic functions implemented by a processor or chip), and / or any combination thereof).

[0051] Those skilled in the art will understand that in the methods described in the above specific embodiments, the order in which the steps are written does not imply a strict execution order, and the specific execution order of each step should be determined by its function and possible internal logic.

[0052] Based on the retry method for atomic operations provided in the above embodiments, this application also provides an atomic operation module.

[0053] like Figure 3 As shown, the atomic operation module is applied to the graphics processor. The atomic operation module includes a response detection unit 10, a retry control unit 20, a main state machine 30, and an atomic operation execution unit 40. The response detection unit 10 is used to trigger the main state machine 30 according to the response result of the atomic operation response after receiving the atomic operation response. The main state machine 30 is used to synchronize the response result to the retry control unit 20. If the response result is a failure response, the retry control unit 20 is used to wait for a preset retry interval and then trigger the main state machine 30. The main state machine 30 is used to trigger the atomic operation execution unit 40 after being triggered by the retry control unit 20. The atomic operation execution unit 40 is used to resend execution data to the on-chip network NOC after being triggered by the master state 30.

[0054] In some possible embodiments, the master state machine includes a write state, a write success state, and a write failure state; the master state machine is used to transition from the execution failure state to the write state after being triggered by the retry control unit, and to trigger the atomic operation execution unit after transitioning to the write state; if the response result is a failure response, the response detection unit is used to trigger the master state machine to transition from the write state to the write failure state; if the response result is a success response, the response detection unit is used to trigger the master state machine to transition from the write state to the write success state.

[0055] In some possible embodiments, the retry control unit further includes a timing detection subunit. If the response result is a failure response, the retry control unit is used to control the main state machine to be triggered after waiting for a preset retry interval through the timing detection subunit.

[0056] In some possible embodiments, the retry control unit further includes a timing detection subunit and a retry counter. If the response result is a failure response, the retry control unit is used to determine whether the count of the retry counter is less than the preset number of retries. If the count of the retry counter is less than the preset number of retries, the retry control unit is used to control the main state machine to be triggered after waiting for a preset retry interval through the timing detection subunit. If the count of the retry counter is greater than or equal to the preset number of retries, the retry control unit is used to stop retries.

[0057] In some possible embodiments, the master state machine is used to trigger a retry counter after transitioning from a write state to a write failure state, thereby incrementing the retry counter by 1.

[0058] In some possible embodiments, the retry control unit further includes a status management unit. If the count of the retry counter is greater than or equal to a preset number of retries, the status management unit is used to receive a retry failure signal sent by the retry calculator and send retry failure information to the calculation processing unit CPE.

[0059] In some possible embodiments, the atomic operation module further includes a configuration unit, which receives atomic operation commands sent by the computing processing unit and triggers the main state machine to transition from an idle state to a write state; the configuration unit is used to send operation data to the operation unit according to the atomic operation commands; the operation unit sends execution data to the on-chip network (NOC) according to the operation data.

[0060] In some possible embodiments, the retry control unit further includes a status management unit. The configuration unit is used to receive atomic operation commands sent by the computing processing unit and to perform address validity checks on the target address in the atomic operation commands. If the check passes, the configuration unit is used to send operation data to the operation unit. If the check fails, the configuration unit is used to send address error information to the status management unit. The status management unit feeds back abnormal information to the computing processing unit based on the address error information.

[0061] It should be noted that the atomic operation module in the embodiments of this application can implement the various processes of the aforementioned embodiments of the atomic operation retry method and achieve the same effect and function, which will not be repeated here.

[0062] According to some embodiments of this application, a non-volatile computer storage medium is provided for a retry method of atomic operations, having stored thereon computer-executable instructions configured to be executed when run by a processor: the retry method of atomic operations described in the above embodiments.

[0063] Computer-readable media include permanent and non-permanent, removable and non-removable media, which can store information by any method or technology. Information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer-readable storage media include, but are not limited to, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory, read-only memory, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, CD-ROM, digital versatile optical disc (DVD) or other optical storage, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transfer medium that can be used to store information accessible by a computing device. Furthermore, although the operations of the methods of this application are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in that specific order, or that all the operations shown must be performed to achieve the desired result. Additionally, certain steps may be omitted, multiple steps may be combined into one step, and / or a step may be broken down into multiple sub-steps.

[0064] While the spirit and principles of this application have been described above with reference to several specific embodiments, it should be understood that this application is not limited to the disclosed specific embodiments, and the division of aspects does not imply that features in these aspects cannot be combined. This application is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A method of retrying an atomic operation, the method comprising: The method is applied to an atomic operation module in a graphics processing unit (GPU). The atomic operation module includes a response detection unit, a retry control unit, a main state machine, and an atomic operation execution unit. The method includes: After receiving the atomic operation response, the response detection unit triggers the main state machine based on the response result of the atomic operation response. The main state machine is used to synchronize the response result to the retry control unit. If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine. The main state machine is used to trigger the atomic operation execution unit after being triggered by the retry control unit. The atomic operation execution unit is used to resend execution data to the on-chip network (NOC) after being triggered by the master state machine.

2. The method according to claim 1, characterized in that, The main state machine includes a write state, a write success state, and a write failure state; The master state machine is used to transition from the execution failure state to the write state after being triggered by the retry control unit, and to trigger the atomic operation execution unit after transitioning to the write state; If the response result is a failure response, the response detection unit triggers the main state machine, causing the main state machine to change from the write state to the write failure state; If the response result is a successful response, the response detection unit triggers the main state machine, causing the main state machine to change from the write state to the write success state.

3. The method according to claim 2, characterized in that, The retry control unit further includes a timing detection subunit. If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine, including: If the response result is a failure response, the retry control unit controls the main state machine to wait for a preset retry interval through the timing detection subunit.

4. The method according to claim 2, characterized in that, The retry control unit further includes a timing detection subunit and a retry counter. If the response result is a failure response, the retry control unit waits for a preset retry interval and then triggers the main state machine, including: If the response result is a failure response, the retry control unit determines whether the count of the retry counter is less than the preset number of retries; If the count of the retry counter is less than the preset number of retries, the retry control unit controls the main state machine to be triggered after waiting for the preset retry interval through the timing detection subunit. If the count of the retry counter is greater than or equal to the preset number of retries, the retry control unit stops retrying.

5. The method according to claim 4, characterized in that, The method further includes: The master state machine is used to trigger the retry counter after transitioning from the write state to the write failure state, thereby incrementing the count of the retry counter by 1.

6. The method according to claim 5, characterized in that, The retry control unit further includes a status management unit, and the method further includes: If the count of the retry counter is greater than or equal to the preset number of retries, the status management unit receives the retry failure signal sent by the retry calculator and sends the retry failure information to the calculation processing unit (CPE).

7. The method according to claim 1, characterized in that, The atomic operation module further includes a configuration unit, and the method further includes: The configuration unit receives the atomic operation command sent by the computing processing unit and triggers the main state machine, causing the main state machine to switch from the idle state to the write state. The configuration unit sends operation data to the operation unit according to the atomic operation command; The operation unit sends execution data to the on-chip network (NOC) based on the operation data.

8. The method according to claim 7, characterized in that, The retry control unit further includes a status management unit. The configuration unit receives atomic operation commands sent by the computing processing unit and sends operation data to the operation unit, including: The configuration unit receives atomic operation commands sent by the computing processing unit and performs address validity checks on the target address in the atomic operation commands. If the detection passes, the configuration unit sends operation data to the operation unit; If the detection fails, the configuration unit sends an address error message to the status management unit; The status management unit sends an error message back to the computing and processing unit based on the address error information.

9. An atomic operation module, characterized in that, The atomic operation module is applied to the graphics processor, and the atomic operation module includes a response detection unit, a retry control unit, a main state machine, and an atomic operation execution unit. The response detection unit is used to trigger the main state machine based on the response result of the atomic operation response after receiving the atomic operation response. The main state machine is used to synchronize the response result to the retry control unit. If the response result is a failure response, the retry control unit is used to wait for a preset retry interval and then trigger the main state machine. The main state machine is used to trigger the atomic operation execution unit after being triggered by the retry control unit. The atomic operation execution unit is used to resend execution data to the on-chip network (NOC) after being triggered by the master state machine.

10. A graphics processor, characterized in that, The graphics processor includes the atomic operation module as described in claim 9.

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