Cross isa unified exception and execution context management method and system

Abstract

The disclosure provides a cross-ISA unified exception and execution context management method and system, relating to the technical field of heterogeneous processors. The method comprises: if an exception event is detected during execution of a target task, generating local exception state information; performing unified exception semantic normalization processing on the local exception state information to obtain unified exception description information; based on the unified exception description information and a unified semantic state description format, performing unified abstract coding on the current execution state to generate a UECD; starting a cross-ISA context migration process when it is detected that cross-ISA task migration needs to be performed; reading the unified semantic state data corresponding to the UECD and performing target ISA state reconstruction; after the reconstruction is completed, writing the target execution state into a target execution unit; and after the state recovery is completed, continuing to execute the corresponding target task. The method can solve the technical problems of difficult unified management of exception states and large context switching overhead.

Description

Technical Field

[0001] This disclosure relates to the field of heterogeneous processor technology, and in particular to a method and system for cross-ISA unified exception and execution context management. Background Technology

[0002] In related technologies, with the development of artificial intelligence, high-performance computing, and ultra-heterogeneous computing architectures, processor systems have gradually evolved from traditional homogeneous multi-core architectures to ultra-heterogeneous processor systems composed of various heterogeneous computing units such as general-purpose processors, vector processors, graphics processors, neural network processors, digital signal processors, and dedicated acceleration units. Different heterogeneous computing units typically employ different ISAs (Instruction Set Architectures), execution models, and exception handling mechanisms, thus forming a cross-ISA collaborative execution environment. Different ISAs usually have independent register organization, exception encoding methods, context state structures, and interrupt response mechanisms. This can lead to technical problems such as difficulty in uniformly managing exception states and high context switching overhead during ultra-heterogeneous processor execution. Summary of the Invention

[0003] This disclosure provides a method and system for cross-ISA unified exception and execution context management.

[0004] According to a first aspect of this disclosure, a unified exception and execution context management method across ISAs is provided, comprising: If the heterogeneous execution unit detects an abnormal event during the execution of the target task, it generates local abnormal status information and sends it to the IETB; The IEBTB performs unified exception semantic normalization processing on the local exception status information to obtain unified exception description information and sends it to HCME. The HCME obtains the current execution state and, based on the unified exception description information and the unified semantic state description format, performs unified abstract encoding on the current execution state, generates UECD, and saves it to a dedicated context buffer storage structure. When the HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside the HCME initiates the cross-ISA context migration process; The cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure, and performs target ISA state reconstruction according to the state organization structure corresponding to the target ISA; After the target ISA state reconstruction is completed, the cross-ISA state mapping module writes the target execution state into the target execution unit through the hardware state injection interface, so that the target execution unit performs a recovery operation based on the target execution state; After the target execution unit completes state recovery, it continues to execute the corresponding target task.

[0005] According to a second aspect of this disclosure, a unified exception and execution context management system across ISAs is provided, comprising: Heterogeneous execution units are used to detect abnormal events during the target task, generate local abnormal status information, and send it to the IETB. The IEBTB is connected to the heterogeneous execution unit and is used to receive the local abnormal state information, perform unified abnormal semantic normalization processing on the local abnormal state information, obtain unified abnormal description information, and send it to HCME. The HCME, connected to the IEBTB, is used to obtain the current execution state, and based on the unified exception description information and the unified semantic state description format, to perform unified abstract encoding on the current execution state, generate a UECD, and save it to a dedicated context buffer storage structure; and to detect cross-ISA task migration requirements and initiate cross-ISA context migration process. A dedicated context buffer storage structure, connected to the HCME, is used to cache the UECD; The cross-ISA state mapping module is connected to the HCME and the dedicated context buffer storage structure. It is used to read the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure, and to perform target ISA state reconstruction according to the state organization structure corresponding to the target ISA. It is also used to write the target execution state into the target execution unit through the hardware state injection interface after the target ISA state reconstruction is completed. The target execution unit, connected to the cross-ISA state mapping module, is used to receive the reconstructed target execution state and continue to execute the corresponding target task after the state is restored.

[0006] According to a third aspect of this disclosure, an electronic device is provided, comprising: At least one processor; and, A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0007] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0008] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0009] In this embodiment, if a heterogeneous execution unit detects an abnormal event during the execution of a target task, it generates local abnormal state information and sends it to the IEBTB. The IEBTB performs unified abnormal semantic normalization processing on the local abnormal state information to obtain unified abnormal description information, which is then sent to the HCME. The HCME obtains the current execution state and, based on the unified abnormal description information and the unified semantic state description format, performs unified abstract encoding on the current execution state to generate a UECD and saves it to a dedicated context buffer storage structure. When the HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside the HCME initiates the cross-ISA context migration process. The cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure and performs target ISA state reconstruction according to the state organization structure corresponding to the target ISA. After completing the target ISA state reconstruction, the cross-ISA state mapping module writes the target execution state into the target execution unit through a hardware state injection interface, so that the target execution unit performs a recovery operation based on the target execution state. After completing the state recovery, the target execution unit continues to execute the corresponding target task. In this way, by constructing a unified exception semantic abstraction mechanism, a unified execution context description structure, and a cross-ISA state reconstruction mechanism, unified normalized management of exception states across different ISAs, unified maintenance of execution contexts, and unified state recovery during cross-ISA task migration can be achieved. This solves the technical problems of difficult unified management of exception states, high context switching overhead, difficulty in cross-ISA task migration, and poor consistency of exception recovery during the execution of heterogeneous processors. Furthermore, it can reduce cross-ISA context switching overhead, reduce state saving redundancy, improve exception recovery consistency, achieve decoupled management between execution states of different ISAs, and enhance the efficiency of cross-ISA collaborative execution and system scalability in heterogeneous processor systems.

[0010] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0011] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein: Figure 1 A flowchart illustrating a cross-ISA unified exception and execution context management method provided in this embodiment of the disclosure; Figure 2 A schematic diagram of the structure of a cross-ISA unified exception and execution context management system provided in this embodiment of the disclosure; Figure 3 A schematic diagram of the overall structure of a cross-ISA unified exception and execution context management system for heterogeneous processors provided in this disclosure embodiment; Figure 4 This is a schematic diagram of the internal structure of an HCME provided in an embodiment of the present disclosure; Figure 5 This is a schematic diagram of a cross-ISA state reconstruction structure provided in an embodiment of the present disclosure; Figure 6 A flowchart illustrating another cross-ISA unified exception and execution context management method provided in this disclosure embodiment; Figure 7 A schematic diagram of a dynamic context saving and compression process provided in this embodiment of the disclosure; Figure 8 This is a timing diagram illustrating a cross-ISA task migration and anomaly recovery process provided in an embodiment of this disclosure. Detailed Implementation

[0012] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0013] As the background technology shows, with the development of artificial intelligence, high-performance computing, and ultra-heterogeneous computing architectures, processor systems have gradually evolved from traditional homogeneous multi-core architectures to ultra-heterogeneous processor systems composed of various heterogeneous computing units such as general-purpose processors, vector processors, graphics processors, neural network processors, digital signal processors, and dedicated acceleration units. Different heterogeneous computing units typically employ different instruction set architectures (ISAs), execution models, and exception handling mechanisms, thereby forming a cross-ISA collaborative execution environment.

[0014] In related technologies, different ISAs typically have independent register organization, exception encoding methods, context state structures, and interrupt response mechanisms. For example, general-purpose processors usually employ privilege-level-based software exception handling mechanisms, vector processors typically include variable-length vector register states, while neural network processors or tensor acceleration units typically employ dedicated task queues, hardware state descriptors, and asynchronous execution models. Due to the lack of a unified exception semantic description and execution context abstraction mechanism among different ISAs, problems such as difficulty in unified management of exception states, high context switching overhead, difficulty in cross-ISA task migration, and poor exception recovery consistency easily arise during the execution of heterogeneous processors. Furthermore, when tasks migrate or co-execute between different heterogeneous execution units, independent state saving and restoration operations are usually required for each ISA. Because the register state size, execution semantics, and exception state definitions of different ISAs vary significantly, the system is prone to redundant state saving, loss of exception states, or inconsistent restoration during execution context switching, thus affecting system execution efficiency and operational reliability. In addition, exception handling mechanisms in heterogeneous processor systems are mostly designed for independent single ISAs, lacking a unified exception normalization processing capability for cross-ISA collaborative execution scenarios. When different heterogeneous execution units generate abnormal events during joint execution, the system has difficulty in uniformly parsing, scheduling, and recovering abnormal information generated by different ISAs. This can easily lead to complex abnormal propagation links, difficult system debugging, and low efficiency in cross-execution unit error recovery.

[0015] For example, a heterogeneous processor system typically consists of a central processing unit (CPU), a graphics processing unit (GPU), a vector processor, a neural network processor (NPU), a digital signal processor (DSP), and other dedicated acceleration units. Different heterogeneous execution units employ independent instruction set architectures, execution state organization methods, and exception handling mechanisms, and achieve collaborative execution through the operating system, drivers, or runtime framework. In related technologies, task scheduling for heterogeneous execution units typically adopts a unified management approach by the main control processor. As an example, the operating system runtime first receives the tasks to be executed and distributes the target tasks to the corresponding heterogeneous execution units for execution based on task type, computational characteristics, or hardware resource status. During task execution, each heterogeneous execution unit maintains its own corresponding execution context information, including the program counter, control status register, general-purpose register status, vector register status, task descriptor, and local cache status. When task switching, interrupt responses, or exception events occur in heterogeneous execution units, existing technologies typically employ context saving and restoration mechanisms designed independently for each ISA. Taking a general-purpose processor as an example, the system typically saves the program counter, privileged status register, and general-purpose register states after an exception is triggered. For vector processors or neural network processors, the corresponding vector register sets, matrix state information, task queue states, or dedicated control register states are saved respectively. Different execution instances (ISAs) usually employ independent exception entry points, state management structures, and recovery procedures. Furthermore, when a task needs to migrate between different heterogeneous execution units, the system typically reads the context states of different execution units through software drivers or runtime frameworks and remaps the target task to the new execution unit for execution. In this process, each heterogeneous execution unit typically uses its own independently defined state description structure and exception encoding mechanism. For example, different ISAs may use different exception numbering systems, different granularity state saving mechanisms, and different interrupt response modes, resulting in the need to execute multiple sets of state parsing and transition processes during cross-ISA task migration. In addition, exception handling mechanisms are usually implemented independently for a single ISA. When a heterogeneous execution unit generates an exception event, the exception handling module of the corresponding ISA completes exception capture, exception state recording, and exception recovery operations respectively. For cross-ISA collaborative execution scenarios, the system typically relies on the software layer to handle exceptions generated by different ISAs separately, and uses drivers or runtime frameworks to forward and synchronize exception information.

[0016] While the above implementation methods can achieve basic heterogeneous computing functions, the lack of a unified exception semantic abstraction and a unified execution context management mechanism between different ISAs makes it easy to encounter problems such as complex exception handling paths, large context switching overhead, high redundancy of state saving, and poor consistency of exception recovery in cross-ISA collaborative execution scenarios. These problems make it difficult to meet the requirements of efficient cross-ISA collaborative execution in ultra-heterogeneous processor systems.

[0017] Based on this, the cross-ISA unified exception and execution context management method provided in this disclosure can achieve unified and normalized management of exception states across different ISAs, unified maintenance of execution contexts, and unified state recovery during cross-ISA task migration by constructing a unified exception semantic abstraction mechanism, a unified execution context description structure, and a cross-ISA state reconstruction mechanism. This solves the technical problems of difficult unified management of exception states, high context switching overhead, difficulties in cross-ISA task migration, and poor consistency in exception recovery during the execution of heterogeneous processors. Thus, it can reduce cross-ISA context switching overhead, reduce state saving redundancy, improve exception recovery consistency, achieve decoupled management between execution states of different ISAs, and improve cross-ISA collaborative execution efficiency and system scalability in heterogeneous processor systems.

[0018] The following describes a cross-ISA unified exception and execution context management method and system according to embodiments of the present disclosure with reference to the accompanying drawings.

[0019] Figure 1 This is a flowchart illustrating a cross-ISA unified exception and execution context management method provided in an embodiment of this disclosure. Figure 1 As shown, the method includes the following steps: Step 101: If the heterogeneous execution unit detects an abnormal event during the execution of the target task, it generates local abnormal status information and sends it to the IETB.

[0020] In this embodiment, the heterogeneous execution units include CPUs, GPUs, NPUs, DSPs, vector processors, dedicated AI acceleration units, etc. Different heterogeneous execution units can employ different instruction set architectures and different register organization methods. During task execution, when any heterogeneous execution unit detects an abnormal event, the corresponding heterogeneous execution unit generates local abnormal status information. For example, abnormal events include at least one of page faults, memory access out-of-bounds faults, vector execution faults, synchronization execution faults, resource conflict faults, tensor computation faults, hardware failure faults, and task timeout faults. The local abnormal status information includes a local fault number, fault source information, fault execution location, ISA status identifier, fault priority information, and fault context index information. Each heterogeneous execution unit that detects an abnormal event can send the generated local abnormal status information to the IEBTB (Interconnect Exception Translation Bridge).

[0021] Step 102: IEBTB performs unified exception semantic normalization processing on the local exception status information to obtain unified exception description information and sends it to HCME.

[0022] In this embodiment of the disclosure, after receiving local exception status information sent by each heterogeneous execution unit that detected an exception, the IEBTB can perform unified exception semantic normalization processing on each local exception status information to obtain unified exception description information and send it to the HCME (Hardware Context Management Engine). For example, after receiving local exception status information, the IEBTB can perform unified exception semantic normalization processing on the exception status corresponding to different ISAs. For example, the IEBTB can maintain a unified exception mapping table internally, which can establish a correspondence between exception numbers of different ISAs and unified exception semantic types. Based on the unified exception mapping table, unified exception description information is determined and sent to the HCME.

[0023] Step 103: Based on the unified exception description information and the unified semantic state description format, HCME performs unified abstract encoding on the current execution state, generates UECD, and saves it.

[0024] The UECD includes at least one of the following: general state information, ISA type identification information, abnormal state information, execution control state information, vector semantic state information, tensor computation semantic state information, storage access semantic state information, dedicated acceleration state information, state validity bit information, and state compression description information.

[0025] In this embodiment, after receiving unified exception description information, HCME can perform unified abstract encoding on the execution state corresponding to the current task based on the unified exception description information and the unified semantic state description format to generate a UECD (Unified Execution Context Descriptor). For example, the UECD includes at least one of the following: general state information, ISA type identification information, exception state information, execution control state information, vector semantic state information, tensor computation semantic state information, storage access semantic state information, dedicated acceleration state information, state validity bit information, and state compression description information. Specifically, the vector semantic state information describes the vector length, the range of valid vector elements, and the vector computation semantics; the tensor computation semantic state information describes the tensor dimension, matrix operation state, and tensor execution control state. The generated UECD can be stored in a dedicated context buffer storage structure.

[0026] Step 104: When HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside HCME starts the cross-ISA context migration process.

[0027] In this embodiment of the disclosure, when HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside HCME initiates the cross-ISA context migration process. The conditions that trigger cross-ISA migration include at least one of the following: a hardware failure occurs in the current execution unit, the current execution unit has insufficient computing resources, the previous execution unit has excessive load, the current task needs to switch to the target acceleration unit, the system performs heterogeneous load balancing scheduling, and the current execution unit enters a low-power mode.

[0028] Step 105: The cross-ISA state mapping module reads the unified semantic state data corresponding to UECD and performs target ISA state reconstruction.

[0029] In this embodiment of the disclosure, after initiating the cross-ISA context migration process, the cross-ISA state mapping module can read the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure and perform target ISA state reconstruction. For example, the cross-ISA state mapping module can first parse the unified semantic state fields in the UECD. These unified semantic state fields include, but are not limited to, general state information, ISA type identification information, abnormal state information, execution control state information, vector semantic state information, tensor computation semantic state information, storage access semantic state information, and dedicated acceleration state information. Subsequently, the state renaming logic within the cross-ISA state mapping module establishes the correspondence between the unified semantic state fields and the target ISA state fields. Afterwards, the target ISA state reconstruction control logic performs target state reconstruction on the unified semantic state data according to the register width, state field layout, and execution state organization form corresponding to the target ISA.

[0030] Step 106: After completing the target ISA state reconstruction, the cross-ISA state mapping module writes the target execution state into the target execution unit through the hardware state injection interface, so that the target execution unit can perform recovery operations based on the target execution state.

[0031] In some possible implementations, after the target ISA state reconstruction is completed, the cross-ISA state mapping module writes the target execution state into the target execution unit through a hardware state injection interface, including: After completing the target ISA state reconstruction, the cross-ISA state mapping module writes at least one of the reconstructed general state, vector semantic state, tensor computation semantic state, and anomaly recovery semantic state into at least one of the hardware registers, control state registers, vector registers, tensor state buffers, and acceleration state buffer structures corresponding to the target execution unit through the hardware state injection interface.

[0032] In this embodiment of the disclosure, after the target ISA state reconstruction is completed, the cross-ISA state mapping module can write the target execution state into the target execution unit through a hardware state injection interface. For example, after receiving a recovery control signal sent by the exception recovery control logic, the hardware state injection interface can inject the reconstructed target execution state data into the target execution unit. The target execution state is written to at least one of the following: a general-purpose register, a control state register, a vector register, a tensor state buffer, or an accelerated state buffer structure. After the cross-ISA state mapping module writes the target execution state into the target execution unit through the hardware state injection interface, the target execution unit can perform corresponding recovery operations based on the recovered target execution state. Recovery operations include at least one of exception retry, state rollback, task migration, degraded execution, and cross-execution unit recovery. The target execution unit refers to the heterogeneous execution unit selected by the system scheduler during the cross-ISA context migration process to take over and continue executing the target task. The target execution unit and the source heterogeneous execution unit, which serves as the original execution carrier of the task, belong to the same set of heterogeneous execution units in the system, but they play different roles at different stages of task execution. For example, when the first heterogeneous execution unit fails to complete the exception recovery, HCME triggers a task migration process to migrate the target task to the second heterogeneous execution unit and restore the target task's execution state in the second heterogeneous execution unit to continue executing the target task. After the target execution state injection is completed, the target execution unit generates a recovery completion status signal and feeds it back to HCME to indicate that the current cross-ISA recovery process is complete.

[0033] Step 107: After the target execution unit completes the state recovery, it continues to execute the corresponding target task.

[0034] In this embodiment of the disclosure, after completing state recovery, the target execution unit can continue to execute the corresponding target task. For example, after receiving target execution state data from the hardware state injection interface and completing register state writing, the target execution unit can restore the complete execution context required for task execution based on the restored general-purpose register state, control state register state, vector register state, tensor state buffer state, and acceleration state buffer structure state. Subsequently, the target execution unit can continue to execute the target task from the recovery entry point determined by the recovery operation.

[0035] In this embodiment, if a heterogeneous execution unit detects an abnormal event during the execution of a target task, it generates local abnormal state information and sends it to the IEBTB. The IEBTB performs unified abnormal semantic normalization processing on the local abnormal state information to obtain unified abnormal description information, which is then sent to the HCME. The HCME obtains the current execution state and, based on the unified abnormal description information and the unified semantic state description format, performs unified abstract encoding on the current execution state to generate a UECD and saves it to a dedicated context buffer storage structure. When the HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside the HCME initiates the cross-ISA context migration process. The cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure and performs target ISA state reconstruction according to the state organization structure corresponding to the target ISA. After completing the target ISA state reconstruction, the cross-ISA state mapping module writes the target execution state into the target execution unit through a hardware state injection interface, so that the target execution unit performs a recovery operation based on the target execution state. After completing the state recovery, the target execution unit continues to execute the corresponding target task. In this way, by constructing a unified exception semantic abstraction mechanism, a unified execution context description structure, and a cross-ISA state reconstruction mechanism, unified normalized management of exception states across different ISAs, unified maintenance of execution contexts, and unified state recovery during cross-ISA task migration can be achieved. This solves the technical problems of difficult unified management of exception states, high context switching overhead, difficulty in cross-ISA task migration, and poor consistency of exception recovery during the execution of heterogeneous processors. Furthermore, it can reduce cross-ISA context switching overhead, reduce state saving redundancy, improve exception recovery consistency, achieve decoupled management between execution states of different ISAs, and enhance the efficiency of cross-ISA collaborative execution and system scalability in heterogeneous processor systems.

[0036] In some possible implementations, the IEBTB performs unified exception semantic normalization processing on the local exception state information to obtain unified exception description information and sends it to the HCME, including: Based on the unified anomaly mapping table, a correspondence is established between local anomaly numbers of different ISAs and unified anomaly semantic types to obtain unified anomaly description information; wherein, the unified anomaly description information includes at least one of unified anomaly type, unified anomaly level, anomaly recovery mode, associated context identifier and anomaly propagation target information; Send the unified exception description information to HCME.

[0037] In this embodiment, when the IETB performs unified exception semantic normalization on local exception status information to obtain unified exception description information and sends it to the HCME, it can first maintain a unified exception mapping table internally. This unified exception mapping table can establish a correspondence between local exception numbers of different ISAs and unified exception semantic types. The IETB can find the corresponding exception mapping item in the correspondence between local exception numbers of different ISAs and unified exception semantic types based on the ISA type corresponding to the current exception, and generate unified exception semantics. For example, the mapping rules of the unified exception mapping table include at least one of the following: CPU page exceptions are mapped to memory access exception categories; vector execution exceptions are mapped to execution exception categories; NPU task exceptions are mapped to synchronization exception categories; and DSP memory access out-of-bounds exceptions are mapped to resource exception categories. After completing the unified exception semantic normalization, the IETB can generate unified exception description information. The unified exception description information includes at least one of the following: unified exception type (representing the normalized exception semantic category for cross-ISA exception identification), unified exception level (representing the severity or processing priority of the exception), exception recovery mode (indicating the processing strategy adopted for subsequent exception recovery), associated context identifier (used to associate the task execution context corresponding to the current exception), and exception propagation target information (indicating the target module or target execution unit for exception handling or context migration). Then, the IEBB can send the generated unified exception description information to the HCME through the on-chip interconnect structure to trigger the HCME to start the context saving state machine, providing a basis for subsequent generation of the unified execution context descriptor (UECD) and execution dynamic context saving and state compression. Thus, by implementing a normalized mapping from local exception numbers of different ISAs to unified exception semantic types through a unified exception mapping table, the processing barriers caused by the heterogeneity of exception semantics between different ISAs can be eliminated. This allows the subsequent context management module to uniformly handle various exception events in an ISA-independent manner, improving the consistency and scalability of exception handling and reducing the implementation complexity of cross-ISA exception recovery.

[0038] In some possible implementations, HCME acquires the current execution state and, based on unified exception description information and a unified semantic state description format, performs unified abstract encoding on the current execution state, generates a UECD, and saves it to a dedicated context buffer storage structure, including: HCME reads the state validity bit information inside the heterogeneous execution unit and performs state trimming based on the state validity bit information to determine the target state set; HCME uses a set of target states and a unified semantic state description format to perform unified abstract encoding on the current execution state and generate UECD; Save UECD to a dedicated context buffer storage structure.

[0039] In this embodiment, when HCME performs unified abstract encoding on the current execution state based on unified anomaly description information and unified semantic state description format to generate and save UECD, HCME can first obtain the target ISA type and target execution unit identifier corresponding to the current task to determine the source and encoding format benchmark of the execution state to be saved. HCME can also read the state validity bit information or state dirty bit register inside each heterogeneous execution unit, and perform state pruning according to the state validity bit information to remove inactive execution states, thereby determining the target state set. Among them, the state pruning rules include not saving vector state when the current task does not use vector execution resources; not saving tensor state when the current task does not call tensor execution unit; and not saving at least one of the corresponding acceleration states when the dedicated acceleration unit is in an idle state. HCME can also perform unified abstract encoding on the execution state corresponding to the current task based on the target state set determined after state pruning and the unified semantic state description format to generate UECD. UECD includes at least one of the following: general state information (describing general registers and basic control states), ISA type identification information (identifying the source ISA type corresponding to the current execution state), exception state information (describing state data related to the current exception), execution control state information (describing execution control-related states such as program counter and status register), vector semantic state information (describing vector length, range of valid vector elements, and vector computation semantics), tensor computation semantic state information (describing tensor dimension, matrix operation state, and tensor execution control state), storage access semantic state information (describing storage access-related states), dedicated acceleration state information (describing the state of dedicated hardware such as dedicated AI acceleration units), state validity bit information (identifying the validity of each state field), and state compression description information (describing relevant parameters for subsequent state compression processing).

[0040] Furthermore, the HCME's internal hardware compression coding circuitry can also perform state compression processing on the target state set. This state compression processing includes at least one of the following: zero-value state compression (a zero-value detection circuit detects zero-value states in the data stream and records only non-zero state data), sparse state compression (compressing and encoding sparsely distributed state data), differential state encoding (a differential encoding circuit generates differential data corresponding to the current state based on historical context states), segmented state encoding (encoding state data in segments), and state increment saving (saving only incremental changes relative to historical states). Afterward, the HCME can save the generated UECD to a dedicated context buffer storage structure for subsequent use by the cross-ISA state mapping module in the cross-ISA context migration process. Thus, dynamic state pruning driven by valid state bit information can effectively eliminate inactive execution states, significantly reducing state storage redundancy; abstracting and encoding heterogeneous ISA states through a unified semantic state description format can achieve cross-ISA state decoupling, enabling the same UECD to adapt to the state reconstruction requirements of different target ISAs; combining hardware compression coding circuitry to perform multi-mode state compression on the target state set can reduce context storage overhead and transmission bandwidth usage, improving the efficiency of cross-ISA context switching in ultra-heterogeneous processor systems.

[0041] In some possible implementations, when HCME detects that a cross-ISA task migration is required, the cross-ISA context migration controller within HCME initiates the cross-ISA context migration process, including: When HCME detects at least one of the following: hardware anomaly in the current execution unit, insufficient computing resources, excessive load, task need to be switched to the target acceleration unit, system performs heterogeneous load balancing scheduling, or the current execution unit enters a low-power mode, the cross-ISA context migration controller inside HCME initiates the cross-ISA context migration process.

[0042] In this embodiment of the disclosure, when HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside HCME initiates the cross-ISA context migration process. HCME detects the triggering conditions for cross-ISA task migration through at least one of the following methods: hardware anomaly detection (monitoring whether a hardware failure occurs in the current execution unit; when a hardware anomaly is detected and the current execution unit cannot complete local anomaly recovery, cross-ISA task migration is triggered); computing resource assessment (assessing the available computing resources of the current execution unit; when insufficient computing resources are detected and the target task's computational requirements cannot be met, cross-ISA task migration is triggered); load status monitoring (monitoring the real-time load level of the current execution unit; when...). When excessive load is detected, exceeding the preset load threshold, cross-ISA task migration is triggered; Task acceleration requirement determination (determining whether the current task needs to switch to the target acceleration unit to obtain higher execution efficiency or lower energy consumption, and triggering cross-ISA task migration when it is determined that a switch is required); Heterogeneous load balancing scheduling (responding to the heterogeneous load balancing scheduling strategy at the system level, and triggering cross-ISA task migration when the system determines that migrating the current task to other execution units is beneficial to overall load balancing); Low-power mode switching (monitoring whether the current execution unit has entered low-power mode, and triggering cross-ISA task migration when it is detected that the current execution unit is about to enter or has already entered low-power mode and can no longer guarantee the normal execution of the target task).

[0043] The aforementioned triggering conditions can trigger cross-ISA task migration individually or in combination. When HCME detects that at least one of the above triggering conditions is met, the cross-ISA context migration controller within HCME initiates the cross-ISA context migration process. For example, the cross-ISA context migration controller sends a control signal to the cross-ISA state mapping module to trigger the cross-ISA state mapping module to read the corresponding UECD data from the dedicated context buffer storage structure and execute the subsequent target ISA state reconstruction process. In this way, through HCME's unified monitoring and intelligent judgment of various system operating states, the triggering conditions for cross-ISA task migration can be diversified and flexible. This allows the system to dynamically decide the timing of task migration based on multiple dimensions such as hardware anomalies, resource constraints, load balancing, acceleration requirements, and power management. This can effectively improve the resource utilization, task execution efficiency, and energy efficiency ratio of the heterogeneous processor system, while also enhancing the system's fault tolerance and reliability in abnormal scenarios.

[0044] In some possible implementations, the cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from a dedicated context buffer storage structure, and performs target ISA state reconstruction according to the state organization structure corresponding to the target ISA, including: The cross-ISA state mapping module reads and parses the unified semantic state fields in UECD from a dedicated context buffer storage structure; Establish a correspondence between unified semantic status fields and target ISA status fields; Reconstruct the execution target ISA state based on at least one of the following: register width of the target execution unit, status field layout, and execution state organization.

[0045] In this embodiment, after receiving a control signal from the cross-ISA context migration controller, the cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure and performs target ISA state reconstruction based on the ISA characteristics of the target execution unit. For example, the cross-ISA state mapping module can respond to the control signal sent by the cross-ISA context migration controller and read the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure. The cross-ISA state mapping module can parse the UECD and extract the unified semantic state fields therein. The unified semantic state fields include at least one of the following: general state information, ISA type identification information, abnormal state information, execution control state information, vector semantic state information, tensor computation semantic state information, storage access semantic state information, dedicated acceleration state information, state validity bit information, and state compression description information. Then, the state renaming logic inside the cross-ISA state mapping module can establish a correspondence between the unified semantic state fields and the target ISA state fields. This correspondence is determined based on the correspondence rules between the abstract semantics defined in the unified semantic state description format and the specific hardware state of the target ISA, rather than based on the direct register mapping between the source ISA and the target ISA. For example, the correspondence includes at least one of the following: mapping the vector semantic state to the vector execution state corresponding to the target ISA; mapping some general control states to the target ISA specific control states; and mapping the unified anomaly recovery state to the target ISA anomaly recovery entry.

[0046] Subsequently, the target ISA state reconstruction control logic within the cross-ISA state mapping module can perform target ISA state reconstruction on the unified semantic state data based on the ISA characteristics of the target execution unit. The target ISA state reconstruction is performed based on at least one of the following ISA characteristic parameters of the target execution unit: register width (based on the data bit width of the target ISA's general-purpose registers, vector registers, control registers, etc., bit width adaptation and data truncation or expansion processing are performed on the unified semantic state data), state field layout (based on the register organization form, state field arrangement order and address mapping rules of the target ISA, field rearrangement and address mapping are performed on the unified semantic state data), and execution state organization form (based on the execution unit structure, pipeline state organization method and acceleration unit interface specification of the target ISA, structure reorganization and interface adaptation are performed on the unified semantic state data).

[0047] In some possible implementations, performing target ISA state reconstruction also includes: Physical path reconstruction is performed on the target state data using the MUX path reconstruction array.

[0048] In this embodiment of the disclosure, the MUX (Multiple-Use Selector) path reconfiguration array in the cross-ISA state mapping module can perform physical path reconfiguration on the target state data after the target ISA state reconstruction, generating target execution state data suitable for the target ISA. The MUX path reconfiguration array dynamically configures and reconfigures the transmission paths of the state data according to the physical data path width, number of paths, and connection topology of the target ISA. For example, the MUX path reconfiguration array receives state reconstruction output data from the target ISA state reconstruction control logic and performs at least one of the following physical path reconfiguration operations: Bit-width adaptation and reassembly: Based on the data bus bit width of the target execution unit, the status data is split or merged and reassembled. For example, when the vector register bit width of the source ISA is 512 bits and the vector register bit width of the target ISA is 256 bits, the 512-bit status data is split into two 256-bit data packets and transmitted through two physical paths respectively; Path number configuration: Based on the number of register groups and parallel access ports of the target execution unit, the number of MUX gated paths is dynamically configured to realize parallel or serial transmission of multiple status data; Data alignment adjustment: Based on the storage access alignment requirements of the target execution unit, the status data is adjusted for byte alignment or word alignment and transmitted through the reassembled physical path; Connection topology mapping: Based on the physical layout of the hardware registers of the target execution unit and the interface topology of the acceleration unit, the status data is routed to the corresponding physical target port. After physical path reassembly by the MUX path reassembly array, target execution status data that is completely matched with the hardware interface of the target execution unit is generated. The target execution status data can be directly recognized by the subsequent hardware status injection interface and written into the corresponding hardware register of the target execution unit without additional software layer format conversion.

[0049] In some possible implementations, after the target execution unit completes state recovery, it continues to execute the corresponding target task, including: After the target execution unit performs at least one recovery operation based on the recovered target execution state, such as abnormal retry, state rollback, task migration, degraded execution, or cross-execution unit recovery, it continues to execute the corresponding target task.

[0050] In this embodiment of the disclosure, after the target execution unit receives and writes the target execution state through the hardware state injection interface and performs corresponding recovery operations based on the recovered target execution state, it can continue to execute the corresponding target task from the recovery entry point to ensure the continuity of task execution. For example, the target execution unit performs at least one of the following recovery operations based on the recovered target execution state: Exception Retry: When the exception recovery mode in the unified exception description information indicates exception retry, the target execution unit re-executes the target task from the instruction address before the exception occurred or a preset retry entry point. In one embodiment, the target execution unit locates the location of the exception instruction and performs a retry based on the program counter value and exception status information in the recovered execution control status information. State Rollback: When the exception recovery mode indicates state rollback, the target execution unit restores the execution state to the historical checkpoint state before the exception occurred and continues to execute the target task from the instruction address corresponding to the checkpoint. Task Migration: When the recovery operation is task migration, the target execution unit, as the receiving execution unit after migration, continues to execute the target task from the migration breakpoint. In one embodiment, when the first heterogeneous execution unit cannot complete exception recovery, HCME triggers a task migration process, migrating the target task to the second heterogeneous execution unit (i.e., the target execution unit), and the target execution unit restores the execution state of the target task within it and continues execution. Degraded Execution: When the recovery mode indicates degraded execution, the target execution unit continues to execute the target task in a degraded resource mode or precision mode. In one embodiment, degraded execution includes at least one of reducing vector operation precision, reducing the number of parallel execution threads, and switching to a low-power execution mode. Cross-execution unit recovery: When a target task requires coordinated recovery across different types of execution units, the target execution unit collaborates with other heterogeneous execution units in the system to complete state recovery and continues to execute the portion of the target task that is undertaken by this unit.

[0051] Understandably, after the target execution state injection is complete and the recovery operation is ready, the target execution unit generates a recovery completion status signal and feeds it back to the HCME to indicate that the current cross-ISA recovery process is complete. The recovery completion status signal may include at least one of the following: recovery operation type identifier, recovery entry address, and status validity confirmation information. After completing the above recovery operation, the target execution unit continues to execute the corresponding target task based on the recovered complete execution context. The starting point for continued execution is jointly determined by the recovery operation type and the recovered execution control state information. For example: when retrying due to execution exception, execution continues from the address of the exception instruction or its preceding instruction; when the execution state is rolled back, execution continues from the instruction address corresponding to the checkpoint; when the execution task is migrated, execution continues from the migration breakpoint address; when execution is downgraded, execution continues from the current instruction address in downgraded mode. During the continued execution process, the target execution unit recovers the vector length and the range of valid vector elements based on the vector semantic state information stored in the UECD, or recovers the tensor dimension and matrix operation state based on the tensor calculation semantic state information, to ensure that the execution behavior of the target task after migration remains consistent with that before migration.

[0052] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method.

[0053] Based on the same inventive concept, embodiments of this disclosure also provide a cross-ISA unified exception and execution context management system, such as... Figure 2 As shown, it includes: Heterogeneous execution units are used to detect abnormal events during the target task, generate local abnormal status information, and send it to the IETB. The IEBTB is connected to the heterogeneous execution unit and is used to receive the local abnormal state information, perform unified abnormal semantic normalization processing on the local abnormal state information, obtain unified abnormal description information, and send it to HCME. The HCME, connected to the IEBTB, is used to obtain the current execution state, and based on the unified exception description information and the unified semantic state description format, to perform unified abstract encoding on the current execution state, generate a UECD, and save it to a dedicated context buffer storage structure; and to detect cross-ISA task migration requirements and initiate cross-ISA context migration process. A dedicated context buffer storage structure, connected to the HCME, is used to cache the UECD; The cross-ISA state mapping module is connected to the HCME and the dedicated context buffer storage structure. It is used to read the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure, and to perform target ISA state reconstruction according to the state organization structure corresponding to the target ISA. It is also used to write the target execution state into the target execution unit through the hardware state injection interface after the target ISA state reconstruction is completed. The target execution unit, connected to the cross-ISA state mapping module, is used to receive the reconstructed target execution state and continue to execute the corresponding target task after the state is restored.

[0054] The target execution unit is the target heterogeneous execution unit among the heterogeneous execution units, which is dynamically determined by HCME according to task migration requirements and is used to receive the target execution state after reconstruction by the cross-ISA state mapping module.

[0055] It should be noted that the descriptions of the features in the corresponding embodiments of the cross-ISA unified exception and execution context management system can be found in the relevant descriptions of the corresponding embodiments of the cross-ISA unified exception and execution context management method, and will not be repeated here.

[0056] To make the methods provided in this disclosure clearer, the following examples will be used for illustration.

[0057] This disclosure provides a method and system for unified exception and execution context management across ISAs for heterogeneous processors. By constructing a unified exception semantic abstraction mechanism, a unified execution context description structure, and a cross-ISA state reconstruction mechanism, it achieves unified management of exception states across different heterogeneous instruction set architectures (ISAs), unified switching of execution contexts, and unified state recovery during cross-ISA task migration. This disclosure is applicable to heterogeneous processor systems composed of multiple heterogeneous execution units. The heterogeneous processor system can be a system-on-a-chip (SoC), a chiplet system, or other heterogeneous computing systems. Heterogeneous execution units include, but are not limited to, central processing units (CPUs), vector processors, graphics processing units (GPUs), neural network processors (NPUs), digital signal processors (DSPs), and dedicated acceleration units. Different heterogeneous execution units can employ different instruction set architectures and different physical register organization forms.

[0058] I. System Architecture.

[0059] In one embodiment, the cross-ISA unified exception and execution context management system for heterogeneous processors mainly includes: Heterogeneous Execution Units (HEUs); Interconnect Exception Translation Bridge (IETB); Hardware Context Management Engine (HCME); Dedicated context buffer storage structure; Cross-ISA state mapping module.

[0060] The heterogeneous execution unit (IETB) executes the target task under the corresponding ISA architecture and generates local exception states and local execution states. The on-chip interconnect exception translation bridge (IETB) is deployed at the on-chip interconnect structure, cache-coherent interconnect structure, or heterogeneous execution unit interconnect nodes. It performs unified exception semantic normalization processing on local exception information corresponding to different ISAs at the hardware layer. The hardware context management engine (HCME) is an independent hardware control module used to uniformly generate, maintain, and switch cross-ISA execution contexts. The dedicated context buffer storage structure consists of an on-chip independent dedicated SRAM (static random access memory) array and a context register cache structure, used to cache the normalized unified execution context data.

[0061] In one embodiment, a dedicated SRAM (Static Random-Access Memory) array is used to store large-scale context state data, and a context register cache structure is used to cache the current active context state. A cross-ISA state mapping module is used to establish the correspondence between a unified semantic state and the execution state of the target ISA, and to complete cross-ISA state reconstruction and context recovery.

[0062] II. Unified execution context descriptor construction mechanism.

[0063] During task execution, HCME can obtain the target ISA type and target execution unit identifier corresponding to the current task, and based on the state description information corresponding to the target ISA, perform unified abstraction of the current execution state to generate a Unified Execution Context Descriptor (UECD). The ISA state description information includes: register state structure; exception state structure; execution control state structure; memory access state structure; and acceleration unit state structure.

[0064] In one embodiment, UECD does not mirror and save the physical registers of the source ISA one by one. Instead, it abstracts and encodes the execution states in different ISAs based on a unified semantic state description format to achieve state decoupling and unified recovery across ISAs. Specifically, UECD includes at least one of the following: 1. General state information; 2. ISA type identification information; 3. Abnormal state information; 4. Execution control state information; 5. Vector semantic state information; 6. Tensor computation semantic state information; 7. Storage access semantic state information; 8. Dedicated acceleration state information; 9. State validity bit information; 10. State compression description information.

[0065] Among them: general state information is used to describe the basic general computation state; vector semantic state information is used to describe the vector length, the range of valid vector elements, and the semantics of vector computation; tensor computation semantic state information is used to describe the tensor dimension, matrix operation state, and tensor execution control state; state validity bit information is used to identify whether the corresponding state field is valid; and state compression description information is used to indicate the state compression encoding method used in the current context.

[0066] In one embodiment, the UECD is stored in an on-chip dedicated context buffer storage structure and is maintained uniformly by HCME.

[0067] III. Unified anomaly normalization handling mechanism.

[0068] During task execution, when any heterogeneous execution unit generates an exception event, the corresponding execution unit first generates local exception status information. This local exception status information includes: local exception number; exception source information; exception execution location; ISA status identifier; exception priority information; and exception context index information.

[0069] In one embodiment, the IETB monitors the abnormal status signaling issued by heterogeneous execution units in real time at the hardware layer, and performs unified abnormal semantic normalization processing on the local abnormal status corresponding to different ISAs.

[0070] Specifically, the IEBTB maintains a unified exception mapping table, which establishes a correspondence between local exception numbers of different ISAs and unified exception semantic types. For example, CPU page exceptions, vector execution exceptions, NPU task exceptions, and DSP memory access exceptions can be mapped to: memory access exception category; execution exception category; synchronization exception category; and resource exception category, respectively. After completing the exception mapping, the IEBTB generates unified exception description information and sends it to the HCME. The unified exception description information includes: unified exception type; unified exception level; exception recovery mode; associated context identifier; and exception propagation target information. Through this mechanism, unified semantic normalization of exception states across different ISAs is achieved.

[0071] In one embodiment, the exception recovery mode is dynamically determined by HCME based on a unified exception type, the target execution unit state, and the current task execution state.

[0072] IV. Dynamic context saving mechanism.

[0073] During an exception trigger or task switching, HCME starts the context saving state machine and performs context saving operations based on UECD.

[0074] In one embodiment, each heterogeneous execution unit maintains a valid state bit register or a dirty state bit register. Before saving the execution state, HCME first reads the corresponding valid state bit information and determines the target state set based on the valid state bit information. For example: when the current task does not use vector execution resources, the vector state is not saved; when the current task does not call the tensor execution unit, the tensor state is not saved; when the dedicated acceleration unit is in an idle state, the corresponding acceleration state is not saved. This reduces the redundancy of state saving.

[0075] Furthermore, in one embodiment, the HCME integrates a hardware compression encoding circuit to perform state compression processing on the target state set during the execution context saving process. The state compression processing includes at least one of the following: zero-value state compression; sparse state compression; differential state encoding; segmented state encoding; and state increment saving. For example, a zero-value detection circuit detects zero-value states in the data stream and records only non-zero state data; a differential encoding circuit generates differential data of the current state based on historical context states.

[0076] The above mechanism can reduce context storage bandwidth consumption and state transition overhead.

[0077] V. Cross-ISA context migration and state reconstruction mechanism.

[0078] When a task needs to migrate between heterogeneous execution units corresponding to different ISAs, HCME performs cross-ISA context migration operations based on UECD.

[0079] In one embodiment, the HCME first parses the ISA type identifier information and state description information in the UECD, and establishes a correspondence between the unified semantic state and the target ISA execution state by combining the ISA state organization format corresponding to the target execution unit. Subsequently, the cross-ISA state mapping module performs state reconstruction on the unified semantic state in the UECD according to the ISA state structure of the target execution unit, generating an execution state structure suitable for the target ISA. Specifically, the cross-ISA state mapping module parses the unified semantic state encoded data in the UECD under the control of configuration signals through a multiplexer array, state renaming logic, and state reconstruction control logic, and performs target state reconstruction according to the state organization format corresponding to the target ISA.

[0080] In one embodiment, the state reconstruction control logic, based on the register width, state field layout, and execution state organization of the target execution unit, performs physical path reorganization on the unified semantic state encoded data and generates target execution state data suitable for the target ISA. Subsequently, the target execution state data is written to the hardware register, control state register, or accelerated state buffer structure corresponding to the target execution unit through a hardware state injection interface. For example, vector semantic states are mapped to vector execution states corresponding to the target ISA; some general control states are mapped to dedicated control states of the target ISA; and unified anomaly recovery states are mapped to the anomaly recovery entry point of the target ISA.

[0081] In one embodiment, the target execution unit performs an anomaly recovery operation based on the reconstructed target execution state. The anomaly recovery operation includes at least one of the following: anomaly retry; state rollback; state reconstruction; task migration; degraded execution; and cross-execution unit recovery. For example, when the first heterogeneous execution unit cannot complete the anomaly recovery, HCME triggers a task migration process to migrate the target task to the second heterogeneous execution unit, and restores the execution state of the target task in the second heterogeneous execution unit based on UECD to continue executing the target task.

[0082] The system provided in this disclosure, by constructing a unified exception semantic abstraction mechanism, a unified execution context description structure, and a cross-ISA state reconstruction mechanism, can achieve unified normalized management of exception states across different ISAs, unified maintenance of execution contexts, and unified state recovery during cross-ISA task migration. This reduces cross-ISA context switching overhead, decreases state saving redundancy, improves exception recovery consistency, decouples execution states between different ISAs, and enhances cross-ISA collaborative execution efficiency and system scalability in heterogeneous processor systems.

[0083] The following specific examples will illustrate this point.

[0084] Example 1: System structure example.

[0085] In one embodiment, this disclosure provides a unified exception and execution context management system across ISAs for heterogeneous processors. This system is applicable to heterogeneous processor platforms composed of multiple heterogeneous execution units, and is used to achieve unified exception management, unified execution context maintenance, and cross-ISA task migration and recovery across different instruction set architectures (ISAs).

[0086] Please see Figure 3 , Figure 3 This is a schematic diagram of the overall structure of a cross-ISA unified exception and execution context management system for heterogeneous processors, provided in an embodiment of this disclosure. Specifically, the cross-ISA unified exception and execution context management system mainly includes: a heterogeneous execution unit (HEU); an on-chip interconnect exception translation bridge (IETB); a hardware context management engine (HCME); a dedicated context buffer storage structure; and a cross-ISA state mapping module. The modules are connected via an on-chip interconnect structure, a dedicated control bus, or a high-speed state transmission path.

[0087] 1. Heterogeneous Execution Unit (HEU).

[0088] In one embodiment, the heterogeneous execution unit is used to execute the target task under the corresponding ISA architecture and generate local execution state and local exception state information. The heterogeneous execution unit includes, but is not limited to: a central processing unit (CPU); a vector processing unit (VPU); a graphics processing unit (GPU); a neural network processing unit (NPU); a digital signal processor (DSP); and a dedicated AI acceleration unit. Different heterogeneous execution units can adopt different instruction set architectures and different register organization forms. For example, the CPU can adopt RISC-V (Reduced Instruction Set Computer - Five) or ARM ISA (Advanced RISC Machine Instruction Set Architecture); the GPU can adopt a SIMT (Single Instruction, Multiple Threads) execution architecture; the NPU (Neural Processing Unit) can adopt a tensor computation instruction architecture; and the DSP can adopt a fixed-length digital signal processing instruction structure.

[0089] In one embodiment, each heterogeneous execution unit maintains corresponding local execution state information, including: general-purpose register state; control state register; vector register state; tensor computation state; pipelined execution state; memory access state; and exception state information. When an exception event occurs during task execution, the corresponding heterogeneous execution unit generates local exception state information and sends it to the IEBTB through the on-chip interconnect structure.

[0090] 2. On-chip Interconnect Anomaly Translation Bridge (IETB).

[0091] In one embodiment, the IEBTB is deployed at an on-chip interconnect structure, a cache coherence interconnect structure, or a heterogeneous execution unit interconnect node, and is used to perform unified exception semantic normalization processing on the local exception states corresponding to different ISAs at the hardware layer. Specifically, the IEBTB internally maintains a unified exception mapping table, which establishes a correspondence between exception numbers of different ISAs and unified exception semantics. The local exception state information includes: local exception number; exception source information; exception execution location; ISA status identifier; exception priority information; and exception context index information.

[0092] In one embodiment, after receiving local exception status information, the IEBTB converts the local exception semantics from different ISAs into unified exception semantics by looking up a unified exception mapping table. For example, CPU page exceptions can be mapped to memory access exception categories; vector execution exceptions can be mapped to execution exception categories; NPU task exceptions can be mapped to synchronization exception categories; and DSP memory access out-of-bounds exceptions can be mapped to resource exception categories. After completing the unified exception semantic normalization, the IEBTB generates unified exception description information and sends it to the HCME. The unified exception description information includes: unified exception type; unified exception level; exception recovery mode; associated context identifier; and exception propagation target information.

[0093] 3. Hardware Context Management Engine (HCME).

[0094] In one embodiment, HCME is a standalone hardware control module used for the unified generation, maintenance, switching, and recovery of cross-ISA execution contexts. See also... Figure 4 , Figure 4 This is a schematic diagram of the internal structure of the HCME provided in an embodiment of this disclosure. Specifically, the HCME mainly includes: a cross-ISA context migration controller; a context-preserving state machine; state validity bit detection logic; state parsing control logic; state reconstruction control logic; hardware compression encoding circuit; and exception recovery control logic. Wherein: The cross-ISA context migration controller is used to control the context migration process between different ISA execution units; Context-preserving state machines are used to save context state during exception triggering or task switching. The valid state bit detection logic is used to detect the valid state set corresponding to the current task, and drive the context to save the state machine to perform state pruning based on the valid state set, so as to eliminate the redundant execution states that are not enabled. The state resolution control logic is used to generate state resolution control signals and control the cross-ISA state mapping module to perform resolution operations on the unified semantic state data; The state reconstruction control logic is used to generate the target execution state based on the state structure corresponding to the target ISA; Hardware compression encoding circuitry is used to perform state compression processing during context saving; The exception recovery control logic is used to perform exception recovery control, state rollback control, and task migration control, and to send recovery control signals to the hardware state injection interface inside the cross-ISA state mapping module.

[0095] 4. Dedicated context buffer storage structure.

[0096] In one embodiment, the dedicated context buffer storage structure comprises an on-chip independent dedicated SRAM storage array and a context register cache structure, used to cache normalized unified execution context data. Specifically: the dedicated SRAM storage array is used to store large-scale context state data; the context register cache structure is used to cache the currently active context state.

[0097] In one embodiment, HCME abstracts the execution states in different ISAs in a unified manner based on a unified semantic state description format and generates a unified execution context descriptor (UECD). The UECD includes at least one of the following: general state information; ISA type identification information; abnormal state information; execution control state information; vector semantic state information; tensor computation semantic state information; storage access semantic state information; dedicated acceleration state information; state validity bit information; and state compression description information.

[0098] In one embodiment, UECD does not perform one-to-one mirroring of the source ISA physical registers, but instead performs unified abstract encoding of different ISA states based on a unified semantic state description format, thereby achieving decoupling across ISA states.

[0099] 5. Cross-ISA state mapping module.

[0100] In one embodiment, the cross-ISA state mapping module is used to establish the correspondence between the unified semantic state and the target ISA execution state, and to complete cross-ISA state reconstruction and target state restoration. See also... Figure 5 , Figure 5 This is a schematic diagram of the cross-ISA state reconstruction structure provided in this embodiment. Specifically, the cross-ISA state mapping module mainly includes: state parsing logic; state renaming logic; target ISA state reconstruction control logic; MUX path reassembly array; and hardware state injection interface. Specifically: the state parsing logic is used to parse the unified semantic state data in the UECD; the state renaming logic is used to establish the correspondence between the unified semantic state fields and the target ISA state fields; the target ISA state reconstruction control logic is used to generate the target execution state according to the register width, state field layout, and execution state organization form corresponding to the target ISA; the MUX path reassembly array is used to perform physical path reassembly on the target state data; and the hardware state injection interface is used to write the reconstructed target execution state into the hardware register, control state register, or accelerated state buffer structure corresponding to the target execution unit when the recovery control signal is enabled. For example: mapping the vector semantic state to the vector execution state corresponding to the target ISA; mapping some general control states to the target ISA-specific control states; and mapping the unified anomaly recovery state to the target ISA anomaly recovery entry.

[0101] 6. Overall system operation process.

[0102] In one embodiment, when an abnormal event occurs in the source execution unit, the corresponding execution unit first generates local abnormal state information and sends it to the IETB. The IETB performs unified abnormal semantic normalization on the local abnormal state and then sends the unified abnormal description information to the HCME. Subsequently, the HCME starts the context-preserving state machine, performs unified abstraction of the current task execution state, and generates a corresponding UECD. The generated UECD is stored in a dedicated context buffer storage structure in a unified semantic state description format. When cross-ISA task migration is required, the HCME triggers the cross-ISA migration process. The cross-ISA state mapping module reads the unified semantic state data in the UECD and performs target ISA state reconstruction. After reconstruction, the hardware state injection interface writes the target execution state into the target execution unit to restore the execution state of the target task.

[0103] In one embodiment, the target execution unit may further perform: exception retry; state rollback; task migration; degraded execution; and cross-execution unit recovery. This achieves unified exception management, unified execution context maintenance, and cross-ISA task recovery across heterogeneous processor systems.

[0104] Example 2: Method Flow Example.

[0105] In one embodiment, this disclosure provides a cross-ISA unified exception and execution context management method for heterogeneous processors. See also... Figure 6 , Figure 6 This is a flowchart illustrating a cross-ISA unified exception and execution context management method provided in this embodiment of the disclosure. Specifically, the method includes the following steps: S201: A local exception was generated in a heterogeneous execution unit.

[0106] The heterogeneous execution units (HEUs) in the system execute target tasks under the corresponding ISA architecture. In one embodiment, the heterogeneous execution units include: CPU; GPU; NPU; DSP; vector processor; and dedicated AI acceleration unit. Different heterogeneous execution units employ different instruction set architectures and different register organization methods.

[0107] During task execution, each heterogeneous execution unit maintains its corresponding local execution state. The local execution state includes at least one of the following: general-purpose register state; control status register; vector register state; tensor computation state; memory access state; pipelined execution state; and exception state information.

[0108] S202: Generate local abnormal status information.

[0109] During task execution, when any heterogeneous execution unit detects an abnormal event, the corresponding execution unit generates local abnormal status information. Abnormal events include at least one of the following: page fault; memory access out-of-bounds fault; vector execution fault; synchronization execution fault; resource conflict fault; tensor computation fault; hardware failure fault; task timeout fault.

[0110] In one embodiment, the local exception status information includes: local exception number; exception source information; exception execution location; ISA status identifier; exception priority information; and exception context index information.

[0111] S203: Abnormal status signaling is sent to the on-chip interconnect.

[0112] The corresponding heterogeneous execution unit sends local exception status information to the IETB through the on-chip interconnect structure.

[0113] S204: IETB monitors and intercepts abnormal commands in real time.

[0114] S205: Read the Uniform Exception Mapping Table (LUT).

[0115] S206: Perform unified exception semantic normalization.

[0116] S207: Production Unified Anomaly Description Information.

[0117] After receiving local anomaly status information, the IETB performs unified anomaly semantic normalization processing on the anomaly statuses corresponding to different ISAs. Specifically, the IETB maintains a unified anomaly mapping table internally, which establishes a correspondence between anomaly numbers of different ISAs and unified anomaly semantic types. In one embodiment, the IETB looks up the corresponding anomaly mapping item based on the ISA type corresponding to the current anomaly and generates unified anomaly semantics. For example, CPU page anomalies are mapped to memory access anomalies; vector execution anomalies are mapped to execution anomalies; NPU task anomalies are mapped to synchronization anomalies; and DSP memory access out-of-bounds anomalies are mapped to resource anomalies. After completing the unified anomaly semantic normalization, the IETB generates unified anomaly description information and sends it to the HCME. The unified anomaly description information includes: unified anomaly type; unified anomaly level; anomaly recovery mode; associated context identifier; and anomaly propagation target information.

[0118] S208: Send to HCME.

[0119] Upon receiving the unified exception description information, the HCME initiates the context-saving state machine and generates a unified execution context descriptor (UECD). In one embodiment, the HCME first obtains the target ISA type and target execution unit identifier corresponding to the current task. Subsequently, the HCME performs unified abstract encoding on the execution state corresponding to the current task based on the unified semantic state description format. In one embodiment, the UECD includes at least one of the following: general state information; ISA type identifier information; exception state information; execution control state information; vector semantic state information; tensor computation semantic state information; storage access semantic state information; dedicated acceleration state information; state validity bit information; and state compression description information. Wherein: the vector semantic state information describes the vector length, the range of valid vector elements, and the semantics of vector computation; the tensor computation semantic state information describes the tensor dimension, matrix operation state, and tensor execution control state. In one embodiment, the UECD does not perform a one-to-one mirror saving of the source ISA registers, but rather abstracts and encodes different ISA states based on the unified semantic state description format to achieve decoupling across ISA states.

[0120] HCME first reads the valid state bits or dirty state registers from each heterogeneous execution unit. Based on the valid state bits, it performs state pruning to eliminate inactive execution states, thereby determining the target state set. For example, when the current task is not using vector execution resources, the vector state is not saved; when the current task does not call the tensor execution unit, the tensor state is not saved; when a dedicated acceleration unit is idle, the corresponding acceleration state is not saved. This reduces state saving redundancy.

[0121] Furthermore, in one embodiment, the hardware compression coding circuit within the HCME performs state compression processing on the target state set. The state compression processing includes at least one of the following: zero-value state compression; sparse state compression; differential state coding; segmented state coding; and state increment storage. For example, a zero-value detection circuit detects zero-value states in the data stream and records only non-zero state data; a differential coding circuit generates differential data corresponding to the current state based on historical context states. Subsequently, the HCME saves the generated UECD to a dedicated context buffer storage structure.

[0122] S209: Trigger the unified exception recovery process.

[0123] When the system detects the need to perform cross-ISA task migration, the cross-ISA context migration controller within HCME initiates the cross-ISA context migration process. In one embodiment, the conditions triggering cross-ISA migration include at least one of the following: a hardware failure occurs in the current execution unit; the current execution unit has insufficient computing resources; the current execution unit is overloaded; the current task needs to switch to the target acceleration unit; the system performs heterogeneous load balancing scheduling; or the current execution unit enters a low-power mode. Subsequently, the cross-ISA context migration controller sends a control signal to the cross-ISA state mapping module to trigger the cross-ISA state mapping module to read the corresponding UECD data.

[0124] The cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure and performs target ISA state reconstruction. Specifically, the cross-ISA state mapping module first parses the unified semantic state fields in the UECD. Subsequently, the state renaming logic establishes the correspondence between the unified semantic state fields and the target ISA state fields. Afterward, the target ISA state reconstruction control logic performs target state reconstruction on the unified semantic state data according to the register width, state field layout, and execution state organization form corresponding to the target ISA.

[0125] In one embodiment, the MUX path reassembly array performs physical path reassembly on the target state data and generates target execution state data suitable for the target ISA. For example, it maps vector semantic states to vector execution states corresponding to the target ISA; maps some general control states to target ISA-specific control states; and maps unified anomaly recovery states to the target ISA anomaly recovery entry point.

[0126] After completing the target ISA state reconstruction, the cross-ISA state mapping module writes the target execution state into the target execution unit through the hardware state injection interface. Specifically, after receiving the recovery control signal sent by the exception recovery control logic, the hardware state injection interface injects the reconstructed target execution state data into the hardware register of the target execution unit.

[0127] In one embodiment, the target execution state is written to at least one of the following: a general-purpose register; a control state register; a vector register; a tensor state buffer; and an acceleration state buffer structure.

[0128] Subsequently, the target execution unit performs the corresponding recovery operation based on the recovered target execution state. The recovery operation includes at least one of the following: exception retry; state rollback; task migration; degraded execution; cross-execution unit recovery. For example, when the first heterogeneous execution unit cannot complete the exception recovery, HCME triggers a task migration process, migrating the target task to the second heterogeneous execution unit and restoring the target task's execution state in the second heterogeneous execution unit to continue executing the target task. After the target execution state injection is completed, the target execution unit generates a recovery completion status signal and feeds it back to HCME to indicate that the current cross-ISA recovery process is complete.

[0129] After the target execution unit completes state recovery, it continues to execute the corresponding target task.

[0130] Through the above process, unified and normalized management of abnormal states across different ISAs, unified maintenance of execution contexts, and unified state recovery during cross-ISA task migration are achieved. The embodiments of this disclosure can reduce cross-ISA context switching overhead, reduce state saving redundancy, improve abnormal recovery consistency, and enhance cross-ISA collaborative execution efficiency in heterogeneous processor systems.

[0131] Example 3: Example of cross-ISA state reconstruction driven by unified semantic state.

[0132] In one embodiment, this disclosure provides a unified semantic state-driven cross-ISA state reconstruction mechanism to achieve unified abstraction of execution state, state decoupling, and target execution state recovery between different instruction set architectures (ISAs).

[0133] Please see Figure 5 , Figure 5 This is a schematic diagram of the cross-ISA state reconstruction structure provided in an embodiment of this disclosure.

[0134] In traditional heterogeneous processor systems, different ISAs typically employ independent register organization, exception semantics, and execution state structures. Therefore, related technologies usually only support context switching within the same ISA, making it difficult to achieve unified state recovery across different ISAs. For example, CPUs use a general-purpose register and control register organization; GPUs use a SIMT thread state organization; NPUs use a tensor computation state organization; and DSPs use a fixed-length pipelined state organization. The lack of a unified state description structure across different ISAs makes cross-ISA execution state migration difficult.

[0135] To address the aforementioned issues, this disclosure proposes a unified semantic state-driven cross-ISA state reconstruction mechanism.

[0136] Specifically, HCME first uses a unified semantic state description format to perform unified abstract encoding on the execution state corresponding to the source execution unit and generates a unified execution context descriptor UECD.

[0137] In one embodiment, UECD does not mirror and save each physical register of the source ISA, but instead performs a unified abstraction of the execution semantic state across different ISAs. The unified semantic state includes at least one of the following: general computation semantic state; vector computation semantic state; tensor computation semantic state; storage access semantic state; execution control semantic state; exception recovery semantic state; and accelerator execution semantic state. For example, when the source execution unit is a vector processor, HCME does not directly save the physical location information of the corresponding vector register, but extracts: vector length; effective element range; vector operation type; data organization method; and vector execution control state; and generates corresponding vector semantic state information.

[0138] Furthermore, when the target execution unit is an NPU, the cross-ISA state mapping module does not need to restore the physical layout of the source vector registers. Instead, it reconstructs the vector semantic state into the tensor computation state corresponding to the target ISA based on unified semantic state information. For example, the vector length is mapped to tensor dimension information; the vector computation semantics is mapped to matrix operation control state; and the range of valid vector elements is mapped to the valid tensor computation region.

[0139] In one embodiment, after receiving an enable control signal from the cross-ISA context migration controller, the cross-ISA state mapping module first parses the unified semantic state field in the UECD. Then, the state renaming logic establishes a correspondence between the unified semantic state field and the target ISA state field. Afterwards, the target ISA state reconstruction control logic performs target state reconstruction on the unified semantic state based on the target execution unit's: register width; state field layout; execution state organization; and accelerator control structure.

[0140] Furthermore, in one embodiment, the MUX path reassembly array within the cross-ISA state mapping module performs physical path reassembly on the target execution state data based on the target state reconstruction result. For example: bit concatenation is performed on state fields of different widths via the physical interconnect logic of the MUX array; signal line redirection is performed on the target register input path via multiplexer control; concatenation is performed on state fields of different widths; redirection is performed on the target register input path; dynamic mapping is performed on the target control state field; and state reorganization is performed on the accelerator execution buffer. Subsequently, the reconstructed target execution state data is written to the target execution unit via a hardware state injection interface.

[0141] In one embodiment, after the target execution unit completes the target state recovery, it generates a recovery completion status signal and feeds it back to the HCME. Upon receiving the recovery completion status signal, the HCME updates the execution status table entry corresponding to the current task and terminates the current cross-ISA recovery process. Through the above mechanism, this embodiment of the present disclosure achieves a unified semantic abstraction of execution states and target state reconstruction between different ISAs, thereby avoiding the problem of strong binding to the physical register structure of the source ISA.

[0142] The embodiments disclosed herein can: reduce cross-ISA state coupling; improve heterogeneous execution state compatibility; reduce context transition complexity; improve exception recovery consistency; and enhance cross-ISA collaborative execution capabilities in ultra-heterogeneous processor systems.

[0143] Example 4: Application example of cross-ISA task migration and anomaly recovery.

[0144] In one embodiment, this disclosure provides an application example of cross-ISA task migration and anomaly recovery based on unified anomaly semantics and unified execution context descriptor UECD.

[0145] Please see Figure 6 , Figure 7 , Figure 8 and Figure 4 , Figure 7 This is a schematic diagram of the dynamic context saving and compression process provided in the embodiments of this disclosure. Figure 8 This is a timing diagram illustrating the cross-ISA task migration and anomaly recovery process provided in an embodiment of this disclosure.

[0146] This embodiment uses the "abnormal recovery scenario during CPU to NPU migration" as an example to illustrate the unified abnormality normalization mechanism, unified execution context management mechanism, and cross-ISA state reconstruction mechanism in this disclosure. It should be noted that this embodiment is merely illustrative, and this disclosure is not limited to task migration between CPU and NPU, but also applies to: task migration between CPU and GPU; task migration between GPU and DSP; task migration between vector processors and AI accelerators; task migration between different Chiplet computing units; and abnormal recovery between different ISA execution cores.

[0147] 1. The CPU executes the target task.

[0148] In one embodiment, the first heterogeneous execution unit is a CPU, and the CPU adopts a first ISA architecture. During the execution of the target task, the CPU maintains the corresponding local execution state. The local execution state includes: general-purpose register state; control status register; vector execution state; memory access state; and exception state information.

[0149] In one embodiment, the current target task is an AI inference task, and the CPU is responsible for performing preprocessing and some vector calculation operations.

[0150] 2. An abnormal event occurred in the CPU.

[0151] During task execution, the CPU detects an abnormal event. This abnormal event includes at least one of the following: page fault; memory access fault; vector execution fault; resource conflict fault; execution timeout fault; hardware failure fault. For example, the CPU detects insufficient vector execution resources or that the current task has exceeded a preset execution time limit during vector computation. Subsequently, the CPU generates local abnormal status information and sends it to the IEBTB via the on-chip interconnect structure. In one embodiment, the local abnormal status information includes: a local abnormality number; abnormality source information; abnormal execution location; ISA status identifier; abnormality priority information; and abnormal context index information.

[0152] 3. IETB performs unified exception semantic normalization.

[0153] After receiving the local exception status information sent by the CPU, the IETB performs unified exception semantic normalization processing on the current exception. Specifically, the IETB converts the local exception semantics corresponding to the CPU into unified exception semantics based on a unified exception mapping table. For example, CPU page exceptions are mapped to memory access exception categories; CPU vector execution exceptions are mapped to execution exception categories; and CPU resource shortage exceptions are mapped to resource exception categories. After completing the unified exception semantic normalization, the IETB generates unified exception description information and sends it to the HCME.

[0154] 4. HCME generates UECD and performs state saving.

[0155] After receiving the unified exception description information, HCME starts the context saving state machine.

[0156] In one embodiment, HCME first reads the valid state bit information or dirty state bit register maintained internally by the CPU, and performs state pruning based on the valid state bit information to remove inactive execution states, thereby determining the target state set. For example, if the current task does not enable tensor execution resources, the tensor state is not saved; if the current task does not enable some vector resources, the corresponding vector state is not saved. Subsequently, HCME performs unified abstract encoding on the current CPU execution state based on the unified semantic state description format and generates UECD.

[0157] In one embodiment, the UECD includes: general state information; vector semantic state information; storage access semantic state information; anomaly recovery semantic state information; state validity bit information; and state compression description information.

[0158] Furthermore, the HCME's internal hardware compression coding circuitry performs state compression processing on the target state set. For example, it performs zero-value compression on zero-value states; sparse coding on sparse vector states; and differential coding on historical states. Subsequently, the HCME saves the generated UECD to a dedicated context buffer storage structure.

[0159] 5. Trigger cross-ISA task migration.

[0160] In one embodiment, HCME detects that the current CPU is unable to continue completing the target task. For example: the current CPU has insufficient computing power; the current CPU load is too high; the current CPU has experienced a hardware failure; or the current task is more suitable to be executed by an AI accelerator. Subsequently, the cross-ISA context migration controller within HCME initiates the cross-ISA migration process.

[0161] In one embodiment, the cross-ISA context migration controller determines: the target ISA type; the target execution unit identifier; and the target recovery mode. For example, the HCME determines that the target execution unit is an NPU and that the current recovery mode is the task migration recovery mode. Subsequently, the cross-ISA context migration controller sends a state recovery control signal to the cross-ISA state mapping module.

[0162] 6. Perform cross-ISA state reconstruction.

[0163] The cross-ISA state mapping module reads the corresponding UECD data from a dedicated context buffer storage structure. Subsequently, the state resolution logic parses the unified semantic state fields in the UECD.

[0164] In one embodiment, the state renaming logic establishes a correspondence between unified semantic states and NPU execution states. For example, it maps vector semantic states to tensor computation semantic states; it maps the range of valid vector elements to the valid computation region of tensors; and it maps vector execution control states to matrix operation control states. Then, the target ISA state reconstruction control logic generates the target execution state based on the state organization structure corresponding to the NPU.

[0165] Furthermore, the MUX path reconfiguration array performs physical path reconfiguration on the target state data and generates target execution state data suitable for the NPU.

[0166] 7. Perform target state injection and recovery.

[0167] After completing the state reconstruction, the cross-ISA state mapping module writes the target execution state into the NPU through the hardware state injection interface. Specifically, after receiving the recovery control signal enabled by the exception recovery control logic inside the HCME, the hardware state injection interface adaptively injects the reconstructed target execution state data into the hardware storage structure corresponding to the NPU.

[0168] In one embodiment, the target execution state is written to: a tensor state buffer; an NPU control state register; an AI computation control queue; and an accelerator execution state cache structure. Subsequently, the NPU continues to execute the target task based on the restored target execution state.

[0169] In one embodiment, after the NPU completes recovery, it generates a recovery completion status signal and sends it back to the HCME. Upon receiving the recovery completion status signal, the HCME updates the execution status table entry corresponding to the current task and terminates the current cross-ISA recovery process.

[0170] This embodiment achieves the following technical effects: unified normalization of abnormal states between different ISAs; unified abstraction of execution states between different ISAs; unified state recovery during cross-ISA task migration; and collaborative abnormal recovery between different heterogeneous execution units. This embodiment can: reduce the complexity of cross-ISA task migration; reduce context saving redundancy; improve heterogeneous recovery consistency; enhance heterogeneous collaboration efficiency in AI SoC (Artificial Intelligence System on Chip); and improve runtime elasticity and scalability in ultra-heterogeneous processor systems.

[0171] Embodiments of this disclosure also provide an electronic device including a memory and a processor, the memory storing a computer program and the processor being configured to run the computer program to perform the steps in any of the above method embodiments.

[0172] Embodiments of this disclosure also provide a computer-readable storage medium storing a computer program configured to perform the steps in any of the above method embodiments when executed.

[0173] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0174] Embodiments of this disclosure also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0175] Embodiments of this disclosure also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0176] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0177] The foregoing has provided a detailed description of a cross-ISA unified exception and execution context management method and system provided by this disclosure. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this disclosure without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this disclosure.

Claims

1. A method for cross-ISA unified exception and execution context management, the method comprising: include: If the heterogeneous execution unit detects an abnormal event during the execution of the target task, it generates local abnormal status information and sends it to the IETB; The IEBTB performs unified exception semantic normalization processing on the local exception status information to obtain unified exception description information and sends it to HCME. The HCME obtains the current execution state and, based on the unified exception description information and the unified semantic state description format, performs unified abstract encoding on the current execution state, generates UECD, and saves it to a dedicated context buffer storage structure. When the HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside the HCME initiates the cross-ISA context migration process; The cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure, and performs target ISA state reconstruction according to the state organization structure corresponding to the target ISA; After the target ISA state reconstruction is completed, the cross-ISA state mapping module writes the target execution state into the target execution unit through the hardware state injection interface, so that the target execution unit performs a recovery operation based on the target execution state; After the target execution unit completes state recovery, it continues to execute the corresponding target task.

2. The cross-ISA unified exception and execution context management method of claim 1, wherein, The IEBTB performs unified exception semantic normalization processing on the local exception status information to obtain unified exception description information and sends it to HCME, including: A correspondence between local anomaly numbers of different ISAs and unified anomaly semantic types is established based on a unified anomaly mapping table to obtain unified anomaly description information; wherein, the unified anomaly description information includes at least one of unified anomaly type, unified anomaly level, anomaly recovery mode, associated context identifier, and anomaly propagation target information; The unified anomaly description information is sent to HCME.

3. The cross-ISA unified exception and execution context management method of claim 1, wherein, The HCME acquires the current execution state and, based on the unified exception description information and unified semantic state description format, performs unified abstract encoding on the current execution state, generates a UECD, and saves it to a dedicated context buffer storage structure, including: The HCME reads the state validity bit information inside the heterogeneous execution unit and performs state trimming based on the state validity bit information to determine the target state set; The HCME performs unified abstract encoding on the current execution state based on the target state set and the unified semantic state description format to generate UECD; Save the UECD to a dedicated context buffer storage structure.

4. The cross-ISA unified exception and execution context management method of claim 3, wherein, The UECD includes at least one of the following: general state information, ISA type identification information, abnormal state information, execution control state information, vector semantic state information, tensor computation semantic state information, storage access semantic state information, dedicated acceleration state information, state validity bit information, and state compression description information.

5. The cross-ISA unified exception and execution context management method of claim 1, wherein, When the HCME detects that a cross-ISA task migration needs to be performed, the cross-ISA context migration controller inside the HCME initiates the cross-ISA context migration process, including: When the HCME detects at least one of the following: hardware anomaly, insufficient computing resources, excessive load, task needing to be switched to target acceleration unit, system performing heterogeneous load balancing scheduling, or the current execution unit entering low-power mode, the cross-ISA context migration controller inside the HCME initiates the cross-ISA context migration process.

6. The cross-ISA unified exception and execution context management method of claim 1, wherein, The cross-ISA state mapping module reads the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure, and performs target ISA state reconstruction according to the state organization structure corresponding to the target ISA, including: The cross-ISA state mapping module reads and parses the unified semantic state field in the UECD from the dedicated context buffer storage structure; Establish the correspondence between the unified semantic status field and the target ISA status field; The execution target ISA state is reconstructed based on at least one of the following: register width, status field layout, and execution status organization form of the target execution unit.

7. The cross-ISA unified exception and execution context management method of claim 6, wherein, The execution of the target ISA state reconstruction also includes: Physical path reconstruction is performed on the target state data using the MUX path reconstruction array.

8. The cross-ISA unified exception and execution context management method of claim 1, wherein, After completing the target ISA state reconstruction, the cross-ISA state mapping module writes the target execution state into the target execution unit through a hardware state injection interface, including: After completing the target ISA state reconstruction, the cross-ISA state mapping module writes at least one of the reconstructed general state, vector semantic state, tensor computation semantic state, and anomaly recovery semantic state into at least one of the hardware registers, control state registers, vector registers, tensor state buffers, and acceleration state buffer structures corresponding to the target execution unit through the hardware state injection interface.

9. The cross-ISA unified exception and execution context management method of claim 1, wherein, After completing state recovery, the target execution unit continues to execute the corresponding target task, including: The target execution unit performs at least one recovery operation based on the recovered target execution state, including abnormal retry, state rollback, task migration, degraded execution, and cross-execution unit recovery, and then continues to execute the corresponding target task.

10. A cross-ISA unified exception and execution context management system, comprising: include: Heterogeneous execution units are used to detect abnormal events during the target task, generate local abnormal status information, and send it to the IETB. The IEBTB is connected to the heterogeneous execution unit and is used to receive the local abnormal state information, perform unified abnormal semantic normalization processing on the local abnormal state information, obtain unified abnormal description information, and send it to HCME. The HCME, connected to the IEBTB, is used to obtain the current execution state and, based on the unified exception description information and the unified semantic state description format, to perform unified abstract encoding on the current execution state, generate UECD, and save it to a dedicated context buffer storage structure. And for detecting cross-ISA task migration requirements and initiating cross-ISA context migration processes; A dedicated context buffer storage structure, connected to the HCME, is used to cache the UECD; The cross-ISA state mapping module is connected to the HCME and the dedicated context buffer storage structure. It is used to read the unified semantic state data corresponding to the UECD from the dedicated context buffer storage structure, and to perform target ISA state reconstruction according to the state organization structure corresponding to the target ISA. It is also used to write the target execution state into the target execution unit through the hardware state injection interface after the target ISA state reconstruction is completed. The target execution unit, connected to the cross-ISA state mapping module, is used to receive the reconstructed target execution state and continue to execute the corresponding target task after the state is restored.

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