Access method and access system based on a generic configuration interface

Abstract

The application discloses an access method and system based on a general configuration interface. The access method comprises the following steps: in response to an access request, a starting end sends a first valid flag signal, a first clock signal and a first data signal with a target bit width to a responding end through a general configuration interface; the responding end analyzes the first data signal and performs an access operation based on the first valid flag signal and the first clock signal; the responding end sends a second valid flag signal, a second clock signal and a second data signal with the target bit width to the starting end through the general configuration interface; and the starting end analyzes the second data signal to obtain an access result based on the second valid flag signal and the second clock signal. The access method defines a standardized interface interaction process, can flexibly set the data transmission bit width according to actual needs, is suitable for various register access scenes, does not need to design multiple sets of communication protocols for different scenes, and reduces the workload of protocol adaptation and function verification.

Description

Technical Field

[0001] This application belongs to the field of chip testing technology, specifically relating to an access method and system based on a general configuration interface. Background Technology

[0002] When the main control module inside the chip or the initiator outside the chip accesses the chip's readable and writable register components, data transmission and reception must be performed through an appropriate logic interface. For example, during chip performance testing, the external ATE device generates test stimuli, configures the chip to be in test mode and triggers test behavior through an appropriate logic interface, and returns the test results to the ATE device after the final test is completed; before the chip completes initialization, the internal chips use simple register access paths to complete the initialization operation, and so on.

[0003] Currently, due to the different performance requirements of different access scenarios, the access path methods adopted are also different. For example, common inter-chip access interfaces can use protocols such as SPI / QSPI, MDIO, I2C / I3C, PCIe, and Local Bus, while the access interfaces within a chip or between chips are more commonly AXI and APB interface protocols.

[0004] The characteristics and performance of the various interface protocols mentioned above are quite different, and they are applicable to different scenarios. Existing technologies use different interface protocols in different access scenarios. The interfaces in each scenario are not uniform, and they need to be designed and verified separately, which increases the workload and is not conducive to ensuring the stability of the chip. Summary of the Invention

[0005] The purpose of this application is to provide an access method and system based on a universal configuration interface, in order to solve the technical problem that the existing technology uses different interface protocols in different access scenarios, the interfaces in each scenario are not uniform, and they need to be designed and verified separately, which increases the workload and is not conducive to ensuring the stability of the chip.

[0006] To achieve the above objectives, the first aspect of this application provides an access method based on a universal configuration interface, applied to an access system, the access system including an initiating end and a responding end connected through a universal configuration interface, the universal configuration interface having a configurable bit width parameter to determine the target bit width of the universal configuration interface;

[0007] The access methods include:

[0008] In response to the access request, the initiating end sends a first valid flag signal, a first clock signal, and a first data signal configured with the target bit width to the responding end through the general configuration interface. The first valid flag signal is used to describe the validity period of the first data signal, and the first data signal includes a command field and an address field that are within the validity period.

[0009] The response terminal parses the first data signal and performs an access operation based on the first valid flag signal and the first clock signal;

[0010] The responding end sends a second valid flag signal, a second clock signal, and a second data signal configured with the target bit width to the initiating end through the general configuration interface. The second valid flag signal is used to describe the validity period of the second data signal, and the second data signal includes a result status field within the validity period.

[0011] The initiating end obtains the access result by parsing the second data signal based on the second valid flag signal and the second clock signal.

[0012] In one or more embodiments, the command field is transmitted within the first clock cycle of the validity period of the first data signal.

[0013] In one or more embodiments, the result status field is transmitted within the first clock cycle of the validity period of the second data signal.

[0014] In one or more embodiments, the first valid flag signal includes a first level state and a second level state. When the first valid flag signal is in the first level state, the first data signal is invalid, and when the first valid flag signal is in the second level state, the first data signal is valid.

[0015] In one or more embodiments, the second valid flag signal includes a first level state and a second level state. When the second valid flag signal is in the first level state, the second data signal is invalid, and when the second valid flag signal is in the second level state, the second data signal is valid.

[0016] In one or more embodiments, the command field includes a data length flag, an operation type flag, and a custom request flag. The data length flag describes the total number of operation data, the operation type flag describes the operation type, and the custom request flag allows the user to customize access request information.

[0017] In one or more embodiments, the first data signal further includes a request data field within the validity period, wherein the total number of operation data is used to describe the multiple of the total length of the address field and the request data field relative to a preset field length, wherein the preset field length is an integer multiple of the target bit width.

[0018] In one or more embodiments, the operation type includes one of a read operation, a write operation, and an atomic operation.

[0019] In one or more embodiments, the result status field includes a returned data length flag, a returned status flag, and a custom returned flag. The returned data length flag describes the total number of returned data, the returned status flag describes the access status, and the custom returned flag allows the user to customize the access returned information.

[0020] In one or more embodiments, the second data signal further includes a return data field, wherein the total number of return data is used to describe the length of the return data field as a multiple of a preset field length, wherein the preset field length is an integer multiple of the target bit width.

[0021] In one or more embodiments, the access status includes access success, access error, or access timeout.

[0022] In one or more embodiments, the first data signal further includes a request data field within the validity period. When the total length of the address field and / or the request data field is greater than the target bit width, the address field and / or the request data field is split according to the target bit width and transmitted sequentially within the clock cycle of the continuous first clock signal.

[0023] In one or more embodiments, the second data signal further includes a return data field within the validity period. When the total length of the return data field is greater than the target bit width, the return data field is split according to the target bit width and transmitted sequentially within the clock cycle of the continuous first clock signal.

[0024] To achieve the above objectives, a second aspect of this application provides an access system based on a universal configuration interface, which performs access operations using the access method described in any of the above embodiments. The access system includes an initiating end and a responding end connected through a universal configuration interface, wherein the universal configuration interface has a configurable bit width parameter to determine the target bit width of the universal configuration interface.

[0025] In one or more embodiments, the initiating end is an external CPU or an external test device, and the responding end is an internal register module to be accessed within the chip.

[0026] In one or more embodiments, the initiating end is a first core, and the responding end is the accessed register module inside a second core.

[0027] In one or more embodiments, the initiating end is communicatively connected to the responding end via a bidirectional pin to bidirectionally transmit the first data signal and the second data signal at different time periods via the bidirectional pin.

[0028] The advantages of this application, which differ from existing technologies, are:

[0029] This application's access method, by defining a standardized interface interaction process, is applicable to various register access scenarios, including access to external devices, internal registers, inter-chip communication, and ATE chip testing. It eliminates the need to design multiple communication protocols for different scenarios, reducing the workload of protocol adaptation, logic development, and functional verification. The general configuration interface supports configurable target bit width, allowing flexible setting of data transmission bit width according to actual needs. A large bit width can be configured in high-performance scenarios to improve transmission rate, while a small bit width can be configured in scenarios with limited pins and channels to reduce the number of interface signals, achieving flexible adaptation to performance, resources, and application scenarios with strong compatibility. Data transmission is completed using a clock along with a valid flag signal. All data and control signals are synchronously sampled by the corresponding clock, avoiding clock domain risks and sampling instability issues of asynchronous interfaces. The interface timing logic is simple, requiring no complex initialization process; it can operate normally after chip power-on reset, making it particularly suitable for scenarios with high startup speed requirements, such as chip power-on initialization and ATE testing.

[0030] This application's access system can adapt to different bit width requirements by modifying parameters, reducing compatibility issues. The initiating and responding ends follow the same set of signal specifications, and no additional protocol conversion is required between different functional modules and different chips, reducing system integration difficulty, reducing compatibility failures caused by mixing multiple interfaces, and improving chip operation reliability. At the same time, it is compatible with various hardware deployment forms and can be flexibly deployed in scenarios such as external devices and internal components of the chip, and between different chips, making it widely applicable. Attached Figure Description

[0031] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0032] Figure 1 This is a flowchart illustrating one implementation method of the access method based on the general configuration interface in this application;

[0033] Figure 2 This is a schematic diagram of the data format of a first embodiment of the data signal in this application;

[0034] Figure 3 This is a schematic diagram of one embodiment of the transmission signal of the initiator of this application;

[0035] Figure 4 This is a schematic diagram of the data format of a second data signal according to an embodiment of this application;

[0036] Figure 5 This is a schematic diagram of one embodiment of the return signal from the response end of this application;

[0037] Figure 6 This is a schematic diagram of one embodiment of the access system based on the general configuration interface of this application;

[0038] Figure 7 This is a schematic diagram of another implementation of the access system based on the general configuration interface of this application. Detailed Implementation

[0039] To enable those skilled in the art to better understand the technical solutions in this disclosure, the technical solutions in the embodiments of this disclosure will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this disclosure, and not all embodiments. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this disclosure.

[0040] Different interface protocols have vastly different characteristics and performance. For example, MDIO and I2C / I3C protocols require fewer interface signals, and only a minimum of two wires are needed to meet basic access requirements when connecting chips. In particular, I2C / I3C also supports multi-master and multi-slave device connections. SPI, QSPI, and Local Bus protocols can achieve one-master and multi-slave system connections, providing higher access performance than the above three interface protocols. PCIe interfaces only support point-to-point connections, but can provide higher performance and richer features, meeting the needs of high-performance application scenarios. AXI and APB protocol interfaces are generally used for on-chip access interfaces. Among them, the AXI protocol has better performance, but has too many interface signals, making implementation more complex. The APB interface has relatively fewer signals, but its performance is also poorer.

[0041] Based on different interface protocols, existing technologies select different interface protocols to access the read / write register components inside the chip in different scenarios. For example, common inter-chip access interfaces can use protocols such as SPI / QSPI, MDIO, I2C / I3C, PCIe, and Local Bus, while AXI and APB interface protocols are more common for access interfaces inside the chip or between chips.

[0042] Because existing technologies use different interface protocols for different access scenarios, the interfaces in each scenario are not uniform and need to be designed and verified separately, which increases the workload and is not conducive to ensuring the stability of the chip.

[0043] To address the aforementioned issues, the applicant developed an access method based on a universal configuration interface. This access method is based on an interface protocol scheme applicable to all the above working scenarios. It can be applied to internal register access within the chip, configuration access between chips, and data access operations between chips. Performance and bit width can be adjusted according to scenario requirements, simplifying chip implementation difficulty, effectively reducing chip design and verification difficulty, reducing workload, and helping to ensure chip stability.

[0044] Specifically, the access method is applied to an access system that includes an initiating end and a responding end connected through a general configuration interface. The general configuration interface has a configurable bit width parameter to determine the target bit width of the general configuration interface.

[0045] This application defines a parameterizable general configuration interface protocol. The data transmission bit width is specified by a global bit width parameter. It can be flexibly configured from 1 bit to theoretically unlimited range without modifying the underlying logic code. It does not depend on other complex functional components. The chip can enter the working state after being powered on and released from the reset state without any other initialization operations.

[0046] The following describes in detail the method for accessing the system based on this parameterizable general configuration interface.

[0047] Please see Figure 1 , Figure 1 This is a flowchart illustrating one implementation method of the access method based on the general configuration interface in this application.

[0048] like Figure 1 As shown, the method includes:

[0049] S101. In response to the access request, the initiating end sends a first valid flag signal, a first clock signal, and a first data signal configured with a target bit width to the responding end through a general configuration interface.

[0050] The first valid flag signal is used to describe the validity period of the first data signal, which includes a command field and an address field within the validity period.

[0051] S102, The response end parses the first data signal and performs an access operation based on the first valid flag signal and the first clock signal.

[0052] The general configuration interface protocol of this application uses an in-circuit clock scheme, that is, the initiating end synchronously sends the initiating end's first clock signal when sending data.

[0053] The responding end can parse the first data signal based on the first clock signal and the first valid flag signal, and then perform the corresponding access operation.

[0054] In one implementation, the command field can be transmitted within the first clock cycle of the validity period of the first data signal, that is, the command field can be located at the very beginning of the validity period of the first data signal.

[0055] Based on the above scheme, the response end only needs to perform a single sampling of the first data signal when the first valid flag signal is valid to obtain complete command information, which helps to improve the access rate.

[0056] In one implementation, the command field may include a data length flag, an operation type flag, and a custom request flag.

[0057] Among them, the data length flag is used to indicate the total number of operation data units to be transmitted in this access request; the operation type flag is used to indicate the register operation type corresponding to this access request; and the custom request flag is a reserved extensible field used to support users to customize additional control information of the access request according to specific application scenarios.

[0058] Based on the above structured command field design, the responding end can obtain all the core control information required to complete the operation at once within the first clock cycle of the access request, thereby achieving efficient, reliable and flexible configuration access processing.

[0059] Specifically, operation types can include read operations, write operations, atomic operations, etc., and the specific definitions can be set according to actual needs.

[0060] Furthermore, in one embodiment, the first data signal also includes a request data field that is within the validity period.

[0061] The total number of operation data can be specifically used to describe the multiple of the total length of the address field and the request data field relative to the preset field length, where the preset field length is an integer multiple of the target bit width.

[0062] Based on the above scheme, the data length flag can represent the total length of a wide range of operational data with only a few bits, and its bit width and parsing logic are completely independent of the target bit width parameter of the interface, which can adapt to the transmission requirements under all bit width configurations.

[0063] For example, when the target bit width is 16-bit, the address field is 32-bit, and the request data field is 32-bit, the preset field length can be set to twice the 16-bit length, i.e., 32-bit. In this case, the data length flag is 2. Compared with byte-by-byte counting, the bit width occupied by the data length flag is significantly reduced. Even in the ATE test scenario with a 1-bit serial bit width, the 8-bit length flag can still be transmitted completely within one clock cycle, ensuring that the command field can be transmitted within a unit width without splitting the transmission, thus maintaining the simplicity of the protocol.

[0064] In particular, the bits saved by the data length flag can be allocated to the operation type flag or a custom request flag. For example, the operation type flag can be extended from 4 bits to 6 bits to support up to 64 different operation types, greatly improving the protocol's functional scalability.

[0065] Furthermore, based on the target bit width, the address field and the request data field can be split to ensure normal data transmission and meet the needs of different scenarios.

[0066] That is, when the total length of the address field and / or the request data field is greater than the target bit width, the address field and / or the request data field are split according to the target bit width and transmitted sequentially within the clock cycle of the continuous first clock signal.

[0067] For example, when the target bit width is 16-bit, the structure of the first data signal can be as follows: Figure 2 As shown, Figure 2 This is a schematic diagram of the data format of a first embodiment of the data signal in this application.

[0068] like Figure 2 As shown, in this embodiment, the data length flag ReqLength occupies 8 bits, the operation type flag CMD occupies 4 bits, and the custom request flag ReqInfo occupies 4 bits, for a total of 16 bits, which can be transmitted completely within one clock cycle; the address field has a total width of 32 bits. Since the target width is 16 bits, the address field is divided into two ends, namely the low address and the high address; the request data field can be divided into N data according to the preset field length of 32 bits, and each data is divided into low data and high data according to 16 bits.

[0069] Based on the first data signal mentioned above, the data format can be automatically adjusted according to the target bit width to meet the needs of different application scenarios. For example, a larger data transmission bit width can be set on interfaces with high performance requirements, while a smaller data transmission bit width can be set in places where there are no performance requirements but the interface signal bit width needs to be reduced, such as in scenarios with a small number of pins.

[0070] Furthermore, in one embodiment, the first valid flag signal can indicate the validity of the first data signal by a level state. For example, the first valid flag signal may include a first level state and a second level state. When the first valid flag signal is in the first level state, the first data signal is invalid, and when the first valid flag signal is in the second level state, the first data signal is valid.

[0071] For example, when the first valid flag signal is in a low level state, the first data signal can be marked as invalid, and when the first valid flag signal is in a high level state, the first data signal can be marked as valid.

[0072] The responding end can determine the validity of the first data signal through the first valid flag signal, and when the first data signal is valid, it samples and parses it based on the first clock signal and performs the corresponding access operation.

[0073] For example, please refer to Figure 3 , Figure 3 This is a schematic diagram of one embodiment of the transmission signal of the initiator of this application. For example... Figure 3 As shown, the initiating end synchronously sends the first valid flag signal REQ_VALID, the first clock signal REQ_CLK, and the first data signal REQ_DATA. When REQ_VALID switches to a high level, REQ_DATA sequentially transmits the command field, the address field, and the request data field.

[0074] S103. The responding end sends a second valid flag signal, a second clock signal, and a second data signal configured with a target bit width to the initiating end through a general configuration interface.

[0075] The second valid flag signal is used to describe the validity period of the second data signal, which includes a result status field within the validity period.

[0076] S104. The initiating end obtains the access result by parsing the second data signal based on the second valid flag signal and the second clock signal.

[0077] After the corresponding access operation is completed, the responding end can return a signal to the initiating end, which may include the responding end's second clock signal, second valid flag signal, and second data signal.

[0078] Similar to the signal sent by the initiating end, the responding end uses an in-path clock scheme, synchronously sending its own second clock signal when returning data. The initiating end can parse the second data signal based on the second clock signal and the second valid flag signal to obtain the access result.

[0079] Specifically, in one implementation, the result status field may include a returned data length flag, a returned status flag, and a custom returned flag. The returned data length flag describes the total number of returned data, the returned status flag describes the access status, and the custom returned flag allows the user to customize the access returned information.

[0080] The access status can include access success, access error, or access timeout.

[0081] In one implementation, the second data signal also includes a return data field that is within the validity period.

[0082] Similar to the transmit data length flag, in one implementation, the return data length flag can be used to describe the length of the return data field as a multiple of a preset field length, which is an integer multiple of the target bit width. This allows a large range of return data lengths to be represented with fewer bits, adapting to transmission requirements under all bit width configurations, and enabling the result status field to be transmitted within a single clock cycle.

[0083] Furthermore, in one embodiment, the result status field can be transmitted within the first clock cycle of the validity period of the second data signal, that is, the result status field can be located at the very beginning of the validity period of the second data signal.

[0084] Based on the above scheme, the initiating end only needs to perform a single sampling of the second data signal when the second valid flag signal is valid to obtain complete result status information, which helps to improve the access rate.

[0085] Furthermore, similar to the sent data field, when the total length of the returned data field is greater than the target bit width, the returned data field can be split according to the target bit width and transmitted sequentially within the clock cycle of the continuous first clock signal.

[0086] For example, when the target bit width is 16-bit, the structure of the second data signal can be as follows: Figure 4 As shown, Figure 4 This is a schematic diagram of the data format of a second data signal embodiment of this application.

[0087] like Figure 4As shown, in this embodiment, the return data length flag AckLength occupies 8 bits, the return status flag Status occupies 4 bits, and the custom return flag AckInfo occupies 4 bits, for a total of 16 bits, which can be transmitted completely within one clock cycle; the return data field can be divided into N data according to the preset field length of 32-bit, and each data is divided into low-order data and high-order data according to 16-bit.

[0088] Furthermore, similar to the first valid flag signal, the second valid flag signal can also indicate the validity of the first data signal through its level state. For example, the second valid flag signal may include a first level state and a second level state. When the second valid flag signal is in the first level state, the second data signal is invalid, and when the second valid flag signal is in the second level state, the second data signal is valid.

[0089] For example, when the second valid flag signal is in a low level state, the second data signal can be marked as invalid, and when the second valid flag signal is in a high level state, the second data signal can be marked as valid.

[0090] The initiating end can determine the validity of the second data signal by judging the second valid flag signal, and when the second data signal is valid, it can sample and parse based on the second clock signal to obtain the access result.

[0091] For example, please refer to Figure 5 , Figure 5 This is a schematic diagram of one embodiment of the return signal from the response end of this application. For example... Figure 5 As shown, the response end synchronously sends the second valid flag signal ACK_VALID, the second clock signal ACK_CLK, and the second data signal ACK_DATA. When ACK_VALID switches to a high level, ACK_DATA sequentially transmits the result status field and the return data field.

[0092] Based on the second data signal mentioned above, the data format can be automatically adjusted according to the target bit width to meet the needs of different application scenarios. For example, a larger data transmission bit width can be set on interfaces with high performance requirements, while a smaller data transmission bit width can be set in places where there are no performance requirements but the interface signal bit width needs to be reduced, such as in scenarios with a small number of pins.

[0093] Meanwhile, when the first and second data signals are based on the automatic bit-width matching format, it does not affect the parsing operation of the signal by the responding end and the initiating end. Thus, the general configuration interface meets the needs of different working scenarios, effectively simplifies the chip design and verification process, and improves the chip's working stability.

[0094] Based on the access methods described above, by defining standardized interface interaction processes, they can be applied to various register access scenarios such as chip external device access, chip internal register access, chip-to-chip communication, and ATE chip testing. There is no need to design multiple communication protocols for different scenarios, which reduces the workload of protocol adaptation, logic development and functional verification from the root.

[0095] The general configuration interface supports configurable target bit width, which can flexibly set the data transmission bit width according to actual needs. In high-performance scenarios, a large bit width can be configured to improve the transmission rate, while in scenarios with limited pins and channels, a small bit width can be configured to reduce the number of interface signals, achieving flexible adaptation to performance, resources, and application scenarios, and strong compatibility.

[0096] In addition, data transmission is completed by using a clock along with a valid flag signal. All data and control signals are sampled synchronously by the corresponding clock, avoiding the clock domain risk and sampling instability issues of asynchronous interfaces. The interface timing logic is simple, requiring no complex initialization process. It can work normally after the chip is powered on and reset, making it particularly suitable for scenarios with high startup speed requirements, such as chip power-on initialization and ATE testing.

[0097] Furthermore, this application also provides an access system employing the access method of any of the above embodiments. The access system includes an initiating end and a responding end connected through a universal configuration interface, wherein the universal configuration interface has a configurable bit width parameter to determine the target bit width of the universal configuration interface.

[0098] In one implementation, please refer to Figure 6 , Figure 6 This is a schematic diagram of one implementation of the access system based on the general configuration interface of this application.

[0099] like Figure 6 As shown, in this embodiment, the initiating end is an external device of the chip, such as an external ATE test device or an external CPU; the responding end is the register module to be accessed inside the chip, namely internal module A and internal module B in the figure.

[0100] External devices communicate with the chip's internal Demux and MUX modules through the on-chip register access interface. The Demux module distributes signals sent by the initiator to internal module A or internal module B based on their addresses. The MUX module merges the results returned by internal modules A and B into a single stream that is returned to the external device via the on-chip register access interface.

[0101] In this embodiment, the external device of the chip is connected to the on-chip register access interface through a bidirectional pin, and then the first data signal and the second data signal are transmitted bidirectionally at different times through a single pin, as shown by the signal DATA in the figure, in order to save pin resources.

[0102] In other implementations, external devices can also send signals to the on-chip register access interface via a dedicated pin and receive signals from the on-chip register access interface via another dedicated pin, thus enabling read and write access to registers.

[0103] Based on the above access system, unified and efficient access to the internal register modules of the chip can be achieved by external devices. Through a universal configuration interface with parameterizable bit width and standardized signal format design, it can simultaneously adapt to the high-speed configuration access of external CPUs and the low pin count testing requirements of ATE test equipment. In CPU access scenarios, a wider data bit width can be configured to obtain high-performance transmission capabilities, while in ATE testing scenarios, a narrower data bit width can be configured to minimize test channel occupancy.

[0104] This system uses a unified interface protocol to replace multiple independent interfaces such as SPI, I2C, and MDIO in traditional solutions, which greatly reduces the repetitive workload of chip design and verification and improves system reliability. At the same time, through bidirectional pin reuse design, it effectively reduces chip packaging cost and PCB design complexity.

[0105] In another implementation, please refer to Figure 7 , Figure 7 This is a schematic diagram of another implementation of the access system based on the general configuration interface of this application.

[0106] like Figure 7 As shown, in this embodiment, the initiating end is the first core and the responding end is the accessed register module of the second core.

[0107] The first core sends signals to the access register module through the access interface of the second core and receives feedback signals, thereby realizing the access operation of the register module to be accessed.

[0108] Based on the above access system, low-latency and high-reliability access to the register modules to be accessed between chips within a multi-chip can be achieved. The universal configuration interface does not rely on complex PHY components and initialization processes. The chip can immediately enter the working state after power-on reset, perfectly meeting the core requirement that the basic initialization must be completed through the original simple path at the initial power-on stage of the chip. By flexibly configuring the interface data bit width, the optimal balance between the number of interconnect pins between chips and transmission performance can be achieved, significantly reducing the number of high-speed interconnect signals required for multi-chip packaging. In addition, the unified interface protocol eliminates the protocol adaptation overhead between different chips, greatly simplifying the integration difficulty of multi-chip systems, supporting bidirectional peer-to-peer communication between chips, and flexibly adapting to various complex multi-chip architectures.

[0109] The access system based on the above implementation methods can adapt to different bit width requirements by modifying parameters, reducing compatibility issues. The initiating and responding ends follow the same set of signal specifications, and no additional protocol conversion is required between different functional modules and different chips, reducing the difficulty of system integration, reducing compatibility failures caused by the mixing of multiple interfaces, and improving the reliability of chip operation. At the same time, it is compatible with various hardware deployment forms and can be flexibly deployed in scenarios such as external devices and internal components of the chip, and between different chips, with a wide range of applications.

[0110] It will be apparent to those skilled in the art that this disclosure is not limited to the details of the exemplary embodiments described above, and that this disclosure can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of this disclosure is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within this disclosure. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0111] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. An access method based on a generic configuration interface, characterized in that, The system is applied to an access system, which includes an initiating end and a responding end connected through a general configuration interface. The general configuration interface has a configurable bit width parameter to determine the target bit width of the general configuration interface. The access methods include: In response to the access request, the initiating end sends a first valid flag signal, a first clock signal, and a first data signal configured with the target bit width to the responding end through the general configuration interface. The first valid flag signal is used to describe the validity period of the first data signal. The first data signal includes a command field and an address field that are within the validity period. The response terminal parses the first data signal and performs an access operation based on the first valid flag signal and the first clock signal; The responding end sends a second valid flag signal, a second clock signal, and a second data signal configured with the target bit width to the initiating end through the general configuration interface. The second valid flag signal is used to describe the validity period of the second data signal, and the second data signal includes a result status field within the validity period. The initiating end obtains the access result by parsing the second data signal based on the second valid flag signal and the second clock signal.

2. The access method according to claim 1, characterized in that, The command field is transmitted within the first clock cycle of the validity period of the first data signal; and / or, The result status field is transmitted within the first clock cycle of the validity period of the second data signal.

3. The access method according to claim 1, characterized in that, The first valid flag signal includes a first level state and a second level state. When the first valid flag signal is in the first level state, the first data signal is invalid. When the first valid flag signal is in the second level state, the first data signal is valid. And / or, The second valid flag signal includes a first level state and a second level state. When the second valid flag signal is in the first level state, the second data signal is invalid. When the second valid flag signal is in the second level state, the second data signal is valid.

4. The access method according to claim 1, characterized in that, The command field includes a data length flag, an operation type flag, and a custom request flag. The data length flag describes the total amount of operation data, the operation type flag describes the operation type, and the custom request flag allows users to customize access request information.

5. The access method according to claim 4, characterized in that, The first data signal also includes a request data field within its validity period, wherein the total number of operation data is used to describe the multiple of the total length of the address field and the request data field relative to a preset field length, wherein the preset field length is an integer multiple of the target bit width; and / or, The operation type includes one of the following: read operation, write operation, and atomic operation.

6. The access method according to claim 1, characterized in that, The result status field includes a returned data length flag, a returned status flag, and a custom returned flag. The returned data length flag describes the total number of returned data, the returned status flag describes the access status, and the custom returned flag allows users to customize the access returned information.

7. The access method according to claim 6, characterized in that, The second data signal further includes a returned data field, wherein the total number of returned data is used to describe the multiple of the length of the returned data field relative to a preset field length, wherein the preset field length is an integer multiple of the target bit width; and / or, The access status includes access success, access error, or access timeout.

8. The access method according to claim 1, characterized in that, The first data signal also includes a request data field within its validity period. When the total length of the address field and / or the request data field is greater than the target bit width, the address field and / or the request data field are split according to the target bit width and transmitted sequentially within the clock cycles of the consecutive first clock signals; and / or, The second data signal also includes a return data field within the validity period. When the total length of the return data field is greater than the target bit width, the return data field is split according to the target bit width and transmitted sequentially within the clock cycle of the continuous first clock signal.

9. An access system based on a universal configuration interface, characterized in that, An access operation is performed using any one of the access methods described in claims 1 to 8. The access system includes an initiating end and a responding end connected via a general configuration interface, wherein the general configuration interface has a configurable bit width parameter for determining the target bit width of the general configuration interface.

10. The access system according to claim 9, characterized in that, The initiating end is an external CPU or external test equipment, and the responding end is the accessed register module inside the chip; or, The initiating end is the first core, and the responding end is the register module to be accessed inside the second core.

11. The access system according to claim 9, characterized in that, The initiating end is connected to the responding end via a bidirectional pin to transmit the first data signal and the second data signal bidirectionally at different time periods.

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