Method and apparatus for information synchronization in dual master system

Abstract

This application relates to an information synchronization method and apparatus for a dual-master control system. The method includes: a primary master control device allocating a corresponding FPGA memory identifier to a dynamic entry; the primary master control device generating dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier; the primary master control device synchronizing the dynamic synchronization information to a backup master control device in real time; the backup master control device performing a consistency check on the dynamic synchronization information according to a preset verification algorithm; and when the consistency check fails, the backup master control device initiating a full synchronization request to the primary master control device to obtain complete full synchronization information. The information synchronization method and apparatus for a dual-master control system disclosed in this application can maintain normal business operation traffic after the backup master control device takes over, while ensuring the consistency of dynamic information, in the event of a primary master control failure.

Description

Technical Field

[0001] This application relates to the field of computer information processing, and more specifically, to an information synchronization method and apparatus for a dual-master control system. Background Technology

[0002] In a dual-master environment, the primary and backup master controllers must ensure complete consistency in their configuration and dynamically generated information. Inconsistencies may occur if the primary master controller fails and the backup master controller takes over the equipment, potentially causing service disruptions.

[0003] For example, a packet filtering policy targeting a specific IP address is configured on the primary controller, generating a static policy ID and a corresponding FPGA memory ID. Due to some unpredictable factor (such as synchronization failure or data loss), this policy fails to synchronize with the backup primary controller, resulting in the backup primary controller not requesting the corresponding static policy ID and FPGA memory ID. When the primary primary controller triggers a switchover due to an abnormal failure, the backup primary controller, lacking this blocking policy, will encounter maintenance anomalies when attempting to add or delete packet filtering policies after taking over the equipment due to the misalignment of the static policy ID and FPGA memory ID sequences. Ultimately, this anomaly will cause policy information corruption in the FPGA chip, leading to packet loss or service interruption, resulting in incalculable losses for the customer's actual application scenario.

[0004] Therefore, in a dual-master scenario, static configurations and dynamic information must be synchronized in real time, and maintenance personnel must be notified via log reporting, email, or SMS when inconsistencies are detected.

[0005] Existing technical solutions can achieve real-time synchronization of static configurations, but fail to synchronize FPGA memory IDs. When the backup master controller takes over the device, existing solutions typically use a method of dynamically generating information by requesting a full amount from the master controller. However, this full synchronization method, before data reception is complete, is prone to causing service traffic to mis-hit policies due to incomplete dynamic information, leading to packet loss or network outages.

[0006] Therefore, a new method and device for information synchronization in a dual-master control system is needed.

[0007] The information disclosed in the background section is only intended to enhance the understanding of the background of this application, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0008] In view of this, this application provides an information synchronization method and apparatus for a dual master control system, which can maintain normal business operation traffic after the backup master control takes over when the master control fails, while ensuring dynamic information consistency.

[0009] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0010] According to one aspect of this application, an information synchronization method for a dual-master control system is proposed. The method includes: a primary master control device allocating a corresponding FPGA memory identifier to a dynamic entry; the primary master control device generating dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier; the primary master control device synchronizing the dynamic synchronization information to a backup master control device in real time; the backup master control device performing a consistency check on the dynamic synchronization information according to a preset verification algorithm; and when the consistency check fails, the backup master control device initiating a full synchronization request to the primary master control device to obtain complete full synchronization information.

[0011] In one exemplary embodiment of this application, the method further includes: when the consistency check passes, the backup master control device stores the mapping relationship between the dynamic entry and the FPGA memory identifier.

[0012] In one exemplary embodiment of this application, the method further includes: when the main control device fails, the backup control device takes over the device services based on the dynamically obtained entries and FPGA memory identifiers.

[0013] In one exemplary embodiment of this application, the main control device allocates a corresponding FPGA memory identifier for the dynamic table entry, and further includes: the main control device sending the dynamic table entry to the FPGA chip.

[0014] In one exemplary embodiment of this application, the master control device generates dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier, including: the master control device generates the dynamic synchronization information by hash calculation based on the dynamic entry and the corresponding FPGA memory identifier.

[0015] In one exemplary embodiment of this application, the main control device generates the dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier through hash calculation, including: the main control device uses a hash algorithm to perform calculations on the FPGA memory identifier and the dynamic entry to obtain a hash result; performs an XOR operation on the hash result and a global hash value to obtain verification information; and generates the dynamic synchronization information through the verification information, the FPGA memory identifier, and the dynamic entry.

[0016] In one exemplary embodiment of this application, the backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm, including: the backup master control device calculates a local verification value using the received dynamic entry and the FPGA memory identifier; and compares the local verification value with the verification information carried in the dynamic synchronization information to perform consistency verification.

[0017] In one exemplary embodiment of this application, the backup master control device stores the mapping relationship between the dynamic entries and the FPGA memory identifier, including: the backup master control queries the local master configuration database according to the configuration name in the dynamic synchronization information, obtains the corresponding static configuration information, and generates the corresponding static configuration identifier; and stores the static configuration identifier, the dynamic entries, and the FPGA identifier in the backup master control memory in association.

[0018] In one exemplary embodiment of this application, the backup master control device takes over the device service based on the synchronously obtained dynamic entries and FPGA memory identifiers, including: the backup master control device directly performs management operations on the corresponding dynamic entries in the FPGA chip according to the synchronously obtained FPGA memory identifiers.

[0019] According to one aspect of this application, an information synchronization device for a dual-master control system is proposed. The device includes: an identification module for a primary master control device to allocate a corresponding FPGA memory identifier to a dynamic entry; an information module for the primary master control device to generate dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier; a synchronization module for the primary master control device to synchronize the dynamic synchronization information to a backup master control device in real time; a verification module for the backup master control device to perform consistency verification on the dynamic synchronization information according to a preset verification algorithm; and a full synchronization module for the backup master control device to initiate a full synchronization request to the primary master control device to obtain complete full synchronization information when the consistency verification fails.

[0020] According to one aspect of this application, an electronic device is provided, comprising: one or more processors; a storage device for storing one or more programs; and, when the one or more programs are executed by the one or more processors, causing the one or more processors to implement the method as described above.

[0021] According to one aspect of this application, a computer-readable medium is provided having a computer program stored thereon that, when executed by a processor, implements the method described above.

[0022] According to the information synchronization method and apparatus for a dual-master control system of this application, the primary master control device allocates corresponding FPGA memory identifiers to dynamic entries; the primary master control device generates dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers; the primary master control device synchronizes the dynamic synchronization information to the backup master control device in real time; the backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm; when the consistency verification fails, the backup master control device initiates a full synchronization request to the primary master control device to obtain complete full synchronization information. This method ensures the consistency of dynamic information and maintains normal business operation traffic after the backup master control takes over in the event of a primary master control failure.

[0023] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0024] The above and other objects, features, and advantages of this application will become more apparent from the detailed description of exemplary embodiments with reference to the accompanying drawings. The drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0025] Figure 1 This is a flowchart illustrating an information synchronization method for a dual-master system according to an exemplary embodiment.

[0026] Figure 2 This is a flowchart illustrating an information synchronization method for a dual-master system according to another exemplary embodiment.

[0027] Figure 3 This is a flowchart illustrating an information synchronization method for a dual-master system according to another exemplary embodiment.

[0028] Figure 4 This is a block diagram illustrating an information synchronization device for a dual master control system according to an exemplary embodiment.

[0029] Figure 5 This is a block diagram illustrating an electronic device according to an exemplary embodiment.

[0030] Figure 6 This is a block diagram illustrating a computer-readable medium according to an exemplary embodiment. Detailed Implementation

[0031] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0032] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0033] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.

[0034] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0035] It should be understood that although the terms first, second, third, etc., may be used herein to describe various components, these components should not be limited by these terms. These terms are used to distinguish one component from another. Therefore, the first component discussed below may be referred to as the second component without departing from the teachings of this application. As used herein, the term "and / or" includes all combinations of any one and more of the associated listed items.

[0036] Those skilled in the art will understand that the accompanying drawings are merely schematic diagrams of exemplary embodiments, and the modules or processes in the drawings are not necessarily essential for implementing this application, and therefore cannot be used to limit the scope of protection of this application.

[0037] The technical abbreviations used in this application are explained as follows: Dual main control: This refers to equipping two main control boards in one equipment chassis. Only one main control board provides control and management functions. When the main main control board fails, the backup main control board immediately takes over. The purpose is to provide hardware redundancy and minimize business interruption caused by single point of failure.

[0038] The dual-master design is primarily intended to meet the stringent requirements of networks, especially core networks, for high reliability and high availability.

[0039] Eliminating single points of failure: The main control board is the "brain" of the device, responsible for running routing protocols, managing configurations, and directing data forwarding. If the main control board of a single-controller device fails, the entire device may be paralyzed. Dual-controller systems fundamentally solve this problem.

[0040] Achieve seamless switching: When the primary controller fails, the backup controller can take over the service within seconds or even milliseconds, ensuring uninterrupted network forwarding and seamless operation for upper-layer applications.

[0041] Improved maintenance convenience: Supports hot-swapping of the main control board, allowing the main control board to be replaced or upgraded without shutting down the machine or affecting business operations.

[0042] Dual master controllers are one of the cornerstone technologies for building highly reliable enterprise and carrier networks. Essentially, they provide a robust layer of "insurance" for critical services through hardware redundancy and intelligent failover mechanisms.

[0043] Dynamic Information Synchronization: As described above, in a dual-master control environment, the primary master controller provides control and management functions. If the primary master controller fails, the backup master controller takes over device management. This requires complete consistency in the configuration and dynamic information on both master controllers. The dynamic information includes the FPGA chip information jointly managed by both master controllers. This ensures that the FPGA information maintained by the CPU after the backup master controller takes over the device is consistent with the information stored in the FPGA chip. Under normal conditions, control and management are entirely handled by the primary master controller. In this case, the configuration and dynamic information of the primary master controller need to be synchronized to the backup master controller in real time, and the configuration and dynamic information of both master controllers must be completely consistent. This guarantees normal device function during dual-master switchover.

[0044] Figure 1 This is a flowchart illustrating an information synchronization method for a dual-master system according to an exemplary embodiment. The information synchronization method 10 for a dual-master system includes at least steps S102 to S110.

[0045] like Figure 1 As shown, in S102, the main control device allocates a corresponding FPGA memory identifier for the dynamic table entry. It also includes: the main control device sending the dynamic table entry to the FPGA chip.

[0046] For example, after receiving a static configuration at the control level, the main control device generates dynamic entries based on the corresponding configuration content and dynamically requests corresponding FPGA memory identifiers for these dynamic entries. The FPGA memory identifier identifies the target storage location in the FPGA chip, allowing the FPGA chip to write the corresponding dynamic entry into the specified memory area based on the FPGA memory identifier. The dynamic entry can be, for example, a packet filtering entry, an access control entry, a forwarding entry, or a policy entry. After generating the dynamic entry, the main control device can send the dynamic entry and its corresponding FPGA memory identifier to the FPGA chip to form entry information, enabling the FPGA chip to maintain the corresponding dynamic entry information based on the FPGA memory identifier.

[0047] For example, the main control device fetches static configurations M, N, and P, and generates corresponding static configuration identifiers id-m, id-n, and id-p respectively; simultaneously, it dynamically generates corresponding dynamic table entries table-m, table-n, and table-p, and requests corresponding FPGA memory identifiers table-mid, table-nid, and table-pid for each dynamic table entry. Then, the main control device sends {id-m, table-mid, table-m}, {id-n, table-nid, table-n}, and {id-p, table-pid, table-p} to the FPGA chip, so that the FPGA chip stores the corresponding dynamic table entries in the memory locations corresponding to the FPGA memory identifiers.

[0048] In S104, the master control device generates dynamic synchronization information based on the dynamic table entry and the corresponding FPGA memory identifier. More specifically, the master control device generates the dynamic synchronization information through hash calculation based on the dynamic table entry and the corresponding FPGA memory identifier.

[0049] For example, the primary control device maintains a first global hash information, Hash-Master, and the secondary control device maintains a second global hash information, Hash-Slave, with both initial values ​​of 0. When generating dynamic synchronization information, the primary control device can use a hash algorithm to calculate the hash result from the FPGA memory identifier and dynamic entries, and further combine this with the currently maintained global hash information to generate verification information. Then, the primary control device uses the verification information, the FPGA memory identifier, and the dynamic entries to construct the dynamic synchronization information.

[0050] In one embodiment, the hash algorithm may be the jhash algorithm, where jhash(a,b) represents a hash operation on data a and b. The main control device can generate corresponding verification information based on FPGA memory identifiers and dynamic entries, for example: HM = Hash-Master^jhash(table-mid, table-m); HN = Hash-Master^jhash(table-nid, table-n); HP = Hash-Master^jhash(table-pid, table-p).

[0051] Then, the main control device generates the corresponding dynamic synchronization information: {Name M, HM, table-mid, table-m}; {name N, HN, table-nid, table-n}; {name P, HP, table-pid, table-p}.

[0052] The name information carried in the dynamic synchronization information is used to identify the corresponding static configuration.

[0053] In S106, the main control device synchronizes the dynamic synchronization information to the backup control device in real time.

[0054] For example, when the main control device adds, deletes, or modifies dynamic entries, it generates corresponding dynamic synchronization information in real time and synchronizes it to the backup control device through the main-backup synchronization channel to ensure that the dynamic entry information maintained by the main control device and the backup control device, as well as the FPGA memory identifier, remain consistent.

[0055] In S108, the backup master control device performs a consistency check on the dynamic synchronization information according to a preset verification algorithm. For example, the backup master control device uses the received dynamic entry and the FPGA memory identifier to calculate a local verification value; and compares the local verification value with the verification information carried in the dynamic synchronization information to perform a consistency check.

[0056] For example, after receiving the synchronization information {name M, HM, table-mid, table-m}, the backup master device calculates the local checksum using the same hash algorithm as the master device, based on the synchronized table-mid and table-m: HM-S = Hash-Slave^jhash(table-mid, table-m).

[0057] Then, the local verification value HM-S is compared with the verification information HM in the synchronization information.

[0058] If HM-S is the same as HM, it indicates that the current synchronization information is correct and there is no loss of synchronization data. If HM-S is different from HM, it indicates that there is an anomaly in the synchronization information or that synchronization data has been lost.

[0059] Similarly, the backup master control device can also perform the above consistency verification process on the synchronization information corresponding to name N and name P.

[0060] In S110, when the consistency check fails, the backup master control device initiates a full synchronization request to the master master control device to obtain complete full synchronization information.

[0061] For example, when the backup master control device detects an anomaly in the synchronization information or loss of synchronization data, it can request all currently maintained dynamic table entries and all FPGA memory identifier information from the master control device, and rebuild the local dynamic information database based on the received full synchronization information to restore the correspondence between dynamic table entries and FPGA memory identifiers.

[0062] In one embodiment, the method further includes: when the primary control device fails, the backup control device takes over the device services based on the synchronously obtained dynamic entries and FPGA memory identifiers. More specifically, the backup control device directly performs management operations on the corresponding dynamic entries in the FPGA chip based on the synchronously obtained FPGA memory identifiers.

[0063] For example, when a primary control device malfunctions and causes a switchover, the backup control device, having already synchronized with the dynamic entries and corresponding FPGA memory identifiers in real time, maintains an FPGA memory identifier consistent with the one in the FPGA chip. In this case, when the backup control device performs operations to add, delete, or modify dynamic entries, it does not need to re-apply for FPGA memory identifiers. This avoids confusion in the dynamic entry information within the FPGA chip due to inconsistent FPGA memory identifiers, further preventing packet loss or service interruption caused by service traffic mis-hitting policies.

[0064] According to the information synchronization method for a dual-master control system of this application, the primary master control device allocates corresponding FPGA memory identifiers to dynamic entries; the primary master control device generates dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers; the primary master control device synchronizes the dynamic synchronization information to the backup master control device in real time; the backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm; when the consistency verification fails, the backup master control device initiates a full synchronization request to the primary master control device to obtain complete full synchronization information. This method ensures the consistency of dynamic information and maintains normal business operation traffic after the backup master control device takes over when the primary master control device fails.

[0065] This application proposes an information synchronization method for a dual-master control system, applicable to network devices, switching devices, or security devices employing a master master control device and a backup master control device architecture. In a dual-master control operating environment, to ensure service continuity after master-slave failover, it is necessary to ensure that the dynamic information maintained by the master master control device and the backup master control device remains consistent, especially ensuring that the FPGA memory identifier maintained by the master and backup CPUs is consistent with the actual active memory identifier in the FPGA chip.

[0066] In this application, when generating dynamic entries, the primary control device allocates an FPGA memory identifier for the corresponding dynamic entry and sends the dynamic entry and its corresponding FPGA memory identifier to the FPGA chip. Simultaneously, the primary control device generates dynamic synchronization information based on the dynamic entries and the FPGA memory identifier, and synchronizes it to the backup control device in real time. Upon receiving the dynamic synchronization information, the backup control device performs a consistency check on the information using a preset hash algorithm. If the check passes, it stores the mapping relationship between the dynamic entries and the FPGA memory identifier; if the check fails, it initiates a full synchronization request to the primary control device to re-acquire the complete dynamic information.

[0067] This application further introduces an incremental consistency verification mechanism based on hash operations to achieve rapid verification and anomaly detection of dynamic synchronization information. When a synchronization anomaly or data loss is detected, the backup master control device can promptly trigger a full synchronization recovery mechanism, thereby ensuring the continuous consistency of the dynamic information maintained by the master and backup master control devices.

[0068] In this way, after the main control device fails and a master-slave switch is performed, the backup control device can directly perform add, delete or modify operations on the dynamic entries in the FPGA chip based on the synchronized FPGA memory identifier, without having to reapply for FPGA memory identifiers. This effectively avoids problems such as FPGA entry information confusion, service traffic mishitting of policies, traffic packet loss or service interruption caused by inconsistent FPGA memory identifiers, thus improving the reliability and service continuity of the dual master control system.

[0069] It should be clearly understood that this application describes how specific examples are formed and used, but the principles of this application are not limited to any details of these examples. Rather, based on the teachings of the disclosure of this application, these principles can be applied to many other embodiments.

[0070] Figure 2 This is a flowchart illustrating an information synchronization method for a dual-master system according to another exemplary embodiment. Figure 2 The process shown in step 20 is... Figure 1 The process shown in the diagram is described in detail in step S104, "The main control device generates dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier."

[0071] like Figure 2 As shown, in S202, the main control device uses a hash algorithm to perform calculations on the FPGA memory identifier and the dynamic table entry to obtain a hash result. For example, the main control device may call a preset hash algorithm module to perform joint calculations on the FPGA memory identifier and the dynamic table entry to generate a corresponding hash result for subsequent consistency verification.

[0072] In S204, the hash result is XORed with the global hash value to obtain the verification information. For example, the master control device XORs the currently calculated hash result with the currently maintained first global hash information to generate the corresponding verification information, thereby achieving fast verification of the consistency of dynamic synchronization information with a small amount of data.

[0073] In S206, the dynamic synchronization information is generated using the verification information, the FPGA memory identifier, and the dynamic table entry. For example, the master control device encapsulates the configuration name, verification information, FPGA memory identifier, and dynamic table entry into a dynamic synchronization message and sends it to the backup master control device.

[0074] Figure 3 This is a flowchart illustrating an information synchronization method for a dual-master system according to another exemplary embodiment. Figure 3 The process shown in step 30 is... Figure 2 The process shown in the diagram includes a detailed description of S106, "The backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm."

[0075] like Figure 3 As shown, in S302, the backup master control device uses the received dynamic entry and the FPGA memory identifier to calculate the local check value.

[0076] For example, the backup master device can call the same hash algorithm as the master master device to perform hash operations on the received dynamic entries and FPGA memory identifiers, and combine them with the second global hash information to generate a local check value.

[0077] In S304, the local check value is compared with the check information carried in the dynamic synchronization information to perform a consistency check.

[0078] If the comparison results are the same, it indicates that the synchronization information is complete and no data loss occurred during the synchronization process; If the comparison results are different, it indicates that the synchronization information is abnormal or that data was lost during the synchronization process.

[0079] In S306, when the consistency check fails, the backup master control device initiates a full synchronization request to the master master control device to obtain complete full synchronization information.

[0080] For example, the backup master control device sends a full synchronization request message to the master master control device. In response to the full synchronization request message, the master master control device sends all currently maintained dynamic entries, all FPGA memory identifiers, and corresponding associations to the backup master control device.

[0081] In S308, when the consistency check passes, the backup master device stores the mapping relationship between the dynamic table entry and the FPGA memory identifier.

[0082] For example, the backup master controller queries the local master configuration database based on the configuration name in the dynamic synchronization information to obtain the corresponding static configuration information and generate the corresponding static configuration identifier; the static configuration identifier, dynamic table entry and FPGA identifier are associated and stored in the backup master controller memory.

[0083] Furthermore, the standby master control device can establish an association mapping table between static configuration identifiers, dynamic entries, and FPGA memory identifiers for dynamic entry management after subsequent master-slave switchover.

[0084] This solution effectively ensures the consistency between the FPGA ID maintained by the dual-master CPU and the ID maintained by the FPGA chip through real-time synchronization of FPGA IDs. Furthermore, during the synchronization process, the JHASH algorithm is used to hash incremental data in real time, efficiently detecting the consistency of dynamic information between the two master controllers. If inconsistencies are detected, a full synchronization is requested, further ensuring the consistency of the dual-master controller configuration. Under the premise of ensuring dynamic information consistency, the backup master controller will not affect the ongoing service traffic after the primary master controller fails and takes over.

[0085] Those skilled in the art will understand that all or part of the steps of the above embodiments are implemented as a computer program executed by a CPU. When the computer program is executed by the CPU, it performs the functions defined by the method provided in this application. The program can be stored in a computer-readable storage medium, such as a read-only memory, a magnetic disk, or an optical disk.

[0086] Furthermore, it should be noted that the above figures are merely illustrative representations of the processes included in the method according to exemplary embodiments of this application, and are not intended to be limiting. It is readily understood that the processes shown in the above figures do not indicate or limit the temporal order of these processes. Additionally, it is readily understood that these processes may be executed synchronously or asynchronously, for example, in multiple modules.

[0087] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0088] Figure 4 This is a block diagram illustrating an information synchronization device for a dual-master system according to an exemplary embodiment. Figure 4 As shown, the information synchronization device 40 for the dual master control system includes: an identification module 402, an information module 404, a synchronization module 406, a verification module 408, and a full-data module 410.

[0089] The identification module 402 is used by the main control device to allocate a corresponding FPGA memory identifier to the dynamic table entry; the identification module 402 is also used by the main control device to send the dynamic table entry to the FPGA chip.

[0090] The information module 404 is used by the main control device to generate dynamic synchronization information based on the dynamic table entry and the corresponding FPGA memory identifier; the information module 404 is also used by the main control device to generate the dynamic synchronization information through hash calculation based on the dynamic table entry and the corresponding FPGA memory identifier.

[0091] Synchronization module 406 is used by the main control device to synchronize the dynamic synchronization information to the backup control device in real time; The verification module 408 is used by the backup master control device to perform consistency verification on the dynamic synchronization information according to a preset verification algorithm; the verification module 408 is also used by the backup master control device to calculate a local verification value using the received dynamic entry and the FPGA memory identifier; and to compare the local verification value with the verification information carried in the dynamic synchronization information to perform consistency verification.

[0092] The full synchronization module 410 is used to initiate a full synchronization request from the backup master control device to the master master control device to obtain complete full synchronization information when the consistency check fails.

[0093] According to the information synchronization device for a dual-master control system of this application, the primary master control device allocates corresponding FPGA memory identifiers to dynamic entries; the primary master control device generates dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers; the primary master control device synchronizes the dynamic synchronization information to the backup master control device in real time; the backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm; when the consistency verification fails, the backup master control device initiates a full synchronization request to the primary master control device to obtain complete full synchronization information. This method ensures the consistency of dynamic information and maintains normal business operation traffic after the backup master control takes over in the event of a primary master control failure.

[0094] Figure 5 This is a block diagram illustrating an electronic device according to an exemplary embodiment.

[0095] The following reference Figure 5 To describe an electronic device 500 according to this embodiment of the present application. Figure 5 The electronic device 500 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0096] like Figure 5 As shown, the electronic device 500 is presented in the form of a general-purpose computing device. The components of the electronic device 500 may include, but are not limited to: at least one processing unit 510, at least one storage unit 520, a bus 530 connecting different system components (including storage unit 520 and processing unit 510), a display unit 540, etc.

[0097] The storage unit stores program code that can be executed by the processing unit 510, causing the processing unit 510 to perform the steps described in this specification according to various exemplary embodiments of this application. For example, the processing unit 510 can perform actions such as... Figure 1 , Figure 2 , Figure 3 The steps are shown in the figure.

[0098] The storage unit 520 may include a readable medium in the form of a volatile storage unit, such as a random access memory unit (RAM) 5201 and / or a cache storage unit 5202, and may further include a read-only memory unit (ROM) 5203.

[0099] The storage unit 520 may also include a program / utility 5204 having a set (at least one) program module 5205, such program module 5205 including but not limited to: an operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0100] Bus 530 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0101] Electronic device 500 can also communicate with one or more external devices 500' (e.g., keyboard, pointing device, Bluetooth device, etc.), enabling users to communicate with devices that interact with electronic device 500, and / or any device (e.g., router, modem, etc.) that allows electronic device 500 to communicate with one or more other computing devices. This communication can be performed via input / output (I / O) interface 550. Furthermore, electronic device 500 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 560. Network adapter 560 can communicate with other modules of electronic device 500 via bus 530. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 500, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0102] From the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software, or by combining software with necessary hardware. Therefore, as... Figure 6 As shown, the technical solution according to the embodiments of this application can be embodied in the form of a software product. The software product can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, mobile hard drive, etc.) or on a network, and includes several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the above-described method according to the embodiments of this application.

[0103] The software product may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: an electrical connection having one or more wires, a portable disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0104] The computer-readable storage medium may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. The readable storage medium may also be any readable medium other than a readable storage medium, capable of transmitting, propagating, or transmitting programs for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0105] Program code for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0106] The aforementioned computer-readable medium carries one or more programs. When these programs are executed by a device, the computer-readable medium performs the following functions: the primary control device allocates a corresponding FPGA memory identifier for a dynamic entry; the primary control device generates dynamic synchronization information based on the dynamic entry and the corresponding FPGA memory identifier; the primary control device synchronizes the dynamic synchronization information to a backup control device in real time; the backup control device performs a consistency check on the dynamic synchronization information according to a preset verification algorithm; when the consistency check fails, the backup control device initiates a full synchronization request to the primary control device to obtain complete full synchronization information.

[0107] Those skilled in the art will understand that the above modules can be distributed in the device as described in the embodiments, or they can be modified accordingly and placed in one or more devices that are unique to this embodiment. The modules in the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0108] Through the description of the above embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. Therefore, the technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, mobile terminal, or network device, etc.) to execute the methods according to the embodiments of this application.

[0109] Exemplary embodiments of this application have been specifically shown and described above. It should be understood that this application is not limited to the detailed structures, arrangements, or implementation methods described herein; rather, this application is intended to cover various modifications and equivalent arrangements contained within the spirit and scope of the appended claims.

Claims

1. A method for information synchronization in a dual-master control system, characterized in that, include: The main control device assigns a corresponding FPGA memory identifier to each dynamic entry; The main control device generates dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers; The main control device synchronizes the dynamic synchronization information to the backup control device in real time. The backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm; When the consistency check fails, the backup master control device initiates a full synchronization request to the master master control device to obtain complete full synchronization information.

2. The method as described in claim 1, characterized in that, Also includes: When the consistency check passes, the backup master control device stores the mapping relationship between the dynamic table entry and the FPGA memory identifier.

3. The method as described in claim 1, characterized in that, Also includes: When the main control device fails, the backup control device takes over the device's services based on the dynamically obtained entries and FPGA memory identifiers.

4. The method as described in claim 1, characterized in that, The main control device allocates corresponding FPGA memory identifiers for dynamic entries, and also includes: The main control device sends the dynamic entries to the FPGA chip.

5. The method as described in claim 1, characterized in that, The main control device generates dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers, including: The main control device generates the dynamic synchronization information through hash calculation based on the dynamic entries and the corresponding FPGA memory identifiers.

6. The method as described in claim 5, characterized in that, The main control device generates the dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers through hash calculation, including: The main control device uses a hash algorithm to calculate the hash result by operating on the FPGA memory identifier and the dynamic table entry; The hash result is XORed with the global hash value to obtain the verification information. The dynamic synchronization information is generated using the verification information, the FPGA memory identifier, and the dynamic table entry.

7. The method as described in claim 1, characterized in that, The backup master control device performs consistency verification on the dynamic synchronization information according to a preset verification algorithm, including: The backup master control device uses the received dynamic table entry and the FPGA memory identifier to calculate the local check value; The local checksum is compared with the checksum carried in the dynamic synchronization information to perform a consistency check.

8. The method as described in claim 2, characterized in that, The backup master control device stores the mapping relationship between the dynamic entries and the FPGA memory identifiers, including: The backup master controller queries the local master configuration database based on the configuration name in the dynamic synchronization information to obtain the corresponding static configuration information and generate the corresponding static configuration identifier. The static configuration identifier, dynamic entries, and FPGA identifier are associated and stored in the backup master memory.

9. The method as described in claim 3, characterized in that, The backup master control device takes over the device's services based on the dynamically obtained entries and FPGA memory identifiers, including: The backup master control device directly performs management operations on the corresponding dynamic entries in the FPGA chip based on the FPGA memory identifier that has been synchronously obtained.

10. An information synchronization device for a dual-master control system, characterized in that, include: The identifier module is used by the main control device to assign corresponding FPGA memory identifiers to dynamic entries; The information module is used by the main control device to generate dynamic synchronization information based on the dynamic entries and the corresponding FPGA memory identifiers; The synchronization module is used by the main control device to synchronize the dynamic synchronization information to the backup control device in real time; The verification module is used by the backup master control device to perform consistency verification on the dynamic synchronization information according to a preset verification algorithm; The full synchronization module is used to initiate a full synchronization request from the backup master control device to the master master control device to obtain complete full synchronization information when the consistency check fails.

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