Method and apparatus for training a model

Abstract

This invention provides a method and apparatus for training a semiconductor device model. In the method, a training environment is established including a dataset, wherein the dataset associates multiple parameters of the semiconductor device with at least one electrical parameter. States, represented by a set of parameter values, are defined in the training environment. An action is performed by a prediction model to modify at least one value in the set of values. A reward value is calculated based on a reward function configured to guide the prediction model to maximize the electrical parameter under parameter constraints. Violations of parameter constraints are penalized by a penalty that increases non-linearly with the degree of violation. The prediction model is updated based on the reward value. Therefore, design efficiency and accuracy can be significantly improved.

Description

Technical Field

[0001] This invention relates to semiconductor manufacturing, and more particularly, to a method and apparatus for training semiconductor device models. Background Technology

[0002] In the design of high-voltage power semiconductor devices, such as the guard rings surrounding silicon carbide (SiC) MOSFETs, designers must define numerous structural and process parameters. These parameters typically include the number, width, and spacing of the guard rings, as well as the ion implantation dose and energy. The precise combination of these parameters is crucial for achieving the desired breakdown voltage and overall device performance.

[0003] Traditionally, the design process for these devices has relied heavily on Technology Computer-Aided Design (TCAD) software for simulation and verification. This traditional workflow is essentially a "trial and error" approach. Designers typically propose an initial set of parameters, run a TCAD simulation to evaluate the results, and then manually adjust one or more parameters for the next simulation. This iterative process is repeated until the desired device characteristics are achieved.

[0004] However, this traditional approach has significant drawbacks. A single TCAD simulation of a complex high-voltage device can be extremely time-consuming, typically requiring 14 to 17 hours to complete a single set of parameters. Therefore, relying on numerous consecutive simulations can significantly extend product development cycles and delay time-to-market. Summary of the Invention

[0005] This disclosure provides a method and apparatus for training a model.

[0006] According to one or more exemplary embodiments of this disclosure, a processor-implemented model training method is provided. The method includes establishing a training environment comprising a dataset, wherein the dataset associates semiconductor device parameters with at least one outcome electrical parameter. The semiconductor device parameters are for silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistors (MOSFETs). The method further includes defining states within the training environment, wherein the states are represented by a set of values ​​for the semiconductor device parameters. An action is performed by a prediction model to select or modify at least one value within the set of values ​​representing the states. A reward value is then calculated based on a reward function. The reward function is configured to guide the prediction model to maximize the outcome electrical parameter of the semiconductor device and is constrained by parameter constraints on the semiconductor device parameters. Violations of the parameter constraints are penalized by the reward function, the penalty increasing non-linearly with the degree of violation. The method includes updating the prediction model based on the reward value.

[0007] According to one or more exemplary embodiments of the present disclosure, an apparatus including a memory and a processor is provided. The memory is configured to store program code. The processor is coupled to the memory. The processor is configured to load and execute the program code to perform: establishing a training environment including a dataset, wherein the dataset associates semiconductor device parameters with at least one resulting electrical parameter, and the semiconductor device parameters are used by a semiconductor device for a SiC trench MOSFET; defining states within the training environment, wherein the states are represented by a set of values ​​for the semiconductor device parameters; performing actions via a prediction model to select or modify at least one value within the set of values ​​representing the states; calculating a reward value based on a reward function, wherein the reward function is configured to guide the prediction model to maximize the resulting electrical parameter of the semiconductor device and is subject to parameter constraints on the semiconductor device parameters, and violations of the parameter constraints are penalized by the reward function, the penalty increasing non-linearly with the degree of violation; and updating the prediction model based on the reward value. Attached Figure Description

[0008] Figure 1 This is a block diagram of a training model apparatus according to an exemplary embodiment of the present disclosure;

[0009] Figure 2 This is a flowchart of a model training method according to an exemplary embodiment of the present disclosure;

[0010] Figure 3 A schematic diagram illustrating a semiconductor device according to exemplary embodiments of the present disclosure;

[0011] Figure 4 A schematic diagram illustrating the reward function according to an exemplary embodiment of this disclosure;

[0012] Figure 5 A graph illustrating the relationship between the breakdown voltage of a semiconductor device and the ion implantation dose according to exemplary embodiments of the present disclosure;

[0013] Figure 6 A graph showing the learning progress of a reinforcement learning agent according to a first exemplary embodiment of this disclosure;

[0014] Figure 7 A graph showing the learning progress of a reinforcement learning agent according to a second exemplary embodiment of this disclosure;

[0015] Figure 8 A graph showing the learning progress of a reinforcement learning agent according to a third exemplary embodiment of this disclosure;

[0016] Figure 9 A graph showing the learning progress of a reinforcement learning agent according to a fourth exemplary embodiment of this disclosure. Detailed Implementation

[0017] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0018] Figure 1 This is a block diagram of an apparatus 100 for training a model according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 1 Device 100 can be a personal computer, workstation, server, or any electronic device with computing capabilities. Device 100 includes, but is not limited to, memory 110 and processor 120.

[0019] Memory 110 is coupled to processor 120. In some embodiments, memory 110 may be any type of fixed or removable random access memory (RAM), read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other similar elements or combinations thereof. In one embodiment, memory 110 is used to store data and program code. For example, memory 110 stores program code for training methods, datasets generated from simulations, parameters of prediction models, and configuration files.

[0020] Processor 120 is coupled to memory 110. In some embodiments, processor 120 may be a central processing unit (CPU), graphics processing unit (GPU), microprocessor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), neural network accelerator, or other similar programmable device or a combination thereof. In one embodiment, processor 120 is configured to load and execute program code and data stored in memory 110 to perform operations of apparatus 100. For example, processor 120 is configured to perform the training method described in the following exemplary embodiments.

[0021] To facilitate a clear understanding of the operational process of this disclosure, numerous embodiments will be detailed below to illustrate the operation. The methods described below will be combined with... Figure 1 The components will be explained.

[0022] Figure 2 This is a flowchart of a model training method according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 2 The training method is implemented by processor 120. In step S210, processor 120 establishes a training environment. Specifically, the training environment is a virtual space configured for the predictive model or other machine learning model to learn from, and the training environment includes a dataset. The dataset serves as the basis for the learning process. The dataset associates multiple semiconductor device parameters with one or more resulting electrical parameters. In practical applications, this dataset can be generated by running numerous device simulations using various software tools, such as, but not limited to, technical computer-aided design (TCAD) tools or other physics-based simulation platforms. Each entry in the dataset represents a specific simulated device, linking a unique combination of input parameters (e.g., semiconductor device parameters) to a corresponding simulation output performance (e.g., resulting electrical parameters).

[0023] In one embodiment, semiconductor device parameters include one or more structural parameters. Structural parameters are defined as parameters describing the physical geometry or layout of the semiconductor device. For example, structural parameters may include the spacing between guard rings ("s"), the width of the guard rings ("w"), and the number of guard rings ("GR"). Another example, structural parameters may include the drift region doping concentration ("N"). d "), drift region thickness ("t" drift "), oxide layer thickness ("t ox ") and substrate thickness ("t) s ").

[0024] Figure 3 This is a schematic diagram illustrating a semiconductor device 300 according to exemplary embodiments of the present disclosure. (Refer to...) Figure 3The semiconductor device 300 is, for example, a silicon carbide (SiC) trench metal-oxide-semiconductor field-effect transistor (MOSFET). The semiconductor device 300 includes a main transistor structure 301, such as a trench MOSFET, an oxide layer 302, and multiple guard rings 303. The main transistor structure 301 is, for example, a trench MOSFET located in the central region of the semiconductor device 300. The main transistor structure 301 essentially includes a gate, a channel region, and an oxide layer 302. The oxide layer 302, typically a gate oxide layer, is a thin layer of insulating material (e.g., silicon dioxide) that electrically isolates the gate electrode from the semiconductor channel. The quality and thickness of this oxide layer 302 are key parameters directly affecting transistor performance, including its threshold voltage and reliability. The guard rings 303 are structures configured around the main transistor structure 301. The guard rings 303 help the semiconductor device 300 withstand higher voltages, thereby enhancing its high-voltage capability. The semiconductor device parameters discussed in this disclosure, such as the number, width, and spacing of the guard rings, directly correspond to the physical characteristics of these guard rings 303.

[0025] In one embodiment, semiconductor device parameters include one or more process parameters. Process parameters are defined as parameters related to a semiconductor device fabrication or manufacturing step. For example, process parameters may include an ion implantation dose ("Dose") and multiple ion implantation energies (e.g., "energy_300", "energy_600", "energy_900"). The ion implantation energy determines the depth to which impurities are implanted into the semiconductor structure. Higher energy levels result in deeper implantation, while lower energy levels result in shallower implantation closer to the semiconductor device surface. For example, multiple ion implantation energies may be specified in kiloelectron volts (KeV) and may include different levels, such as "energy_300", "energy_600", and "energy_900", corresponding to implantations of 300 KeV, 600 KeV, and 900 KeV, respectively.

[0026] In one embodiment, the resulting electrical parameters are performance metrics obtained from simulation. For example, the resulting electrical parameters could be the breakdown voltage (BV) of a semiconductor device.

[0027] In step S220, the processor 120 defines states within the training environment. Specifically, a state represents a specific instance or potential device design within the design space, and the state is represented by a set of values ​​for semiconductor device parameters. The predictive model observes the current state to determine subsequent actions to explore the design space. For example, a state can be represented by a set of parameter values, such as {s: 1 m, w: 1.5 m, GR: 7, Dose: 5.7e+11, energy_300: 300 keV, energy_600: 900 keV, energy_900: 900 keV}.

[0028] In step S230, the processor 120 executes an action through the predictive model to select or modify at least one value within the set of values ​​representing the state. Specifically, the action is a decision made by the predictive model to change the current state. By executing actions, the predictive model repeatedly modifies semiconductor device parameters to explore different design configurations to find combinations that lead to improved performance. For example, the action could be increasing the value of the "Dose" parameter by a specific percentage or changing the value of the "GR" parameter from one integer to another, such as from 9 to 10.

[0029] In step S240, processor 120 calculates a reward value based on the reward function. Specifically, the reward value is a numerical score provided as feedback to the prediction model, indicating the quality of the state resulting from previous actions. The reward function is the core logic guiding the prediction model's learning process. The reward function is configured to guide the prediction model to maximize the resulting electrical parameters of the semiconductor device under parameter constraints. Violations of parameter constraints are penalized by the reward function, with the penalty increasing non-linearly with the degree of violation. This non-linear penalty is crucial for effectively guiding the prediction model to avoid undesirable regions in the design space. For example, the primary objective could be to maximize the breakdown voltage (BV) (i.e., the resulting electrical parameters of the semiconductor device).

[0030] In one embodiment, the parameter constraint is a predetermined range of ion implantation dose, and the ion implantation dose is one of the semiconductor device parameters. The parameter constraint may be applied to the "Dose" parameter (i.e., the parameter of ion implantation dose), requiring the value of the "Dose" parameter to be within an optimal range (i.e., a predetermined range, for example, between the minimum dose and the maximum dose).

[0031] In one embodiment, processor 120 may determine a reward value based on the breakdown voltage in a response where parameter constraints are met. The reward value is determined based on the achieved breakdown voltage when or only when the selected value of the "Dose" parameter is within a predetermined range. For example, the reward value is equal to the value of the breakdown voltage. The resulting electrical parameters of the semiconductor device will then be improved by the positive reward value (e.g., achieving a higher breakdown voltage).

[0032] In one embodiment, processor 120 may apply a nonlinear penalty to the reward value in response to a violation of a parameter constraint (e.g., the "Dose" parameter is outside a predetermined range). Specifically, the penalty increases nonlinearly with the degree of violation. Compared to linear penalties, nonlinear penalties provide a stronger learning signal to the predictive model because they severely penalize states far from the desired parameter range. For example, the nonlinear penalty is proportional to the fourth power of the degree of violation. The penalty is applied when or only when the selected value of the "Dose" parameter violates this constraint. This penalty may be calculated nonlinearly, for example, as a function of the fourth power of the absolute difference between the selected value of the "Dose" parameter and the median dose value. This nonlinear approach ensures that large deviations from the optimal range are severely penalized, thereby accelerating the learning process. The reward value is inversely proportional to the penalty. The reward value can be, for example, -(penalty) 100).

[0033] In one embodiment, processor 120 may calculate the degree of violation (e.g., ((abs(dose - median_dose))^4)) based on the difference between the ion implantation dose value (dose) and a median value within a predetermined range. The median value may be, for example, (min_dose + max_dose) / 2.

[0034] For example, Figure 4 This is a schematic diagram illustrating a reward function according to an exemplary embodiment of the present disclosure. (Refer to...) Figure 4 The reward function is the logic implemented by processor 120 in step S240 for calculating the reward value. The reward function operates based on whether parameter constraints are met. Specifically, parameter constraints are defined for the ion implantation dose ("Dose"). The parameter constraints specify a predetermined range defined by the minimum dose (min_dose) and the maximum dose (max_dose). The reward function checks whether the current value of the "Dose" parameter falls within this predetermined range. If the constraint is met (i.e., the "Dose" parameter falls within the predetermined range), a reward branch is executed, where the reward value is determined from the corresponding resulting electrical parameter, such as the breakdown voltage (BV). If the constraint is violated (i.e., the "Dose" parameter falls outside the predetermined range), a penalty branch is executed. In this branch, a penalty is calculated based on the degree of violation, which can be the absolute difference between the current "Dose" value and the median dose value. The penalty is non-linear; for example, the penalty is proportional to the fourth power of this difference. The final reward value is then set to the negative of this calculated penalty.

[0035] Figure 5 A graph illustrating the relationship between the breakdown voltage and ion implantation dose of a semiconductor device according to exemplary embodiments of the present disclosure. (Refer to...) Figure 5The figure shows that for different structural parameters (e.g., different combinations of guard ring spacing and width), the peak breakdown voltage is achieved at different optimal ion implantation dose values. For a given structure, doses that are too low or too high result in suboptimal breakdown voltages. This empirical relationship provides a technical basis and rationale for establishing ion implantation dose parameter constraints within the reward function, such as... Figure 4 As described above, by defining a predetermined range for the injection dose, the training process can be guided to focus on the most promising regions in the design space that are likely to produce high-performance devices.

[0036] In step S250, processor 120 updates the prediction model based on the reward value. Specifically, based on the feedback provided by the reward value, the prediction model adjusts its internal parameters (e.g., weights in the neural network). The purpose of the update is to reinforce actions that lead to high rewards and suppress actions that lead to low penalties. In one embodiment, the prediction model is a reinforcement learning (RL) model. Through multiple iterations of this state-action-reward-update loop, the prediction model learns a strategy to effectively find semiconductor device parameters that produce high-result electrical parameters while satisfying all parameter constraints. For example, the successful learning process is demonstrated by a "RL agent learning progress" graph, such as... Figures 6-9 As shown, the total reward for each round increases continuously during training and stabilizes at high reward values.

[0037] The following exemplary embodiments are in Figures 6-9 The documentation illustrates the results of the applied training methods. In these examples, a prediction model, serving as a reinforcement learning (RL) model, is trained to predict the parameters of a semiconductor device with a target breakdown voltage of 2500 V.

[0038] Figure 6 A graph showing the learning progress of an RL agent according to a first exemplary embodiment of this disclosure. (Refer to...) Figure 6 The figure plots the total reward per round and the moving average of the reward against the number of training rounds. The figure illustrates that after an initial exploration period characterized by low and unstable rewards, the performance of the RL agent improves rapidly and converges to a stable and high reward value around round 200. This convergence demonstrates the effectiveness of the training method and the nonlinear reward function in guiding the model to learn the optimal policy. In this embodiment, after training, the prediction model was used to predict the input parameters for a target breakdown voltage of 2500 V. The predicted input parameters were: a spacing ("s") of 1.38, a width ("w") of 1.31, nine guard rings ("GR"), an ion implantation dose ("Dose") of 6.7e+12, and implantation energies of 300 keV, 900 keV, and 900 keV. Subsequent simulations using these predicted parameters yielded a breakdown voltage of 2109 V.

[0039] Figure 7A graph showing the learning progress of an RL agent according to a second exemplary embodiment of this disclosure. (Refer to...) Figure 7 The learning curve is similar to that of the first embodiment, showing rapid convergence to a stable, high-reward state. This further validates the robustness of the training method across different training runs or small variations in hyperparameters. In this embodiment, the trained predictive model predicts a target breakdown voltage of 2500 V using the following input parameters: a spacing ("s") of approximately 1.26, a width ("w") of approximately 1.21, 14 guard rings ("GR"), an ion implantation dose ("Dose") of 1.1e+13, and implantation energies of 300 kEV, 900 kEV, and 900 kEV. Subsequent simulations using these predicted parameters resulted in a breakdown voltage of 2161.65 V.

[0040] Figure 8 A graph showing the learning progress of an RL agent according to a third exemplary embodiment of this disclosure. (Refer to...) Figure 8 The figure again demonstrates the successful learning and convergence of the RL agent. This example illustrates that the method remains effective even when predicting different subsets of parameters. In this example, the prediction model was trained to predict parameters for a target breakdown voltage of 2500 V, excluding specific energy levels. The input parameters for prediction were: a spacing ("s") of approximately 1.09, a width ("w") of approximately 1.10, nine guard rings ("GR"), and an ion implantation dose ("Dose") of 9.3e+12. Note that subsequent simulations using these parameters resulted in a breakdown voltage of 2354 V. Subsequent simulations using these prediction parameters yielded a breakdown voltage of 2215 V.

[0041] Figure 9 A graph showing the learning progress of an RL agent according to a fourth exemplary embodiment of this disclosure. (Refer to...) Figure 9 The learning progress shown is consistent with the previous embodiment. In this fourth embodiment, for the same target breakdown voltage of 2500 V and again excluding energy levels, the trained model predicts different sets of feasible input parameters: a spacing ("s") of approximately 1.43, a width ("w") of approximately 1.45, 6 guard rings ("GR"), and an ion implantation dose ("Dose") of 7.1e+12. Subsequent simulations using these predicted parameters produce a breakdown voltage of 2215 V. Figures 6-9 As illustrated in the embodiments, the ability to generate multiple, different, and high-performance parameter sets is a significant advantage, providing designers with multiple feasible options for device fabrication.

[0042] In one or more exemplary embodiments, the prediction model is implemented as a reinforcement learning (RL) model, such as a proximal policy optimization (PPO) agent or an advantage actor-critic (A2C) agent. The agent's underlying neural network may include multiple hidden layers, for example, two hidden layers each with 128 neurons, using an activation function such as the hyperbolic tangent (tanh) function. The training process is controlled by a set of hyperparameters, which may be configured to include a memory size of 20,000, a batch size of 64, an exploration rate of 0.5, a learning rate of 1e-3, and a discount factor of 0.99.

[0043] exist Figure 2 After the training process described herein is completed, the updated prediction model can be used to perform inverse prediction on a new semiconductor device. Specifically, processor 120 can receive target electrical parameters for the new semiconductor device, such as a new target breakdown voltage. Users, such as device designers, provide a single, high-level performance specification for the new semiconductor device to be designed. For example, a designer can input a target breakdown voltage of 2500 V for a new power application.

[0044] Processor 120 then uses the trained prediction model to determine new semiconductor device parameters based on the received target electrical parameters. Specifically, processor 120 uses the received target electrical parameters as the sole input to the trained prediction model. The prediction model, having learned the relationship between parameters and electrical performance during the training phase, performs inverse prediction. This inverse prediction process does not involve iterative simulation; instead, the prediction model directly computes and generates a complete set of multidimensional input parameters, predicting the achievement of a specified target (e.g., target electrical parameters) according to its learned strategy.

[0045] Finally, processor 120 outputs new semiconductor device parameters, providing a complete and feasible design specification that can be used for subsequent TCAD verification or manufacturing. Specifically, processor 120 outputs new semiconductor device parameters determined by a predictive model. This output constitutes a complete and feasible design specification. For example, in response to a target electrical parameter of 2500 V, the output could be a specific set of parameters {s: 1.09, w: 1.10, GR: 9, Dose: 9.3e+12}. This output can then be used by the designer for final verification simulation in TCAD tools or as a direct benchmark for the manufacturing process, replacing the time-consuming manual trial-and-error loops in traditional design methodologies.

[0046] In summary, the training method and apparatus disclosed herein utilize predictive models, particularly reinforcement learning models, guided by a nonlinear reward function to solve semiconductor device parameter design problems. By performing inverse prediction, the method directly generates a set of optimal input parameters based on a single objective output specification. This method fundamentally overcomes the limitations of traditional trial-and-error methods (inefficient and heavily reliant on engineering experience). The disclosed method significantly reduces the time and computational resources required for device design, accelerates product development cycles, and improves the overall quality and reliability of the final design by systematically exploring the design space to find high-performance solutions.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for training a model, implemented by a processor, the training method comprising: Establish a training environment including a dataset, wherein the dataset associates multiple semiconductor device parameters with at least one resulting electrical parameter, and the multiple semiconductor device parameters are used by a semiconductor device for a silicon carbide trench metal-oxide-semiconductor field-effect transistor; A state is defined within the training environment, wherein the state is represented by a set of values ​​for the plurality of semiconductor device parameters; The predictive model performs an action to select or modify at least one value within the set of values ​​representing the state; The reward value is calculated based on the reward function, wherein the reward function is configured to guide the prediction model to maximize the resulting electrical parameters of the semiconductor device and is subject to parameter constraints on the plurality of semiconductor device parameters, and the violation of the parameter constraints is penalized by the reward function, which increases nonlinearly with the degree of violation; as well as The prediction model is updated based on the reward value.

2. The training method for the model according to claim 1, wherein the resulting electrical parameter of the semiconductor device is the breakdown voltage.

3. The training method for the model according to claim 1, wherein the parameter constraint is a predetermined range of ion implantation dose, and the ion implantation dose is one of the plurality of semiconductor device parameters.

4. The training method for the model according to claim 3, wherein calculating the reward value based on the reward function includes: The degree of violation is calculated based on the difference between the value of the ion implantation dose and the median of the predetermined range.

5. The training method for the model according to claim 1, wherein calculating the reward value based on the reward function includes: In response to a violation of the parameter constraint, a nonlinear penalty is applied to the reward value, wherein the nonlinear penalty is proportional to the fourth power of the degree of violation.

6. The training method for the model according to claim 1, wherein the plurality of semiconductor device parameters include at least one structural parameter selected from the following: the spacing between the plurality of guard rings, the width of the plurality of guard rings, and the number of the plurality of guard rings.

7. The training method for the model according to claim 1, wherein the plurality of semiconductor device parameters includes at least one process parameter selected from the following: ion implantation dose and a plurality of ion implantation energies.

8. The training method for the model according to claim 2, wherein calculating the reward value based on the reward function includes: In response to the parameter constraint being satisfied, the reward value is determined based on the breakdown voltage.

9. The training method of the model according to claim 1, wherein the prediction model is a reinforcement learning model.

10. The training method of the model according to claim 1, wherein the prediction model is used to determine a plurality of new semiconductor device parameters of a new semiconductor device based on target electrical parameters.

11. An apparatus for training a model, comprising: Memory, used to store program code; as well as A processor, coupled to the memory, is configured to load and execute the program code to perform: Establish a training environment including a dataset, wherein the dataset associates multiple semiconductor device parameters with at least one resulting electrical parameter, and the multiple semiconductor device parameters are used by a semiconductor device for a silicon carbide trench metal-oxide-semiconductor field-effect transistor; A state is defined within the training environment, wherein the state is represented by a set of values ​​for the plurality of semiconductor device parameters; The predictive model performs an action to select or modify at least one value within the set of values ​​representing the state; A reward value is calculated based on a reward function, wherein the reward function is configured to guide the prediction model to maximize the resulting electrical parameters of the semiconductor device, subject to parameter constraints of a plurality of semiconductor device parameters, and a violation of the parameter constraints is penalized by the reward function, which increases non-linearly with the degree of violation; and The prediction model is updated based on the reward value.

12. The apparatus for training a model according to claim 11, wherein the resulting electrical parameter of the semiconductor device is a breakdown voltage.

13. The apparatus for training a model according to claim 11, wherein the parameter constraint is a predetermined range of ion implantation dose, and the ion implantation dose is one of the plurality of semiconductor device parameters.

14. The apparatus for training a model according to claim 13, wherein the processor is further configured to perform: The degree of violation is calculated based on the difference between the ion implantation dose value and the median value of the predetermined range.

15. The apparatus for training a model according to claim 11, wherein the processor is further configured to perform: In response to a violation of the parameter constraint, a nonlinear penalty is imposed on the reward value, wherein the nonlinear penalty is proportional to the fourth power of the degree of violation.

16. The apparatus for training a model according to claim 11, wherein the plurality of semiconductor device parameters include at least one structural parameter selected from: the spacing between the plurality of guard rings, the width of the plurality of guard rings, and the number of the plurality of guard rings.

17. The apparatus for training a model according to claim 11, wherein the plurality of semiconductor device parameters includes at least one process parameter selected from: ion implantation dose and a plurality of ion implantation energies.

18. The apparatus for training a model according to claim 12, wherein the processor is further configured to perform: In response to the parameter constraint being satisfied, the reward value is determined based on the breakdown voltage.

19. The apparatus for training a model according to claim 11, wherein the prediction model is a reinforcement learning model.

20. The apparatus associated with the training model according to claim 11, wherein the prediction model is used to determine a plurality of new semiconductor device parameters for a new semiconductor device based on target electrical parameters.

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