Full-dimensional dynamic reconfigurable configuration method and system for parallel computing array

Abstract

The application belongs to the technical field of integrated circuit design and reconfigurable computing, and specifically relates to a full-dimension dynamic reconfigurable configuration method and system for a parallel computing array, wherein the method comprises the following steps: analyzing a standardized configuration file to extract scale, correlation mode and function parameters; dynamically adjusting an activated array scale through row and column enabling technology; dynamically establishing a mapping relationship between a sub-core and a processing unit by using four standardized correlation modes; and independently configuring an operation code for each processing unit to realize heterogeneous computing. All configurations do not require modification of hardware description language code or re-synthesis of hardware, and the configuration time consumption is in the order of milliseconds. The application realizes full-dimension runtime dynamic reconfiguration from hardware scale to unit function, greatly improves hardware resource utilization, algorithm adaptability and reconfiguration real-time performance, and can be widely applied to parallel computing platforms such as AI accelerators, NPUs, GPUs, TPUs and CGRAs.

Description

Technical Field

[0001] This invention relates to the fields of integrated circuit design and reconfigurable computing technology, and in particular to a method and system for full-dimensional dynamic reconfigurable configuration of parallel computing arrays. Background Technology

[0002] Parallel computing arrays are the core hardware carriers for data-parallel computing. Their core structure is a two-dimensional computing array composed of multiple processing units (PEs). By configuring the number of PEs, their interconnections, and computational functions, different algorithms can be mapped and executed. Currently, the mainstream configuration methods for parallel computing arrays in the industry are divided into two categories: static configuration and semi-dynamic configuration. Static configuration determines the PE array size, the relationship between sub-cores and PEs, and the functional scope of PEs during the hardware design phase, and cannot be changed during operation. Semi-dynamic configuration only supports dynamic switching of PE computational functions; the array size and sub-core-PE relationship remain fixed. Existing technologies suffer from several core pain points, including low resource utilization (generally below 40%) due to fixed array size, poor algorithm adaptability due to fixed sub-core-PE relationships, support for only single-dimensional configuration, cumbersome reconstruction processes requiring modification of HDL and re-synthesizing and rewiring (taking hours to days), and poor versatility preventing cross-platform adaptation. Summary of the Invention

[0003] This invention proposes a method and system for full-dimensional dynamic reconfigurable configuration of parallel computing arrays, aiming to solve the technical problems existing in the prior art, such as fixed array size, inflexible sub-core-PE association, support for only single-dimensional configuration, cumbersome reconfiguration process, and lack of real-time performance.

[0004] In a first aspect, the present invention provides a method for the full-dimensional dynamic reconfigurable configuration of parallel computing arrays, including: Parse the standardized configuration file and extract the configuration parameter set, which includes at least array size parameters, association mode parameters, and functional configuration parameters of each processing unit. Perform matrix-level configuration: Based on the array size parameters, dynamically adjust the number of rows and columns of the active processing units in the parallel computing array to form a computing array of the target size; Perform association-level configuration: Based on the association mode parameters, dynamically establish the association mapping relationship between the control sub-core and each processing unit in the target-scale computing array, and generate a sub-core-processing unit mapping table; Perform function-level configuration: Configure opcodes independently for each active processing unit in the target-size computing array according to the function configuration parameters; The matrix-level configuration, association-level configuration, and function-level configuration are executed sequentially.

[0005] Furthermore, the standardized configuration file is a readable text structure that contains the following core configuration items: pe_matrix_rows and pe_matrix_cols are used to define the number of rows and columns of the array, respectively; `subcore_count` is used to define the number of subcores involved in control and the ELF file loading instructions for each subcore. `pe_association_mode` is used to define the association mode between the sub-core and the processing unit. Its values ​​include row, column, adjacent, and custom. pe_association_map is used to explicitly declare the mapping relationship between sub-cores and processing units in custom mode; pe_opcode is used to define the opcode and calculation function of each processing unit.

[0006] Furthermore, the step of dynamically adjusting the number of rows and columns of active processing units in the parallel computing array specifically includes: Parse the pe_matrix_rows and pe_matrix_cols parameters in the configuration parameter set to generate array row and column enable signals; The row and column enable signals are sent to the processing unit array. The processing units corresponding to the rows and columns with valid enable signals are activated, while the processing units corresponding to the rows and columns with invalid enable signals are put into a sleep state.

[0007] Furthermore, the association mode parameter includes any one of row mode, column mode, adjacent mode, and custom mode; The row pattern refers to a row of processing units in the management array corresponding to each control sub-core; The column pattern refers to a column of processing units in the management array corresponding to each control sub-core; The adjacent pattern is defined as the adjacent processing unit block in the management array corresponding to each control sub-core; The custom mode is a one-to-one mapping relationship between sub-cores and processing units explicitly declared through the standardized configuration file.

[0008] Furthermore, the step of dynamically establishing the association mapping relationship between the control sub-core and each processing unit in the target-size computing array specifically includes: Based on the association pattern obtained from parsing, a one-to-one mapping relationship between sub-core identifiers and processing unit identifiers is established according to the corresponding mapping rules, and the sub-core-processing unit mapping table is generated. The sub-core-processing unit mapping table is stored in the configuration register group, so that the control sub-core can control the corresponding processing unit, send data and collect results by querying the mapping table.

[0009] Furthermore, the step of independently configuring opcodes for each activated processing unit in the target-size computing array specifically includes: Parse the opcode parameters specified for each activated processing unit in the standardized configuration file; Write the opcode into the configuration register of the corresponding processing unit; Each processing unit switches to the corresponding computation function mode according to the opcode in its configuration register.

[0010] Furthermore, the method also includes: receiving an updated standardized configuration file during the execution of a computational task by the parallel computing array; Repeat the steps of parsing, matrix-level configuration, association-level configuration, and function-level configuration to dynamically update the array size, sub-core-processing unit association, or processing unit computational function at runtime.

[0011] Furthermore, the entire configuration process of the method does not require modification of the hardware description language code, nor does it require re-execution of hardware synthesis, placement and routing, and bitstream generation operations.

[0012] Furthermore, the parallel computing array includes a coarse-grained reconfigurable computing array, an AI acceleration array, a multi-core processor array, or a DSP array.

[0013] Secondly, the present invention provides a fully dynamic reconfigurable configuration system for parallel computing arrays, the system being used to execute the method, the system comprising: A configuration parser is used to parse standardized configuration files and extract configuration parameter sets; The main control unit is connected to the configuration parser, the processing unit array, and the sub-core management unit, respectively. It is used to perform matrix-level configuration, that is, to dynamically adjust the number of rows and columns of the active processing units in the parallel computing array according to the array size parameters in the configuration parameter set, and to perform function-level configuration, that is, to independently configure opcodes for each active processing unit in the computing array of the target size according to the function configuration parameters in the configuration parameter set. The processing unit association mapper is connected to the main control unit and the sub-core management unit, and is used to perform association-level configuration, that is, to dynamically establish the association mapping relationship between the control sub-core and the processing unit according to the association mode parameters in the configuration parameter set, and generate a sub-core-processing unit mapping table. The system is configured to perform matrix-level configuration, association-level configuration, and function-level configuration sequentially.

[0014] The technical effects of the technical solution disclosed in this invention are: 1. Architectural Innovation Results: A three-tiered dynamic configuration mechanism—"matrix-association-functionality"—is proposed, achieving for the first time a fully refined configuration of parallel computing arrays across all dimensions, from hardware scale and sub-core-PE association to PE computing functionality. All configurations require no modification to HDL code or resynthesis of hardware, with configuration time <10ms. Hardware resource utilization is increased from ≤40% in traditional solutions to 100%, and refactoring efficiency is improved by more than a thousandfold.

[0015] 2. Flexibility and Innovation: Four standardized sub-core-PE association mapping modes (row, column, adjacent, and custom) are designed. The association mode can be optimized according to the algorithm's parallelism and locality characteristics to achieve sub-core load balancing. The algorithm mapping flexibility is more than 5 times higher than the traditional fixed mapping scheme, and the algorithm execution efficiency is improved by more than 25%.

[0016] 3. Real-time innovation effect: Enables dynamic updates of all-dimensional configurations at runtime, and configuration switching can be completed without stopping the array operation. The operation code switching time is <1ms and the array size switching time is <10ms. It is fully adapted to industrial scenarios where multiple algorithms such as real-time video processing and real-time signal processing can be seamlessly switched.

[0017] 4. Versatile and innovative effects: This configuration method is not limited to the CGRA single platform. It can be seamlessly adapted to all parallel computing platforms such as AI acceleration arrays, multi-core processor arrays, DSP arrays, and reconfigurable computing arrays, and has extremely strong industrial promotion value. Attached Figure Description

[0018] Figure 1 This is a flowchart illustrating the full-dimensional dynamic reconfigurable configuration method for parallel computing arrays proposed in this embodiment of the invention. Detailed Implementation

[0019] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] Existing related patent technologies all have limitations: they may only support dynamic switching of PE functions, unable to adjust the array size and correlation, thus limiting hardware resource utilization; or the array size may be fixed, unable to flexibly allocate hardware resources according to algorithm requirements, easily leading to idle resources or insufficient performance; or the reconstruction process may be cumbersome, requiring modification of the hardware description language and re-integration and routing to adjust the configuration, making it impossible to achieve rapid reconstruction at runtime and unable to adapt to real-time computing scenarios with dynamic switching of multiple algorithms, severely restricting the algorithm adaptability, resource utilization and versatility of parallel computing arrays.

[0021] Based on this, the present invention provides a full-dimensional dynamic reconfigurable configuration method for parallel computing arrays. The present invention relates to the fields of integrated circuit design and reconfigurable computing technology, specifically belonging to the subfield of dynamic configuration technology for parallel computing arrays. It is applicable to all parallel computing and reconfigurable acceleration platforms, including but not limited to: coarse-grained reconfigurable computing arrays (CGRA), AI acceleration arrays, multi-core processor arrays, and DSP arrays.

[0022] This invention uses a coarse-grained reconfigurable computing array (CGRA) platform with a 16×16 processing unit (PE) array as an example. However, those skilled in the art should understand that this invention is also applicable to all parallel computing and reconfigurable acceleration platforms such as AI acceleration arrays, multi-core processor arrays, and DSP arrays.

[0023] The entire technical process of this invention is designed as a progressive closed loop: First, a standardized configuration file format is defined and a configurable hardware foundation is built; then, the configuration file is parsed to extract core parameters; next, the first-level matrix-level configuration (adjusting the array size), the second-level association-level configuration (establishing sub-core-PE mapping), and the third-level functional-level configuration (configuring PE opcodes) are executed sequentially; finally, the array is calculated to execute tasks according to the configuration, and dynamic configuration updates are supported at runtime. (Reference) Figure 1 As shown, the specific steps include: Step 1: Preliminary Preparations – Defining a standardized configuration file format and hardware foundation.

[0024] Before configuration can be executed, a standardized configuration file format must first be defined, and a configurable parallel computing array hardware foundation must be built.

[0025] In this embodiment, the standardized configuration file adopts a readable text structure (such as JSON, YAML, or a custom format) and supports a unified declaration of all configuration parameters. The configuration file contains the following core configuration items: pe_matrix_rows: Defines the number of rows in the target array; pe_matrix_cols: Defines the number of columns in the target array; subcore_count: Defines the number of subcores involved in control, and the ELF file loading instructions for each subcore; pe_association_mode: Defines the association mode between the sub-core and PE. Values ​​include row (row mode), column (column mode), adjacent (adjacent mode), and custom (custom mode). pe_association_map: Used only in custom mode, it is used to explicitly declare a one-to-one mapping between sub-cores and PEs; pe_opcode: Configures the opcode independently for each PE, defining its computational function.

[0026] In terms of hardware infrastructure, it includes: a main control unit, a configuration resolver, a configurable PE computing array, a PE association mapper, a sub-core management unit, and a configuration register set. The main control unit is connected to the configuration resolver, the PE array, and the sub-core management unit; the PE association mapper is connected to the main control unit and the sub-core management unit. Each PE is equipped with an independent configuration register for storing opcodes; the configuration register set is used to store the sub-core-PE mapping table.

[0027] Step 2: Parse the configuration file and extract the configuration parameter set.

[0028] The configuration parser reads the standardized configuration file, performs lexical and syntactic analysis on it, and extracts a structured set of configuration parameters. This set of parameters includes at least: array size parameters (such as pe_matrix_rows=6, pe_matrix_cols=6), subcore count parameters (such as subcore_count=6), association mode parameters (such as pe_association_mode="row"), and functional configuration parameters for each PE (such as the pe_opcode value for each PE).

[0029] Technical results: The configuration file parsing accuracy reaches 100%, and the parsing process takes negligible time (typically <1ms). The parsed parameter set will serve as the input for the subsequent three-layer configuration.

[0030] Step 3: Matrix-level configuration - dynamically adjust the array size (first-level configuration).

[0031] The main operating components of this step are the main control unit and the configurable PE computing array, employing row and column enable control technology and dynamic activation technology for processing units.

[0032] Specific technical solution: The main control unit obtains the values ​​of pe_matrix_rows and pe_matrix_cols from the parameter set. In this embodiment, assuming the target size is 6 rows × 6 columns, then pe_matrix_rows = 6 and pe_matrix_cols = 6. The main control unit generates row and column enable signals based on these two parameters: for row addresses 0-5 and column addresses 0-5, the enable signals are set to active (e.g., high level); for row addresses 6-15 and column addresses 6-15, the enable signals are set to inactive (e.g., low level). The PEs (36 in total) corresponding to the rows and columns with active enable signals are activated and enter the working state, participating in subsequent calculations and data interactions; the PEs (256-36=220 in total) corresponding to the rows and columns with inactive enable signals are put into a dormant state and do not participate in calculations and data interactions, thereby reducing dynamic power consumption.

[0033] The preferred approach is to use a grouped enable method for row and column enable signals, i.e., one row enable register and one column enable register for each column. PEs are activated only when both the row and column enable signals are valid. This approach supports activation of non-rectangular arrays (such as L-shaped arrays), but this embodiment uses a rectangular activation method. Furthermore, dynamic adjustment at runtime is supported: upon receiving a new configuration file, the main control unit can regenerate the row and column enable signals, thereby changing the number of activated PEs without resetting the array.

[0034] Technical Results: Matrix-level configuration takes less than 10ms. This step breaks through the limitations of traditional fixed array size, enabling on-demand allocation of hardware resources. When processing small-scale algorithms (such as 2×2 matrix operations), only 4 PEs are activated, significantly reducing power consumption; when processing large-scale algorithms (such as high-definition image filtering), all 256 PEs are activated to meet performance requirements. Hardware resource utilization is increased from ≤40% of traditional fixed arrays to 100%.

[0035] Step 4: Association-level configuration - dynamically establish sub-core-PE association relationship (second-level configuration).

[0036] The main operations in this step are the PE association mapper and the sub-core management unit, which use hash mapping technology and dynamic mapping table update technology.

[0037] Specific technical solution: The PE association mapper parses the association mode parameter pe_association_mode, which in this embodiment is set to "row", i.e., row mode. According to the row mode mapping rules: each control subcore manages one row of PEs in the array. For a 6×6 array, there are 6 subcores (subcore_count=6). Subcore 0 manages the 6 PEs in row 0 (PEIDs are (0,0) to (0,5)), subcore 1 manages the 6 PEs in row 1, and so on. The PE association mapper establishes a one-to-one mapping relationship between subcore IDs and PEIDs, generates a subcore-PE mapping table, and stores it in the configuration register group. Afterwards, the subcore can query this mapping table to control the corresponding PE, send data, and collect results.

[0038] This embodiment also provides preferred solutions for three other standardized association patterns: Column mode (pe_association_mode="column"): Each sub-core manages one column of PEs in the array. For example, sub-core 0 manages the 6 PEs in column 0, and sub-core 1 manages the 6 PEs in column 1. This mode is suitable for column vector operations and column-parallel computing scenarios.

[0039] Adjacent mode (pe_association_mode="adjacent"): Each sub-core manages adjacent PE blocks in the array. For example, a 6×6 array can be divided into nine 2×2 blocks, with each sub-core managing one 2×2 block. This mode is suitable for scenarios with data locality, such as convolution operations (e.g., a 3×3 convolution kernel sliding window) and image patch processing.

[0040] Custom mode (pe_association_mode="custom"): This mode explicitly declares the mapping relationship between sub-kernels and PEs through the pe_association_map in the configuration file, achieving non-uniform PE allocation. For example, in complex neural network inference scenarios, sub-kernel 0 (responsible for the main computation of the convolutional layer) needs to manage 10 PEs, sub-kernel 1 (responsible for activation function computation) needs to manage 8 PEs, and sub-kernel 2 (responsible for pooling operations) needs to manage 6 PEs. These can be specified individually through pe_association_map. This mode perfectly adapts to complex algorithms with uneven sub-kernel loads.

[0041] Preferred technical solution: When generating the mapping table, a hash mapping technique is used, with the sub-core ID as the key and the corresponding PEID list as the value, to construct a hash table stored in the configuration register group. This solution can achieve a mapping query response time of O(1). Simultaneously, the mapping table supports dynamic updates at runtime: when the association mode parameters change, the PE association mapper regenerates the mapping table and updates the configuration register group without requiring an array reset.

[0042] Technical Results: Configuration time at the association level is less than 3ms, and the response time for mapping table calls is less than 1μs. Compared to traditional fixed mapping schemes, the algorithm mapping flexibility is improved by more than 5 times, and the algorithm execution efficiency is improved by more than 25%. For example, in custom mode, load balancing can avoid the problem of insufficient resources in heavily loaded sub-cores and idle resources in lightly loaded sub-cores, improving load balancing by 40%.

[0043] Step 5: Functional configuration – Configure the computing functions of each PE independently (third-level configuration).

[0044] The main operating components of this step are the main control unit and the configurable PE computing array, employing dynamic configuration technology using opcodes and real-time switching technology for PE functions.

[0045] Specific technical solution: The main control unit parses the opcode parameter (pe_opcode) corresponding to each activated PE in the configuration file. In this embodiment, the opcode of all 36 PEs is configured as GRAYSCALE (grayscale conversion), and its corresponding opcode is, for example, 0x05. The main control unit writes the opcode to the configuration register of the corresponding PE through the internal bus. Each PE contains a decoding unit that continuously monitors the value of its configuration register. When the opcode is written, the PE switches to the corresponding calculation function mode according to the new opcode. For example, if the opcode is 0x05, the PE switches to grayscale conversion mode and performs a weighted summation operation of R, G, and B components on the input pixels; if the opcode is 0x01, the PE switches to addition mode; if the opcode is 0x03, the PE switches to multiply-accumulate (MAC) mode.

[0046] Preferred technical solution: In this embodiment, the PE supports seven basic opcodes (ADD, SUB, MUL, MAC, SQUARE, GRAYSCALE, SOBEL) and can support more custom functions by expanding the opcode table. Opcode switching adopts a single-cycle write operation, that is, the writing of the configuration register is completed within one clock cycle, and the PE function takes effect in the next clock cycle, thereby realizing single-cycle dynamic switching. In addition, this step supports heterogeneous configuration: in the same array, different PEs can be configured with different opcodes. For example, the PEs in the left half of the array (columns 0-2) are configured as SOBEL edge detection, and the PEs in the right half (columns 3-5) are configured as GRAYSCALE grayscale conversion, thereby realizing parallel heterogeneous computing of the image preprocessing pipeline.

[0047] Technical benefits: Function-level configuration (opcode switching) takes less than 1ms and supports dynamic switching without downtime during runtime. This step overcomes the limitations of traditional solutions where PE functions are fixed or only support limited switching, enabling the same hardware array to execute multiple computing tasks in a time-sharing or simultaneous manner, perfectly adapting to the staged computing needs of complex algorithms.

[0048] Step Six: Implementation and Dynamic Updates During Runtime.

[0049] After completing the above three-layer configuration, the parallel computing array executes the computing tasks according to the final configuration. Taking the image processing scenario in this embodiment as an example: all 36 PEs in the 6×6 array are in grayscale conversion mode, inputting high-definition video frame data. Each PE processes one pixel block or pixel point in parallel, and the overall grayscale processing throughput of the array can reach 82K pixels / second, which is 3.64 times faster than the 4×4 array (36 pixels / second), and the hardware resource utilization rate reaches 100%.

[0050] This invention also supports runtime dynamic updates, enabling seamless switching between multiple algorithm scenarios without stopping the array. The specific process is as follows: During the array's current task execution, the main control unit monitors the configuration file update flag. When a new configuration file (e.g., for edge detection) is detected, steps two through five are repeated. Since the entire configuration process requires no modification to HDL code or re-synthesization, placement, and routing, and can be completed solely through the configuration file, configuration can be completed within milliseconds. After the switch is complete, the array immediately begins executing the new algorithm. For example, in real-time video processing scenarios, the entire array can be configured to perform grayscale conversion first, and then the configuration can be dynamically switched, changing some PEs to Sobel edge detection, forming a "grayscale conversion → edge detection" pipeline with a reconstruction time of less than 10ms, fully meeting real-time requirements.

[0051] In all configuration levels of this invention, from initial configuration to dynamic runtime updates, everything is accomplished simply by modifying standardized configuration files. The entire configuration process requires no modification to any Hardware Description Language (HDL) code, and eliminates the need to re-execute hardware synthesis, placement and routing, and bitstream generation operations. This is fundamentally different from traditional solutions where adjusting array size or correlation requires re-synthesis and bitstream generation (which can take hours to days), resulting in a reconfiguration efficiency improvement of over a thousand times.

[0052] Although this embodiment is described using the CGRA platform, the configuration method and system disclosed in this invention are also applicable to other parallel computing platforms. For AI acceleration arrays, simply integrating the main control unit, configuration parser, PE association mapper, and configuration register set into the platform, and following the standardized configuration file format of this invention, enables full-dimensional dynamic reconfigurability. For multi-core processor arrays, each processor core can be considered as a PE. The method of this invention enables dynamic activation of the number of processor cores, dynamic configuration of inter-core relationships, and dynamic switching of core functions (such as floating-point operations, fixed-point operations, and vector operations). Therefore, this invention possesses strong cross-platform versatility and industrial application value.

[0053] This embodiment has passed end-to-end functional verification on the FPGA verification platform and software simulator, achieving the following indicators: PE matrix configurable size: arbitrary matrix size (this embodiment supports a maximum of 16×16). Matrix-level configuration time: <10ms; Maximum number of configurable sub-cores: 16; Number of PE association modes: 4 (row / column / adjacent / custom); PE supports 7 basic opcodes (expandable). PE opcode switching time: <1ms; PE association mode switching time: <3ms; Hardware resource utilization rate improvement rate: over 60%; Algorithm execution efficiency improvement: over 25%; Configuration file parsing accuracy: 100%; Configuration success rate: 100%; Reconfigurable feature: Supports dynamic reconfiguration without downtime during runtime.

[0054] Based on the same inventive concept, embodiments of the present invention also provide a fully dynamic reconfigurable configuration system for parallel computing arrays, the system being used to execute the method, the system comprising: A configuration parser is used to parse standardized configuration files and extract configuration parameter sets; The main control unit is connected to the configuration parser, the processing unit array, and the sub-core management unit, respectively. It is used to perform matrix-level configuration, that is, to dynamically adjust the number of rows and columns of the active processing units in the parallel computing array according to the array size parameters in the configuration parameter set, and to perform function-level configuration, that is, to independently configure opcodes for each active processing unit in the computing array of the target size according to the function configuration parameters in the configuration parameter set. The processing unit association mapper is connected to the main control unit and the sub-core management unit, and is used to perform association-level configuration, that is, to dynamically establish the association mapping relationship between the control sub-core and the processing unit according to the association mode parameters in the configuration parameter set, and generate a sub-core-processing unit mapping table. The system is configured to perform matrix-level configuration, association-level configuration, and function-level configuration sequentially.

[0055] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in conjunction with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for full-dimensional dynamic reconfigurable configuration of parallel computing arrays, characterized in that, include: Parse the standardized configuration file and extract the configuration parameter set, which includes at least array size parameters, association mode parameters, and functional configuration parameters of each processing unit. Perform matrix-level configuration: Based on the array size parameters, dynamically adjust the number of rows and columns of the active processing units in the parallel computing array to form a computing array of the target size; Perform association-level configuration: Based on the association mode parameters, dynamically establish the association mapping relationship between the control sub-core and each processing unit in the target-scale computing array, and generate a sub-core-processing unit mapping table; Perform function-level configuration: Configure opcodes independently for each active processing unit in the target-size computing array according to the function configuration parameters; The matrix-level configuration, association-level configuration, and function-level configuration are executed sequentially.

2. The method according to claim 1, characterized in that, The standardized configuration file is a readable text structure and contains the following core configuration items: pe_matrix_rows and pe_matrix_cols are used to define the number of rows and columns of the array, respectively; `subcore_count` is used to define the number of subcores involved in control and the ELF file loading instructions for each subcore. `pe_association_mode` is used to define the association mode between the sub-core and the processing unit. Its values ​​include row, column, adjacent, and custom. pe_association_map is used to explicitly declare the mapping relationship between sub-cores and processing units in custom mode; pe_opcode is used to define the opcode and calculation function of each processing unit.

3. The method according to claim 2, characterized in that, The steps for dynamically adjusting the number of rows and columns of active processing units in the parallel computing array specifically include: Parse the pe_matrix_rows and pe_matrix_cols parameters in the configuration parameter set to generate array row and column enable signals; The row and column enable signals are sent to the processing unit array. The processing units corresponding to the rows and columns with valid enable signals are activated, while the processing units corresponding to the rows and columns with invalid enable signals are put into a sleep state.

4. The method according to claim 1, characterized in that, The association mode parameter includes any one of row mode, column mode, adjacent mode, and custom mode; The row pattern refers to a row of processing units in the management array corresponding to each control sub-core; The column pattern refers to a column of processing units in the management array corresponding to each control sub-core; The adjacent pattern is defined as the adjacent processing unit block in the management array corresponding to each control sub-core; The custom mode is a one-to-one mapping relationship between sub-cores and processing units explicitly declared through the standardized configuration file.

5. The method according to claim 4, characterized in that, The step of dynamically establishing the association mapping relationship between the control sub-core and each processing unit in the target-size computing array specifically includes: Based on the association pattern obtained from parsing, a one-to-one mapping relationship between sub-core identifiers and processing unit identifiers is established according to the corresponding mapping rules, and the sub-core-processing unit mapping table is generated. The sub-core-processing unit mapping table is stored in the configuration register group, so that the control sub-core can control the corresponding processing unit, send data and collect results by querying the mapping table.

6. The method according to claim 1, characterized in that, The step of independently configuring opcodes for each active processing unit in the target-size computing array specifically includes: Parse the opcode parameters specified for each activated processing unit in the standardized configuration file; Write the opcode into the configuration register of the corresponding processing unit; Each processing unit switches to the corresponding computation function mode according to the opcode in its configuration register.

7. The method according to claim 1, characterized in that, The method further includes: receiving an updated standardized configuration file during the execution of a computing task by the parallel computing array; Repeat the steps of parsing, matrix-level configuration, association-level configuration, and function-level configuration to dynamically update the array size, sub-core-processing unit association, or processing unit computational function at runtime.

8. The method according to claim 1, characterized in that, The entire configuration process of the method does not require modification of the hardware description language code, nor does it require re-execution of hardware synthesis, placement and routing, and bitstream generation operations.

9. The method according to claim 1, characterized in that, The parallel computing array includes a coarse-grained reconfigurable computing array, an AI acceleration array, a multi-core processor array, or a DSP array.

10. A fully dynamic reconfigurable configuration system for parallel computing arrays, characterized in that, The system is used to perform the method according to any one of claims 1-9, the system comprising: A configuration parser is used to parse standardized configuration files and extract configuration parameter sets; The main control unit is connected to the configuration parser, the processing unit array, and the sub-core management unit, respectively. It is used to perform matrix-level configuration, that is, to dynamically adjust the number of rows and columns of the active processing units in the parallel computing array according to the array size parameters in the configuration parameter set, and to perform function-level configuration, that is, to independently configure opcodes for each active processing unit in the computing array of the target size according to the function configuration parameters in the configuration parameter set. The processing unit association mapper is connected to the main control unit and the sub-core management unit, and is used to perform association-level configuration, that is, to dynamically establish the association mapping relationship between the control sub-core and the processing unit according to the association mode parameters in the configuration parameter set, and generate a sub-core-processing unit mapping table. The system is configured to perform matrix-level configuration, association-level configuration, and function-level configuration sequentially.

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