Aluminum switch box design method and system based on FPGA wiring matrix

Abstract

The application relates to the technical field of FPGA design, in particular to an aluminum switch box design method and system based on an FPGA wiring matrix, which comprises the following steps: acquiring initial connection topological data of the FPGA wiring matrix, wherein the initial connection topological data comprises a plurality of node coordinates and a plurality of connection paths; generating first layout data based on the initial connection topological data; generating second layout data based on the first layout data; generating aluminum wiring pattern data based on the second layout data; generating etching mask data based on the aluminum wiring pattern data; and forming an aluminum switch box on an aluminum substrate based on the etching mask data. The first layout data is generated through node clustering analysis and signal priority driven offset, then the channels are dynamically divided into segments according to the signal priority, and different power supply levels are given, so that the interconnection structure of the switch box is closely matched with the original wiring requirement of the FPGA, the wiring density and the signal transmission efficiency are significantly improved, and the parasitic capacitance and resistance are reduced.

Description

Technical Field

[0001] This invention relates to the field of FPGA design technology, specifically to a design method and system for aluminum switch boxes based on FPGA wiring matrices. Background Technology

[0002] Currently, traditional methods typically generate layouts directly using the original node coordinates of the FPGA without performing node clustering analysis and priority-driven offset adjustments. This results in low wiring density, fixed channel division, and an inability to allocate more refined channel segments or multiple power supply levels for high-priority signals. Consequently, parasitic capacitance and resistance are large, leading to poor signal transmission efficiency.

[0003] Furthermore, traditional methods do not consider the relationship between oxide layer thickness and passivation layer thickness when generating etching masks, and the mask window size is set uniformly, resulting in large deviations in window size after etching different power areas and poor isolation. The passivation layer and pads are formed in steps, the top surface is uneven, and there is a lack of optical proximity correction, which easily produces linewidth distortion and step height difference, reducing the yield and long-term working stability of the switch box. Summary of the Invention

[0004] To achieve the above objectives, the present invention provides the following technical solution: a design method for an aluminum switch box based on an FPGA wiring matrix, comprising: Obtain the initial connection topology data of the FPGA routing matrix. The initial connection topology data includes multiple node coordinates and multiple connection paths. The multiple connection paths extend along a first direction and are arranged at intervals along a second direction. The second direction intersects with the first direction. First layout data is generated based on the initial connection topology data. The first layout data includes multiple first node positions. The orthographic projection of the multiple first node positions onto the coordinates of each node in the initial connection topology data is located on the corresponding connection path. The multiple first node positions located on each connection path are distributed at intervals along the first direction and cross the connection path along the second direction. A second layout data is generated based on the first layout data. The second layout data includes multiple channel segments. The orthographic projection of each of the multiple channel segments onto each connecting path in the initial connection topology data is located on the corresponding connecting path. The multiple channel segments located on each connecting path are distributed at intervals along the first direction and cross the connecting path along the second direction. The positions of a single channel segment located on each connecting path and a single first node located on each connecting path are arranged alternately at intervals along the first direction. Aluminum wiring pattern data is generated based on the second layout data. The aluminum wiring pattern data includes multiple first wiring segments and multiple second wiring segments. The orthographic projections of the multiple first wiring segments and multiple second wiring segments in the initial connection topology data are arranged alternately along the first direction. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. Etching mask data is generated based on the aluminum wiring pattern data, and an aluminum switch box is formed on the aluminum substrate based on the etching mask data.

[0005] Preferably, generating first layout data based on the initial connection topology data includes: Perform node clustering analysis on the initial connection topology data to generate multiple cluster center coordinates; The coordinates of each cluster center are offset by a preset distance along the second direction to generate the position of the first node in the first layout data; The distance threshold for node clustering analysis and the preset distance are determined based on the density distribution of node coordinates and the signal priority of node coordinates in the initial connection topology data.

[0006] Preferably, generating second layout data based on the first layout data includes: Based on the location of the first node, determine the available channel intervals on each of the connecting paths; The available channel intervals are divided into multiple sub-intervals at equal intervals along the first direction to generate the channel segments; The number of available channel segments is determined based on the signal priority of each first node location, and each channel segment corresponds to a different power supply level.

[0007] Preferably, before generating aluminum wiring pattern data based on the second layout data, the method further includes: Based on the second layout data, oxide protection layer data is generated, which includes the oxide layer thickness distribution on the surfaces of each of the switching units and each of the interconnect lines; Etching mask data is generated based on the aluminum wiring pattern data, including: The thickness of the aluminum material layer on the surface of the aluminum substrate is determined based on the oxide protective layer data, and the size parameters of each mask window pattern in the etching mask data are generated based on the thickness of the aluminum material layer. The etching mask data includes multiple mask window patterns, and the orthographic projection of each connection path in the initial connection topology data of the multiple mask window patterns corresponds one-to-one with the first wiring segment and the second wiring segment.

[0008] Preferably, the aluminum switch box further includes a first power supply area, a second power supply area, and a third power supply area, wherein the first power supply area is connected to the first-level interconnection lines, the second power supply area is connected to the second-level interconnection lines, and the third power supply area is connected to the third-level interconnection lines. After forming an aluminum switch box on an aluminum substrate based on the etching mask data, the method further includes: A first passivation layer, a second passivation layer, and a third passivation layer are formed on the first power region, the second power region, and the third power region, respectively, and the first passivation layer, the second passivation layer, and the third passivation layer are formed simultaneously. A first pad, a second pad, and a third pad are formed on the first passivation layer, the second passivation layer, and the third passivation layer, respectively, and the first pad, the second pad, and the third pad are formed simultaneously.

[0009] Preferably, the top surfaces of the first passivation layer, the second passivation layer, and the third passivation layer are flush, and the top surface of each switch unit is flush with the top surface of each interconnection line.

[0010] Preferably, after generating etching mask data based on the aluminum wiring pattern data, the method further includes: Optical proximity correction is performed on the etched mask data to correct the edge positions of each mask window pattern.

[0011] Preferably, forming an aluminum switch box on an aluminum substrate based on the etching mask data includes: The reactive ion etching process is used to sequentially etch the oxide layer, aluminum layer and titanium nitride adhesion layer on the surface of the aluminum substrate in the same etching machine based on the etching mask data. The aluminum switch box includes several switch units and interconnecting lines connecting each switch unit. Each switch unit includes a first wiring segment and a second wiring segment.

[0012] Preferably, the first pad includes the portion of the aluminum material layer located in the first power region, the first passivation layer, and the first pad metal layer; the second pad includes the portion of the aluminum material layer located in the second power region, the second passivation layer, and the second pad metal layer; the third pad includes the portion of the aluminum material layer located in the third power region, the third passivation layer, and the third pad metal layer; the oxide protection layer data is associated with the thickness data of the first passivation layer, the second passivation layer, and the third passivation layer, and the size of each mask window pattern is determined jointly based on the oxide protection layer data and the passivation layer thickness data.

[0013] An aluminum switch box design system based on an FPGA routing matrix is ​​applicable to the aforementioned aluminum switch box design method based on an FPGA routing matrix, including: The data acquisition module is configured to acquire the initial connection topology data of the FPGA wiring matrix. The initial connection topology data includes multiple node coordinates and multiple connection paths. The multiple connection paths extend along a first direction and are arranged at intervals along a second direction. The second direction intersects with the first direction. The first layout module is configured to generate first layout data based on the initial connection topology data. The first layout data includes multiple first node positions. The orthographic projection of the multiple first node positions onto the coordinates of each node in the initial connection topology data is located on the corresponding connection path. The multiple first node positions located on each connection path are distributed at intervals along the first direction and span the connection path along the second direction. The second layout module is configured to generate second layout data based on the first layout data. The second layout data includes multiple channel segments. The orthographic projection of each of the multiple channel segments onto the connection path in the initial connection topology data is located on the corresponding connection path. The multiple channel segments located on each connection path are distributed at intervals along the first direction and cross the connection path along the second direction. The positions of a single channel segment located on each connection path and a single first node located on each connection path are arranged alternately at intervals along the first direction. The pattern wiring module is configured to generate aluminum wiring pattern data based on the second layout data. The aluminum wiring pattern data includes multiple first wiring segments and multiple second wiring segments. The orthographic projections of the multiple first wiring segments and multiple second wiring segments in the initial connection topology data are arranged alternately along the first direction. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. The etching generation module is configured to generate etching mask data based on the aluminum wiring pattern data, and to form an aluminum switch box on an aluminum substrate based on the etching mask data.

[0014] Compared with the prior art, the beneficial effects of the present invention are: (1) The present invention generates the first layout data by node clustering analysis and signal priority-driven offset, and then dynamically divides the channel into segments according to the signal priority and assigns different power levels, so that the interconnection structure of the switch box closely matches the original wiring requirements of the FPGA, significantly improving the wiring density and signal transmission efficiency, while reducing parasitic capacitance and resistance. (2) The present invention determines the window size of the etching mask by combining the oxide protection layer data and the passivation layer thickness data, and simultaneously forms the passivation layer and pads of each power area. Combined with optical proximity correction and reactive ion etching processes, it ensures good isolation between different power areas and planarization of the top surface, thereby improving the yield, power integrity and long-term working stability of the switch box. Attached Figure Description

[0015] Figure 1 This is a schematic flowchart of the overall method in one embodiment of the present invention; Figure 2 This is a schematic diagram of the overall system architecture in one embodiment of the present invention.

[0016] In the diagram: 1. Data acquisition module; 2. First layout module; 3. Second layout module; 4. Pattern routing module; 5. Etching generation module. Detailed Implementation

[0017] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0018] Example 1, please refer to Figure 1 This invention provides a technical solution: a design method for an aluminum switch box based on an FPGA wiring matrix, comprising: S1. Obtain the initial connection topology data of the FPGA routing matrix. The initial connection topology data includes multiple node coordinates and multiple connection paths. The multiple connection paths extend along the first direction and are arranged at intervals along the second direction. The second direction intersects the first direction. S2. Generate first layout data based on the initial connection topology data. The first layout data includes multiple first node positions. The orthographic projection of the multiple first node positions onto the coordinates of each node in the initial connection topology data is located on the corresponding connection path. The multiple first node positions located on each connection path are distributed at intervals along the first direction and span the connection path along the second direction. S3. Generate second layout data based on the first layout data. The second layout data includes multiple channel segments. The orthographic projection of each channel segment onto the connection path in the initial connection topology data is located on the corresponding connection path. The multiple channel segments located on each connection path are distributed at intervals along the first direction and cross the connection path along the second direction. The positions of a single channel segment and a single first node located on each connection path are arranged alternately at intervals along the first direction. S4. Generate aluminum wiring pattern data based on the second layout data. The aluminum wiring pattern data includes multiple first wiring segments and multiple second wiring segments. The orthographic projections of the multiple first wiring segments and multiple second wiring segments in the initial connection topology data are arranged alternately along the first direction. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. S5. Generate etching mask data based on aluminum wiring pattern data, and form an aluminum switch box on an aluminum substrate based on the etching mask data.

[0019] It should be noted that there is a set of wiring resources inside the FPGA chip. Its initial connection topology data includes multiple node coordinates and several connection paths. All connection paths extend along the first horizontal direction and are arranged at equal intervals along the second vertical direction. For example, there are 4 horizontal tracks, each track has several nodes, and the nodes are located at specific horizontal positions on the track. Obtain these initial connection topology data; the data shows that: the track numbers are 1 to 4 from bottom to top, each track is 10 mm long, and the horizontal coordinates of the nodes on the track are 2 mm, 5 mm, 8 mm, etc.; all nodes are located on the center line of the track; First layout data is generated based on the initial connection topology data. The first layout data contains multiple first node positions. The orthographic projection of these first node positions onto the initial connection path coincides with the original node coordinates. Each first node position is actually a rectangular area, centered horizontally at the node coordinates, and spanning the width of the entire track vertically. For example, if the track width is 0.2 mm, the height of the first node position is 0.2 mm and the width is 0.1 mm. Therefore, multiple first node positions on each track are distributed at intervals horizontally, and each first node position spans the entire track vertically. For example, there is a first node position at horizontal distances of 2 mm, 5 mm, and 8 mm on track 1. The second layout data is generated based on the first layout data. The second layout data includes multiple channel segments. The channel segments are also located on the connecting path. Each channel segment is a rectangular area, which is projected onto the track and has a certain length in the horizontal direction and spans the entire track in the vertical direction. The channel segments and the first node position are arranged alternately in the horizontal direction. For example, on track 1, from left to right, they are: channel segment, first node position, channel segment, first node position, channel segment. The horizontal length of the channel segment is designed to be approximately equal to the horizontal length of the first node position or adjusted as needed. Assuming the width of the first node position is 0.1 mm and the width of the channel segment is 0.15 mm, the total length after alternating arrangement covers the entire track. Aluminum wiring pattern data is generated based on the second layout data. The aluminum wiring pattern data includes a first wiring segment and a second wiring segment. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. That is, the first wiring segment corresponds to the channel segment, and the second wiring segment corresponds to the first node position. They are arranged alternately on the track. For example, on track 1, the first wiring segment, the second wiring segment, the first wiring segment, the second wiring segment, and the first wiring segment are arranged in sequence. These wiring segments are part of aluminum wires used to connect the switch box inside the FPGA. Etching mask data is generated based on aluminum wiring pattern data; the etching mask data is a photomask pattern, in which transparent areas correspond to areas where aluminum should be retained, and opaque areas correspond to areas to be etched away; according to the mask data, photolithography and etching are performed on a substrate covered with an aluminum layer to finally form an aluminum switch box; the aluminum lines on the switch box are arranged alternately according to the first wiring segment and the second wiring segment, so that the signal can be transmitted along the horizontal track and vertical connection or switching is realized at the node position.

[0020] In an optional embodiment, generating first layout data based on initial connection topology data includes: Perform node clustering analysis on the initial connection topology data to generate multiple cluster center coordinates; The coordinates of each cluster center are offset by a preset distance along the second direction to generate the position of the first node in the first layout data; The distance threshold and preset distance for node clustering analysis are determined based on the density distribution of each node's coordinates and the signal priority of each node's coordinates in the initial connection topology data.

[0021] It should be noted that the initial connection topology data in the FPGA chip's wiring matrix includes nodes distributed across multiple horizontal tracks. Taking one of these horizontal tracks as an example, this track is 10 mm long and contains 15 nodes with horizontal coordinates of 0.1 mm, 0.3 mm, 0.35 mm, 0.38 mm, 0.6 mm, 0.62 mm, 0.65 mm, 0.9 mm, 0.92 mm, 1.2 mm, 1.25 mm, 1.28 mm, 1.6 mm, 1.63 mm, and 1.65 mm. Some of these nodes are clustered together, while others are scattered. Cluster analysis was performed on these nodes. The clustering distance threshold was dynamically determined based on the density distribution of nodes on the track and the signal priority of each node. The density distribution analysis showed that there were 4 nodes in the 0.3 to 0.4 mm range with a spacing of less than 0.05 mm, indicating high density; 3 nodes in the 0.6 to 0.65 mm range with a spacing of approximately 0.03 mm, also indicating high density; and 4 nodes in the 1.2 to 1.3 mm range with a spacing of approximately 0.03 mm. The remaining nodes were relatively sparse. At the same time, nodes with higher signal priority, such as clock signal nodes, require more precise wiring, so the clustering threshold was reduced accordingly to ensure that high-priority nodes were not over-merged. The basic clustering distance threshold was set to 0.08 mm, and reduced to 0.04 mm for high-priority node regions. The nodes were then clustered as follows: in the 0.3 to 0.4 mm range, all four nodes with pairwise distances less than 0.04 mm were clustered into one cluster with a cluster center at 0.36 mm; in the 0.6 to 0.65 mm range, all three nodes with pairwise distances less than 0.08 mm were clustered into one cluster with a center at 0.625 mm; in the 1.2 to 1.3 mm range, all four nodes with pairwise distances less than 0.08 mm were clustered into one cluster with a center at 1.258 mm; the other two isolated nodes at 0.1 mm and 1.6 mm each formed their own cluster, centered on themselves; the nodes at 0.9 mm and 0.92 mm, with a distance of 0.02 mm, were clustered into one cluster with a center at 0.91 mm; a total of six cluster center coordinates were obtained: 0.1, 0.36, 0.625, 0.91, 1.258, and 1.6 mm. Offset the coordinates of these cluster centers along the second direction, i.e., the vertical direction, by a preset distance. The preset distance is also determined based on the node density distribution and signal priority. For high-density areas, the offset distance can be slightly larger to avoid congestion in the vertical direction. For high-priority signals, the offset distance is smaller to shorten the signal path. In this example, the basic offset distance is set to 0.05 mm, and the high-priority area is offset by 0.02 mm. Assuming the cluster corresponding to 0.36 mm contains high-priority signals, the offset is 0.02 mm; the cluster corresponding to 0.625 mm has moderate signal priority, so the offset is 0.05 mm; the remaining clusters are processed normally with an offset of 0.04 mm; the offset direction is uniformly towards the positive vertical direction, i.e., away from the track centerline; thus, the new coordinates of the first node positions in the vertical direction are obtained; for example, if the original track centerline is located at Y=0, then the Y coordinates of each first node position are 0.04, 0.02, 0.05, 0.04, 0.04, and 0.04 mm respectively; while the horizontal coordinates remain unchanged and are the coordinates of the cluster centers; These first node positions are the node positions in the first layout data; they have the same horizontal coordinates on the orthographic projection of the initial connection path, but their vertical directions have deviated from the original node positions, so that a staggered structure can be formed in the subsequent aluminum wiring pattern, reducing parasitic capacitance and improving signal integrity.

[0022] In an optional embodiment, generating second layout data based on first layout data includes: The available channel intervals on each connecting path are determined based on the location of the first node; Within each available channel interval, multiple sub-intervals are equally spaced along the first direction to generate channel segments; The number of available channel segments is determined based on the signal priority at each first node position, and each channel segment corresponds to a different power supply level.

[0023] It should be noted that the horizontal coordinates of the first node positions in the first layout data of a horizontal connection path of the FPGA routing matrix are 0.1 mm, 0.36 mm, 0.625 mm, 0.91 mm, 1.258 mm, and 1.6 mm, respectively, and the total length of the track is 2.0 mm. Based on these first node positions, the available channel intervals on the connection path are determined, namely the blank intervals between adjacent first node positions and between the two ends of the track and the first and last nodes. Specifically, there are seven available channel intervals: interval A0 to 0.1 mm, interval B0.1 to 0.36 mm, interval C0.36 to 0.625 mm, interval D0.625 to 0.91 mm, interval E0.91 to 1.258 mm, interval F1.258 to 1.6 mm, and interval G1.6 to 2.0 mm. The number of sub-sections for each available channel interval is determined by the signal priority of its adjacent first node. In this example, signal priorities are divided into three levels: high, medium, and low. High-priority nodes require finer channel segmentation to provide multiple power levels or lower parasitic resistance. Specific rules: If at least one of the two adjacent nodes of an interval is of high priority, the interval is divided into 4 sub-sections; if both adjacent nodes are of medium priority, it is divided into 3 sub-sections; if both are of low priority, it is divided into 2 sub-sections; if there is no node at one end, i.e., the track endpoint, it is treated according to the priority of the only adjacent node. The first node position is assigned as follows: 0.1 mm is low priority, 0.36 mm is high priority, 0.625 mm is medium priority, 0.91 mm is medium priority, 1.258 mm is high priority, and 1.6 mm is low priority; therefore: Interval A is divided into two sub-intervals, each with a length of 0.05 mm, with adjacent nodes having a low priority of 0.1. Interval B has adjacent nodes with a low value of 0.1 and a high value of 0.36, which have high priority and are divided into 4 sub-intervals, each with a length of 0.065 mm. Among the adjacent nodes of interval C, those with a height of 0.36 and 0.625 have higher priority and are divided into 4 sub-intervals, each with a length of 0.06625 mm. Interval D is adjacent to nodes 0.625 and 0.91, both of which are in the middle, so it is divided into 3 sub-intervals, each with a length of 0.095 mm; Interval E has adjacent nodes with a middle value of 0.91 and a height value of 1.258, which have high priority. It is divided into 4 sub-intervals, each with a length of 0.087 mm. Interval F has adjacent nodes with a height of 1.258 and a low height of 1.6, which have high priority and are divided into 4 sub-intervals, each with a length of 0.0855 mm; Interval G is divided into two sub-intervals, each with a length of 0.2 mm, with adjacent nodes 1.6 low. Within each sub-interval, there corresponds to a channel segment; a channel segment is a rectangular area that spans the entire connecting line along the second direction, i.e., the vertical direction, and its horizontal length is equal to the length of the sub-interval; therefore, on the entire track, the channel segments and the first node positions are arranged alternately along the horizontal direction, in the following order: channel segment from interval A, first node position 0.1, channel segment from interval B, first node position 0.36, channel segment from interval C, first node position 0.625, channel segment from interval D, first node position 0.91, channel segment from interval E, first node position 1.258, channel segment from interval F, first node position 1.6, channel segment from interval G; Each channel segment can be assigned a different power level; for example, the channel segments corresponding to high-priority areas are more finely divided and can be connected to different power voltage rails, such as 1.0V, 1.2V, 1.5V, etc.; while low-priority areas only provide a single reference voltage; in this way, when generating aluminum wiring patterns later, these channel segments will form wires with different potentials to meet the needs of multiple power domains inside the FPGA; through this method of dynamically adjusting the partition density based on signal priority, the second layout data realizes fine-grained management of wiring resources, improving the design flexibility and power integrity of the switch box.

[0024] In an optional embodiment, before generating aluminum wiring pattern data based on the second layout data, the method further includes: Oxide protection layer data is generated based on the second layout data. The oxide protection layer data includes the oxide layer thickness distribution on the surface of each switching unit and each interconnect line. Etching mask data is generated based on aluminum wiring pattern data, including: The thickness of the aluminum material layer on the surface of the aluminum substrate is determined based on the oxide protective layer data, and the size parameters of each mask window pattern in the etching mask data are generated based on the thickness of the aluminum material layer. The etching mask data includes multiple mask window patterns, and the orthographic projections of each connection path in the initial connection topology data of the multiple mask window patterns correspond one-to-one with the first wiring segment and the second wiring segment.

[0025] It should be noted that in the FPGA switch box design, a layer of pure aluminum with a thickness of 1 micrometer has been deposited on the surface of the aluminum substrate. According to the second layout data, multiple horizontal wiring segments and node regions will be formed on this aluminum layer. However, before etching, the aluminum surface naturally oxidizes to form a layer of aluminum oxide with uneven thickness: in the central area, due to masking, the oxide is thinner, about 5 nanometers; in the edge area, which is exposed to air for a longer time, the oxide layer is about 10 nanometers thick. In addition, some switch units need to withstand higher voltages, so a thicker oxide layer needs to be grown as insulation, with a thickness of up to 50 nanometers. Oxide protective layer data is generated based on the second layout data, which records the target oxide layer thickness at each location; for example, for the area corresponding to a typical wiring channel segment, the oxide layer thickness requirement is 8 nanometers; for the switch node area, the oxide layer thickness requirement is 5 nanometers; and for the high-voltage isolation area, the requirement is 50 nanometers. The actual thickness of the aluminum material layer on the aluminum substrate surface was determined based on the oxide protective layer data. The original deposition thickness of the aluminum material layer was 1 micrometer, but due to oxidation consumption, the actual remaining aluminum thickness will be slightly less than 1 micrometer. For example, the volume ratio of aluminum oxide to aluminum is about 1.3:1, and generating 10 nanometers of aluminum oxide will consume about 7.7 nanometers of aluminum. Therefore, in areas with a thicker oxide layer, the underlying aluminum layer will be thinner. The remaining thickness of the aluminum material layer at each location was calculated as follows: the aluminum thickness in the ordinary channel segmentation area is about 0.992 micrometers, the aluminum thickness in the switch node area is about 0.996 micrometers, and the aluminum thickness in the high-voltage isolation area is about 0.96 micrometers. Based on the thickness of these aluminum material layers, the mask window pattern size parameters in the etching mask data are generated. The etching mask data includes multiple mask window patterns, each corresponding to a first wiring segment or a second wiring segment. Due to different aluminum layer thicknesses, the required etching time or over-etching compensation also varies. To ensure that the width and shape of the aluminum lines retained after etching conform to the design, the size of the mask window pattern needs to be corrected according to the aluminum layer thickness. The thinner the aluminum layer, the more severe the lateral corrosion during etching, so the mask window pattern needs to be appropriately reduced to compensate. For example, for the channel segmentation region with an aluminum layer thickness of 0.992 micrometers, the mask window pattern width is set to the design width of 0.15 mm minus a correction value of 0.002 mm, resulting in 0.148 mm. For the node region with an aluminum layer thickness of 0.996 micrometers, the correction value is smaller, and the window width is 0.1 mm minus 0.001 mm, resulting in 0.099 mm. For the high-voltage isolation area, where the aluminum layer is the thinnest, the window width needs to be reduced by 0.003 mm. All mask window patterns in the etching mask data are generated according to these corrected dimensions, and their orthographic projections correspond one-to-one with the first and second wiring segments. When photolithography and wet etching are performed using this mask, the aluminum wiring patterns obtained after etching have neat edges and high line width accuracy due to the difference in aluminum layer thickness caused by the oxide layer thickness, making the electrical performance of the switch box more reliable.

[0026] In an optional embodiment, the aluminum switch box further includes a first power supply area, a second power supply area, and a third power supply area, wherein the first power supply area is connected to a first-level interconnection line, the second power supply area is connected to a second-level interconnection line, and the third power supply area is connected to a third-level interconnection line. After forming an aluminum switch box on an aluminum substrate based on etching mask data, the method further includes: A first passivation layer, a second passivation layer, and a third passivation layer are formed on the first power region, the second power region, and the third power region, respectively, and the first passivation layer, the second passivation layer, and the third passivation layer are formed simultaneously. A first pad, a second pad, and a third pad are formed on the first passivation layer, the second passivation layer, and the third passivation layer, respectively, and the first pad, the second pad, and the third pad are formed simultaneously.

[0027] It should be noted that the aluminum switch box is used for the FPGA wiring matrix and contains a first power supply area, a second power supply area, and a third power supply area. The first power supply area connects to the first-level interconnect lines, which are used to power the core logic at a voltage of 0.8 volts. The second power supply area connects to the second-level interconnect lines and is used to power the input / output interfaces at a voltage of 1.8 volts. The third power supply area connects to the third-level interconnect lines and is used to power auxiliary circuits or flash memory at a voltage of 3.3 volts. The three power supply areas are isolated from each other on the aluminum substrate and separated by trenches formed by etching. After etching the aluminum wiring pattern based on the etching mask data, aluminum wires in different areas are exposed on the surface of the switch box; next, a passivation layer is deposited. Plasma-enhanced chemical vapor deposition (PECVD) is used to simultaneously deposit a silicon nitride (SiN) layer as a passivation layer on the entire wafer surface. This layer is continuous and covers all areas. Then, through photolithography and etching, windows are created in the passivation layer above the first power region, retaining the SiN in this region to form the first passivation layer with a thickness of 0.5 micrometers. Simultaneously, a second passivation layer with a thickness of 0.5 micrometers is formed above the second power region, and a third passivation layer with a thickness of 0.5 micrometers is formed above the third power region. Although these three passivation layers are formed in the same deposition step, the patterns of their respective regions can be preserved through subsequent selective etching, so they can be said to be formed simultaneously. Pads are formed at the passivation layer openings; a titanium-tungsten alloy layer as an adhesion layer and a gold layer as a conductive layer are simultaneously sputtered on the wafer surface using physical vapor deposition, and then thickened by photolithography and electroplating; finally, a first pad with a size of 100 micrometers by 100 micrometers is formed on the first power region for connecting to a 0.8-volt power supply; a second pad with a size of 120 micrometers by 120 micrometers is formed on the second power region for connecting to a 1.8-volt power supply; and a third pad with a size of 150 micrometers by 150 micrometers is formed on the third power region for connecting to a 3.3-volt power supply; these three pads are formed simultaneously in the same metal deposition and patterning process.

[0028] In an optional embodiment, the top surfaces of the first passivation layer, the second passivation layer, and the third passivation layer are flush, and the top surface of each switching unit is flush with the top surface of each interconnecting line.

[0029] It should be noted that during the manufacturing process of the aluminum switch box, aluminum wiring patterns for the first power area, the second power area, and the third power area are formed on the aluminum substrate by etching. The interconnection line thickness of the first power area is 1 micrometer, the interconnection line thickness of the second power area is also 1 micrometer, and the interconnection line thickness of the third power area is also 1 micrometer. The top surface height of the switching unit, such as a transistor or a transmission gate, in each area is consistent with the top surface design of the interconnection line. After forming the aluminum conductors, a silicon nitride passivation layer is deposited over the entire wafer surface with an initial deposition thickness of 1.2 micrometers. Due to surface undulations, the passivation layer is thinner above the conductors and switching units and thicker in the trench region. Subsequently, global planarization is performed using a chemical mechanical polishing (CMP) process. The CMP polishing slurry and parameters are optimized to uniformly thin the passivation layer until the top surfaces of all aluminum conductors and switching units are exposed. At this point, the top surfaces of the first, second, and third passivation layers are polished to be flush with the top surfaces of the aluminum conductors below. Actual measurements show that the height difference between the top surface of the first passivation layer and the top surface of the aluminum conductors in the first power region is less than 5 nanometers. The second and third passivation layers are similar, and the height difference between the top surfaces of each passivation layer is also within the allowable range. Since the top surfaces of the source, drain, and gate of each switching unit, such as the MOS transistor, have been planarized and aligned with the top surfaces of the aluminum interconnects in the previous process, after CMP, the top surfaces of all switching units, all interconnects, and the three passivation layers are all on the same horizontal plane. This flush structure is beneficial for the subsequent formation of uniform pad contacts and packaging, and avoids the risk of stress concentration or open circuit caused by step height differences. For example, in a sample of an actual manufactured switch box, the height of the top surface of the first passivation layer region was measured by atomic force microscopy. The height of the top surface of the adjacent first interconnect line was 1.02 micrometers, the height of the top surface of the second passivation layer region was 1.02 micrometers, and the height of the top surface of the second interconnect line was 1.00 micrometers. The differences were all less than 30 nanometers, which is far better than the 200 nanometer step when it was not planarized. This flush design significantly improves the subsequent photolithography alignment accuracy and the reliability of the pad connection.

[0030] In an optional embodiment, after generating etching mask data based on aluminum wiring pattern data, the method further includes: Optical proximity correction is performed on the etched mask data to correct the edge positions of each mask window pattern.

[0031] It should be noted that in the design of the aluminum switch box, the etching mask data includes multiple rectangular window patterns used to define the first and second wiring segments in the aluminum wiring pattern; these rectangles are designed to have a width of 0.25 micrometers, a spacing of 0.35 micrometers, and straight right angles at the edges; however, in the actual photolithography process, due to light diffraction and proximity effect, the light fields of adjacent patterns will interfere with each other, resulting in distortions such as rounded corners, shortened line ends, narrowed line width, and even bridging in the pattern formed on the photoresist; To compensate for these distortions, optical proximity correction is performed on the mask data. First, for the ends of isolated lines, a hammer-shaped auxiliary graphic is added to the end of the mask window pattern. For example, the end of an isolated wiring was originally designed as a rectangular end face with a width of 0.25 micrometers. After correction, a square hammer with a width of 0.05 micrometers and a length of 0.05 micrometers is extended outward at its end so that the exposed end of the line remains at a right angle and does not shrink back. For densely packed line areas, such as parallel line groups with a spacing of 0.35 micrometers, the width of the mask window pattern is increased and the edge position is adjusted; the original width of 0.25 micrometers is adjusted to 0.27 micrometers, while a tiny indentation is introduced on the sidewalls of the lines, i.e., a 0.02-micrometer-deep serrated compensation is created on the opposite edges of adjacent lines to reduce the light intensity superposition between adjacent lines and prevent bridging; for areas between line ends, sub-resolution auxiliary patterns are added, i.e., thin strips smaller than the lithographic resolution are placed on the mask to improve the focusing depth at the line ends; After correction, the edge position of the mask window pattern was locally offset relative to the original design. For example, in the original design, a rectangle with all four corners at 90 degrees was extended outward by a square auxiliary structure with a side length of 0.03 micrometers after correction. The straight edges of the dense line area were shifted outward by 0.01 micrometers, while the line ends were extended by an additional 0.02 micrometers. These corrections were determined through optical simulation and iterative optimization, making the exposed photoresist profile closer to the original design. Using the corrected mask for photolithography, the actual aluminum line width formed is 0.251 micrometers, the line end shortening is less than 0.01 micrometers, the minimum spacing between adjacent lines is 0.352 micrometers, and there are no bridging defects. Compared with the uncorrected mask, the line width error is reduced from 15% to less than 3%, which significantly improves the yield and signal integrity of aluminum switch boxes.

[0032] In an optional embodiment, forming an aluminum switch box on an aluminum substrate based on etching mask data includes: The reactive ion etching process is used to sequentially etch the oxide layer, aluminum layer and titanium nitride adhesion layer on the surface of the aluminum substrate based on the etching mask data in the same etching machine. The aluminum switch box includes several switch units and interconnecting lines connecting each switch unit. Each switch unit includes a first wiring segment and a second wiring segment.

[0033] It should be noted that a titanium nitride adhesion layer, an aluminum layer, and a surface natural oxide layer have been deposited on the aluminum substrate; the titanium nitride adhesion layer is 50 nanometers thick, the aluminum layer is 1 micrometer thick, and the oxide layer is about 5 nanometers thick; the mask data has been optically proximity corrected, and the wiring pattern of the switch box is defined on the photoresist, including a pattern of alternating first and second wiring segments; The substrate is placed in the vacuum chamber of a reactive ion etching machine, which is equipped with multiple gas passages and an RF power supply; the etching process is carried out continuously in three steps without breaking the vacuum. Etching of the surface oxide layer; introduction of a mixture of trifluoromethane and oxygen, setting the RF power to 200 watts and the chamber pressure to 10 Pa; the reaction of trifluoromethane and aluminum oxide to generate volatile products, with oxygen assisting in the removal of residual carbon; the etching time is approximately 30 seconds, and the process automatically stops after the aluminum oxide signal is detected to have disappeared at the endpoint; upon completion of this step, the oxide layer in the area to be etched is completely removed, exposing the underlying aluminum layer, while the oxide layer in the photoresist-covered area remains intact; Etching of the aluminum layer; switching gas to a mixture of chlorine and boron trichloride, RF power adjusted to 300 watts, pressure 15 Pa; chlorine reacts with aluminum to generate aluminum chloride volatiles, boron trichloride provides physical bombardment assistance; etching time is calculated based on an aluminum layer thickness of 1 micrometer and an etching rate of 1.2 micrometers per minute, approximately 50 seconds; during the process, laser interference endpoint detection is used, and when etching reaches the titanium nitride adhesion layer, the reflected signal changes, and the process is immediately stopped; this step precisely etches away the exposed aluminum layer, forming an aluminum wire pattern, including a first wiring segment and a second wiring segment, as well as the isolation trench between them; each switching unit consists of an adjacent first wiring segment and a second wiring segment, which are connected through subsequent vias or directly to form a switching node; Etch the titanium nitride adhesion layer; switch the gas to chlorine and argon, RF power 250 W, pressure 8 Pa; titanium nitride reacts with chlorine to generate titanium tetrachloride and nitrogen, argon enhances anisotropic etching; etching time is about 20 seconds, etching away the exposed titanium nitride until the underlying aluminum substrate or insulating layer is reached; end when the titanium signal disappears at the endpoint. Throughout the etching process, photoresist acts as a mask to protect areas that do not require etching. After etching, oxygen is introduced to remove residual photoresist, followed by cleaning with deionized water and drying. In the resulting aluminum switch box, the interconnecting lines consist of alternating first and second wiring segments. Each switch unit includes one first wiring segment and one second wiring segment, which are electrically connected through sidewalls or subsequent dielectric windows. For example, in a transmission gate switch unit, the source is connected to the first wiring segment, the drain is connected to the second wiring segment, and the gate is controlled by the upper polysilicon layer. These wiring segments and interconnecting lines have uniform linewidths, sidewall perpendicularity greater than 85 degrees, and no residual aluminum or titanium nitride, ensuring low contact resistance and high reliability of the switch box.

[0034] In an optional embodiment, the first pad includes a portion of an aluminum material layer located in the first power region, a first passivation layer, and a first pad metal layer; the second pad includes a portion of an aluminum material layer located in the second power region, a second passivation layer, and a second pad metal layer; the third pad includes a portion of an aluminum material layer located in the third power region, a third passivation layer, and a third pad metal layer; the oxide protection layer data is associated with the thickness data of the first passivation layer, the second passivation layer, and the third passivation layer, and the size of each mask window pattern is determined based on the oxide protection layer data and the passivation layer thickness data.

[0035] It should be noted that the aluminum switch box includes a first, second, and third power supply area, which are used for powering the core logic, input / output interfaces, and auxiliary circuits, respectively. The aluminum material layer thickness in the first power supply area is 1.0 micrometer, and the second and third areas are the same. Aluminum oxide is formed by natural oxidation on the surface of the aluminum layer, but due to process differences, the oxide layer thickness is 12 nanometers in the first area, 8 nanometers in the second area, and 5 nanometers in the third area. Oxidation protection layer data is generated, and the oxide layer thickness of each area is recorded. Subsequent passivation layer deposition: The first passivation layer is 0.6 μm thick, the second passivation layer is 0.5 μm thick, and the third passivation layer is 0.4 μm thick; these thicknesses are set independently according to the withstand voltage requirements of each power region; there is a correlation between the oxide protection layer data and the passivation layer thickness data, because the two together determine the total dielectric thickness that needs to be penetrated when etching the openings; for the first region, the total thickness is 12 nm oxide layer plus 0.6 μm passivation layer equals 0.612 μm; for the second region, it is 8 nm plus 0.5 μm equals 0.508 μm; for the third region, it is 5 nm plus 0.4 μm equals 0.405 μm; When generating etching mask data, the size of the mask window pattern needs to be determined based on the combined data of the oxide protective layer and the passivation layer thickness. Since the lateral corrosion amount varies with the total thickness, compensation is needed to adjust the window size to ensure consistent final aperture size. The target aperture size is a square with a side length of 20 micrometers. Through simulation and experimentation, the compensation rule is determined: for every 10 nanometers of total thickness deviation, the window size needs to be corrected by 0.02 micrometers. Taking the thinnest region (third region) as the benchmark, its window size is set to 20.00 micrometers. The second region has a total thickness 0.103 micrometers greater than the third region, requiring additional compensation; the window size is reduced by 0.206 micrometers to 19.794 micrometers. The first region has a total thickness 0.207 micrometers greater than the third region, so the window size is reduced by 0.414 micrometers to 19.586 micrometers. In actual fabrication, this mask is used for photolithography and etching. A 19.586-micrometer square window is etched into the passivation and oxide layers of the first region. Due to lateral etching, the final window size is increased to approximately 20 micrometers. Similarly, the window in the second region is increased to approximately 20 micrometers, and the window in the third region is also increased to 20 micrometers. Then, in the same process, pad metal layers are formed simultaneously: the first pad metal layer is 1.2 micrometers thick, the second pad metal layer is 1.0 micrometer thick, and the third pad metal layer is 0.8 micrometers thick, deposited within their respective windows and in contact with the underlying aluminum material layer. The final pad structure is as follows: The first pad includes a portion of an aluminum material layer located in the first power region, a first passivation layer opening thereon, and a first pad metal layer that fills the pad. The second pad includes a portion of the aluminum material layer located in the second power region, a second passivation layer opening, and a second pad metal layer; The third pad includes the portion of the aluminum material layer located in the third power region, the third passivation layer opening, and the third pad metal layer; The simultaneous formation of the three solder pads ensures the consistency and reliability of the electrical connections in the multi-power domain switch box.

[0036] Example 2, please refer to Figure 2 This invention provides a technical solution: an aluminum switch box design system based on an FPGA wiring matrix, applicable to the aforementioned aluminum switch box design method based on an FPGA wiring matrix, comprising: Data acquisition module 1 is configured to acquire the initial connection topology data of the FPGA wiring matrix. The initial connection topology data includes multiple node coordinates and multiple connection paths. The multiple connection paths extend along a first direction and are arranged at intervals along a second direction. The second direction intersects with the first direction. The first layout module 2 is configured to generate first layout data based on the initial connection topology data. The first layout data includes multiple first node positions. The orthographic projection of the multiple first node positions onto the coordinates of each node in the initial connection topology data is located on the corresponding connection path. The multiple first node positions located on each connection path are distributed at intervals along the first direction and span the connection path along the second direction. The second layout module 3 is configured to generate second layout data based on the first layout data. The second layout data includes multiple channel segments. The orthographic projection of each channel segment in the initial connection topology data is located on the corresponding connection path. The multiple channel segments located on each connection path are distributed at intervals along the first direction and cross the connection path along the second direction. The positions of a single channel segment and a single first node located on each connection path are arranged alternately at intervals along the first direction. The pattern routing module 4 is configured to generate aluminum wiring pattern data based on the second layout data. The aluminum wiring pattern data includes multiple first wiring segments and multiple second wiring segments. The orthographic projections of the multiple first wiring segments and multiple second wiring segments in the initial connection topology data are arranged alternately along the first direction. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. The etching generation module 5 is configured to generate etching mask data based on aluminum wiring pattern data, and form an aluminum switch box on an aluminum substrate based on the etching mask data.

[0037] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited thereto. Various changes can be made within the scope of knowledge possessed by those skilled in the art without departing from the spirit of the present invention.

Claims

1. A design method for an aluminum switch box based on an FPGA routing matrix, characterized in that, include: Obtain the initial connection topology data of the FPGA routing matrix. The initial connection topology data includes multiple node coordinates and multiple connection paths. The multiple connection paths extend along a first direction and are arranged at intervals along a second direction. The second direction intersects with the first direction. First layout data is generated based on the initial connection topology data. The first layout data includes multiple first node positions. The orthographic projection of the multiple first node positions onto the coordinates of each node in the initial connection topology data is located on the corresponding connection path. The multiple first node positions located on each connection path are distributed at intervals along the first direction and cross the connection path along the second direction. A second layout data is generated based on the first layout data. The second layout data includes multiple channel segments. The orthographic projection of each of the multiple channel segments onto each connecting path in the initial connection topology data is located on the corresponding connecting path. The multiple channel segments located on each connecting path are distributed at intervals along the first direction and cross the connecting path along the second direction. The positions of a single channel segment located on each connecting path and a single first node located on each connecting path are arranged alternately at intervals along the first direction. Aluminum wiring pattern data is generated based on the second layout data. The aluminum wiring pattern data includes multiple first wiring segments and multiple second wiring segments. The orthographic projections of the multiple first wiring segments and multiple second wiring segments in the initial connection topology data are arranged alternately along the first direction. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. Etching mask data is generated based on the aluminum wiring pattern data, and an aluminum switch box is formed on the aluminum substrate based on the etching mask data.

2. The aluminum switch box design method based on FPGA wiring matrix according to claim 1, characterized in that, First layout data is generated based on the initial connection topology data, including: Perform node clustering analysis on the initial connection topology data to generate multiple cluster center coordinates; The coordinates of each cluster center are offset by a preset distance along the second direction to generate the position of the first node in the first layout data; The distance threshold for node clustering analysis and the preset distance are determined based on the density distribution of node coordinates and the signal priority of node coordinates in the initial connection topology data.

3. The aluminum switch box design method based on FPGA wiring matrix according to claim 2, characterized in that, Generate second layout data based on the first layout data, including: Based on the location of the first node, determine the available channel intervals on each of the connecting paths; The available channel intervals are divided into multiple sub-intervals at equal intervals along the first direction to generate the channel segments; The number of available channel segments is determined based on the signal priority of each first node location, and each channel segment corresponds to a different power supply level.

4. The aluminum switch box design method based on FPGA wiring matrix according to claim 3, characterized in that, Before generating aluminum wiring pattern data based on the second layout data, the method further includes: Based on the second layout data, oxide protection layer data is generated, which includes the oxide layer thickness distribution on the surfaces of each of the switching units and each of the interconnect lines; Etching mask data is generated based on the aluminum wiring pattern data, including: The thickness of the aluminum material layer on the surface of the aluminum substrate is determined based on the oxide protective layer data, and the size parameters of each mask window pattern in the etching mask data are generated based on the thickness of the aluminum material layer. The etching mask data includes multiple mask window patterns, and the orthographic projection of each connection path in the initial connection topology data of the multiple mask window patterns corresponds one-to-one with the first wiring segment and the second wiring segment.

5. The aluminum switch box design method based on FPGA wiring matrix according to claim 4, characterized in that, The aluminum switch box further includes a first power supply area, a second power supply area, and a third power supply area. The first power supply area is connected to the first-level interconnection lines, the second power supply area is connected to the second-level interconnection lines, and the third power supply area is connected to the third-level interconnection lines. After forming an aluminum switch box on an aluminum substrate based on the etching mask data, the method further includes: A first passivation layer, a second passivation layer, and a third passivation layer are formed on the first power region, the second power region, and the third power region, respectively, and the first passivation layer, the second passivation layer, and the third passivation layer are formed simultaneously. A first pad, a second pad, and a third pad are formed on the first passivation layer, the second passivation layer, and the third passivation layer, respectively, and the first pad, the second pad, and the third pad are formed simultaneously.

6. The aluminum switch box design method based on FPGA wiring matrix according to claim 5, characterized in that, The top surfaces of the first passivation layer, the second passivation layer, and the third passivation layer are flush, and the top surface of each switch unit is flush with the top surface of each interconnection line.

7. The aluminum switch box design method based on FPGA wiring matrix according to claim 6, characterized in that, After generating etching mask data based on the aluminum wiring pattern data, the method further includes: Optical proximity correction is performed on the etched mask data to correct the edge positions of each mask window pattern.

8. The aluminum switch box design method based on FPGA wiring matrix according to claim 7, characterized in that, An aluminum switch box is formed on an aluminum substrate based on the etching mask data, including: The reactive ion etching process is used to sequentially etch the oxide layer, aluminum layer and titanium nitride adhesion layer on the surface of the aluminum substrate in the same etching machine based on the etching mask data. The aluminum switch box includes several switch units and interconnecting lines connecting each switch unit. Each switch unit includes a first wiring segment and a second wiring segment.

9. The aluminum switch box design method based on FPGA wiring matrix according to claim 8, characterized in that, The first pad includes the portion of the aluminum material layer located in the first power region, the first passivation layer, and the first pad metal layer; the second pad includes the portion of the aluminum material layer located in the second power region, the second passivation layer, and the second pad metal layer; the third pad includes the portion of the aluminum material layer located in the third power region, the third passivation layer, and the third pad metal layer; the oxide protection layer data is associated with the thickness data of the first passivation layer, the second passivation layer, and the third passivation layer, and the size of each mask window pattern is determined jointly based on the oxide protection layer data and the passivation layer thickness data.

10. An aluminum switch box design system based on an FPGA routing matrix, applicable to the aluminum switch box design method based on an FPGA routing matrix as described in any one of claims 1-9, characterized in that, include: The data acquisition module is configured to acquire the initial connection topology data of the FPGA wiring matrix. The initial connection topology data includes multiple node coordinates and multiple connection paths. The multiple connection paths extend along a first direction and are arranged at intervals along a second direction. The second direction intersects with the first direction. The first layout module is configured to generate first layout data based on the initial connection topology data. The first layout data includes multiple first node positions. The orthographic projection of the multiple first node positions onto the coordinates of each node in the initial connection topology data is located on the corresponding connection path. The multiple first node positions located on each connection path are distributed at intervals along the first direction and span the connection path along the second direction. The second layout module is configured to generate second layout data based on the first layout data. The second layout data includes multiple channel segments. The orthographic projection of each of the multiple channel segments onto the connection path in the initial connection topology data is located on the corresponding connection path. The multiple channel segments located on each connection path are distributed at intervals along the first direction and cross the connection path along the second direction. The positions of a single channel segment located on each connection path and a single first node located on each connection path are arranged alternately at intervals along the first direction. The pattern wiring module is configured to generate aluminum wiring pattern data based on the second layout data. The aluminum wiring pattern data includes multiple first wiring segments and multiple second wiring segments. The orthographic projections of the multiple first wiring segments and multiple second wiring segments in the initial connection topology data are arranged alternately along the first direction. The orthographic projection of the first wiring segment coincides with the orthographic projection of the channel segment, and the orthographic projection of the second wiring segment coincides with the orthographic projection of the first node position. The etching generation module is configured to generate etching mask data based on the aluminum wiring pattern data, and to form an aluminum switch box on an aluminum substrate based on the etching mask data.

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