A hardware-gated chip and method based on input quality perception

Abstract

The application discloses a kind of hardware door control chip and method based on input quality perception, belong to artificial intelligence chip and analog computing technical field.The chip includes: event polarity extraction and mapping circuit, external input event is converted into six-dimensional differential analog voltage;Effective polarity coverage calculation circuit, effective polarity coverage is calculated by analog comparator array;Initial uncertainty calculation circuit, statistical variance is calculated by differential amplifier and integrator;Causal chain activation state detection circuit, whether event matches preset causal chain is detected by analog correlation matching;U degree calculation circuit, according to the three elements of coverage, initial uncertainty and causal chain activation, the input quality index U degree is calculated by weighting;Gate comparison circuit, U degree is compared with gate threshold to generate gate signal;Uncertainty overrun forced interception circuit, when initial uncertainty is over threshold, independent trigger forced interception;Physical gate execution circuit, when U degree is below threshold or initial uncertainty is over threshold, input is physically blocked into main processing link by analog switch.The whole core calculation of the application is completed by analog circuit, response delay is nanosecond level, power consumption is microwatt level, and gate decision cannot be bypassed by software.

Description

Technical Field

[0001] This invention belongs to the field of artificial intelligence chips and analog computing technology, specifically relating to a chip and its data processing method that uses analog circuits to perceive the semantic quality of input events in real time and perform physical gating before the events enter the main processing link. Background Technology

[0002] Existing computing systems typically send external input directly into the main processing chain, lacking the ability to proactively assess the semantic quality of the input before it enters the main processing chain. This results in the following fundamental defects: (1) Lack of proactive input quality perception. When processing external input, existing chips typically send the input directly to the main processing link, unable to distinguish between meaningful input and garbled, meaningless, or abnormal data. Invalid input entering the main processing link not only consumes computing resources and power but may also cause the main processing link to make incorrect cognitive judgments. In safety-critical scenarios such as autonomous driving and industrial control, this "process first, judge later" mode poses serious safety hazards.

[0003] (2) Input verification remains at the physical or format layer. Current input verification circuits can only verify the physical integrity or format compliance of input data, but cannot determine whether the input is meaningful or credible at the semantic level. For example, a correctly formatted sensor data frame may be completely invalid, and current chips cannot detect such semantic-level anomalies at the input stage.

[0004] (3) Invalid inputs consume the computing resources of the main processing link. When the main processing link processes invalid inputs, it not only wastes computing power and power consumption, but may also pollute the internal state of the main processing link, which will affect the judgment of subsequent normal inputs.

[0005] (4) Lack of semantic-level hardware gating mechanism. Existing chips do not implement a hardware-level gating mechanism that determines whether to allow input based on the semantic quality of the input. Once the input enters the chip, it flows along the preset data path and cannot be intercepted by semantic-level judgment at the entry point.

[0006] The applicant's prior patent applications (such as CN202610601934.3, CN202610506445.X, etc.) have disclosed an energy evolution method, event relationship syntax, and global cognitive potential monitoring mechanism based on a six-dimensional situation coding space. The applicant also previously filed a patent application entitled "An Autonomous Perception and Security Arbitration Method and System for a Cognitive System," which discloses an algorithmic scheme for implementing input quality perception and gating decisions at the software level. However, these prior applications still pertain to software-level implementations. In scenarios requiring nanosecond-level response, microwatt-level power consumption, and physically unbypassable security gating, software implementations have inherent limitations: software operation requires CPU participation, resulting in instruction cycle delays; the software can be bypassed or tampered with by attackers; and software implementations cannot be deployed in resource-constrained scenarios such as sensor deployments. Therefore, there is an urgent need for a chip solution that can directly implement input quality perception and gating at the hardware physical level. Summary of the Invention

[0007] (a) Purpose of the invention The purpose of this invention is to provide a hardware gating chip and method based on input quality awareness, so as to solve the technical problems in the prior art, such as the lack of active input quality awareness capability of chips, input verification remaining at the physical layer or format layer, invalid input consuming the main processing link computing resources, and the lack of semantic-level hardware gating mechanism.

[0008] Specific objectives include: (1) A chip architecture that realizes input quality perception at the hardware physical level is provided, and the input semantic quality is calculated in real time before the event enters the main processing link through analog circuit.

[0009] (2) Provide a hardware calculation circuit for “effective polarity coverage”, which completes the statistics of effective semantic components in input events in nanosecond time through an analog comparator array.

[0010] (3) Provide a hardware calculation circuit for “initial uncertainty”, which calculates the degree of internal divergence of input events in real time through a differential amplifier and an integrator.

[0011] (4) Provide a hardware detection circuit for “causal chain activation state”, which uses a voltage mode matching circuit to determine whether the input event matches the preset safety key causal chain.

[0012] (5) Provides a physical gating circuit that, when the input quality index is lower than the preset gating threshold, physically intercepts the current input through a pure hardware circuit to block it from entering the main processing link.

[0013] (6) Provides a hardware gating mechanism with nanosecond-level response, so that input quality perception and gating decision are completed entirely at the analog circuit level, without software response delay, and cannot be bypassed by software attacks.

[0014] (II) Technical Solution To achieve the above objectives, the present invention provides the following technical solution: A hardware gating chip based on input quality perception, characterized in that it comprises: Event polarity extraction and mapping circuit: used to convert external input events into six-dimensional differential analog voltage signals.

[0015] The external input events include at least one of natural language text, sensor data, and control signals. When the input event is text, the external microprocessor extracts the event words, obtains the six-dimensional polarity values ​​through a lookup table, and then converts them into six differential voltages via a digital-to-analog converter. When the input event is sensor data, the external microprocessor maps the sensor feature vectors into six-dimensional polarity values ​​according to a preset rule template, and then converts them into six differential voltages via a digital-to-analog converter. When the input event itself is an analog signal, it can be directly connected to the event polarity extraction and mapping circuit.

[0016] The six dimensions of the six-dimensional polarity vector correspond to the first to the sixth dimensions, respectively. The first dimension corresponds to the system's foundational dimension, the second to the action dimension, the third to the information dimension, the fourth to the resource dimension, the fifth to the boundary dimension, and the sixth to the environment dimension. The polarity value of each dimension ranges from -1 to 1, with positive values ​​indicating a positive bias and negative values ​​indicating a negative bias. The difference between the positive and negative terminals of each of the six differential voltage channels is proportional to the polarity value of that dimension.

[0017] Effective polarity coverage calculation circuit: used to calculate the coverage of effective polarity in the six-dimensional differential voltage in real time.

[0018] The effective polarity coverage calculation circuit includes: six analog comparators, each of which receives the absolute value of the differential voltage of the corresponding dimension at its first input terminal and a preset reference voltage Vref at its second input terminal. When the absolute value of the differential voltage of the dimension is greater than or equal to Vref, it outputs a high level; otherwise, it outputs a low level; an analog adder, which accumulates the outputs of the six comparators and outputs the number of effective polarities; and a voltage divider network, which divides the number of effective polarities by 6 and outputs a coverage voltage of 0 to 1V.

[0019] The reference voltage Vref can be preset and calibrated via an on-chip programmable resistor array or an external configuration interface to adapt to the sensitivity requirements of effective polarity determination in different application scenarios. A typical value for Vref is 0.1V; this value is merely an example and does not constitute a limitation of the invention.

[0020] The effective polarity coverage rate, in physical terms, refers to the number of dimensions in the six-dimensional event polarity vector where the voltage intensity is sufficient to drive subsequent gravitational calculations. A higher effective polarity coverage rate indicates more comprehensive effective semantic information carried by the input event.

[0021] Initial uncertainty calculation circuit: used to calculate the statistical variance of the six-dimensional differential voltage in real time.

[0022] The initial uncertainty calculation circuit includes: a differential amplifier, which calculates the mean of the six differential voltages; six squarers, which calculate the square of the difference between the voltage in each dimension and the mean; and an integrator, which accumulates the outputs of the six squarers and divides them by 6 to output an initial uncertainty voltage of 0 to 1V.

[0023] The differential amplifier can be implemented using a fully differential operational amplifier architecture to suppress common-mode noise and improve computational accuracy. The squarer can be implemented using an analog multiplier (such as a Gilbert unit multiplier), which multiplies the input voltage by itself and outputs a current or voltage signal proportional to the square of the input voltage. The integrator can be constructed by cascading a transconductance amplifier with an integrating capacitor, which accumulates the input current and outputs a voltage.

[0024] The initial uncertainty, in physical terms, refers to the degree of divergence between the dimensions of the six-dimensional differential voltage. A higher initial uncertainty indicates inconsistencies in the directions of the input events across different dimensions, making it more difficult for the system to determine the outcome; conversely, a lower initial uncertainty indicates consistency across the directions of the input events.

[0025] Causal chain activation state detection circuit: used to detect whether the voltage mode of the six-dimensional differential voltage matches the preset causal chain reference voltage mode.

[0026] The causal chain activation state detection circuit includes: a non-volatile memory that pre-stores reference voltage modes corresponding to multiple causal chains, wherein the causal chains include at least one of fault-recovery relationship, obstacle-avoidance relationship, demand-goal relationship, social-connection relationship, and conflict-resolution relationship; a simulated correlation matching array that performs correlation calculation between the six-dimensional differential voltage and each causal chain reference voltage mode; and a maximum value selection circuit that selects the causal chain with the highest correlation and outputs the corresponding causal chain activation voltage (0 to 1V, 0V indicates inactive).

[0027] The simulated correlation matching array can be composed of an array of simulated multipliers and a summing circuit. Each causal chain reference voltage mode occupies one row of the simulated multiplier array. The voltage of each dimension is multiplied by the corresponding reference voltage and then summed to output the correlation voltage of the causal chain.

[0028] Input quality index U-degree calculation circuit: used to calculate the analog voltage of the input quality index U-degree based on the effective polarity coverage voltage, the initial uncertainty voltage and the causal chain activation voltage.

[0029] The U-degree calculation circuit includes a weighted summation circuit, which calculates according to the following formula: U-degree = α × Coverage + β × (1 - Initial Uncertainty) + γ × Causal Chain Activation Where α, β, and γ are preset weighting coefficients, and α + β + γ = 1. These weighting coefficients are implemented using an on-chip programmable resistor array and can be preset and calibrated via an external configuration interface to adapt to the varying importance of different elements in different application scenarios. The U-degree voltage ranges from 0 to 1V; a higher U-degree indicates a more reliable input, while a lower U-degree indicates a less reliable input.

[0030] Gating comparison circuit: used to compare the U-degree voltage with the preset gate threshold voltage Vgate to generate a gate signal.

[0031] The gated comparison circuit includes a high-speed voltage comparator. Its first input receives the U-degree voltage, and its second input receives the preset gate threshold voltage. When the U-degree voltage is lower than Vgate, the voltage comparator outputs a first-level state, indicating interception; when the U-degree voltage is greater than or equal to Vgate, the voltage comparator outputs a second-level state, indicating permission. The gate threshold voltage Vgate can be preset and calibrated via an on-chip programmable resistor array or an external configuration interface to adapt to the security requirements of different application scenarios.

[0032] Uncertainty Exceedance Forced Interception Circuit: Used to force an interception state when the initial uncertainty voltage exceeds the preset maximum tolerance uncertainty threshold Vuncertain_max.

[0033] The uncertainty over-limit forced interception circuit includes an independent voltage comparator. Its first input receives the initial uncertainty voltage, and its second input receives the preset maximum tolerance uncertainty threshold voltage. When the initial uncertainty voltage exceeds Vuncertain_max, the voltage comparator outputs a forced interception signal. This signal directly controls the physical gating execution circuit through an OR logic gate, bypassing the output of the gating comparator circuit.

[0034] The maximum tolerance uncertainty threshold Vuncertain_max can be preset and calibrated via an on-chip programmable resistor array or an external configuration interface. This circuit configuration ensures that when an input event is highly contradictory, the system can physically intercept the input regardless of the U-degree weighted calculation result, preventing contradictory information from entering the main processing link.

[0035] Physical gating execution circuit: used to physically block the current input event from entering the main processing link through pure hardware circuit when the gating signal is in the interception state or the forced interception signal is in the valid state.

[0036] The physical gating execution circuit includes an analog switch array controlled by the gating signal and the forced interception signal. When the gating signal is interception or the forced interception signal is valid, the analog switch array performs at least one of the following operations: disconnects the electrical connection between the input event and the main processing link; forcibly pulls the input event signal line low or high to a preset invalid level; or triggers an external clarification signal output.

[0037] Output interface: Used to output the gating decision result. The information output by the output interface includes at least one of the following: gating signal status, U-degree voltage value, effective polarity coverage voltage value, initial uncertainty voltage value, and causal chain activation state.

[0038] Furthermore, all the core computing circuits of the chip are implemented by analog circuits, and the total response delay from the application of the input event voltage to the output of the gating signal does not exceed the inherent physical propagation delay of the analog circuit.

[0039] Furthermore, the chip also includes a low-power operating mode: when there is no external input event, the chip is in a sleep state; when an external input event is detected, the chip is woken up and automatically returns to the sleep state after completing input quality perception and gating decision.

[0040] An input quality sensing and hardware gating method based on the above-mentioned chip, characterized by comprising the following steps: Step S1: Convert the external input event into a six-dimensional differential analog voltage signal.

[0041] Step S2: Calculate the effective polarity coverage of the six-dimensional differential voltage and output the coverage voltage.

[0042] Step S3: Calculate the statistical variance of the six-dimensional differential voltage and output the initial uncertainty voltage.

[0043] Step S4: Detect whether the voltage mode of the six-dimensional differential voltage matches the preset causal chain reference voltage mode, and output the causal chain activation voltage.

[0044] Step S5: Calculate the analog voltage of the input quality index U degree based on the coverage voltage, the initial uncertainty voltage, and the causal chain activation voltage.

[0045] Step S6: Compare the U-degree voltage with a preset gate threshold voltage to generate a gate signal; at the same time, compare the initial uncertainty voltage with a preset maximum tolerance uncertainty threshold voltage to generate a forced interception signal.

[0046] Step S7: When the gating signal is in an intercept state or the forced intercept signal is in an effective state, the current input event is physically blocked from entering the main processing link; when the gating signal is in an allow state and the forced intercept signal is in an invalid state, the current input event is allowed to enter the main processing link.

[0047] Furthermore, step S7 also includes: when the gating signal is in an interception state or the forced interception signal is in a valid state, outputting a clarification request signal.

[0048] (III) Beneficial Effects Compared with the prior art, the present invention has the following beneficial effects: (1) Hardware-level perception and gating of input semantic quality is realized. This invention completes the real-time calculation of the "effective semantic coverage", "internal uncertainty" and "causal chain matching state" of input events at the hardware physical level by using an analog comparator array, differential amplifier, correlation matching circuit and weighted summation circuit, realizing the improvement from physical layer input verification to semantic layer input verification.

[0049] (2) Nanosecond-level response. All core calculations in this invention are performed by analog circuits, without any digital processor, without executing any software code, and without waiting for any clock cycles. From the application of the input event voltage to the output of the gate signal, the entire response delay is limited only by the physical propagation delay of the analog circuit, which is several orders of magnitude faster than software implementation.

[0050] (3) Physically unbypassable. The gating decision chain of this invention is entirely completed by analog circuits, without any modifiable software code, and there are no software interfaces that can be exploited by attackers.

[0051] (4) Ultra-low power consumption. The core calculations of this invention are performed through passive analog circuits, requiring no high-frequency clock drive or instruction decoding. Combined with the event-driven sleep-wake working mode, the average power consumption can be controlled at the microwatt level.

[0052] (5) Double-insurance safety mechanism. In addition to the U-degree gating, this invention independently sets up an uncertainty over-limit forced interception circuit. When the input event is extremely contradictory, the input is physically intercepted regardless of the weighted calculation result, ensuring that extremely contradictory information is not mistakenly allowed to pass.

[0053] (6) High versatility. This invention does not depend on a specific type of input data and can be applied to various input formats such as text, sensor signals, and control signals. Attached Figure Description

[0054] Figure 1 : Overall architecture diagram of the chip described in this invention.

[0055] Figure 2 : Schematic diagram of the internal structure of the effective polarity coverage calculation circuit.

[0056] Figure 3 : Schematic diagram of the internal structure of the initial uncertainty calculation circuit.

[0057] Figure 4 : Schematic diagram of the internal structure of the causal chain activation state detection circuit.

[0058] Figure 5 : Schematic diagram of the connection relationship between the U-degree calculation circuit and the gated comparison circuit.

[0059] Figure 6 Schematic diagram of the connection relationship of the forced interception circuit when uncertainty exceeds the limit. Detailed Implementation

[0060] It should be understood that the following embodiments are used to illustrate the technical solutions of the present invention and not to limit them. Those skilled in the art can implement the complete technical solutions of the present invention based on the teachings of this specification. The specific numerical values ​​(such as voltage values, resistance values, threshold values, etc.) involved in the following embodiments are merely illustrative and do not constitute a limitation of the present invention.

[0061] Principle Verification: The core control algorithm of the chip described in this invention—calculating the input quality index U-degree based on three factors: effective polarity coverage, initial uncertainty, and causal chain activation state, and then making gating decisions—has been fully verified in the applicant's prior research. This verification fully implements the same U-degree gating perception algorithm as this invention at the software level. Verification results show that: for clear inputs, the effective polarity coverage is 100%, the initial uncertainty is low, the causal chain is activated, the overall U-degree is ≥0.7, and the gating decision is "allow"; for untrusted inputs, the effective polarity coverage is 0%, the initial uncertainty is 0, the causal chain is not activated, the overall U-degree is ≈0, and the gating decision is "intercept"; for internally contradictory inputs, the initial uncertainty is extremely high, triggering forced interception.

[0062] Correspondence between core algorithms and chip circuits: Map event words to six-dimensional polar vectors Event polarity extraction and mapping circuit The polarity of each event word is superimposed Six-channel differential voltage analog adder Effective polarity coverage calculation Six-channel analog comparator array + analog adder + voltage divider network Initial uncertainty calculation Fully differential operational amplifier + Gilbert unit multiplier + transconductance amplifier - capacitor integrator Causal chain activation state detection Non-volatile memory + analog multiplier array + maximum value selection circuit U-degree calculation On-chip programmable resistor array + analog adder Gating threshold judgment High-speed voltage comparator Uncertainty exceeding the limit, forced interception Independent voltage comparator + OR logic gate Trigger clarification response Physical gating execution circuit (analog switch array) Example 1: Basic Structure of a Chip Construct a hardware gating chip based on input quality awareness. The chip integrates the following core components: The event polarity extraction and mapping circuit employs a six-channel differential voltage driver. Each dimension is equipped with a differential driver, generating a pair of differential voltages V⁺ and V⁻. The difference between the differential voltages, V⁺-V⁻, is proportional to the polarity value of that dimension. The polarity value ranges from [-1, 1], corresponding to a differential voltage range of [-100mV, 100mV] (this voltage range is merely an example and does not constitute a limitation of the invention). For text input, an external microprocessor writes the six-dimensional polarity digital values ​​into the chip's internal digital-to-analog converter via an on-chip interface. The digital-to-analog converter then converts the digital values ​​into six differential voltages.

[0063] The effective polarity coverage calculation circuit employs a six-channel analog comparator array. The non-inverting input of each comparator receives the absolute value of the differential voltage for the corresponding dimension (obtained through a precision full-wave rectifier circuit), while the inverting input receives a reference voltage Vref provided by an on-chip programmable resistor array. Vref can be preset and calibrated via an external configuration interface. When the absolute value of the differential voltage for that dimension is ≥ Vref, the comparator outputs a high level (indicating that the dimension is valid); otherwise, it outputs a low level (indicating that the dimension is invalid). The outputs of the six comparators are connected to an analog adder, which outputs a voltage from 0 to 6V (each valid channel contributes 1V). This voltage is divided by 6 through a voltage divider network to output a coverage voltage from 0 to 1V. When all six channels are valid, the coverage voltage is 1.0V; when four channels are valid, the coverage voltage is 0.667V; and when all channels are invalid, the coverage voltage is 0V.

[0064] The initial uncertainty calculation circuit uses a fully differential operational amplifier architecture to calculate the mean of the six differential voltages, thereby suppressing common-mode noise and improving calculation accuracy. Then, six Gilbert unit multipliers are used to calculate the square of the difference between each voltage dimension and the mean. Finally, an integrator consisting of a transconductance amplifier cascaded with an integrating capacitor accumulates the six squared values ​​and divides them by 6, outputting an initial uncertainty voltage ranging from 0 to 1V. When the six voltages are highly consistent, the initial uncertainty voltage approaches 0V; when the six voltages are highly divergent, the initial uncertainty voltage approaches 1V.

[0065] The core of the causal chain activation state detection circuit is a 64x6 analog correlation matching array. Multiple reference voltage patterns corresponding to causal chains are pre-stored in non-volatile memory. The analog correlation matching array consists of an array of analog multipliers and a summing circuit. It multiplies the six-dimensional differential voltage with each causal chain reference voltage pattern dimension by dimension and sums the results, outputting the correlation voltage of each causal chain. The maximum value selection circuit selects the causal chain with the highest correlation and outputs the corresponding causal chain activation voltage. When an input event matches a causal chain, the correlation voltage corresponding to that causal chain is the highest, and the causal chain activation voltage output is 1.0V; when no causal chain is matched, the causal chain activation voltage output is 0V.

[0066] The U-degree calculation circuit adopts a weighted summation circuit composed of an on-chip programmable resistor array and an analog adder. The coverage voltage is divided by the α resistor and then connected to the adder, the (1-initial uncertainty) voltage is divided by the β resistor and then connected to the adder, and the causal chain activation voltage is divided by the γ resistor and then connected to the adder. The weight values of α, β and γ can be preset and calibrated through an external configuration interface. The adder outputs a U-degree voltage with a range from 0 to 1V.

[0067] The gating comparison circuit adopts a high-speed voltage comparator. The U-degree voltage is connected to the non-inverting input terminal, and the gating threshold voltage Vgate (provided by the on-chip programmable resistor array) is connected to the inverting input terminal. When the U-degree is lower than Vgate, the comparator outputs a low level; when the U-degree is greater than or equal to Vgate, the comparator outputs a high level. Vgate can be preset and calibrated through an external configuration interface.

[0068] The uncertainty over-limit forced interception circuit adopts an independent voltage comparator. The initial uncertainty voltage is connected to the non-inverting input terminal, and the maximum tolerated uncertainty threshold voltage Vuncertain_max (provided by the on-chip programmable resistor array) is connected to the inverting input terminal. When the initial uncertainty voltage exceeds Vuncertain_max, the comparator outputs a high level (the forced interception signal is valid). The forced interception signal performs a logical OR operation with the output of the gating comparison circuit through an OR logic gate, and jointly controls the physical gating execution circuit. When the initial uncertainty voltage does not exceed Vuncertain_max, the comparator outputs a low level (the forced interception signal is invalid), and the gating decision is determined by the output of the gating comparison circuit.

[0069] The physical gating execution circuit is composed of a high-speed analog switch array. The gating signal and the forced interception signal jointly control the analog switch through an OR logic gate: when the gating signal is interception or the forced interception signal is valid, the analog switch disconnects the electrical connection between the input event and the main processing link, at the same time pulls the input event signal line down to an invalid level forcibly, and outputs a clarification request signal outward through an independent output pin; when the gating signal is pass and the forced interception signal is invalid, the analog switch is conducted, and the input event flows into the main processing link normally.

[0070] Example 2: Processing Flow of Clear Input This example takes the natural language input "Hello" as an example to demonstrate the complete working flow of the chip.

[0071] The external microprocessor extracts the event word "Hello", queries the polarity library, and obtains the six-dimensional polarity vector corresponding to "Hello". The digital-to-analog converter converts the six-dimensional polarity vector into six channels of differential voltage.

[0072] Effective polarity coverage calculation: Six comparators compare the absolute value of the differential voltage in each dimension with Vref. Since all differential voltages in each dimension meet the effective condition, the analog adder outputs 6V, and the voltage divider network outputs a coverage voltage of 1.0V.

[0073] Initial uncertainty calculation: The fully differential operational amplifier calculates the average of the six voltages, the Gilbert unit multiplier calculates the square of the deviation in each dimension, and the transconductance amplifier-capacitor integrator outputs the initial uncertainty voltage.

[0074] Causal chain activation status detection: The six-dimensional differential voltage mode is correlated with the pre-stored social-connection causal chain reference voltage mode. The highest correlation is found, and the causal chain activation voltage output is 1.0V.

[0075] U-degree calculation: U-degree = 0.5×1.0 + 0.3×(1-initial uncertainty) + 0.2×1.0.

[0076] Gating Comparison: When the voltage U is higher than the gate threshold voltage Vgate, the comparator outputs a high level (allows passage).

[0077] Uncertainty Exceeding Limit Forced Interception: When the initial uncertainty voltage is lower than Vuncertain_max, the comparator output is forced to go low (invalid).

[0078] Physical gating execution: OR logic gate output is allowed, analog switch is turned on, and input events flow normally into the main processing link.

[0079] Example 3: Processing flow for untrusted input This embodiment uses garbled input as an example to demonstrate the chip's interception process.

[0080] An external microprocessor extracts event words and queries the polarity library. No words are mapped to the situation code, resulting in a six-dimensional polarity vector of [0, 0, 0, 0, 0, 0]. A digital-to-analog converter then converts this six-dimensional polarity vector into six differential voltages: all 0V.

[0081] Effective polarity coverage calculation: All six comparators output low level, the analog adder outputs 0V, and the voltage divider network outputs coverage voltage = 0V.

[0082] Initial uncertainty calculation: All six voltages are 0V, and the integrator outputs an initial uncertainty voltage of 0V.

[0083] Causal chain activation status detection: The six-dimensional differential voltage mode does not match any causal chain reference voltage mode, and the causal chain activation voltage output is 0V.

[0084] U-degree calculation: U-degree = 0.5×0 + 0.3×(1-0) + 0.2×0 = 0.3V.

[0085] Gated Comparison: When the voltage U is 0.3V lower than the gate threshold voltage Vgate, the comparator outputs a low level (intercept).

[0086] Uncertainty Exceeding Limit Forced Interception: When the initial uncertainty voltage (0V) is lower than Vuncertain_max, the comparator output is forced to go low (invalid).

[0087] Physical gating execution: The logic gate output intercepts, the analog switch disconnects the electrical connection between the input event and the main processing link, and at the same time forces the input event signal line low to 0V, and outputs a clarification request signal to the outside through an independent output pin.

[0088] The main processing link is not woken up and does not consume any computing power or power.

[0089] Example 4: Forced Interception of Internal Conflict Input This embodiment uses an extremely contradictory internal input as an example to demonstrate the workflow of the uncertainty-exceeding forced interception circuit.

[0090] An external microprocessor extracts event words, resulting in a six-dimensional polar vector with varying degrees of divergence across its dimensions. A digital-to-analog converter then converts this six-dimensional polar vector into six differential voltages.

[0091] Effective polarity coverage calculation: All six comparators output high level, coverage voltage = 1.0V.

[0092] Initial uncertainty calculation: The six voltage channels are highly divergent, and the integrator outputs an initial uncertainty voltage of 0.9V (exceeding Vuncertain_max).

[0093] Causal chain activation status detection: The six-dimensional differential voltage mode does not match any causal chain reference voltage mode, and the causal chain activation voltage output is 0V.

[0094] U-degree calculation: U-degree = 0.5×1.0+0.3×(1-0.9)+0.2×0=0.5+0.03+0 = 0.53V.

[0095] Gating comparison: When the voltage U is 0.53V higher than the gate threshold voltage Vgate, the comparator outputs a high level (allows passage).

[0096] Uncertainty Exceeding Limit Forced Interception: When the initial uncertainty voltage of 0.9V exceeds Vuncertain_max, the comparator output is forced to go high (valid).

[0097] Physical gating execution: OR logic gate output interception (forced interception signal valid, overriding the gate comparator's release output), analog switch disconnects the electrical connection between the input event and the main processing link, and simultaneously outputs a clarification request signal.

[0098] This embodiment demonstrates the core value of the dual insurance mechanism of the present invention: even if the weighted calculation result of U degree is "allow", the extreme over-limit of the initial uncertainty can still independently trigger physical interception, ensuring that extremely contradictory inputs will not be mistakenly allowed.

[0099] Example 5: Prioritizing the release of safety-critical inputs This embodiment uses the input "red light" as an example to demonstrate the chip's processing flow under safety-critical inputs.

[0100] An external microprocessor extracts the event term "red light," queries a polarity library, and obtains the six-dimensional polarity vector corresponding to "red light." A digital-to-analog converter then converts this six-dimensional polarity vector into six differential voltages.

[0101] Effective polarity coverage calculation: All six comparators output high level, coverage voltage = 1.0V.

[0102] Initial uncertainty calculation: The integrator outputs the initial uncertainty voltage.

[0103] Causal chain activation state detection: The six-dimensional differential voltage mode is highly matched with the pre-stored obstacle-avoidance causal chain reference voltage mode, with the highest correlation voltage and a causal chain activation voltage output of 1.0V.

[0104] U-degree calculation: U-degree = 0.5 × 1.0 + 0.3 × (1 - initial uncertainty) + 0.2 × 1.0.

[0105] Gating comparison: When the voltage U is higher than the gate threshold voltage, the comparator outputs a high level (allows passage).

[0106] Uncertainty Exceeding Limit Forced Interception: When the initial uncertainty voltage is lower than Vuncertain_max, the comparator output is forced to go low (invalid).

[0107] Physical gating execution: The logic gate output is released, the analog switch is turned on, the input event flows normally into the main processing link, and the causal chain activation status is marked as "obstacle-avoidance", so the main processing link can respond with priority.

[0108] Example 6: Deployment of Chips in Robotic Scenarios The robot's onboard vision sensors continuously acquire environmental images. Under normal operating conditions, the images are clear, the six-dimensional polar vector output by the feature extraction module is effective in all dimensions, the coverage voltage is high, the initial uncertainty voltage is low, the U-degree is higher than the gate threshold, and the initial uncertainty is lower than Vuncertain_max. The gate signal is "allow," and the image data flows normally into the main processing chip for processing.

[0109] When the camera lens is obstructed by a foreign object, the six-dimensional polar vector output by the feature extraction module approaches 0 in each dimension, the coverage voltage approaches 0V, the initial uncertainty voltage approaches 0V, the causal chain activation voltage is 0V, the U-degree is below the gating threshold, and the gating signal is "intercept". The analog switch disconnects the image data from the main processing chip, the main processing chip is not woken up, and the chip outputs a clarification signal.

[0110] Example 7: Deployment of Chips in Autonomous Driving Scenarios The autonomous driving domain controller simultaneously receives data from cameras, LiDAR, and millimeter-wave radar. Under normal operating conditions, the data from all sensors are consistent, the U-degree is higher than the gating threshold, the initial uncertainty is lower than Vuncertain_max, and the gating signal is "allow".

[0111] When the data from a certain sensor is disturbed, its output six-dimensional polarity vector severely conflicts with that of other sensors. The chip's effective polarity coverage calculation circuit detects the inconsistency in polarity patterns, and the initial uncertainty voltage increases.

[0112] If the initial uncertainty voltage exceeds Vuncertain_max, the uncertainty over-limit forced interception circuit is immediately triggered, directly outputting the interception result independent of the U-degree calculation result. An analog switch disconnects the interference-affected sensor data from the fusion decision module, and simultaneously outputs a warning signal. Based on this, the decision system determines that the sensor data is unreliable and relies solely on other reliable sensors for decision-making.

[0113] If the initial uncertainty voltage does not exceed Vuncertain_max but U is below the gating threshold, the gating comparator circuit output is blocked. The two blocking mechanisms complement each other, ensuring that any abnormal input is physically blocked.

Claims

1. A hardware gating chip based on input quality perception, characterized in that, include: An event polarity extraction and mapping circuit is used to convert external input events into six-dimensional differential analog voltage signals; An effective polarity coverage calculation circuit is used to calculate the coverage of the effective polarity in the six-dimensional differential voltage in real time and output the coverage voltage. An initial uncertainty calculation circuit is used to calculate the statistical variance of the six-dimensional differential voltage in real time and output the initial uncertainty voltage. The causal chain activation state detection circuit is used to detect whether the voltage mode of the six-dimensional differential voltage matches the preset causal chain reference voltage mode, and outputs the causal chain activation voltage. The input quality index U-degree calculation circuit is used to calculate the analog voltage of the input quality index U-degree based on the coverage voltage, the initial uncertainty voltage and the causal chain activation voltage; A gated comparison circuit is used to compare the U-degree voltage with a preset gated threshold voltage to generate a gated signal; Uncertainty Exceedance Forced Interception Circuit is used to generate a forced interception signal when the initial uncertainty voltage exceeds the preset maximum tolerance uncertainty threshold voltage; A physical gating execution circuit is used to physically block the current input event from entering the main processing link through pure hardware circuitry when the gating signal is in an intercepted state or the forced interception signal is in an effective state; the gating signal and the forced interception signal jointly control the physical gating execution circuit through a logical OR operation.

2. The chip according to claim 1, characterized in that, The event polarity extraction and mapping circuit includes a digital-to-analog converter, which converts the six-dimensional polarity digital value provided by the external microprocessor into six differential analog voltages; the six dimensions of the six-dimensional polarity vector correspond to the first to the sixth dimensions respectively, and the polarity value of each dimension ranges from [-1, 1].

3. The chip according to claim 1, characterized in that, The effective polarity coverage calculation circuit includes: six analog comparators, each of which receives the absolute value of the differential voltage of the corresponding dimension at its first input terminal and a preset reference voltage at its second input terminal, and outputs a high level when the absolute value of the differential voltage of the dimension is greater than or equal to the reference voltage; an analog adder that accumulates the outputs of the six comparators; and a voltage divider network that divides the accumulated result by 6 and outputs a coverage voltage of 0 to 1V.

4. The chip according to claim 1, characterized in that, The initial uncertainty calculation circuit includes: a differential amplifier, which calculates the mean of the six differential voltages; six squarers, which calculate the square of the difference between the voltage in each dimension and the mean; and an integrator, which accumulates the outputs of the six squarers and divides them by 6 to output an initial uncertainty voltage of 0 to 1V.

5. The chip according to claim 1, characterized in that, The causal chain activation state detection circuit includes: a non-volatile memory that pre-stores reference voltage modes corresponding to multiple causal chains, wherein the causal chain includes at least one of fault-recovery relationship, obstacle-avoidance relationship, demand-goal relationship, social-connection relationship, and conflict-resolution relationship; a simulated correlation matching array that performs correlation calculation between the six-dimensional differential voltage and each causal chain reference voltage mode; and a maximum value selection circuit that selects the causal chain with the highest correlation and outputs the corresponding causal chain activation voltage.

6. The chip according to claim 1, characterized in that, The U-degree calculation circuit includes a weighted summation circuit, which calculates the U-degree voltage according to the following formula: U-degree = α × coverage rate + β × (1 - initial uncertainty) + γ × causal chain activation, where α, β, and γ are preset weighting coefficients, and α + β + γ = 1.

7. The chip according to claim 1, characterized in that, The gated comparison circuit includes a high-speed voltage comparator, whose first input terminal receives the U-degree voltage and its second input terminal receives a preset gated threshold voltage; when the U-degree voltage is lower than the gated threshold voltage, the voltage comparator outputs an interception state; when the U-degree voltage is greater than or equal to the gated threshold voltage, the voltage comparator outputs a release state.

8. The chip according to claim 1, characterized in that, The uncertainty over-limit forced interception circuit includes a voltage comparator, whose first input terminal receives the initial uncertainty voltage and its second input terminal receives the preset maximum tolerance uncertainty threshold voltage; when the initial uncertainty voltage exceeds the maximum tolerance uncertainty threshold voltage, the voltage comparator outputs a valid forced interception signal.

9. The chip according to claim 1, characterized in that, The chip's parameter configuration interface is used to preset and calibrate the preset reference voltage, gate threshold voltage, maximum tolerance uncertainty threshold voltage, and weighting coefficients; all core computing circuits of the chip are implemented by analog circuits, and the total response delay from the application of the input event voltage to the output of the gate signal does not exceed the inherent physical propagation delay of the analog circuit.

10. An input quality sensing and hardware gating method based on the chip according to any one of claims 1 to 9, characterized in that, Includes the following steps: Step S1: Convert the external input event into a six-dimensional differential analog voltage signal; Step S2: Calculate the effective polarity coverage of the six-dimensional differential voltage and output the coverage voltage; Step S3: Calculate the statistical variance of the six-dimensional differential voltage and output the initial uncertainty voltage; Step S4: Detect whether the voltage mode of the six-dimensional differential voltage matches the preset causal chain reference voltage mode, and output the causal chain activation voltage; Step S5: Calculate the analog voltage of the input quality index U degree based on the coverage voltage, the initial uncertainty voltage, and the causal chain activation voltage; Step S6: Compare the U-degree voltage with a preset gate threshold voltage to generate a gate signal; at the same time, compare the initial uncertainty voltage with a preset maximum tolerance uncertainty threshold voltage to generate a forced interception signal; Step S7: When the gating signal is in an intercept state or the forced intercept signal is in an effective state, the current input event is physically blocked from entering the main processing link; when the gating signal is in an allow state and the forced intercept signal is in an invalid state, the current input event is allowed to enter the main processing link.

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