Preparation method and device of asymmetric w state in quantum system, and electronic equipment

Abstract

This application proposes a method, apparatus, and electronic device for preparing asymmetric W-states in a quantum system. The preparation method includes: (1) constructing a graph structure based on the topology of a quantum computing chip; (2) applying a first quantum operation to the qubits corresponding to the nodes with larger node values ​​in the first edge; (3) applying a second parametric quantum operation to the qubits corresponding to the two nodes in the first edge; (4) determining a second edge from the adjacent edges of the first edge; (5) applying the second parametric quantum operation to the qubits corresponding to the two nodes in the second edge respectively; (6) repeating steps (4) and (5) with the first edge and the second edge as the current first edge until the generated parametric asymmetric W-state reaches a preset scale; (7) generating a quantum circuit based on the quantum operation; and (8) measuring the qubits corresponding to the quantum circuit and iteratively optimizing the quantum circuit. According to the embodiment, asymmetric W-states suitable for large-scale preparation are prepared, and the accuracy is improved.

Description

Technical Field

[0001] This application relates to the field of quantum circuit technology, and more specifically, to a method and apparatus for preparing asymmetric W states in a quantum system, an electronic device, and a non-transient computer-readable storage medium. Background Technology

[0002] In quantum information science, the W-state is a special type of multi-particle entangled state. Its characteristic is that when any one particle decoheres, the remaining particles still maintain maximum entanglement. It is widely used in scenarios such as quantum teleportation, quantum key distribution, quantum secure direct communication, and quantum secret sharing, and is a key basic unit for constructing quantum relay networks and realizing quantum interconnection. The asymmetric W-state is a more general form of the W-state, with coefficients that can be unequal. This asymmetry brings additional degrees of freedom and flexibility, opening up applications not available with standard symmetric W-states. For example, in many quantum communication protocols, different users or paths may have different loss or noise levels. Using asymmetric W-states, this asymmetric loss can be compensated by adjusting the coefficients, thereby maximizing the overall fidelity or success rate of the task. In quantum metrology, asymmetric W-states can be used to optimize specific asymmetric noise models to obtain the best measurement accuracy. In the field of quantum machine learning, the coefficients of asymmetric W-states can be used as parameters to encode classical data, helping to more effectively discover complex patterns in data within quantum machine learning models. Asymmetric W-states can also serve as the initial or intermediate state for specific layers in quantum neural networks. Optimizing its asymmetric entangled structure to perform specific classification or regression tasks; furthermore, similar to the attention mechanism in the classic Transformer model, the amplitude of the asymmetric W state can be naturally represented as an "attention weight," thus being applied to the quantum version of the Transformer model, providing a new paradigm for designing quantum natural language processing or sequence models; in the financial field, the asymmetric W state can be used to prepare a quantum state whose probability distribution is correlated with the desired investment return distribution, and through algorithms such as quantum amplitude estimation, the portfolio that maximizes returns at a given risk level can be found more quickly.

[0003] Current quantum computing is still in a noisy, medium-scale stage, meaning the number of qubits is "medium," insufficient for fault tolerance, and physical qubits contain significant noise. Furthermore, limited by decoherence time, only shallow quantum circuits can operate. Therefore, existing methods for preparing asymmetric W-states are typically based on fault-tolerant quantum computing systems, easily affected by the qubit connectivity, quantum gate noise, and environmental noise of current quantum computing chips. These methods also result in numerous quantum circuit layers, leading to poor accuracy of the generated asymmetric W-states and making them unsuitable for large-scale fabrication tasks. Summary of the Invention

[0004] This application aims to provide a method and apparatus for preparing asymmetric W states in a quantum system, an electronic device, and a non-transient computer-readable storage medium, in order to solve the problem of low precision in the preparation of asymmetric W states in the prior art.

[0005] According to one aspect of this application, a method for preparing an asymmetric W state in a quantum system is proposed, comprising: (1) Based on the topology of the quantum computing chip in the quantum system, construct a graph structure corresponding to the quantum computing chip, wherein the graph structure includes multiple nodes and an edge connecting any two nodes among the multiple nodes, and the edge includes a first edge and a second edge; (2) Apply the first quantum operation to the qubit corresponding to the node with the larger node value in the first edge; (3) Apply a second parametric quantum operation to the qubits corresponding to the two nodes in the first side to generate a parametric asymmetric W state corresponding to the first side; (4) Determine the second side from the adjacent sides of the first side; (5) Apply the second parametric quantum operation to the qubits corresponding to the two nodes in the second side to generate the parametric asymmetric W state corresponding to the second side; (6) Using the first edge and the second edge as the current first edge, repeat steps (4) and (5) until the generated parameterized asymmetric W state reaches the scale required by the preset asymmetric W state; (7) Generate the corresponding quantum circuit according to the execution order of the first quantum operation and the second parameterized quantum operation; (8) Measure the qubits corresponding to the quantum circuit, and use the measurement results to iteratively optimize the variational parameters in the quantum circuit using a preset loss function.

[0006] According to some embodiments, based on the topology of the quantum computing chip in the quantum system, a graph structure corresponding to the quantum computing chip is constructed, including: The nodes of the graph structure represent the qubits of the quantum computing chip, the node value of the node represents the single-bit gate fidelity of the qubit, the edges of the graph structure represent the relationships between the qubits of the quantum computing chip, and the two-bit gate fidelity between qubits is used as the weight value of the corresponding edge.

[0007] According to some embodiments, the first edge includes a first node, and determining the second edge from the adjacent edges of the first edge includes: A node connected to the first node but not in the first edge is designated as a second node. The edge between the first node and the second node is defined as the second edge, and each first node and each second node can form at most one second edge.

[0008] According to some embodiments, a node connected to the first node but not in the first edge is designated as a second node, and the edge between the first node and the second node is defined as the second edge. Furthermore, each first node and each second node can form at most one second edge, including: The edges between the first node and the second node are sorted according to their weight values, and the second edge is determined one by one in descending order.

[0009] According to some embodiments, a first quantum operation is applied to the qubit corresponding to the node with the larger node value in the first edge, including: Construct a weight set using the weight values ​​corresponding to all edges of the graph structure; The edge corresponding to the largest weight value is selected as the first edge based on the weight values ​​of the weight set; A first quantum operation is applied to the qubit corresponding to the node with the larger node value in the first edge.

[0010] According to some embodiments, the first quantum operation includes an X gate.

[0011] According to some embodiments, the second parametric quantum operation includes a variable quantum circuit module, which is represented by the following formula:

[0012] Among them, CNOT, For universal quantum gates, This is a controlled NOT gate where qubit 1 is the control bit and qubit 2 is the controlled bit. A control NOT gate where qubit 2 is the control bit and qubit 1 is the controlled bit. A parametric rotation about the y-axis acting on qubit 1 The revolving door To select a parametric rotation about the y-axis for operation on qubit 1 A revolving door.

[0013] According to some embodiments, the loss function value is calculated using the following formula:

[0014] in, Let B be the loss function value, and B be a single excited state of the target asymmetric W state. The set that is formed For the target asymmetric W state, the corresponding single excited state Amplitude on The quantum state in the measurement result collapses into a single excited state. The probability of it, The probability of a quantum state collapsing into a non-single excited state in the measurement result.

[0015] According to one aspect of this application, a device for preparing an asymmetric W state in a quantum system is proposed, comprising: The graph structure construction unit is used to construct a graph structure corresponding to the quantum computing chip according to the topology of the quantum computing chip in the quantum system. The graph structure includes multiple nodes and an edge connecting any two nodes among the multiple nodes. The edge includes a first edge and a second edge. The first quantum operation unit is used to apply a first quantum operation to the qubit corresponding to the node with the larger node value in the first edge; The first unit of the second parametric quantum operation is used to apply the second parametric quantum operation to the qubits corresponding to the two nodes in the first edge to generate the parametric asymmetric W state corresponding to the first edge. The second side determination unit is used to determine the second side from the adjacent sides of the first side; The second parameterized quantum operation second unit is used to apply the second parameterized quantum operation to the qubits corresponding to the two nodes in the second side respectively, so as to generate a parameterized asymmetric W state corresponding to the second side; A quantum circuit generation unit is used to generate a corresponding quantum circuit according to the execution order of the first quantum operation and the second parameterized quantum operation; An iterative optimization unit is used to measure the qubits corresponding to the quantum circuit, and to iteratively optimize the variational parameters in the quantum circuit using a preset loss function based on the measurement results; The second edge determination unit uses the first edge and the second edge as the current first edge, and repeats the operation with the second parametric quantum operation second unit until the generated parametric asymmetric W state reaches the scale required by the preset asymmetric W state.

[0016] According to one aspect of this application, an electronic device is provided, comprising: a processor; and a memory storing a computer program that, when executed by the processor, causes the processor to perform the preparation method as described in any of the preceding embodiments.

[0017] According to one aspect of this application, a non-transitory computer-readable storage medium is provided, on which computer-readable instructions are stored, which, when executed by a processor, cause the processor to perform the preparation method as described in any of the preceding embodiments.

[0018] According to an embodiment of this application, ...

[0019] It should be understood that the above general description and the following detailed description are merely exemplary and do not limit this application. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. The above and other objectives, features, and advantages of this application will become more apparent by referring to the accompanying drawings and describing exemplary embodiments in detail.

[0021] Figure 1 A flowchart illustrating a method for preparing an asymmetric W state in a quantum system according to an example embodiment of this application is shown.

[0022] Figure 2 A flowchart illustrating a method for preparing an asymmetric W state in another quantum system according to this application is shown.

[0023] Figure 3 A schematic diagram of the topology of a quantum computing chip according to an embodiment of this application is shown.

[0024] Figure 4 A schematic diagram of a variable quantum circuit for preparing an asymmetric W-state according to an embodiment of this application is shown.

[0025] Figure 5 A quantum circuit schematic diagram of a submodule of a variable quantum circuit according to an embodiment of this application is shown.

[0026] Figure 6 A block diagram of an apparatus for preparing an asymmetric W state in a quantum system according to an example embodiment of this application is shown.

[0027] Figure 7 An electronic device is shown according to an exemplary embodiment of this application. Detailed Implementation

[0028] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this application will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same drawings in the figures show the same or similar parts, and therefore repeated descriptions of them will be omitted.

[0029] The described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a full understanding of embodiments of this disclosure. However, those skilled in the art will recognize that the technical solutions of this disclosure can be practiced without one or more of these specific details, or other methods, components, materials, apparatus, or operations may be employed. In these cases, well-known structures, methods, apparatuses, implementations, materials, or operations will not be shown or described in detail.

[0030] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0031] The terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.

[0032] The asymmetric W-state is a special type of entangled state in a multi-qubit system. It is a single-excitation entangled state, meaning that only one qubit is in the W-state. The remaining qubits are in The basis vector combination. The expression for an asymmetric W state containing n qubits is shown in Equation (1).

[0033] (1) Among them, the i-th qubit is in an excited state. The remaining qubits are in the ground state. single excited state It is stated that the above Form set B, , Different single excited states correspond to asymmetric W states The amplitude of the wave.

[0034] As mentioned earlier, the mainstream method for preparing asymmetric W states is based on universal quantum gates in fault-tolerant quantum computing systems. However, current quantum computing is still at a noisy, medium-scale stage, meaning the number of qubits is "medium," which is insufficient to achieve fault tolerance, and the physical qubits contain noise that cannot be ignored. Moreover, due to the limitation of decoherence time, only shallow quantum circuits can be operated.

[0035] Therefore, existing methods for preparing asymmetric W states are easily affected by the bit connectivity, quantum gate noise, and environmental noise of current quantum computing chips. They also have a large number of quantum circuit layers, resulting in poor accuracy of the generated asymmetric W states, and are not suitable for large-scale preparation tasks.

[0036] The graph-based asymmetric W-state fabrication method proposed in the embodiments of this application can generate matching asymmetric W-state fabrication quantum circuits for different quantum computing chip structures. These quantum circuits only require... With a line layer count on the order of magnitude, it has the advantage of scalability.

[0037] Furthermore, the quantum circuit for generating the target asymmetric W state is based on a variable quantum circuit submodule. The optimal parameters of the quantum circuit are obtained through parameter optimization methods, which can effectively resist quantum gate noise and environmental noise and improve the accuracy of preparing the target quantum state.

[0038] The specific embodiments according to this application will now be described in detail with reference to the accompanying drawings.

[0039] Figure 1 A flowchart illustrating a method for preparing an asymmetric W state in a quantum system according to an example embodiment of this application is shown, as follows: Figure 1 The preparation method shown includes steps S101, S103, and S105. The following will use... Figure 1 Taking an example, a peak detection method for a spectrum signal according to an example embodiment of this application will be described in detail.

[0040] like Figure 1 As shown, in step S101, a graph structure corresponding to the quantum computing chip is constructed according to the topology of the quantum computing chip in the quantum system. The graph structure includes multiple nodes and an edge connecting any two nodes among the multiple nodes. The edge includes a first edge and a second edge.

[0041] According to an embodiment of this application, when constructing the graph structure, the nodes of the graph structure represent the qubits of the quantum computing chip, the node value of the node represents the single-bit gate fidelity of the qubit, the edges of the graph structure represent the relationship between the qubits of the quantum computing chip, and the two-bit gate fidelity between the qubits is used as the weight value of the corresponding edge.

[0042] In step S103, a first quantum operation is applied to the qubit corresponding to the node with the larger node value in the first edge.

[0043] According to an embodiment of this application, step S103 includes steps S1031 to S1037, wherein: In step S1031, a weight set is constructed using the weight values ​​corresponding to all edges of the graph structure; In step S1033, the edge corresponding to the largest weight value is selected as the first edge according to the weight values ​​of the weight set.

[0044] In step S1035, a first quantum operation is applied to the qubit corresponding to the node with the larger node value in the first edge.

[0045] In a specific embodiment, the first quantum operation includes an X gate.

[0046] In step S105, a second parametric quantum operation is applied to the qubits corresponding to the two nodes in the first edge to generate a parametric asymmetric W state corresponding to the first edge.

[0047] According to an embodiment of this application, the second parametric quantum operation includes a variable quantum circuit module, which is implemented as shown in formula (2).

[0048] (2) Among them, CNOT, For universal quantum gates, This is a controlled NOT gate where qubit 1 is the control bit and qubit 2 is the controlled bit. A control NOT gate where qubit 2 is the control bit and qubit 1 is the controlled bit. A parametric rotation about the y-axis acting on qubit 1 The revolving door To select a parametric rotation about the y-axis for operation on qubit 1 A revolving door.

[0049] In step S107, the second side is determined from the adjacent sides of the first side.

[0050] According to an embodiment of this application, the first edge includes a first node. In step S107, a node connected to the first node but not in the first edge is used as a second node, and the edge between the first node and the second node is determined as the second edge. Each first node and each second node can form at most one second edge.

[0051] In order to select high-fidelity operations while maximizing the entanglement of qubits, and to ensure the use of a shallow number of quantum circuit layers, when nodes that have undergone the second parametric quantum operation share an edge with the same node that has not undergone the second parametric quantum operation, in order to ensure that the second parametric quantum operation is applied to each edge at most once, in some embodiments, the edges between the first node and the second node are sorted according to the edge weight value, and the second edge is determined one by one in descending order.

[0052] In step S109, the second parametric quantum operation is applied to the qubits corresponding to the two nodes in the second side to generate the parametric asymmetric W state corresponding to the second side.

[0053] According to an embodiment of this application, in step S109, a second parametric quantum operation as shown in formula (2) is applied to the qubits corresponding to the two nodes in the second side.

[0054] In step S111, steps S107 to S109 are repeated, using the first edge and the second edge as the current first edge, until the generated parameterized asymmetric W state reaches the scale required by the preset asymmetric W state.

[0055] According to an embodiment of this application, when executing the next iteration in step S111, the first edge and the second edge are taken as the current first edge, and the current second edge is determined by executing step S107. Then, in step S109, the second parametric quantum operation is applied to the qubits corresponding to the two nodes of the current second edge. Steps S107 to S109 are repeated multiple times until the generated parametric asymmetric W state reaches the scale required by the preset asymmetric W state.

[0056] In step S113, a corresponding quantum circuit is generated according to the execution order of the first quantum operation and the second parameterized quantum operation.

[0057] It should be noted that this application does not specify the method of generating quantum circuits. Any method that can generate the corresponding quantum circuits according to the order of quantum operations is applicable to this application.

[0058] In step S115, the qubits corresponding to the quantum circuit are measured, and the variational parameters in the quantum circuit are iteratively optimized using a preset loss function based on the measurement results.

[0059] In some embodiments, when iteratively optimizing the variational parameters in the quantum circuit using a preset loss function, the optimization is stopped when the loss function value calculated based on the measurement result is less than a preset threshold by measuring the qubits of the quantum computing chip. By optimizing the quantum circuit, optimized quantum parameters can be obtained, allowing the target asymmetric W state to be reconstructed using the optimized quantum circuit without retraining its parameters.

[0060] According to an embodiment of this application, the loss function value is as shown in formula (3).

[0061] (3) in, The loss function value is given, where B is a single excited state of the asymmetric W state. The set that is formed The asymmetric W state corresponds to a single excited state. Amplitude on The quantum state in the measurement result collapses into a single excited state. The probability of it, The probability of a quantum state collapsing into a non-single excited state in the measurement result.

[0062] It should be noted that this application does not limit the size of the threshold; in specific embodiments, the value of the threshold can be set according to the accuracy requirements. Figure 1 The embodiment shown demonstrates the preparation of asymmetric W-states suitable for large-scale operations by constructing a corresponding graph structure using the topology of a quantum computing chip and applying quantum operations based on the constructed graph structure.

[0063] According to other embodiments, by constructing shallow quantum circuits with logarithmic layers, a variable quantum circuit more suitable for current noisy quantum hardware is obtained, and through continuous iterative learning, a more precise asymmetric W state is prepared.

[0064] After a detailed description of the preparation method of this application, the following will be used as a reference. Figure 2 For example, using existing quantum computing chips, a method for preparing an asymmetric W state in a quantum system according to an example embodiment of this application will be illustrated.

[0065] The topology of a quantum computing chip is as follows: Figure 3 As shown, it contains a total of 72 qubits. Except for the qubits at the edge of the chip, each of the other qubits has 4 directly connected qubits.

[0066] In step S301, the graph structure corresponding to the quantum computing chip is constructed.

[0067] according to Figure 3 Based on the topology and related parameters shown, a graph G containing information such as the single-bit gate fidelity and two-bit gate fidelity of the quantum computing chip is generated.

[0068] For example, the qubits of a quantum computing chip can be represented as nodes in a graph G, the single-bit gate fidelity of a qubit can be represented as the node value, the connection between qubits in a quantum computing chip can be represented as edges in a graph G, and the two-bit gate fidelity between qubits can be represented as the edge weight.

[0069] In step S303, an edge of the graph structure is selected and a quantum operation is applied.

[0070] For example, first, an X gate is applied to the qubit corresponding to one of the two nodes of the edge; then, a variable quantum circuit module M is applied to the qubit corresponding to the two nodes to generate a two-bit W state.

[0071] The two-bit W state generated at this time may be a symmetric two-bit W state or an asymmetric two-bit W state.

[0072] Specifically, such as Figure 3 As shown, we can select the edge with the largest edge weight in graph G, namely the edge composed of nodes 32 and 38, and take nodes 32 and 38 as the first node. By comparing the fidelity of the single-qubit quantum gates of nodes 32 and 38, the qubit corresponding to node 32 is better. Therefore, we choose to apply an X-gate to the qubit corresponding to node 32, and then apply quantum operations to the qubits corresponding to nodes 32 and 38. The variable quantum circuit module corresponding to the quantum operation is as follows: Figure 4 As shown, the quantum gates applied to the qubits corresponding to nodes 32 and 38 are denoted as follows: This generates a two-bit W state.

[0073] In step S305, a quantum operation is applied to the other edges connected to all qubits to which a quantum operation has been applied.

[0074] In order to select high-fidelity operations while maximizing the entanglement of qubits, and to ensure the use of a shallow number of quantum circuit layers, a quantum operation is applied to each edge, and it is guaranteed that at most one quantum operation is applied to each edge.

[0075] To achieve this objective, according to an embodiment of this application, the other nodes in graph G connected to the first node (currently nodes 32 and 38), namely nodes 26, 27, 39, 31, 43, and 44, are designated as second nodes. Node 32 is connected to nodes 26, 27, and 39, and node 38 is connected to nodes 31, 43, and 44. Then, the edges formed by the first and second nodes are sorted in descending order of edge weight into sequence E, namely edge 38-44, edge 38-43, edge 38-31, edge 32-27, edge 32-39, and edge 32-26. Secondly, following the order of edge weights from largest to smallest, quantum operations are performed on the qubits corresponding to the two nodes of the current edge. First, the qubits corresponding to edge 38-44 are selected for quantum operations. Since node 38 has already undergone a quantum operation in this layer of the quantum circuit, edges 38-43 and 38-31 are skipped. Then, edge 32-27 is selected for quantum operations. Again, since node 32 has already undergone a quantum operation, edges 32-39 and 32-26 are skipped, thus completing the traversal of all edges in sequence E. The quantum operations are as follows: Figure 4 The quantum gate shown and .

[0076] Furthermore, to ensure the fidelity of the quantum state, before applying a quantum operation, it is determined whether the weight value of the current edge exceeds the threshold K. If it does, the operation continues; otherwise, it is skipped.

[0077] In step S307, step S305 is repeated until the generated parametric asymmetric W state reaches the scale required by the preset asymmetric W state.

[0078] If a 4-bit asymmetric W-state needs to be prepared, the preparation process can now be completed. If a more-bit asymmetric W-state needs to be prepared, operation S305 needs to be executed.

[0079] For example, to prepare an 8-qubit asymmetric W-state, we take the nodes to which quantum operations have been previously performed as the current first node, i.e., nodes 32, 38, 44, and 27. Following the previous principle, we obtain the edges to which quantum operations are performed this time, i.e., edges 27-21, 44-50, 32-39, and 38-43. Their corresponding quantum gates are denoted as... , , and This continues until the target asymmetric W-state is prepared on a scale that is achieved.

[0080] It is important to note that when the number of qubits subjected to quantum operations has reached the scale of the target asymmetric W state, subsequent addition of quantum operations should be stopped in time to determine the final variable quantum circuit module M.

[0081] In step S309, a quantum circuit is generated according to the sequence of quantum operations applied in the above steps.

[0082] Specifically, based on the quantum gate sequence applied in the previous steps, quantum circuit C is obtained, resulting in... Figure 4 The variational quantum circuit shown can support the preparation of up to 72 qubits of asymmetric W-states. Before executing quantum circuit C, the variational parameters of the quantum circuit need to be initialized. , , The parameter sequence S is composed of, etc.

[0083] In step S311, the parameters of the quantum circuit are optimized.

[0084] According to an embodiment of this application, a quantum circuit C is run and all qubits are measured. The loss function value L is calculated based on the measurement results, and an optimization algorithm is used to solve for the parameter sequence S' of the next iteration.

[0085] Specifically, the loss function corresponding to the asymmetric W-state variable quantum circuit is shown in Equation (3). When using optimization algorithms to solve for the parameter sequence S' of the next iteration, gradient-based optimization algorithms, such as Adam and Newton's method, or non-gradient-based optimization algorithms, such as Nelder-Mead simplex method and Powell conjugate direction method, can be used. No specific limitation is made here. During the optimization process, optimization is performed in the direction of decreasing loss function value L to obtain the parameter sequence of the next iteration.

[0086] In step S313, the parameter sequence in the quantum circuit is updated, and step S311 is repeated until the loss function value reaches a preset threshold, and the quantum circuit and the parameter sequence are output.

[0087] Specifically, the parameter sequence S' obtained through the optimization algorithm in the previous step is used to update the parameter sequence of the parameterized quantum circuit C, and the loss function value L is recalculated until the loss function value converges to a minimum or reaches a preset threshold. Otherwise, the process of optimizing and iteratively updating the parameters is repeated continuously. Finally, when the loss function value converges to the preset threshold, the parameter sequence S at this point is the optimal parameter. By utilizing the quantum circuit C and the optimized parameter sequence S, we can reconstruct the target asymmetric W state without retraining the quantum parameters of the quantum circuit.

[0088] according to Figure 2The embodiment shown employs a variable quantum algorithm architecture, which is more suitable for existing noisy hardware and can effectively resist related quantum gate noise and environmental noise. The number of quantum circuit layers obtained only needs to be logarithmic, and the scheme is scalable and can be used for large-scale asymmetric W-state preparation tasks. At the same time, the loss function has the advantage of low measurement complexity, and the prepared target asymmetric W-states have higher accuracy.

[0089] Figure 5 A schematic diagram of a submodule of a variable quantum circuit according to an example embodiment of this application is shown, and the corresponding parametric quantum gate is represented as shown in formula (2).

[0090] like Figure 5 As shown, the corresponding sub-modules include quantum gate 1, quantum gate 2, quantum gate 3, quantum gate 4, quantum gate 5 and quantum gate 6.

[0091] When the variable quantum circuit submodule M acts on two qubits Q1 and Q2, quantum gate 1 is a controlled NOT gate with qubit Q1 as the control bit and qubit Q2 as the controlled bit; quantum gate 2 is a parametric quantum gate Ry1 rotating around the y-axis acting on qubit Q1; quantum gate 3 is a controlled NOT gate with qubit Q2 as the control bit and qubit Q1 as the controlled bit; quantum gate 4 is a parametric quantum gate Ry2 rotating around the y-axis acting on qubit Q1; quantum gate 5 is a controlled NOT gate with qubit Q2 as the control bit and qubit Q1 as the controlled bit; and quantum gate 6 is a controlled NOT gate with qubit Q1 as the control bit and qubit Q2 as the controlled bit.

[0092] To maximize the accuracy of the target asymmetric W state, single-bit gates are applied to qubits with higher single-bit gate fidelity, i.e., qubits corresponding to nodes with larger node values. For example, the X gate can be applied to the qubit corresponding to the node with the larger node value among two nodes, and in the variable quantum circuit submodule, qubit Q1 is selected as the qubit corresponding to the node with the larger node value among two nodes.

[0093] The above description primarily focuses on the methodological aspects of the embodiments of this application. Those skilled in the art should readily recognize that, based on the operations or steps described in conjunction with the embodiments disclosed herein, this application can be implemented in hardware or a combination of hardware and computer software. Those skilled in the art can implement the described functionality in different ways for each specific operation or method, and such implementations should not be considered beyond the scope of this application.

[0094] The apparatus embodiments of this application are described below. For details not described in the apparatus embodiments of this application, please refer to the method embodiments of this application.

[0095] Figure 6A block diagram of an apparatus for preparing an asymmetric W-state in a quantum system according to an example embodiment of this application is shown, such as... Figure 6 The fabrication apparatus shown includes a graph structure construction unit 601, a first quantum operation unit 603, a second parametric quantum operation first unit 605, a second edge determination unit 607, a second parametric quantum operation second unit 609, a quantum circuit generation unit 611, and an iterative optimization unit 613. The graph structure construction unit 601 is used to construct a graph structure corresponding to the quantum computing chip in the quantum system, based on the topology of the quantum computing chip. The graph structure includes multiple nodes and edges connecting any two nodes, including a first edge and a second edge. The first quantum operation unit 603 is used to apply a first quantum operation to the qubit corresponding to the node with the larger node value in the first edge. The second parametric quantum operation first unit 605 is used to apply a second parametric quantum operation to the qubits corresponding to the two nodes in the first edge to generate a parametric asymmetric W state corresponding to the first edge. The second edge determination unit 607, the first parametric quantum operation second unit 609, and the second edge determination unit 6007 are all used in this process. Unit 607 is used to determine the second side from the adjacent sides of the first side; second parameterized quantum operation second unit 609 is used to apply the second parameterized quantum operation to the qubits corresponding to the two nodes in the second side respectively to generate a parameterized asymmetric W state corresponding to the second side; quantum circuit generation unit 611 is used to generate a corresponding quantum circuit according to the execution order of the first quantum operation and the second parameterized quantum operation; iterative optimization unit 613 is used to measure the qubits corresponding to the quantum circuit to iteratively optimize the variational parameters in the quantum circuit using a preset loss function based on the measurement results.

[0096] According to an embodiment of this application, the second side determination unit uses the first side and the second side as the current first side, and repeats the operation with the second parametric quantum operation second unit until the generated parametric asymmetric W state reaches the scale required by the preset asymmetric W state.

[0097] Figure 7 An electronic device according to an exemplary embodiment of this application is shown. Reference is made below. Figure 7 To describe an electronic device 200 according to this embodiment of the present application. Figure 7 The electronic device 200 shown is merely an example and should not impose any limitations on the functionality and scope of use of the embodiments of this application.

[0098] like Figure 7 As shown, the electronic device 200 is presented in the form of a general-purpose computing device. The components of the electronic device 200 may include, but are not limited to: at least one processing unit 210, at least one storage unit 220, a bus 230 connecting different system components (including storage unit 220 and processing unit 210), a display unit 240, etc.

[0099] The storage unit stores program code, which can be executed by the processing unit 210 to perform the methods described in this specification according to various exemplary embodiments of this application. For example, the processing unit 210 can perform, for example... Figure 1 The method shown.

[0100] Storage unit 220 may include readable media in the form of volatile storage units, such as random access memory (RAM) 2201 and / or cache memory 2202, and may further include read-only memory (ROM) 2203.

[0101] Storage unit 220 may also include a program / utility 2204 having a set (at least one) program module 2205, such program module 2205 including but not limited to: operating system, one or more application programs, other program modules and program data, each or some combination of these examples may include an implementation of a network environment.

[0102] Bus 230 can represent one or more of several types of bus structures, including a memory cell bus or memory cell controller, a peripheral bus, a graphics acceleration port, a processing unit, or a local bus using any of the various bus structures.

[0103] Electronic device 200 can also communicate with one or more external devices 300 (e.g., keyboard, pointing device, Bluetooth device, etc.), and with one or more devices that enable a user to interact with electronic device 200, and / or with any device that enables electronic device 200 to communicate with one or more other computing devices (e.g., router, modem, etc.). This communication can be performed via input / output (I / O) interface 250. Furthermore, electronic device 200 can also communicate with one or more networks (e.g., local area network (LAN), wide area network (WAN), and / or public networks, such as the Internet) via network adapter 260. Network adapter 260 can communicate with other modules of electronic device 200 via bus 230. It should be understood that, although not shown in the figures, other hardware and / or software modules can be used in conjunction with electronic device 200, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems.

[0104] Through the above description of the embodiments, those skilled in the art will readily understand that the exemplary embodiments described herein can be implemented by software or by combining software with necessary hardware. The technical solutions according to the embodiments of this application can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (such as a CD-ROM, USB flash drive, external hard drive, etc.) or on a network, including several instructions to cause a computing device (such as a personal computer, server, or network device, etc.) to execute the methods described above according to the embodiments of this application.

[0105] Software products may employ any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0106] Computer-readable storage media may include data signals propagated in baseband or as part of a carrier wave, carrying readable program code. Such propagated data signals may take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A readable storage medium may also be any readable medium other than a readable storage medium that can transmit, propagate, or transfer a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the readable storage medium may be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, etc., or any suitable combination thereof.

[0107] Program code for performing the operations of this application can be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can execute entirely on the user's computing device, partially on the user's computing device, as a standalone software package, partially on the user's computing device and partially on a remote computing device, or entirely on a remote computing device or server. In cases involving remote computing devices, the remote computing device can be connected to the user's computing device via any type of network, including a local area network (LAN) or a wide area network (WAN), or it can be connected to an external computing device (e.g., via the Internet using an Internet service provider).

[0108] The aforementioned computer-readable medium carries one or more programs, which, when executed by a device, cause the computer-readable medium to perform the aforementioned functions.

[0109] Those skilled in the art will understand that the above modules can be distributed in the device as described in the embodiments, or they can be modified accordingly and placed in one or more devices that are unique to this embodiment. The modules in the above embodiments can be combined into one module, or they can be further divided into multiple sub-modules.

[0110] According to an embodiment of this application, a computer program is proposed, including a computer program or instructions, which, when executed by a processor, can perform the methods described above.

[0111] The embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the method and core ideas of this application. Furthermore, any changes or modifications made by those skilled in the art based on the ideas of this application, and on the specific implementation methods and application scope of this application, are all within the scope of protection of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for preparing an asymmetric W state in a quantum system, characterized in that, include: (1) Based on the topology of the quantum computing chip in the quantum system, construct a graph structure corresponding to the quantum computing chip, wherein the graph structure includes multiple nodes and an edge connecting any two nodes among the multiple nodes, and the edge includes a first edge and a second edge; (2) Apply the first quantum operation to the qubit corresponding to the node with the larger node value in the first edge; (3) Apply a second parametric quantum operation to the qubits corresponding to the two nodes in the first side to generate a parametric asymmetric W state corresponding to the first side; (4) Determine the second side from the adjacent sides of the first side; (5) Apply the second parametric quantum operation to the qubits corresponding to the two nodes in the second side to generate the parametric asymmetric W state corresponding to the second side; (6) Using the first edge and the second edge as the current first edge, repeat steps (4) and (5) until the generated parameterized asymmetric W state reaches the scale required by the preset asymmetric W state; (7) Generate the corresponding quantum circuit according to the execution order of the first quantum operation and the second parameterized quantum operation; (8) Measure the qubits corresponding to the quantum circuit, and use the measurement results to iteratively optimize the variational parameters in the quantum circuit using a preset loss function.

2. The preparation method according to claim 1, characterized in that, Based on the topology of the quantum computing chip in the quantum system, a graph structure corresponding to the quantum computing chip is constructed, including: The nodes of the graph structure represent the qubits of the quantum computing chip, the node value of the node represents the single-bit gate fidelity of the qubit, the edges of the graph structure represent the relationships between the qubits of the quantum computing chip, and the two-bit gate fidelity between qubits is used as the weight value of the corresponding edge.

3. The preparation method according to any one of claims 1-2, characterized in that, The first edge includes a first node, and the second edge is determined from the adjacent edges of the first edge, including: A node connected to the first node but not in the first edge is designated as a second node. The edge between the first node and the second node is defined as the second edge, and each first node and each second node can form at most one second edge.

4. The preparation method according to claim 3, characterized in that, A node connected to the first node but not in the first edge is designated as a second node. The edge between the first node and the second node is defined as the second edge, and each first node and each second node can form at most one second edge, including: The edges between the first node and the second node are sorted according to their weight values, and the second edge is determined one by one in descending order.

5. The preparation method according to claim 1, characterized in that, Applying a first quantum operation to the qubit corresponding to the node with the larger node value in the first edge includes: Construct a weight set using the weight values ​​corresponding to all edges of the graph structure; The edge corresponding to the largest weight value is selected as the first edge based on the weight values ​​of the weight set; A first quantum operation is applied to the qubit corresponding to the node with the larger node value in the first edge.

6. The preparation method according to claim 1, characterized in that, The first quantum operation includes the X gate.

7. The preparation method according to claim 1, characterized in that, The second parametric quantum operation includes a variable quantum circuit module, which is represented by the following formula: Among them, CNOT, For universal quantum gates, This is a controlled NOT gate where qubit 1 is the control bit and qubit 2 is the controlled bit. A control NOT gate where qubit 2 is the control bit and qubit 1 is the controlled bit. A parametric rotation about the y-axis acting on qubit 1 The revolving door To select a parametric rotation about the y-axis for operation on qubit 1 A revolving door.

8. The preparation method according to claim 1, characterized in that, The loss function value is calculated using the following formula: in, Let B be the loss function value, and B be a single excited state of the target asymmetric W state. The set that is formed For the target asymmetric W state, the corresponding single excited state Amplitude on The quantum state in the measurement result collapses into a single excited state. The probability of it, The probability of a quantum state collapsing into a non-single excited state in the measurement result.

9. A device for preparing an asymmetric W state in a quantum system, characterized in that, include: The graph structure construction unit is used to construct a graph structure corresponding to the quantum computing chip according to the topology of the quantum computing chip in the quantum system. The graph structure includes multiple nodes and an edge connecting any two nodes among the multiple nodes. The edge includes a first edge and a second edge. The first quantum operation unit is used to apply a first quantum operation to the qubit corresponding to the node with the larger node value in the first edge; The first unit of the second parametric quantum operation is used to apply the second parametric quantum operation to the qubits corresponding to the two nodes in the first edge to generate the parametric asymmetric W state corresponding to the first edge. The second side determination unit is used to determine the second side from the adjacent sides of the first side; The second parameterized quantum operation second unit is used to apply the second parameterized quantum operation to the qubits corresponding to the two nodes in the second side respectively, so as to generate a parameterized asymmetric W state corresponding to the second side; A quantum circuit generation unit is used to generate a corresponding quantum circuit according to the execution order of the first quantum operation and the second parameterized quantum operation; An iterative optimization unit is used to measure the qubits corresponding to the quantum circuit, and to iteratively optimize the variational parameters in the quantum circuit using a preset loss function based on the measurement results; The second edge determination unit uses the first edge and the second edge as the current first edge, and repeats the operation with the second parametric quantum operation second unit until the generated parametric asymmetric W state reaches the scale required by the preset asymmetric W state.

10. An electronic device, comprising: processor; as well as A memory storing a computer program that, when executed by the processor, causes the processor to perform the preparation method as described in any one of claims 1-8.

11. A non-transitory computer-readable storage medium having stored thereon computer-readable instructions that, when executed by a processor, cause the processor to perform the preparation method as described in any one of claims 1-8.

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