Display panel and display device

Abstract

This invention relates to the field of display technology, specifically to a display panel and a display device. The display panel includes a display section, a first bent section, and a first circuit section. The display section includes scan lines and light-emitting control lines extending along a first direction. In the first direction, the first circuit section is located on the side of the first bent section away from the display section. The first circuit section includes a first shift register unit and a second shift register unit. The first bent section includes a first connecting line and a second connecting line. One end of the first connecting line is coupled to the output terminal of the first shift register unit, and the other end is coupled to the scan line. One end of the second connecting line is coupled to the output terminal of the second shift register unit, and the other end is coupled to the light-emitting control line. A dummy line is provided between adjacent first and second connecting lines. This invention can reduce the corrosion risk caused by the high and low voltage difference between the first and second connecting lines during long-term operation, thereby improving the reliability of the display panel.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more particularly to a display panel and a display device. Background Technology

[0002] With the development of display technology, electronic display products are increasingly demanding higher resolution, higher screen-to-body ratios, and lower power consumption. Narrow bezel design is a crucial means of achieving a high screen-to-body ratio. For example, in mobile phones, narrow bezels include not only narrowing the top and bottom non-display areas but also narrowing the left and right non-display areas. Currently, solutions for narrowing the left and right non-display area bezels reduce the spacing between adjacent signal lines transmitting different signals, creating a risk of corrosion and impacting product performance and reliability. Summary of the Invention

[0003] This invention provides a display panel and a display device to solve the problem of corrosion risk between adjacent signal lines, which affects the reliability of product performance.

[0004] In a first aspect, the present invention provides a display panel, the display panel including a display part, a first bending part and a first circuit part, the display part including scan lines and light emission control lines extending along a first direction, and in the first direction, the first circuit part is located on the side of the first bending part away from the display part; The first circuit section includes a first shift register unit and a second shift register unit, and the first bent section includes a first connecting line and a second connecting line; one end of the first connecting line is coupled to the output terminal of the first shift register unit and the other end is coupled to the scan line, and one end of the second connecting line is coupled to the output terminal of the second shift register unit and the other end is coupled to the light emission control line. A dummy line is provided between adjacent first and second connecting lines.

[0005] Secondly, based on the same inventive concept, the present invention also provides a display device, including any of the display panels provided by the present invention.

[0006] The display panel and display device provided by the present invention have the following beneficial effects: The present invention provides a dummy line between adjacent first connecting lines and second connecting lines, and uses the dummy line to adjust the electric field distribution between the first connecting lines and second connecting lines, suppressing electrochemical migration between the first connecting lines and second connecting lines, thereby reducing the risk of corrosion caused by high and low voltage differences between the first connecting lines and second connecting lines under long-term operation, and improving the performance reliability of the display panel. Attached Figure Description

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0008] Figure 1 A schematic diagram of a display panel provided in an embodiment of the present invention; Figure 2 A schematic diagram of a pixel circuit provided in an embodiment of the present invention; Figure 3 For driving Figure 2 A signal timing diagram for a pixel circuit; Figure 4 for Figure 1 A wiring diagram at location Q1 in the central area; Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 7 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention; Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention; Figure 13 for Figure 1 A wiring diagram at location Q2 in the central region; Figure 14 for Figure 1 Another wiring diagram for location Q2 in the central area; Figure 15 This is a schematic diagram of a display device provided in an embodiment of the present invention. Detailed Implementation

[0009] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0010] The terminology used in the embodiments of this invention is for the purpose of describing particular embodiments only and is not intended to limit the invention. The singular forms “a,” “the,” and “the” as used in the embodiments of this invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0011] Various modifications and variations can be made to this invention without departing from its spirit or scope, as will be apparent to those skilled in the art. Therefore, this invention is intended to cover modifications and variations falling within the scope of the corresponding claims (the claimed technical solutions) and their equivalents. It should be noted that the embodiments provided by this invention can be combined with each other without contradiction.

[0012] This invention provides a display panel with a first circuit section and a first bend section. A shift register unit is disposed in the first circuit section, and the output terminal of the shift register unit is connected to a response signal line in the display section via a connecting line arranged in the first bend section. When the first bend section is in a bent state, the first circuit section can be placed on the back of the display panel, that is, the shift register unit can be placed on the back of the display panel, thereby narrowing the bezel. Considering that the shift register unit includes a first shift register unit that provides signals to the scan line and a second shift register unit that provides signals to the light emission control line, and the enable phase of the scan signal and the enable phase of the light emission control signal do not overlap. Taking a low-potential signal as the enable signal as an example, the light emission control signal is a low-potential signal for a long time, and the scan signal is a high-potential signal for a long time. Therefore, the first connecting line coupled to the scan line in the first bend section transmits a high-potential signal for a long time, and the second connecting line coupled to the light emission control line transmits a low-potential signal for a long time. The dense arrangement of connecting lines within the first bend and the reduced spacing between adjacent connecting lines result in a prolonged high-low pressure difference between adjacent first and second connecting lines. One of the first and second connecting lines acts as an anode and the other as a cathode, creating a risk of corrosion between adjacent connecting lines.

[0013] To address the corrosion risk between adjacent connecting lines within a bend, this invention employs a dummy line between the first and second connecting lines. This dummy line adjusts the electric field distribution between the first and second connecting lines, suppressing electrochemical migration and thus reducing the corrosion risk during prolonged operation, thereby improving the reliability of the display panel. Furthermore, in some embodiments, a dummy line is also arranged between adjacent first connecting lines transmitting different scanning signals to further reduce the corrosion risk between them. Moreover, the dummy bus electrically connected to the dummy line is designed, with a first dummy bus located within the first circuit section and / or a second dummy bus located in the non-display area of ​​the display section. The positional relationships between the first dummy bus and the power bus, and between the second dummy bus and the power bus, are also designed. The above outlines the main technical concept of this invention; specific embodiments are described below.

[0014] Figure 1 This is a schematic diagram of a display panel provided in an embodiment of the present invention. Figure 1 As shown, the display panel includes a display section 10, a first bending section 21, and a first circuit section 22. Figure 1 This diagram illustrates the structure of the display panel in its unfolded state, with the first bending portion 21 positioned on the side of the first bending portion 21 away from the display unit 10 in the first direction x. The first bending portion 21 connects the display unit 10 and the first circuit portion 22. When the first bending portion 21 is bent, the first circuit portion 22 is located on the side of the display unit 10 facing away from the display surface. In other words, when the first bending portion 21 is bent, the first circuit portion 22 is placed on the back side of the display panel. The display unit 10 includes a display area AA, within which multiple pixel circuits and multiple signal lines 30 extending along the first direction x are arranged. The multiple signal lines 30 include scan lines and light-emitting control lines required to drive the pixel circuits. A shift register circuit 40 is arranged within the first circuit portion 22. The shift register circuit 40 includes multiple shift register units, which provide signals to the corresponding signal lines 30.

[0015] Figure 2 This is a schematic diagram of a pixel circuit provided in an embodiment of the present invention. Figure 3 For driving Figure 2 A signal timing diagram for a pixel circuit. For example... Figure 2As shown, the pixel circuit includes a driving transistor Tm, a gate reset transistor T1, an electrode reset transistor T2, a data write transistor T3, a threshold compensation transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. The driving transistor Tm is connected in series between the first and second light-emitting control transistors T5 and T6. The first light-emitting control transistor T5 is connected to the positive power supply voltage Pvdd, and the second electrode of the light-emitting device PD is connected to the negative power supply voltage Pvee. The operation of the pixel circuit includes at least a reset phase t1, a write phase t2, and a light-emitting phase t3. During the reset phase t1, gate reset transistor T1 is turned on under the control of scan signal S1, writing reset signal Vref1 to the gate of driving transistor Tm, and electrode reset transistor T2 is turned on under the control of scan signal S1, writing reset signal Vref2 to the first electrode of light-emitting device PD. During the writing phase t2, data writing transistor T3 and threshold compensation transistor T4 are turned on under the control of scan signal S2, writing data voltage Data to the gate of driving transistor Tm and performing self-testing and compensation on the threshold voltage of driving transistor Tm. During the light-emitting phase t3, first light-emitting control transistor T5 and second light-emitting control transistor T6 are turned on under the control of light-emitting control signal Emit, and driving transistor Tm generates driving current under the control of its gate voltage and provides driving current to light-emitting device PD.

[0016] Figure 2 The diagram illustrates the pixel circuit using p-type transistors. In other embodiments, the transistors in the pixel circuit may be n-type transistors, or some transistors may be p-type and some may be n-type. These are not illustrated in the accompanying drawings.

[0017] Depend on Figure 3 As shown in the schematic timing diagram, the enable signals for scan signals S1 and S2, as well as the enable signal for the emission control signal Emit, are all low-level signals. During the pixel circuit's operating cycle, the scan signals are high-level signals for a long period, while the emission control signals are low-level signals for a long period. To meet the driving requirements of the pixel circuit, the scan lines need to transmit high-level signals for a long time, while the emission control lines need to transmit low-level signals for a long time.

[0018] Figure 4 for Figure 1 A wiring diagram for location Q1 in the central region. (Example) Figure 4 As shown, the display unit 10 includes a scan line 31 extending along a first direction x and a light emission control line 32. The scan line 31 provides a scan signal to the pixel circuit 33, and the light emission control line 32 provides a light emission control signal to the pixel circuit 33. (Combined with...) Figure 2As shown in the schematic pixel circuit diagram, driving a row of pixel circuits 33 arranged in the first direction x requires at least two scan lines 31 and one light-emitting control line 32. The scan lines 31 include a first sub-scan line 311 and a second sub-scan line 312. Figure 4 The diagram illustrates the coupling of the first sub-scan line 311 and the second sub-scan line 312 with the first connecting line 51 within the first bend portion 21.

[0019] The first circuit section 22 includes a first shift register unit 41 and a second shift register unit 42. The first bending section 21 includes a first connecting line 51 and a second connecting line 52. One end of the first connecting line 51 is coupled to the output terminal of the first shift register unit 41, and the other end is coupled to the scan line 31. One end of the second connecting line 52 is coupled to the output terminal of the second shift register unit 42, and the other end is coupled to the light emission control line 32. A dummy line 60 is provided between adjacent first connecting lines 51 and second connecting lines 52.

[0020] The display panel provided in this embodiment of the invention includes a display section 10, a first bending section 21, and a first circuit section 22. The first bending section 21 connects the first circuit section 22 and the display section 10. A shift register unit is arranged in the first circuit section 22, and a connecting line is arranged in the first bending section 21. One end of the first connecting line 51 is coupled to the first shift register unit 41, and the other end is coupled to a scan line 31 in the display section 10. One end of the second connecting line 52 is coupled to the second shift register unit 42, and the other end is coupled to a light emission control line 32 in the display section 10. When the first bending section 21 is in a bent state, the first circuit section 22 can be placed on the back side of the display panel, thereby narrowing the bezel of the display panel. When the display panel is working, the first connecting line 51 transmits a scan signal, and the second connecting line 52 transmits a light emission control signal. There is a long-term high and low voltage difference between adjacent first connecting lines 51 and second connecting lines 52. In this embodiment of the invention, a dummy line 60 is provided between adjacent first connecting lines 51 and second connecting lines 52. The dummy line 60 is used to adjust the electric field distribution between the first connecting lines 51 and second connecting lines 52, suppressing electrochemical migration between the first connecting lines 51 and second connecting lines 52. This reduces the risk of corrosion caused by the high and low voltage difference between the first connecting lines 51 and second connecting lines 52 during long-term operation, and improves the reliability of the display panel performance.

[0021] For example, such as Figure 4As shown, the first connecting line 51 includes adjacent first sub-connecting lines 511 and 512, which are coupled to scan lines 31 respectively. A dummy line 60 is provided between the first sub-connecting line 511 and the second sub-connecting line 512. For example, the first sub-connecting line 511 is coupled to the first sub-scanning line 311 in the display unit 10, and the second sub-connecting line 512 is coupled to the second sub-scanning line 312. The first sub-scanning line 311 and the second sub-scanning line 312 transmit different scan signals; for example, the first sub-scanning line 311 provides scan signal S1 to the pixel circuit 33, and the second sub-scanning line 312 provides scan signal S2 to the pixel circuit 33. Figure 3 As shown in the schematic timing diagram, during certain periods, scan signal S1 and scan signal S2 are at different potentials, one being a high-potential signal and the other a low-potential signal. Therefore, during these periods, a voltage difference also exists between adjacent first sub-connection lines 511 and 512, posing a risk of corrosion. In this embodiment of the invention, a dummy line 60 is provided between adjacent first sub-connection lines 511 and 512. This dummy line 60 adjusts the electric field distribution between the first sub-connection lines 511 and 512, suppressing electrochemical migration between them. This reduces the risk of corrosion caused by the voltage difference between the first sub-connection lines 511 and 512 during prolonged operation.

[0022] In some implementations, the dummy line 60 is connected to a constant voltage signal. This constant voltage signal adjusts the electric field distribution between adjacent connecting lines, suppressing electrochemical migration caused by long-term high-low voltage differences and reducing the risk of corrosion between adjacent connecting lines during prolonged operation.

[0023] For example, the voltage of the constant voltage signal on dummy line 60 is 0V.

[0024] In other embodiments, the dummy line 60 is connected to a square wave signal. The square wave signal is a periodic signal, including a high-potential signal and a low-potential signal. The square wave signal is used to adjust the electric field distribution between two adjacent connection lines, suppressing electrochemical migration caused by long-term high and low voltage differences between the two adjacent connection lines, and reducing the risk of corrosion between the two adjacent connection lines under long-term operation.

[0025] For example, the display panel includes a clock signal line that transmits a clock signal. The period of the square wave signal is the same as the period of the clock signal. The clock signal line can be either the clock signal line that drives the first shift register unit 41 or the clock signal line that drives the second shift register unit 42.

[0026] For example, scan line 31 transmits scan signal, light emission control line 32 transmits light emission control signal, the high voltage of square wave signal is lower than the high voltage of scan signal, and the low voltage of square wave signal is higher than the low voltage of light emission control signal line.

[0027] For example, the low potential of the scanning signal on the scanning line 31 has a first frequency, the high potential of the light emission control signal on the light emission control line 32 has a second frequency, and the frequency of the over-wave signal on the dummy line 60 is between the first frequency and the second frequency.

[0028] For example, such as Figure 1 As shown, the display panel includes two first bends 21 and two first circuit sections 22. In the first direction x, the two first bends 21 are located on both sides of the display section 10, and the two first circuit sections 22 are located on both sides of the display section 10. A shift register circuit 40 can be arranged in each of the two first circuit sections 22, and correspondingly, a dummy line 60 can be arranged in each of the two first bends 21. The shift register circuit 40 arranged in each of the two first circuit sections 22 provides signals to the scan lines and light emission control lines within the display area AA, making the signals on the scan lines and the light emission control lines more uniform, thereby improving display uniformity.

[0029] For example, such as Figure 4 As shown, the distance between the dummy line 60 and its adjacent first connecting line 51 is d1, and the distance between the dummy line 60 and its adjacent second connecting line 52 is d2, where d1 = d2. On the one hand, when the dummy line 60, the first connecting line 51, and the second connecting line 52 are fabricated in the same layer, the etching uniformity of each signal line can be ensured; on the other hand, when the first bending portion 21 is in a bent state, the bending stress on each signal line can be relatively uniform, reducing the risk of line breakage.

[0030] Optionally, within the first bend 21, the spacing between the dummy line 60 and its adjacent first sub-connecting line 511 is d1, and the spacing between the dummy line 60 and its adjacent second sub-connecting line 512 is d1. Within the first bend 21, multiple connecting lines and multiple dummy lines are arranged at equal intervals.

[0031] For example, Figure 5 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 5As shown, the first circuit section 22 includes a first dummy bus 61, and multiple dummy lines 60 are coupled to the first dummy bus 61 at their first ends in the first direction x. Signals can be provided to the multiple dummy lines 60 using the first dummy bus 61. When the first bend 21 is in a bent state, the first dummy bus 61 is positioned on the back side of the display panel along with the first circuit section 22. The placement of the first dummy bus 61 does not affect the bezel width of the display panel.

[0032] like Figure 5 As shown, the first circuit section 22 includes a plurality of first bonding terminals 221, and the first dummy bus 61 is coupled to at least one first bonding terminal 221. In this embodiment, the first bonding terminals 221 provide signals to the first dummy bus 61, and then the first dummy bus 61 provides signals to multiple dummy lines 60 respectively. In application, the plurality of first bonding terminals 221 can be bonded to a flexible circuit board. The plurality of first bonding terminals 221 include not only terminals connected to the first dummy bus 61, but also terminals connected to drive signal lines located in the first circuit section 22. The drive signal lines are used to drive cascaded shift register units.

[0033] like Figure 5 As shown, in the first direction x, the first dummy bus 61 is located on the side of the shift register circuit 40 near the first bend 21. The shift register circuit 40 includes a first shift register unit 41 and a second shift register unit 42, meaning that in the first direction x, the first dummy bus 61 is located on the side of the first shift register unit 41 and the second shift register unit 42 near the first bend 21. Considering that the first shift register unit 41 and the second shift register unit 42 each include multiple transistors, if the first dummy bus 61 is located on the side of the shift register circuit 40 away from the first bend 21, multiple traces need to be set up to cross the shift register circuit 40 when the first dummy bus 61 is connected to multiple dummy lines 60, increasing the wiring complexity within the first circuit section 22. The positioning of the first dummy bus 61 in this embodiment of the invention can shorten the connection distance between the first dummy bus 61 and multiple dummy lines 60, and the connection between the two does not require bridge lines, simplifying the wiring method within the first circuit section 22.

[0034] In some implementations... Figure 6 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 6 The diagram illustrates the wiring arrangement at the locations of the first bend 21 and part of the display section 10 in the top view. For example... Figure 6As shown, the first circuit section 22 also includes a first power bus 70, and a first dummy bus 61 and the first power bus 70 are located on the same layer. In this embodiment of the invention, the first dummy bus 61 and the first power bus 70 can both be double-layered wiring, or both can be single-layered wiring. Specifically, in the first direction x, the first dummy bus 61 is located on the side of the first power bus 70 away from the first bend 21. When the first bend 21 is in a bent state, the first circuit section 22 is placed on the back side of the display panel, so the wiring structure arranged in the first circuit section 22 does not affect the bezel width of the display panel. When the first power bus 70 and the first dummy bus 61 are provided in the first circuit section 22, placing the first power bus 70 and the first dummy bus 61 on the same layer can avoid large-area overlap of metal phases transmitting different signals, which would increase coupling on the bus and affect signal voltage drop.

[0035] Furthermore, considering that the first power bus 70 is located on the side of the shift register circuit 40 near the first bend 21, the output terminals of the first shift register unit 41 and the second shift register unit 42 in the shift register circuit 40 need to be connected by wires (i.e., the first connecting line 51 and the second connecting line 52) respectively to the first bend 21. In other words, the traces led out from the output terminals of the first shift register unit 41 and the second shift register unit 42 need to cross the location of the first power bus 70 to reach the location of the first bend 21. Figure 6The diagram simplifies the representation of only one first shift register unit 41 and one second shift register unit 42 within the shift register circuit 40. A first trace 91 extends from the output of the first shift register unit 41, and a second trace 92 extends from the output of the second shift register unit 42. Both traces 91 and 92 are insulated from and overlap with the first power bus 70. The first trace 91 is electrically connected to a first connecting line 51 located at the first bend 21, and the second trace 92 is electrically connected to a second connecting line 52 located at the first bend 21. In other words, the signal from the output of the first shift register unit 41 is transmitted to the scan line of the display area AA via the first trace 91 (insulated from and overlapping with the first power bus 70) and the first connecting line 51 located at the first bend 21. Similarly, the signal from the output of the second shift register unit 42 is transmitted to the light-emitting control line of the display area AA via the second trace 92 (insulated from and overlapping with the first power bus 70) and the second connecting line 52 located at the first bend 21. In this embodiment of the invention, a first dummy bus 61 is located on the side of the first power bus 70 away from the first bend 21. A dummy connection line 63 is also provided between the first dummy bus 61 and the dummy line 60 located in the first bend 21. At the location of the first power bus 70, the dummy connection line 63 connected to the first dummy bus 61 can also be routed between adjacent first traces 91 and second traces 92. The dummy connection line 63 is used to adjust the electric field distribution between the first traces 91 and second traces 92, reducing the risk of corrosion caused by the high and low voltage difference between the first traces 91 and second traces 92 during long-term operation.

[0036] For example, such as Figure 6 As shown, the first power bus 70 includes a first positive power bus 71 and a first negative power bus 72. The first positive power bus 71 is used to transmit the positive power supply voltage Pvdd, and the first negative power supply bus 72 is used to transmit the negative power supply voltage Pvee. Figure 6 The diagram only shows the first positive power bus 71 located on the side of the first negative power bus 72 away from the first bend 21. In other embodiments, the first power bus 70 includes a first positive power bus 71 and a first negative power bus 72, with the first positive power bus 71 located on the side of the first negative power bus 72 closer to the first bend 21; these are not shown in the diagram here.

[0037] like Figure 6As shown, the display panel also includes a second power bus 80 located in the display section 10, which is located in the non-display area NA. For example, the second power bus 80 is coupled to the first power bus 70 via a third connecting line. The second power bus 80 includes a second positive power bus 81 and a second negative power bus 82. The third connecting line includes a third sub-connecting line 711 and a fourth sub-connecting line 721. The second positive power bus 81 is electrically connected to the first positive power bus 71 via the third sub-connecting line 711 passing through the first bend 21, and the second negative power bus 82 is electrically connected to the first negative power bus 72 via the fourth sub-connecting line 721 passing through the first bend 21. The first power bus 70 located in the first circuit section 22 is electrically connected to the corresponding second power bus 80 located in the non-display area NA using the connecting line passing through the first bend 21. The second power bus 80 is then coupled to a corresponding circuit structure located in the display area AA, such as the second positive power bus 81 being coupled to the positive power signal line in the display area AA, and the first negative power bus 72 being coupled to the cathode of the light-emitting device in the display area AA. The embodiments of the present invention utilize the wiring space of the first circuit section 22, which can reduce the voltage drop of the power supply voltage and improve the uniformity of the power supply voltage in the plane.

[0038] In some embodiments of the present invention, in the first bend 21, the third sub-connecting line 711 and the fourth sub-connecting line 721 are both disposed in the peripheral area of ​​the plurality of dummy lines 60. Specifically, within the first bend 21, the plurality of dummy lines 60 are arranged in the second direction y, which intersects the first direction x; the third sub-connecting line 711 is located on the side of the fourth sub-connecting line 721 away from the plurality of dummy lines 60. By setting the positions of the third sub-connecting line 711 and the fourth sub-connecting line 721 in accordance with the relative positions of the first positive power bus 71 and the first negative power bus 72, it is possible to avoid wire entanglement when the wiring connects to the power bus, thus simplifying the wiring method.

[0039] For example, the first dummy bus 61 and the first power bus 70 are on the same layer and made of the same material. The dummy connection line 63 led out from the first dummy bus 61 is insulated and overlapped with the first power bus 70. The dummy connection line 63 and the first dummy bus 61 are set on different layers.

[0040] Figure 6 The diagram illustrates that the first power bus 70 located in the first circuit section 22 includes a first positive power bus 71 and a first negative power bus 72. In other embodiments, the first power bus 70 located in the first circuit section 22 includes only one of the first positive power bus 71 and the first negative power bus 72. Figure 7 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 7As shown, a first negative power bus 72 is also arranged in the first circuit section 22, and a first dummy bus 61 is located on the side of the first negative power bus 72 away from the first bend 21. A second negative power bus 82 is arranged in the non-display area NA of the display section 10, and the first negative power bus 72 and the second negative power bus 82 are coupled by a third connecting line (i.e., a fourth sub-connecting line 721) passing through the first bend 21. The fourth sub-connecting line 721 is located in the peripheral area of ​​the plurality of dummy lines 60.

[0041] In some embodiments, the first connecting line 51, the second connecting line 52, and the dummy line 60 are on the same layer and made of the same material. The first connecting line 51 and the second connecting line 52 are located at the first bend 21. When assembling the display device, the first bend 21 is bent so that the first circuit section 22 is placed on the back side of the display panel. At this time, the first connecting line 51 and the second connecting line 52 also bend along with the first bend 21. To avoid wire breakage due to bending and to improve the reliability of the display panel, the first connecting line 51 and the second connecting line 52 are placed on the same layer and at the bend neutral plane of the first bend 21 to reduce the bending stress borne by the first connecting line 51 and the second connecting line 52. In this embodiment of the invention, the dummy line 60 is placed on the same layer as the first connecting line 51 and the second connecting line 52. On the one hand, this ensures the bending resistance of the dummy line 60; on the other hand, it also better inhibits electrochemical migration between the first connecting line 51 and the second connecting line 52.

[0042] For example, the materials used to manufacture the first connecting line 51, the second connecting line 52, and the dummy line 60 include titanium and / or aluminum. For instance, the first connecting line 51, the second connecting line 52, and the dummy line 60 may all be titanium / aluminum / titanium three-layer structures.

[0043] In addition, the portion of the third sub-connecting line 711 located at the first bend 21 and the portion of the fourth sub-connecting line 721 located at the first bend 21 are also in the same layer and made of the same material as the first connecting line 51, the second connecting line 52 and the dummy line 60.

[0044] For example, Figure 8 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 8As shown, the display unit 10 includes a display area AA and a non-display area NA surrounding the display area AA. The first circuit unit 22 includes a first dummy bus 61, and the non-display area NA includes a second dummy bus 62. Multiple dummy lines 60 are coupled to the first dummy bus 61 at a first end and to the second dummy bus 62 at a second end in the first direction x. In this embodiment, the first dummy bus 61 is coupled to the second dummy bus 62 on the left and right sides of the multiple dummy lines 60, respectively. This makes the impedance of the overall dummy line smaller, reduces the voltage drop on the dummy lines 60, improves the voltage uniformity on the dummy lines 60, and makes the ability of the dummy lines 60 at different positions to adjust the electric field distribution between adjacent connecting lines basically consistent.

[0045] Figure 8 The diagram shows that a first bonding terminal 221 is arranged in the first circuit section 22, and the first dummy bus 61 is coupled to at least one first bonding terminal 221, and a voltage signal is provided to the first dummy bus 61 by means of the first bonding terminal 221.

[0046] For example, Figure 9 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 9 As shown, the display panel also includes a second bending portion 23 and a second circuit portion 24. When the second bending portion 23 is in a flattened state, in the second direction y, the second circuit portion 24 is located on the side of the second bending portion 23 away from the display portion 10, and the second direction y intersects the first direction x. That is, in the second direction y, the second bending portion 23 is connected between the display portion 10 and the second circuit portion 24. The second circuit portion 24 includes a plurality of second bonding terminals 241, and the second dummy bus 62 is coupled to at least one of the second bonding terminals 241. The plurality of second bonding terminals 241 can be used to bond a flexible circuit board, and fix a display driver chip on the flexible circuit board. When the second bending portion 23 is bent, the second circuit portion 24 and the flexible circuit board are placed on the back side of the display panel, thereby narrowing the width of the bottom bezel of the display panel. In this embodiment, the second dummy bus 62 in the non-display area NA is coupled to the second bonding terminal 241, and the second bonding terminal 241 is used to provide a voltage signal to the second dummy bus 62.

[0047] Figure 9 As illustrated in the embodiment, the first dummy bus 61 is coupled to at least one first binding terminal 221, and the second dummy bus 62 is coupled to at least one second binding terminal 241. The first binding terminal 221 provides a voltage signal to the first dummy bus 61, and the second binding terminal 241 provides a voltage signal to the second dummy bus 62, so that the voltage signal uniformity on the multiple dummy lines 60 is better.

[0048] For example, Figure 10 This is a schematic diagram of another display panel provided in an embodiment of the present invention. Figure 10As shown, a second dummy bus 62 is arranged in the non-display area NA of the display unit 10. The second ends of multiple dummy lines 60 are coupled to the second dummy bus 62, and the second dummy bus 62 is coupled to at least one second bonding terminal 241 located in the second circuit unit 24. Furthermore, a first dummy bus 61 is arranged in the first circuit unit 22, and the first ends of multiple dummy lines 60 are coupled to the first dummy bus 61. This reduces the overall impedance of the dummy lines and improves the uniformity of the voltage signal on the multiple dummy lines 60.

[0049] For example, Figure 11 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention, such as... Figure 11 As shown, the non-display area NA includes a second power bus 80 and a second dummy bus 62; along the plane perpendicular to the substrate, the second dummy bus 62 and the second power bus 80 at least partially overlap. In this embodiment, the second dummy bus 62 and the second power bus 80 are located on different layers, and the two at least partially overlap, which can reduce the total area occupied by the bus in the non-display area NA, and is beneficial for narrowing the bezel.

[0050] Figure 11 As shown, the second power bus 80 includes a second positive power bus 81 and a second negative power bus 82. Along a direction perpendicular to the plane of the substrate, the second dummy bus 62 and the second negative power bus 82 at least partially overlap.

[0051] The second dummy bus 62 is located on the side of the second power bus 80 away from the substrate, or the second dummy bus 62 is located on the side of the second power bus 80 closer to the substrate.

[0052] In some implementations, such as Figure 8 As shown, the first circuit section 22 includes a first dummy bus 61, and multiple dummy lines 60 are coupled to the first dummy bus 61 at a first end in the first direction x; a second dummy bus 62 is arranged in the non-display area NA of the display section 10, and multiple dummy lines 60 are coupled to the second dummy bus 62 at a second end in the first direction x; the first dummy bus 61, the second dummy bus 62, and the dummy lines 60 are on the same layer and made of the same material. This embodiment sets the entire dummy circuit on the same layer, allowing for the design of the film layer positions of the first circuit section 22 and other circuit structures within the non-display area NA in accordance with the film layer positions of the dummy circuit.

[0053] For example, Figure 12 This is a partial schematic diagram of another display panel provided in an embodiment of the present invention. Figure 12As shown, the first circuit section 22 includes a first dummy bus 61, with multiple dummy lines 60 coupled to the first dummy bus 61 at a first end in the first direction x; a second dummy bus 62 is arranged in the non-display area NA of the display section 10, with multiple dummy lines 60 coupled to the second dummy bus 62 at a second end in the first direction x. Along the second direction y, the width of the first dummy bus 61 is greater than the width of the second dummy bus 62. This embodiment, by providing the first dummy bus 61 and the second dummy bus 62 on both sides of the multiple dummy lines 60, can reduce the overall impedance of the dummy circuit and improve the voltage uniformity on the multiple dummy lines 60. The larger width of the first dummy bus 61 further reduces the overall impedance of the dummy circuit. Moreover, since the first circuit section 22 is placed on the back side of the display panel when the first bend 21 is in a bent state, the wiring within the first circuit section 22 has relatively large freedom, and the larger width of the first dummy bus 61 does not affect the bezel width of the display panel.

[0054] For example, such as Figure 1 As shown, the display unit 10 includes a display area AA, which includes a first display area AA1 and a second display area AA2. The first display area AA1 has arc-shaped boundaries on both sides of the first direction x, and the second display area AA2 has straight boundaries on both sides of the first direction x.

[0055] Figure 13 for Figure 1 A wiring diagram at location Q2 in the central region. (Example) Figure 13 As shown, scan line 31 includes a first scan line 31-1 located in the first display area AA1, and light emission control line 32 includes a first light emission control line 32-1 located in the first display area AA1. The first circuit section 22 includes a shift unit group 40Y, which includes a first shift register unit 41 and a second shift register unit 42. The shift unit group 40Y includes a first unit group 40Y1. The output terminal of the first shift register unit 41 within the first unit group 40Y1 is coupled to one end of a first connecting line 51, and the other end of the first connecting line 51 is coupled to the first scan line 31-1 in the first display area AA1. The output terminal of the second shift register unit 42 within the first unit group 40Y1 is coupled to one end of a second connecting line 52, and the other end of the second connecting line 52 is coupled to the first light emission control line 32-1 in the first display area AA1. Figure 1 As can be seen, the first display area AA1 has an arc-shaped boundary, and the left and right sides of the first display area AA1 are adjacent to the arc-shaped corners of the display panel. The shape of the non-display area NA is designed to adapt to the boundary shape of the first display area AA1. In this embodiment, the shift register unit that drives the first display area AA1 is set in the first circuit section 22. There is no need to set the shift register unit in the non-display area adjacent to the first display area AA1, which can narrow the width of the bezel adjacent to the first display area AA1.

[0056] like Figure 13 As shown, a third trace 85 is arranged within the display area AA. The first connecting line 51, which is coupled to the first shift register unit 41 within the first unit group 40Y1, is coupled to the first scan line 31-1 through the third trace 85. The second connecting line 52, which is coupled to the second shift register unit 42 within the first unit group 40Y1, is coupled to the first light emission control line 32-1 through the third trace 85. Arranging the third trace 85 in the display area AA does not occupy the space of the non-display area NA, and can further narrow the bezel width adjacent to the first display area AA1.

[0057] Figure 13 The schematic diagram shows a shift unit group 40Y comprising two first shift register units 41 and one second shift register unit 42. The second shift register unit 42 outputs a light emission control signal. Within the shift unit group 40Y, the second shift register unit 42 is located on the side of the first shift register unit 41 furthest from the first bend 21. The shift unit group 40Y outputs two scan signals and one light emission control signal. This application does not limit the order of the output signals of the shift unit group 40Y. Figure 13 Taking the output signal sequence of shift unit group 40Y as an example, which is scan signal, scan signal, and light emission control signal.

[0058] For example, Figure 14 for Figure 1 Another wiring diagram for location Q2 in the central area. (See diagram below.) Figure 14As shown, the display area AA includes a second display area AA2, and the boundaries of the second display area AA2 on both sides of the first direction x are straight boundaries; the scan line 31 includes a second scan line 31-2 located in the second display area AA2, and the light emission control line 32 includes a second light emission control line 32-2 located in the second display area AA2. The shift unit group 40Y located in the first circuit section 22 includes a second unit group 40Y2, the output end of the first shift register unit 41 in the second unit group 40Y2 is coupled to one end of the first connecting line 51, and the other end of the first connecting line 51 is coupled to the second scan line 31-2, the output end of the second shift register unit 42 in the second unit group 40Y2 is coupled to one end of the second connecting line 52, and the other end of the second connecting line 52 is coupled to the second light emission control line 32-2; wherein, the first unit group 40Y1 is located on the side of the second unit group 40Y2 away from the first bending section 21. The number of pixel circuit rows in the first display area AA1 is less than the number of pixel circuit rows in the second display area AA2. Therefore, the number of shift unit groups 40Y required to drive the first display area AA1 is less than the number of shift unit groups 40Y required to drive the second display area AA2. Positioning the second unit group 40Y2 closer to the first bend 21 makes the wiring more regular when multiple second unit groups 40Y2 are arranged, and shortens the distance between the output terminal of the shift register unit in the second unit group 40Y2 and the first bend 21, thus reducing the wiring length.

[0059] For example, such as Figure 13 As shown, the first unit group 40Y1 is located on the side of the second unit group 40Y2 away from the first bending part 21, and multiple first unit groups 40Y1 are arranged in the second direction y. Figure 13 The virtual boundary YY between the first display area AA1 and the second display area AA2 is indicated by the label. Along the second direction y, the first scan line 31-1 and the first light emission control line 32-1, which are farther away from the virtual boundary YY within the first display area AA1, are coupled to the first unit group 40Y1, which is also farther away from the virtual boundary YY in the first circuit section 22. Figure 13 Taking the four first unit groups 40Y1 illustrated in the diagram as an example, four signal line groups are arranged from top to bottom within the first display area AA1. Each signal line group includes two first scan lines 31-1 and one first light emission control line 32-1. One signal line group is used to drive one pixel circuit row. Multiple first unit groups 40Y1 arranged along the second direction y away from the virtual boundary YY are sequentially coupled to multiple signal line groups arranged along the second direction y away from the virtual boundary YY.

[0060] For example, such as Figure 13As shown, the first unit group 40Y1 is coupled to two first connecting lines 51 and one second connecting line 52, and these two first connecting lines 51 and one second connecting line 52 form a first connecting line group 50Z1. The second unit group 40Y2 is coupled to two first connecting lines 51 and one second connecting line 52, and these two first connecting lines 51 and one second connecting line 52 form a second connecting line group 50Z2. Within the first bend 21, the first connecting line group 50Z1 is located between two adjacent second connecting line groups 50Z2. This arrangement ensures that the traces led out from the first unit group 40Y1 and the traces led out from the second unit group 40Y2 do not intersect, and the connecting lines corresponding to each unit group can be sequentially connected to the corresponding scan lines or light-emitting control lines within the display area AA, avoiding wire wrapping.

[0061] Based on the same inventive concept, embodiments of the present invention also provide a display device. Figure 15 This is a schematic diagram of a display device provided in an embodiment of the present invention, such as... Figure 15 As shown, the display device includes a display panel 100 provided in any embodiment of the present invention. The structure of the display panel has been described in the above embodiments and will not be repeated here. The display device provided in the embodiments of the present invention can be, for example, an electronic device with display function such as a mobile phone, tablet, computer, television, or smart wearable product.

[0062] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

[0063] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, The display panel includes a display section, a first bent section, and a first circuit section. The display section includes scan lines and light-emitting control lines extending along a first direction. In the first direction, the first circuit section is located on the side of the first bent section away from the display section. The first circuit section includes a first shift register unit and a second shift register unit, and the first bent section includes a first connecting line and a second connecting line; one end of the first connecting line is coupled to the output terminal of the first shift register unit and the other end is coupled to the scan line, and one end of the second connecting line is coupled to the output terminal of the second shift register unit and the other end is coupled to the light emission control line; A dummy line is provided between adjacent first and second connecting lines.

2. The display panel according to claim 1, characterized in that, The first circuit section includes a first dummy bus, and a plurality of the dummy lines are coupled to the first dummy bus at a first end in the first direction.

3. The display panel according to claim 2, characterized in that, The first circuit section includes a plurality of first bonding terminals, and the first dummy bus is coupled to at least one of the first bonding terminals.

4. The display panel according to claim 2, characterized in that, In the first direction, the first dummy bus is located on the side of the first shift register unit and the second shift register unit near the first bend.

5. The display panel according to claim 4, characterized in that, The first circuit section further includes a first power bus, and the first dummy bus and the first power bus are located on the same layer; In the first direction, the first dummy bus is located on the side of the first power bus away from the first bend.

6. The display panel according to claim 5, characterized in that, The display unit includes a second power bus, and the first power bus and the second power bus are coupled together by a third connecting line, which passes through the first bend in the first direction. The third connecting line is located in the outer area of ​​the plurality of dummy lines.

7. The display panel according to claim 1 or 2, characterized in that, The display unit includes a display area and a non-display area surrounding the display area; The non-display area includes a second dummy bus, and multiple dummy lines are coupled to the second dummy bus at the second end in the first direction.

8. The display panel according to claim 7, characterized in that, The display panel further includes a second bending portion and a second circuit portion; in a second direction, the second circuit portion is located on the side of the second bending portion away from the display portion; The second circuit section includes a plurality of second bonding terminals, and the second dummy bus is coupled to at least one of the second bonding terminals.

9. The display panel according to claim 7, characterized in that, The non-display area includes a second power bus; The display panel includes a substrate, and along a plane perpendicular to the substrate, the second dummy bus and the second power bus at least partially overlap.

10. The display panel according to claim 7, characterized in that, The first circuit section includes a first dummy bus, and a plurality of the dummy lines are coupled to the first dummy bus at a first end in the first direction; Along the second direction, the width of the first dummy bus is greater than the width of the second dummy bus.

11. The display panel according to claim 1, characterized in that, The first connection line includes an adjacent first sub-connection line and a second sub-connection line, and the first sub-connection line and the second sub-connection line are respectively coupled to the scan line; The dummy line is provided between the first sub-connecting line and the second sub-connecting line.

12. The display panel according to claim 1, characterized in that, The first connecting line, the second connecting line, and the dummy line are made of the same layer and material.

13. The display panel according to claim 1, characterized in that, The dummy line is connected to a constant voltage signal or a square wave signal.

14. The display panel according to claim 13, characterized in that, The voltage of the constant voltage signal is 0V; Alternatively, the display panel includes a clock signal line that transmits a clock signal, wherein the period of the square wave signal is the same as the period of the clock signal; Alternatively, the scan line transmits a scan signal, the light emission control line transmits a light emission control signal, the high voltage of the square wave signal is lower than the high voltage of the scan signal, and the low voltage of the square wave signal is higher than the low voltage of the light emission control signal line.

15. The display panel according to claim 1, characterized in that, The distance between the dummy line and the first connecting line adjacent to it is d1, and the distance between the dummy line and the second connecting line adjacent to it is d2, where d1 = d2.

16. The display panel according to claim 1, characterized in that, The display unit includes a display area, which includes a first display area, the boundaries of which on both sides in the first direction are arc-shaped boundaries; the scan line includes a first scan line located in the first display area, and the light emission control line includes a first light emission control line located in the first display area; The first circuit section includes a shift unit group, which includes a first shift register unit and a second shift register unit; The shift unit group includes a first unit group, wherein the output terminal of the first shift register unit in the first unit group is coupled to one end of the first connecting line and the other end of the first connecting line is coupled to the first scan line, and the output terminal of the second shift register unit in the first unit group is coupled to one end of the second connecting line and the other end of the second connecting line is coupled to the first light emission control line.

17. The display panel according to claim 16, characterized in that, The display area includes a second display area, the boundaries of which on both sides in the first direction are straight boundaries; the scan line includes a second scan line located in the second display area, and the light emission control line includes a second light emission control line located in the second display area; The shifting unit group includes a second unit group. The output terminal of the first shifting register unit in the second unit group is coupled to one end of the first connecting line and the other end of the first connecting line is coupled to the second scan line. The output terminal of the second shifting register unit in the second unit group is coupled to one end of the second connecting line and the other end of the second connecting line is coupled to the second light emission control line. The first unit group is located on the side of the second unit group away from the first bend.

18. The display panel according to claim 17, characterized in that, The first unit group is correspondingly coupled to two first connecting lines and one second connecting line, and the two first connecting lines and one second connecting line form a first connecting line group; The second unit group is correspondingly coupled to two first connecting lines and one second connecting line, and the two first connecting lines and one second connecting line form a second connecting line group; Within the first bend, the first connecting group is located between two adjacent second connecting groups.

19. The display panel according to claim 1, characterized in that, The display panel includes two first bent portions and two first circuit portions. In the first direction, the two first bends are located on both sides of the display unit, and the two first circuits are located on both sides of the display unit.

20. A display device, characterized in that, Includes the display panel as described in any one of claims 1 to 19.

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