Driving method and display device

Abstract

The application relates to the display technical field and discloses a driving method and a display device, the method is applied to a time sequence controller in the display device, the display device further comprises a source driver, a demultiplexing switch array and a display panel provided with a plurality of rows of pixels, the method comprises the following steps: when the scanning period of the current row of pixels starts, the conduction sequence of the sub-pixel of each pixel in the current row of pixels in the scanning period is randomly generated; according to the conduction sequence, corresponding control signals are sequentially output to the demultiplexing switch array, so that the demultiplexing switch array sequentially controls the corresponding sub-pixels to be turned on according to the corresponding control signals; the conduction sequence is transmitted to the source driver, so that the source driver determines the color data output sequence of each sub-pixel according to the conduction sequence, and corresponding color data is output to the corresponding sub-pixels according to the output sequence for charging display; the output sequence and the conduction sequence correspond to each other in the time domain. The application can reduce periodic picture flicker.

Description

Technical Field

[0001] This application relates to the field of display technology, and in particular to a driving method and display device. Background Technology

[0002] As the demands for display resolution (such as 4K and 8K) and refresh rate (such as 120Hz and 144Hz) continue to increase in terminal devices such as smartphones, tablets, and automotive displays, the number of data drive channels required inside display panels is growing exponentially. To reduce the size of driver chips, the industry generally adopts a demultiplexing display driver architecture.

[0003] However, in existing Demux driving methods, the conduction sequence of each demultiplexed control clock (CKH1, CKH2, CKH3...) remains fixed within each pixel scan cycle (for example, it always conducts in a fixed order of CKH1→CKH2→CKH3→... across the entire screen). This fixed timing results in all pixel channels having the same charging and discharging start time in each horizontal scan cycle. Since polarity inversion technology is commonly used in display drivers to avoid liquid crystal polarization, at the moment of polarity inversion, all pixel electrodes experience a voltage jump simultaneously, and all channels synchronously switch from forward charging to reverse charging (or vice versa).

[0004] Therefore, the aforementioned synchronous charging and discharging behavior induces transient current surges on the common electrode (Vcom), causing severe synchronous fluctuations in the common electrode voltage (i.e., Vcom bounce). Since the charging and discharging sequence of each line and each frame is completely repeated, the frequency of this Vcom fluctuation is locked at the display frame rate (e.g., 60Hz) or its integer multiples, which happens to fall into the low-frequency band (approximately 50~100Hz) where the human eye is most sensitive to brightness fluctuations. This results in a visually obvious periodic screen flicker, affecting the user's viewing experience. Summary of the Invention

[0005] The main purpose of this application is to provide a driving method and display device that aims to solve the technical problem that the existing fixed timing causes all pixel channels to have the same charging and discharging start time in each horizontal scan cycle, resulting in screen flicker and affecting the user's viewing experience.

[0006] To achieve the above objectives, this application provides a driving method applied to a timing controller in a display device. The display device further includes a source driver, a demultiplexing switch array, and a display panel with a plurality of rows of pixels. The method includes: At the start of the scanning cycle of the current row of pixels, the conduction order of the sub-pixels of each pixel in the current row of pixels during the scanning cycle is randomly generated. According to the conduction sequence, the corresponding control signals are sequentially output to the demultiplexing switch array, so that the demultiplexing switch array sequentially controls the conduction of the corresponding sub-pixels according to the corresponding control signals; The conduction sequence is transmitted to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence, and outputs the corresponding color data to the corresponding sub-pixel for charging and display according to the output order. The output order and the conduction sequence correspond one-to-one in the time domain.

[0007] In one embodiment, the step of randomly generating the conduction order of sub-pixels of each pixel within the current row of pixels during the scan cycle includes: A first-order pseudo-random vector is randomly generated for each pixel in the current row of pixels, and the conduction sequence corresponding to the first-order pseudo-random vector is determined according to a first preset mapping relationship. The conduction sequence is used to characterize the conduction order of the sub-pixels of each pixel in the current row of pixels in the scanning cycle. The step of sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction sequence includes: According to the conduction sequence, the corresponding control signals are sequentially output to the demultiplexing switch array; The step of transmitting the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence includes: The conduction sequence is transmitted to the source driver so that the source driver determines the color data output order of each sub-pixel based on the conduction sequence.

[0008] In one embodiment, the demultiplexing switch array includes at least two logic blocks, and each logic block includes at least two sets of demultiplexing switches; The control terminal of each demultiplexing switch in each group is connected to the output terminal of the control signal corresponding to the timing controller. The input terminal of each demultiplexing switch in each group is connected to the output terminal of the color data corresponding to the source driver. The output terminal of each demultiplexing switch in each group is connected to the data line of the corresponding column pixel in the display panel. A group of demultiplexing switches is used to control the on / off state of a sub-pixel within a pixel. Wherein, at least one set of two adjacent demultiplexing switches within a logic block have different width-to-length ratios, wherein the width-to-length ratio is the ratio of the channel width to the channel length of the demultiplexing switch.

[0009] In one embodiment, the width-to-length ratio of each group of demultiplexed switches within the same logic block is set non-linearly.

[0010] In one embodiment, among the M groups of demultiplexing switches within the same logic block, the width-to-length ratio of the i-th group of demultiplexing switches is... ;

[0011] in, Based on the width-to-length ratio, is the spatial size perturbation coefficient, and M is the total number of demultiplexed switching transistors within the same logic block.

[0012] In one embodiment, the step of sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction sequence includes: The corresponding initial signals are generated sequentially according to the conduction sequence, and the fine-tuning duration corresponding to each initial signal is obtained according to the second preset mapping relationship. The corresponding initial signal is phase-adjusted according to the fine-tuning duration to obtain the corresponding control signal; The step of transmitting the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence includes: The conduction sequence and each of the fine-tuning durations are transmitted to the source driver so that the source driver determines the output timing and output order of the color data of each sub-pixel according to the conduction sequence and the fine-tuning duration.

[0013] In addition, to achieve the above objectives, this application also proposes a display device, which includes: a source driver, a demultiplexing switch array, a timing controller, and a display panel with a plurality of rows of pixels; The timing controller includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the driving method as described above.

[0014] In one embodiment, the demultiplexing switch array includes at least two logic blocks, and each logic block includes at least two sets of demultiplexing switches; The display panel includes: a liquid crystal layer and at least two metal layers. The liquid crystal layer includes at least two display areas. Each display area has a plurality of rows of pixels. Each display area corresponds to each logic block. The demultiplexing switch in each logic block is used to control the on / off state of the pixels in the corresponding display area. The signal lines of control signals for at least two adjacent display areas are located on different metal layers.

[0015] In one embodiment, the display panel further includes: an interlayer insulating layer; An interlayer insulating layer is provided between two adjacent metal layers, and a via region is provided at the intersection node of the signal lines of different metal layers in adjacent display areas, and a via is provided in the via region to penetrate the interlayer insulating layer; The number of vias in adjacent via regions is different.

[0016] In one embodiment, the display panel further includes: a parasitic balancing unit; The parasitic balancing unit is disposed on the side of at least one of the straight signal lines in the display area, and is spaced apart along the extension direction of the straight signal lines. The parasitic balancing unit is electrically connected to a constant reference potential and is used to form a parasitic capacitance with the adjacent signal lines.

[0017] This application provides a driving method and a display device. The method is applied to a timing controller in the display device, which further includes a source driver, a demultiplexing switch array, and a display panel with a plurality of rows of pixels. The method includes: at the beginning of the scanning cycle of the current row of pixels, randomly generating the conduction order of sub-pixels of each pixel in the current row of pixels during the scanning cycle; sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction order, so that the demultiplexing switch array sequentially controls the conduction of the corresponding sub-pixels according to the corresponding control signals; transmitting the conduction order to the source driver, so that the source driver determines the color data output order of each sub-pixel according to the conduction order, and outputs the corresponding color data to the corresponding sub-pixel for charging display according to the output order, wherein the output order and the conduction order correspond one-to-one in the time domain.

[0018] When preparing to scan a new row of pixels, this application allows the timing controller to generate a random conduction sequence, which determines the charging order of the red, green, and blue sub-pixels in the current row. Then, according to the determined conduction sequence, the timing controller sequentially outputs control signals to the demultiplexing switch array. The demultiplexing switch array, following the received control signals, sequentially opens the corresponding switches, conducting the corresponding sub-pixels one by one, preparing to receive data. Simultaneously, after determining the random conduction sequence, the timing controller synchronously sends this sequence to the source driver. The source driver adjusts the output color data order according to the received conduction sequence, ensuring that the output data order is completely consistent with the switch opening order. Because this application randomly generates the conduction sequence of each sub-pixel in the row at the beginning of each row pixel scanning cycle, and synchronously adjusts the color data output sequence of the source driver while the conduction sequence changes, so that the data sequence and the switching sequence correspond one-to-one in the time domain, compared with the fixed conduction sequence used in the prior art, this application randomly disperses the originally uniform charging and discharging impact, so that the voltage fluctuation generated on the common electrode is no longer a fixed frequency periodic spike, thereby converting the low-frequency flicker that the human eye is sensitive to into high-frequency random noise, reducing periodic screen flicker and improving the user's viewing experience. Attached Figure Description

[0019] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application.

[0020] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of this application; Figure 2 This is a flowchart illustrating the first embodiment of the driving method of this application; Figure 3 This is a schematic diagram of the display device in the first embodiment of the driving method of this application; Figure 4 This is a schematic diagram showing the change in the width-to-length ratio of each group of demultiplexed switching transistors within the same logic block in the second embodiment of the driving method of this application; Figure 5 This is a flowchart illustrating the third embodiment of the driving method of this application; Figure 6 This is a schematic diagram of phase fine-tuning in the third embodiment of the driving method of this application; Figure 7 This is a schematic diagram of the structure of the display panel in the first embodiment of the display device of this application; Figure 8 This is a schematic diagram of cross-layer wiring in the display panel of the first embodiment of the display device of this application; Figure 9 This is a schematic diagram of each via region in the first embodiment of the display device of this application.

[0022] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0023] It should be understood that the specific embodiments described herein are merely illustrative of the technical solutions of this application and are not intended to limit this application.

[0024] Reference Figure 1 , Figure 1 This is a schematic diagram of the device structure of the hardware operating environment involved in the embodiments of this application.

[0025] like Figure 1 As shown, the timing controller may include: a processor 1001, such as a central processing unit (CPU), a communication bus 1002, a user interface 1003, a network interface 1004, and a memory 1005. The communication bus 1002 is used to implement communication between these components. The user interface 1003 may include a display screen, and optionally, the user interface 1003 may also include a standard wired interface or a wireless interface. In this application, the wired interface of the user interface 1003 may be a USB interface. The network interface 1004 may optionally include a standard wired interface or a wireless interface (such as a Wireless-Fidelity (Wi-Fi) interface). The memory 1005 may be high-speed random access memory (RAM) or non-volatile memory (NVM), such as a disk storage device. The memory 1005 may also optionally be a storage device independent of the aforementioned processor 1001.

[0026] Those skilled in the art will understand that Figure 1 The structure shown does not constitute a limitation on the timing controller and may include more or fewer components than shown, or combine certain components, or have different component arrangements.

[0027] like Figure 1As shown, the memory 1005, which is identified as a computer storage medium, may include an operating system, a network communication module, a user interface module, and a driver.

[0028] exist Figure 1 In the device shown, the network interface 1004 is mainly used to connect to the backend server and communicate with the backend server; the user interface 1003 is mainly used to connect to the user equipment; the device calls the driver stored in the memory 1005 through the processor 1001 and executes the driver method provided in the embodiments of this application.

[0029] It should be noted that as the demands for display resolution (such as 4K, 8K) and refresh rate (such as 120Hz, 144Hz) from terminal devices such as smartphones, tablets, and automotive displays continue to increase, the number of data drive channels required inside the display panel is growing exponentially. In order to reduce the size of the driver chip, the industry generally adopts a demultiplexing display driver architecture.

[0030] However, in existing Demux driving methods, the conduction sequence of each demultiplexed control clock (CKH1, CKH2, CKH3...) remains fixed within each pixel scan cycle (for example, it always conducts in a fixed order of CKH1→CKH2→CKH3→... across the entire screen). This fixed timing results in all pixel channels having the same charging and discharging start time in each horizontal scan cycle. Since polarity inversion technology is commonly used in display drivers to avoid liquid crystal polarization, at the moment of polarity inversion, all pixel electrodes experience a voltage jump simultaneously, and all channels synchronously switch from forward charging to reverse charging (or vice versa).

[0031] Therefore, the aforementioned synchronous charging and discharging behavior induces transient current surges on the common electrode (Vcom), causing severe synchronous fluctuations in the common electrode voltage (i.e., Vcom bounce). Since the charging and discharging sequence of each line and each frame is completely repeated, the frequency of this Vcom fluctuation is locked at the display frame rate (e.g., 60Hz) or its integer multiples, which happens to fall into the low-frequency band (approximately 50~100Hz) where the human eye is most sensitive to brightness fluctuations. This results in a visually obvious periodic screen flicker, affecting the user's viewing experience.

[0032] Therefore, to address the aforementioned shortcomings, this embodiment provides a driving method. When preparing to scan a new row of pixels, the timing controller internally generates a random conduction sequence, which determines the charging order of the red, green, and blue sub-pixels in the current row. Then, according to the determined conduction sequence, the timing controller sequentially outputs control signals to the demultiplexing switch array. The demultiplexing switch array sequentially opens the corresponding switches according to the received control signals, conducting the corresponding sub-pixels one by one in preparation for data reception. Simultaneously, after determining the random conduction sequence, the timing controller synchronously sends this sequence to the source driver. The source driver adjusts the output color data order according to the received conduction sequence to ensure that the output data order is completely consistent with the switch opening order. Because this embodiment randomly generates the conduction sequence of each sub-pixel in the row at the beginning of each row pixel scanning cycle, and synchronously adjusts the color data output sequence of the source driver while the conduction sequence changes, so that the data sequence and the switching sequence correspond one-to-one in the time domain, compared with the fixed conduction sequence used in the prior art, this embodiment randomly disperses the originally uniform charging and discharging impact, so that the voltage fluctuation generated on the common electrode is no longer a fixed frequency periodic spike, thereby converting the low-frequency flicker that the human eye is sensitive to into high-frequency random noise, reducing periodic screen flicker and improving the user's viewing experience.

[0033] For ease of understanding, the following is combined with Figures 2 to 9 The driving method provided in the embodiments of this application will be described in detail.

[0034] Reference Figure 2 , Figure 2 This is a flowchart illustrating the first embodiment of the driving method of this application. The first embodiment of the driving method of this application is presented as follows: Figure 2 As shown, in this embodiment, the method is applied to a timing controller in a display device, which further includes a source driver, a demultiplexing switch array, and a display panel with several rows of pixels.

[0035] It should be explained that the aforementioned timing controller (TCON) can refer to a chip or circuit module in a display device that generates and controls the driving timing of the display panel. For example, it can be a timing control chip that is responsible for receiving image data, generating control signals for gate driving and source driving, and coordinating the charging and discharging actions of each pixel in the display panel.

[0036] Reference Figure 3 , Figure 3 This is a schematic diagram of the display device in the first embodiment of the driving method of this application. Figure 3As shown, the aforementioned timing controller (TCON) can integrate a pseudo-random number generator (PRNG), a clock modulation unit, and a storage register array. The PRNG generates a pseudo-random logic vector at the beginning of each pixel scan cycle; the clock modulation unit dynamically modulates the phase and pulse width of the demultiplexing control clock signal based on the pseudo-random logic vector and a pre-stored physical delay mapping table in the storage register array; and the storage register array (e.g., non-volatile memory or eFuse) pre-programs and stores parameters such as the inherent charging delay compensation for each physical channel.

[0037] It should also be explained that the aforementioned source driver can be a driving circuit chip in the display device used to output pixel voltage signals (i.e., color data) to each column of data lines, such as a source driver chip. In this embodiment, the source driver can be connected to a timing controller, receive image data and control signals from the timing controller, convert digital image data into analog voltage signals, and output them to the corresponding sub-pixel electrodes through data lines to drive the liquid crystal molecules to deflect or the luminescent material to emit light, thereby achieving grayscale display. (Refer to...) Figure 3 The source driver may include multiple channel outputs (SD1, SD2, SD3, etc. as shown in the figure), and each output is connected to a group of sub-pixels (i.e. a group of RGB pixels) through a demultiplexing switch array.

[0038] Understandably, the aforementioned demultiplexing switch array can be a switch array positioned between the source driver output and the display panel data lines, such as a switch network composed of multiple thin-film transistors (TFTs). (See reference...) Figure 3 The demultiplexing switch array can be divided into multiple logic blocks, each logic block corresponding to a display area in the display panel (as shown in the figure, Block 1, Block 2... Block N). Each logic block contains a set of demultiplexing switches (as shown in the figure, T1, T2, T3...). Under the control of the control clock signal (such as CKH1, CKH2, CKH3, etc.) output by the timing controller, each switch is turned on sequentially in time order, transmitting the voltage signal output by a physical output channel of the source driver to multiple sub-pixels connected to that channel in a time-division manner (as shown in the figure, R / G / B sub-pixels).

[0039] It is also understood that the aforementioned display panel can be a screen component for displaying images, such as a liquid crystal display panel or an organic light-emitting diode display panel, etc., and this embodiment does not limit this. The display panel may be provided with several rows of pixels, and each pixel is usually composed of multiple sub-pixels of different colors (e.g., red sub-pixel R, green sub-pixel G, blue sub-pixel B), and the sub-pixels are arranged in an array.

[0040] like Figure 3 As shown, each group of sub-pixels (RGB) is connected to the output of the demultiplexing switch array via corresponding data lines (data1, data2, data3, etc. as shown in the figure). The demultiplexing display driver architecture involved in this embodiment refers to a driving method in which the demultiplexing switch array is controlled by the control clock signal of the timing controller, so that a single output channel of the source driver can drive a group of sub-pixels (such as three sub-pixels: R / G / B) in a time-division multiplexing manner.

[0041] Continue as Figure 2 As shown, the method includes: Step S10: At the start of the scanning cycle of the current row of pixels, randomly generate the conduction order of the sub-pixels of each pixel in the current row within the scanning cycle.

[0042] It should be understood that the aforementioned current row pixel can refer to a row of pixels in the display panel that is currently being scanned. During the display driving process, the timing controller can provide driving signals to each row of pixels sequentially in a line-by-line scanning manner, and the scanned row can be referred to as the current row pixel in this embodiment.

[0043] It should also be understood that the aforementioned sub-pixels can refer to the individual color component units that make up a complete pixel, such as red sub-pixel R, green sub-pixel G, and blue sub-pixel B. A complete pixel can be composed of a group of sub-pixels of different colors, with each sub-pixel independently controlling its brightness, and color display achieved through color mixing.

[0044] It should be explained that the aforementioned conduction sequence refers to the order in which the demultiplexing switches corresponding to each sub-pixel are turned on within the scanning cycle of pixels in the same row. Taking a pixel containing three sub-pixels R / G / B as an example, the conduction sequence can be: first turn on the switch corresponding to the red sub-pixel, then turn on the switch corresponding to the green sub-pixel, and finally turn on the switch corresponding to the blue sub-pixel, i.e., the order R→G→B; or it can be the order G→B→R or B→R→G. In this embodiment, the conduction sequence can be different between different rows, and within the same row, each sub-pixel can be turned on in a determined order.

[0045] In its implementation, the timing controller can activate the pseudo-random number generator integrated within it before starting the scanning drive for the current row of pixels, i.e., at the beginning of the current row pixel scanning cycle. Figure 3 The timing controller (PRNG) randomly generates a pseudo-random number generator to determine the conduction order of multiple sub-pixels contained in each pixel within the current row. This conduction order can be defined as the activation order of the demultiplexing control clock signals (e.g., CKH1, CKH2, CKH3) corresponding to each sub-pixel within the current scan cycle. In an example where a pixel contains three sub-pixels, the conduction order can be the regular order R→G→B, the single-rotation order G→B→R, or the double-rotation order B→R→G; the specific order can be determined by the randomly generated conduction order. Furthermore, the timing controller can repeat the above random generation operation before the start of each row scan cycle, so that the conduction order used between different rows presents a randomized distribution.

[0046] Step S20: Output the corresponding control signals to the demultiplexing switch array in sequence according to the conduction sequence, so that the demultiplexing switch array controls the corresponding sub-pixels to conduct in sequence according to the corresponding control signals; Step S30: The conduction sequence is transmitted to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence, and outputs the corresponding color data to the corresponding sub-pixel for charging and display according to the output order. The output order and the conduction sequence correspond one-to-one in the time domain.

[0047] It should be noted that the aforementioned control signal may refer to the clock control signal output by the timing controller to the demultiplexing switch array, which can be used to control the on and off states of each switch in the demultiplexing switch array. In this embodiment, the aforementioned control signal may be a pulse signal with a certain pulse width, such as the demultiplexing control clock signal (i.e., Figure 3 (e.g., CKH1, CKH2, CKH3, etc.). Each control signal controls a switch in the demultiplexing switch array. When the control signal is at an active level (e.g., high level), the corresponding switch is turned on, allowing the voltage signal output by the source driver to be transmitted to the corresponding sub-pixel through that switch. The demultiplexing switch array has been explained in the preceding section and will not be repeated here.

[0048] It should also be noted that the color data mentioned above can refer to the grayscale voltage signal output by the source driver to each sub-pixel. This grayscale voltage signal can correspond to the brightness of the color component to be displayed by a certain sub-pixel in a pixel. For example, the color data corresponding to the red sub-pixel is the red grayscale voltage, the color data corresponding to the green sub-pixel is the green grayscale voltage, and the color data corresponding to the blue sub-pixel is the blue grayscale voltage.

[0049] Understandably, the aforementioned color data output order refers to the order in which the source driver outputs the grayscale voltage signals corresponding to each sub-pixel to the data line within the same row scan cycle. This output order corresponds one-to-one with the conduction order in the time domain. That is, at any given time point, the color of the sub-pixel corresponding to the color data output by the source driver can be exactly the same as the color of the sub-pixel currently conducted by the demultiplexing switch array. Specifically, red data is output when the red switch is on, green data is output when the green switch is on, and blue data is output when the blue switch is on; the data and switches are strictly matched in time.

[0050] In a specific implementation, after determining the conduction order of the current row of pixels through a random generation operation, the timing controller can sequentially output the corresponding control signals to the demultiplexing switch array according to the order of each sub-pixel defined by the conduction order.

[0051] Specifically, the timing controller can generate multiple independent demultiplexing control clock signals through the aforementioned clock modulation unit. Each control clock signal corresponds to a switch in the demultiplexing switch array. Then, based on the conduction sequence, it determines which sub-pixel's corresponding switch should be turned on at the current moment. This control clock signal is then enabled and output as a pulse to the control terminal of the corresponding switch in the demultiplexing switch array, turning on the switch. After the switch corresponding to the first sub-pixel is turned on and completes charging, the timing controller stops this control clock signal, turning off the switch. Next, following the next sequence in the conduction sequence, the timing controller enables the next control clock signal and outputs it to the control terminal of the next corresponding switch, turning on that next switch. The timing controller can sequentially traverse all sub-pixels in the conduction sequence in this manner until all sub-pixels in the current row are sequentially turned on, completing the charging drive for the current row.

[0052] Meanwhile, after determining the conduction sequence of the pixels in the current row, the timing controller can synchronously transmit this conduction sequence to the source driver via the data transmission interface. Upon receiving this conduction sequence, the source driver can determine the output order of the color data of each sub-pixel within the current row scan cycle based on this sequence.

[0053] Specifically, the source driver internally includes a data formatting module responsible for rearranging the color data of each sub-pixel according to the received conduction order. Then, the source driver sequentially converts the color data corresponding to each sub-pixel into corresponding grayscale voltage signals according to the output order and outputs them sequentially to the data lines connected to the demultiplexing switch array. When the timing controller sequentially outputs control signals to the demultiplexing switch array according to the conduction order, causing the switches corresponding to each sub-pixel to conduct sequentially, the source driver synchronously outputs the corresponding color data according to the output order. Since the output order and conduction order correspond one-to-one in the time domain, at any given time, the color corresponding to the color data transmitted on the data line is the same as the color of the sub-pixel connected to the currently conducting switch, thus ensuring that each color data is correctly written into the corresponding color sub-pixel.

[0054] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, suppose a pixel contains three sub-pixels: R, G, and B, and the current row of pixels is the 5th row. The pseudo-random number generator inside the timing controller generates a conduction sequence of G→B→R at the beginning of the 5th row scan cycle. The timing controller can synchronously transmit this conduction sequence G→B→R to the source driver. The source driver can determine the color data output order of the current row as green data → blue data → red data based on this conduction sequence.

[0055] At the start of the current row scan cycle, the timing controller first outputs a high-level pulse to the control terminal (e.g., CKH2) of the switch corresponding to the green sub-pixel, turning on the switch. At this time, the source driver synchronously outputs a green grayscale voltage to the data line, and the green voltage is written to the green sub-pixel through the turned-on switch. Then, the timing controller stops the high-level pulse of CKH2, turning off the switch corresponding to the green sub-pixel. Next, it outputs a high-level pulse to the control terminal (e.g., CKH3) of the switch corresponding to the blue sub-pixel, at which time the source driver synchronously outputs a blue grayscale voltage, which is written to the blue sub-pixel. Afterward, the timing controller turns off the blue switch, and finally outputs a high-level pulse to the control terminal (e.g., CKH1) of the switch corresponding to the red sub-pixel, and the source driver synchronously outputs a red grayscale voltage, which is written to the red sub-pixel.

[0056] Throughout the process, the data output sequence G→B→R is perfectly synchronized with the switch activation sequence G→B→R in time. Green data always arrives when the green switch is on, preventing the intrusion of red or blue pixels and ensuring correct color display. At the start of the 6th row scan cycle, the pseudo-random number generator may generate an activation sequence of B→R→G. The source driver then adjusts the output sequence to blue data→red data→green data, maintaining synchronization with the 6th row's switch activation sequence. The activation sequence for each row is independently determined by the pseudo-random number generator, and there is no fixed repetition pattern between rows.

[0057] Because this embodiment randomly generates the conduction sequence at the beginning of each row of pixel scanning cycles and synchronously transmits the conduction sequence to the source driver so that the data output sequence of the source driver corresponds one-to-one with the switch conduction sequence of the demultiplexing switch array in the time domain, compared with the existing technology that uses a fixed conduction sequence and data sequence for each row, this embodiment makes the charging and discharging start time of each pixel channel present a random distribution between different rows, breaking up the originally synchronous common electrode voltage fluctuations, thereby converting periodic low-frequency flicker into random high-frequency noise, effectively reducing or eliminating screen flicker that is perceptible to the human eye, and improving display quality and user viewing experience.

[0058] Furthermore, in order to achieve random generation of the above-mentioned conduction order, in this embodiment, the step of randomly generating the conduction order of sub-pixels of each pixel in the current row within the scanning period includes: Step S11: Randomly generate a first-order pseudo-random vector for each pixel in the current row of pixels, and determine the conduction sequence corresponding to the first-order pseudo-random vector according to the first preset mapping relationship. The conduction sequence is used to characterize the conduction order of the sub-pixels of each pixel in the current row of pixels in the scanning period.

[0059] It should be noted that the aforementioned first-order pseudo-random vector can refer to a random value directly output by the pseudo-random number generator built into the timing controller during a single random generation operation. This first-order pseudo-random vector can be used to characterize the randomization state of the current row's conduction order, and its value determines which conduction order is adopted for the current row. For example, when the pseudo-random number generator is a linear feedback shift register and its output is a 2-bit state value, the first-order pseudo-random vector can take any one of the three state values: "00", "01", or "10".

[0060] It should also be noted that the aforementioned first preset mapping relationship can refer to the correspondence between each state value of a first-order pseudo-random vector and a conduction sequence. For example, state value "00" corresponds to a regular conduction sequence, "01" corresponds to a first-order rotation conduction sequence, and "10" corresponds to a second-order rotation conduction sequence. The aforementioned conduction sequence can refer to a predefined order of sub-pixel activation, such as "CKH1→CKH2→CKH3," which can represent activation in the order of red switch, green switch, and blue switch. In this embodiment, the aforementioned conduction sequence can define the activation order of the demultiplexing control clock signal corresponding to each sub-pixel in the current row. The aforementioned demultiplexing switch array and control signal have been explained in the previous steps and will not be repeated here.

[0061] Accordingly, the step of sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction sequence includes: Step S21: Output the corresponding control signals to the demultiplexing switch array sequentially according to the conduction sequence; Accordingly, the step of transmitting the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence includes: Step S31: Transmit the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence.

[0062] In its implementation, the timing controller first performs a random number generation operation using its internally integrated pseudo-random number generator at the start of the current row pixel scanning cycle, obtaining a first-order pseudo-random vector. Then, it reads a pre-stored first preset mapping relationship, which defines the correspondence between different pseudo-random vector state values ​​and different conduction sequences. Based on the generated first-order pseudo-random vector, it searches and determines the conduction sequence matching that first-order pseudo-random vector from the first preset mapping relationship. This conduction sequence is the conduction order of each sub-pixel within the current row pixel during the scanning cycle. For example, when the first-order pseudo-random vector generated by the timing controller is a state value "01", the timing controller determines, according to the first preset mapping relationship, that this state value corresponds to a rotation conduction sequence, i.e., conduction in the order G→B→R.

[0063] Subsequently, after determining the conduction sequence, the timing controller can sequentially output the corresponding control signals to the demultiplexing switch array according to the order of the control clock signals defined in the conduction sequence. Specifically, the timing controller can sequentially enable the demultiplexing control clock signals of each circuit base according to the activation order of the clock signals recorded in the conduction sequence, and output them in pulse form to the control terminals of the corresponding switches in the demultiplexing switch array.

[0064] Simultaneously, the timing controller can synchronously transmit the aforementioned conduction sequence to the source driver via the data transmission interface. After receiving the conduction sequence, the source driver determines the output order of the color data of each sub-pixel within the current row scan cycle based on the conduction sequence. The data formatting module inside the source driver rearranges the color data of each sub-pixel according to the received conduction sequence, so that the output order corresponds one-to-one with the conduction sequence in the time domain.

[0065] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, assume that the pseudo-random number generator inside the timing controller is a 2-bit linear feedback shift register capable of outputting three state values: "00", "01", and "10". The timing controller has a pre-stored first preset mapping relationship: state value "00" corresponds to the normal conduction sequence "R→G→B", state value "01" corresponds to the first rotation conduction sequence "G→B→R", and state value "10" corresponds to the second rotation conduction sequence "B→R→G". At the start of the current row pixel scan cycle, the timing controller can control the pseudo-random number generator to perform a random number generation operation, obtaining a first-order pseudo-random vector, assuming this first-order pseudo-random vector is "01". The timing controller searches for the conduction sequence corresponding to state value "01" according to the first preset mapping relationship, and the found conduction sequence is "G→B→R". The timing controller then follows this conduction sequence, first enabling CKH2 to output a pulse signal to turn on the green switch, then enabling CKH3 to output a pulse signal to turn on the blue switch, and finally enabling CKH1 to output a pulse signal to turn on the red switch. Simultaneously, the timing controller can synchronously transmit this conduction sequence "G→B→R" to the source driver. The source driver determines the current row's color data output order as green data → blue data → red data based on this conduction sequence, and synchronously outputs the corresponding color data as the timing controller sequentially turns on the green, blue, and red switches.

[0066] Continue to refer to Figure 3 Based on the first embodiment described above, a second embodiment of the driving method of this application is proposed.

[0067] Considering that the existing demultiplexing switching transistors all have the same aspect ratio, this easily leads to vertical stripes. To reduce these vertical stripes, we continue as follows... Figure 3 As shown, in this embodiment, the demultiplexing switch array includes at least two logic blocks, and each logic block includes at least two sets of demultiplexing switches. The control terminal of each demultiplexing switch in each group is connected to the output terminal of the control signal corresponding to the timing controller. The input terminal of each demultiplexing switch in each group is connected to the output terminal of the color data corresponding to the source driver. The output terminal of each demultiplexing switch in each group is connected to the data line of the corresponding column pixel in the display panel. A group of demultiplexing switches is used to control the on / off state of a sub-pixel within a pixel. Wherein, at least one set of two adjacent demultiplexing switches within a logic block have different width-to-length ratios, wherein the width-to-length ratio is the ratio of the channel width to the channel length of the demultiplexing switch.

[0068] It should be noted that the aforementioned logic block can refer to several relatively independent area units into which the demultiplexing switch array of the display panel is physically divided. Each logic block can cover a portion of the pixel area in the display panel, used for demultiplexing drive control of the sub-pixels falling within that area. The aforementioned "at least two logic blocks" means that the demultiplexing switch array is divided into two or more logic blocks, with different logic blocks arranged spatially adjacent to each other.

[0069] like Figure 3 As shown, in this embodiment, the demultiplexing switch array can be divided into N logic blocks, each logic block corresponding to a display area in the display panel (i.e., Figure 3 The N logic blocks in the display panel correspond to Block 1 to Block N respectively. Each display area may include several columns of pixels.

[0070] It should also be noted that the above-mentioned demultiplexing switch (i.e. Figure 3 T1 to T3 can refer to the basic switching elements that constitute the demultiplexing switch array, such as thin-film transistors (TFTs). The demultiplexing switch can have a control terminal (i.e., gate), an input terminal (i.e., source or drain), and an output terminal (i.e., drain or source). By applying a voltage signal to the control terminal, the conduction and cutoff between the input and output terminals can be controlled.

[0071] Understandably, the aforementioned "at least two sets of demultiplexing switches" can refer to each logic block containing two or more sets of demultiplexing switches, with each set controlling the on / off state of all sub-pixels contained in a pixel. For example, when a pixel contains three sub-pixels R, G, and B, a set of demultiplexing switches can contain three demultiplexing switches, respectively connected to the data lines of sub-pixels R, G, and B.

[0072] It is also understood that the connection between the control terminal and the output terminal of the control signal corresponding to the timing controller can mean that the gate of each demultiplexing switch is electrically connected to the corresponding control signal output pin of the timing controller, receiving the demultiplexing control clock signal (e.g., CKH1, CKH2, CKH3) output by the timing controller. The switches corresponding to sub-pixels of different colors within the same group are connected to different control signal output terminals. For example, the red switch (e.g., T1) in the group is connected to the CKH1 output terminal, the green switch (e.g., T2) is connected to the CKH2 output terminal, and the blue switch (e.g., T3) is connected to the CKH3 output terminal.

[0073] It should be understood that the connection between the input terminal and the output terminal of the color data corresponding to the source driver can mean that the source (or drain) of each switch in each group of demultiplexing switches is connected to the same channel output terminal of the source driver to receive the color data voltage signal output by that channel. The color data signals connected to the output terminals of different channels arrive at the corresponding group's data lines in the order of conduction.

[0074] It should also be understood that the connection between the output terminal and the data line of the corresponding column of pixels in the display panel can mean that the drain (or source) of each demultiplexing switch is connected to a corresponding column of data lines in the display panel, and this column of data lines can be further connected to the pixel electrode of the sub-pixel corresponding to that column. When the switch is turned on, the voltage signal output by the source driver is transmitted to the data line through the switch, and then written to the corresponding sub-pixel.

[0075] It is important to emphasize that the aforementioned width-to-length ratio refers to the ratio of the channel width W to the channel length L of the demultiplexing switching transistor (i.e., thin-film transistor TFT), i.e., W / L. The channel width W can be the dimension perpendicular to the current flow direction in the transistor, and the channel length L can be the dimension in the current flow direction.

[0076] It is also important to emphasize that the aspect ratio directly determines the on-resistance Ron of the switching transistor. A larger aspect ratio results in a smaller on-resistance and faster charging of the pixel capacitor; a smaller aspect ratio results in a larger on-resistance and slower charging. The statement that at least two adjacent sets of demultiplexed switching transistors within a logic block have different aspect ratios means that within the same logic block, at least two adjacent sets of switching transistors have numerically unequal channel width-to-channel length ratios, meaning that the on-resistance of these two sets of switching transistors differs.

[0077] In the specific implementation, the control signals output by the timing controller are transmitted to the control terminals of each demultiplexed switch transistor in each logic block of the demultiplexed switch array. The color data voltage signals output by the source driver are transmitted to the input terminals of each group of demultiplexed switches in each logic block. When the control terminal of a group of demultiplexed switches receives a valid level control signal output by the timing controller, all demultiplexed switches in that group are simultaneously turned on, transmitting the color data voltage signal output by the corresponding channel of the source driver from the input terminal to the output terminal, and writing it into the sub-pixel of the corresponding column in the display panel through the data line connected to the output terminal. The turn-on time of each group of demultiplexed switches in each logic block is determined by the timing of the control signals output by the timing controller, and the change of the turn-on order in each logic block is uniformly controlled by a pseudo-random turn-on sequence. However, since at least two adjacent groups of demultiplexed switches in one logic block have different aspect ratios, the difference in aspect ratios causes the on-resistance Ron_i between different groups to differ, which in turn causes the RC charging time constant of the channel in each group to differ. The difference in charging speed between different channels causes a slight dispersion in the charging completion time of each sub-pixel, thereby reducing the consistency of charging behavior of each channel across the entire screen. This further increases the dispersion of charging and discharging behavior of each channel, enhances the dispersion effect of common electrode voltage fluctuations, and effectively reduces vertical stripes visible to the human eye.

[0078] To facilitate understanding, the following explanation uses examples, but does not impose specific limitations on this embodiment. For example, assume the display panel is divided into two logic blocks, Block 1 and Block 2, each containing three sets of demultiplexed switches, corresponding to the three sub-pixels R, G, and B respectively. In Block 1, the aspect ratios of the three sets of demultiplexed switches are all the same, for example, (W / L)_1=(W / L)_2=(W / L)_3=30 / 3=10. However, in Block 2, the aspect ratios of adjacent sets of demultiplexed switches are different; for example, the aspect ratio of the first set of switches is (W / L)_1=30 / 3=10, the aspect ratio of the second set of switches is (W / L)_2=36 / 3=12, and the aspect ratio of the third set of switches is (W / L)_3=24 / 3=8. Because the aspect ratio of the second group of switches is greater than that of the first group, its on-resistance is lower and its charging speed is faster; the aspect ratio of the third group of switches is smaller than that of the first group, its on-resistance is higher and its charging speed is slower. This difference in aspect ratio creates a slight dispersion in the charging completion time of the sub-pixels corresponding to different groups within the area covered by Block 2. Combined with the random turn-on sequence control of the timing controller, this further disrupts the synchronicity of the common electrode voltage fluctuations.

[0079] Furthermore, to improve the vertical stripe elimination effect, in this embodiment, the width-to-length ratio of each group of demultiplexed switching transistors within the same logic block is set non-linearly.

[0080] It should be explained that the aforementioned nonlinear configuration may refer to the fact that the width-to-length ratio of the demultiplexing switching transistors is not arranged in a linear pattern (such as arithmetic progression or arithmetic progression) in space, but rather arranged according to a nonlinear functional relationship or a non-monotonic pattern.

[0081] In this embodiment, the width-to-length ratio difference between adjacent groups can be made non-constant through non-linear settings, or the width-to-length ratio can exhibit a non-monotonic fluctuation pattern in space, such as a stepped, sawtooth, sine wave, or cosine wave distribution. This embodiment does not impose any restrictions on this. Under the constraint of the above non-linear settings, the change in the width-to-length ratio does not have a fixed progressive amplitude, which can make the change in charging speed between channels irregular, further enhancing the discrete randomness of the charging behavior at the physical level.

[0082] Furthermore, for ease of calculation, this embodiment can be described using a sinusoidal implementation, that is, in the M groups of demultiplexing switches within the same logic block, the width-to-length ratio of the i-th group of demultiplexing switches is... ;

[0083] in, Based on the width-to-length ratio, is the spatial size perturbation coefficient, and M is the total number of demultiplexed switching transistors within the same logic block.

[0084] It should be noted that the above-mentioned reference width-to-length ratio This can refer to the initial width-to-length ratio, which serves as the basis for size variations. In traditional demultiplexed display driver architectures, the demultiplexing switching transistors for all channels across the entire screen use this fixed size. The aforementioned reference width-to-length ratio... The specific value can be set according to the actual situation, and this embodiment does not impose any restrictions on it.

[0085] It should also be noted that the aforementioned spatial size perturbation coefficient α can refer to a coefficient used to control the fluctuation range of the aspect ratio deviating from the reference value. The larger the value of α, the more significant the difference in aspect ratio between channels. The aforementioned total number of groups M can refer to the total number of groups of demultiplexed switching transistors contained in a logic block. Each group of demultiplexed switching transistors controls all the sub-pixels contained in a pixel.

[0086] It's important to note that in the formula above, *i* can be the index of the current group within the logic block, and *π* is the constant pi. This formula can be derived using a sine function. This generates spatial disturbances that vary with the channel position i, causing the width-to-length ratio of each channel to exhibit a nonlinear, sinusoidal fluctuation distribution centered on the reference width-to-length ratio, thereby breaking the linear variation relationship of charging speed between channels.

[0087] For ease of understanding, please refer to Figure 4 , Figure 4 This is a schematic diagram showing the width-to-length ratio variation of each group of demultiplexed switching transistors within the same logic block in the second embodiment of the driving method of this application. Figure 4 As shown, the horizontal axis represents the channel number i, with a value range from 1 to M, and the vertical axis represents the width-to-length ratio W / L.

[0088] Figure 4 The reference width-to-length ratio is shown in the figure. The horizontal reference line, and according to the formula The calculated aspect ratio curve. Figure 4 The image also shows the TFT channel width corresponding to each channel. , ... ... The channel width of each TFT exhibits a nonlinear fluctuation distribution as the channel number i changes, while the channel length L remains constant.

[0089] The aforementioned TFT 1 to TFT M can refer to M groups of demultiplexed switching transistors arranged sequentially along the channel arrangement direction within a logic block, with each group of switching transistors corresponding to each sub-pixel channel in a pixel. Figure 4 The channel width W of the TFT exhibits a non-linear fluctuation law similar to the width-to-length ratio as the channel number i changes. That is, the TFT channel width of the channel with a large width-to-length ratio is also relatively large, and the TFT channel width of the channel with a small width-to-length ratio is also relatively small.

[0090] In practical implementation, within each logic block of the display panel where the timing controller is applied, the width-to-length ratio of each group of demultiplexed switching transistors is set according to the aforementioned sinusoidal perturbation function relationship. Specifically, the same logic block can contain M groups of demultiplexed switching transistors, where the width-to-length ratio of the i-th group of demultiplexed switching transistors... The calculation and settings can be performed using the following formula: ;in, The reference width-to-length ratio is set in advance, α is the spatial size perturbation coefficient, M is the total number of demultiplexed switching transistors in the current logic block, i is the position index of the current group inside the logic block (values ​​are 1, 2, 3, ..., M), and π is the constant of pi.

[0091] Reference Figure 4 Within the range of channel numbers 1 to M shown on the horizontal axis, the aspect ratio of each channel revolves around the reference aspect ratio along the vertical axis. The channel exhibits a wavy, undulating pattern, with some channels having a width-to-length ratio higher than the reference value (i.e., the TFT channel width is greater than the reference width), while others have a width-to-length ratio lower than the reference value (i.e., the TFT channel width is less than the reference width). Overall, it displays a non-linear, stepped, or sawtooth distribution. Since the channel length L of each TFT remains constant, the change in the width-to-length ratio directly corresponds to the channel width. The change, i.e., the channel width of each TFT in the figure. , ... ... The same fluctuation pattern is observed with channel number i.

[0092] After setting the width-to-length ratio according to the above formula, the width-to-length ratio of each group of switches within the same logic block exhibits a non-linear fluctuation distribution in space. The difference in the width-to-length ratio between adjacent groups changes with the position index i, and its expression is Δ. = - This difference varies depending on the value of i. Since the aspect ratio determines the on-resistance Ron_i of the switching transistor, and the on-resistance directly affects the RC charging time constant of each channel, the charging completion time of each channel is physically assigned a nonlinear discrete distribution characteristic related to its spatial location. This distribution characteristic does not have a fixed spatial period, thus breaking the parasitic RC periodic distribution introduced by uniform routing and uniform size at the physical level.

[0093] For ease of understanding, the following explanations are provided through examples, but these examples do not impose specific limitations on this embodiment. (Refer to...) Figure 4 As shown, assuming that the same logic block contains M=12 groups of demultiplexed switches, the reference width-to-length ratio is... =10, spatial size perturbation coefficient α=0.3. The aspect ratio of each channel is calculated according to the above formula. The aspect ratios of groups 1 to 12 are: 10.8, 11.5, 12.1, 12.5, 12.6, 12.5, 12.1, 11.5, 10.8, 10.0, 9.3, 8.9. The corresponding TFT channel widths change proportionally under a constant channel length L. It can be seen that the aspect ratio increases between channel numbers 1 to 6 and decreases between channel numbers 6 to 12. The difference between adjacent groups varies with position, exhibiting an overall sinusoidal nonlinear distribution. The on-resistance and charging speed of each channel change non-monotonicly with position, and there is no fixed spatial period across the entire screen, which physically reduces the generation of vertical stripes.

[0094] Reference Figure 5 , Figure 5 This is a flowchart illustrating the third embodiment of the driving method of this application. Based on the above embodiments, a third embodiment of the driving method of this application is proposed. Figure 5 As shown in this embodiment, considering that different aspect ratios result in different on-resistances, which in turn lead to different RC charging time constants for different physical channels, if the same width control pulse is used for all channels, it will result in uneven brightness across the screen and vertical stripes will still exist.

[0095] Therefore, in order to further reduce vertical stripes, such as Figure 5 As shown, in this embodiment, the step of sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction sequence includes: Step S22: Generate corresponding initial signals sequentially according to the conduction sequence, and obtain the fine-tuning duration corresponding to each initial signal according to the second preset mapping relationship; Step S23: Perform phase fine-tuning on the corresponding initial signal according to the fine-tuning duration to obtain the corresponding control signal; The step of transmitting the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence includes: Step S32: Transmit the conduction sequence and each of the fine-tuning durations to the source driver, so that the source driver determines the output timing and output order of the color data of each sub-pixel according to the conduction sequence and the fine-tuning duration.

[0096] It should be noted that the aforementioned initial signal may refer to the original demultiplexed control clock signal generated by the clock generation circuit inside the timing controller. This initial signal has not yet undergone phase adjustment and has a standard pulse width and a standard start time position.

[0097] It should also be noted that the aforementioned second preset mapping relationship can refer to a correspondence table pre-stored in the timing controller storage unit, which records each physical channel index i and its corresponding inherent charging delay compensation amount. The mapping relationship between them. The aforementioned second preset mapping relationship can be obtained by measurement after the display device design is completed. Of course, it can also be obtained by other means, and this embodiment does not limit it.

[0098] It is understandable that the aforementioned fine-tuning duration can refer to the amount of time required for phase adjustment of the initial signal of a particular physical channel, i.e., the aforementioned... The unit can be nanoseconds (ns). The aforementioned phase fine-tuning can refer to the operation of shifting the rising edge (turn-on edge) or falling edge (turn-off edge) of the initial signal on the time axis. For example, shifting the turn-on edge of the initial signal forward by a certain amount of time, or shifting the turn-off edge of the initial signal backward by a certain amount of time, so that the pulse width of the final output control signal changes relative to the initial signal.

[0099] It is also understood that the above output timing can refer to the order and specific time position of each data output action on the time axis when the source driver outputs each color data.

[0100] In its implementation, after determining the conduction order of the current row of pixels, the timing controller generates the corresponding initial signals sequentially according to the order of the sub-pixels defined by that conduction order. For the i-th physical channel that needs to be conducted in the conduction order, after generating the initial signal corresponding to that channel, the timing controller can use the index i of that physical channel as the lookup address to access the second preset mapping relationship pre-stored in the timing controller's internal storage register array, and obtain the fine-tuning duration uniquely corresponding to the physical channel index i from the second preset mapping relationship. .

[0101] Subsequently, the clock modulation unit inside the timing controller can adjust the time according to the acquired fine-tuning duration. The clock modulation unit performs phase fine-tuning on the initial signal corresponding to the current physical channel to generate the final control signal. Specifically, the clock modulation unit can shift the on-edge of the initial signal forward. Nanoseconds advance the control signal relative to the initial signal. The effective level is reached in nanoseconds; or the off edge of the initial signal is delayed. Nanoseconds widen the effective pulse width of the control signal relative to the initial signal. Nanosecond; or both of the above operations can be performed simultaneously. The control signal obtained after phase fine-tuning is the final control signal output to the corresponding switch control terminal of the demultiplexing switch array.

[0102] At the same time, the timing controller can adjust the conduction sequence and the fine-tuning duration of each physical channel. The data is transmitted to the source driver. Upon receiving the conduction sequence and fine-tuning duration, the source driver determines the output order of the color data for each sub-pixel based on the conduction sequence, and simultaneously determines the output timing of the color data for each sub-pixel based on the fine-tuning duration corresponding to each physical channel. Specifically, the source driver determines the output order of each color data based on the received conduction sequence, and determines the specific output position of each color data on the time axis based on the fine-tuning duration corresponding to each physical channel—that is, which color data needs to be output earlier, which color data needs to be output later, and the specific amount of time for earlier or later output. In this way, the distribution of the color data output by the source driver on the time axis is synchronized with the distribution of the effective pulses of each control signal in the demultiplexing switch array on the time axis, ensuring that at the moment each control signal turns on the corresponding switch, the voltage signal transmitted on the data line is exactly the corresponding color data.

[0103] For ease of understanding, please refer to Figure 6 To explain, Figure 6 This is a schematic diagram of phase fine-tuning in the third embodiment of the driving method of this application. Figure 6 As shown, Figure 6 The image shows a comparison of the timing waveforms of two adjacent rows (Line n and Line n+1). Each row shows the waveforms of the three demultiplexing control clock signals CKH1, CKH2, and CKH3, as well as the positions of the corresponding color data R, G, and B on the time axis.

[0104] Reference Figure 6 In Line n, for example, if the conduction sequence is determined to be CKH1→CKH2→CKH3, that is, conducting sequentially in the order of R, G, B, where the turn-on edge of CKH2 is marked with " "Early activation" means that the initial signal of CKH2 is adjusted for a duration after being queried according to the second preset mapping table. This means that the control signal corresponding to the green channel was subjected to phase fine-tuning, and its activation edge was shifted forward relative to the standard timing position. The amount of time allowed for the effective conduction time of the channel to be extended.

[0105] Similarly, in Line n+1, the conduction sequence changes to CKH1→CKH3→CKH2 (corresponding to the color sequence R→B→G), meaning the conduction sequence has been randomly rotated. The initial signal of CKH2, after being looked up according to the second preset mapping table, yields a fine-tuning duration of... That is, regardless of where the green channel (corresponding to CKH2) is in the conduction sequence, the phase fine-tuning of its control signal is always applied.

[0106] Using the above method, it is clear that the slow channel, regardless of its random rotation to any position in the conduction sequence across different rows, will receive the same additional charging time compensation, thus ensuring that the sub-pixel corresponding to that channel is charged to the target voltage in every row. This allows the time synchronization disruption effect brought about by the pseudo-random conduction sequence to coexist with the precise compensation for physical layer differences, eliminating both the synchronization impact of the common electrode voltage (eliminating flicker) and ensuring the consistency of charging amount across all channels on the screen (eliminating stripes).

[0107] Furthermore, this application also proposes a display device, which includes: a source driver, a demultiplexing switch array, a display panel with a plurality of rows of pixels, and a timing controller as described above.

[0108] Furthermore, considering that in existing demultiplexed display driver architectures, the control signal lines between adjacent logic blocks are arranged in a completely consistent manner on the metal layer (e.g., using a fixed method where the M2 layer spans the M3 layer throughout the entire screen), this highly consistent physical arrangement can cause the parasitic capacitance of each channel to be periodically distributed throughout the entire screen. This results in the RC delay of each channel having a fixed repetition period in space, thereby generating spatial periodic voltage disturbances during polarity reversal, forming vertical stripes visible to the human eye. Therefore, in order to further reduce vertical stripes, refer to... Figure 7 , Figure 7 This is a schematic diagram of the structure of the display panel in the first embodiment of the display device of this application.

[0109] like Figure 7 As shown, in this embodiment, the demultiplexing switch array includes at least two logic blocks, and each logic block includes at least two sets of demultiplexing switches. The display panel includes: a liquid crystal layer and at least two metal layers. The liquid crystal layer includes at least two display areas. Each display area has a plurality of rows of pixels. Each display area corresponds to each logic block. The demultiplexing switch in each logic block is used to control the on / off state of the pixels in the corresponding display area. The signal lines of control signals for at least two adjacent display areas are located on different metal layers.

[0110] It should be noted that the aforementioned liquid crystal layer can refer to the liquid crystal molecule layer in a liquid crystal display panel used to control luminous flux. The liquid crystal molecules in the liquid crystal layer are deflected under the influence of an electric field, changing the polarization state of the light passing through the layer, and working in conjunction with a polarizer to achieve grayscale display.

[0111] It should also be noted that the aforementioned metal layer can refer to the metal wiring layer on the display panel array substrate used for transmitting electrical signals, such as the source metal layer, the gate metal layer, and additional signal wiring layers. In the multilayer metal wiring process, this embodiment can use different levels of metal layers such as the first metal layer (M1), the second metal layer (M2), and the third metal layer (M3). The different metal layers are stacked sequentially and can be insulated from each other by an interlayer dielectric (ILD). Interconnection is achieved at locations where electrical connection is required through vias penetrating the interlayer dielectric.

[0112] It is understood that the aforementioned display area can refer to the physical display area covered by a corresponding logic block in the liquid crystal layer of the display panel. The entire display area of ​​the display panel can be divided into at least two display areas along the horizontal direction (i.e., Figure 3 As shown in Blocks 1 to N, each display area corresponds to a logic block. The demultiplexed switching transistors within the logic block control the on / off state of each sub-pixel of the pixel within that display area. The signal lines of different display areas are routed on different metal layers, forming a spatially heterogeneous arrangement.

[0113] It is also understood that the signal lines of the aforementioned control signals can refer to metal wires that transmit demultiplexed control clock signals (e.g., CKH1, CKH2, CKH3). During the extension of these signal lines between different display areas, cross-layer routing of metal layers is possible at the boundaries of adjacent display areas. That is, being located on different metal layers can be understood as meaning that the signal lines of the same control signal in two adjacent display areas use different primary metal layers when extending their routing.

[0114] For example, refer to Figure 8 , Figure 8 This is a schematic diagram of the cross-layer wiring in the display panel of the first embodiment of the display device of this application, as shown below. Figure 8 As shown, this embodiment uses two layers, M2 and M3, for illustration, but this is not a limitation. M2 can refer to the second metal layer on the display panel array substrate, and M3 can refer to the third metal layer on the display panel array substrate. In multilayer metal wiring technology, different metal layers are insulated and isolated from each other by interlayer insulating layers. Different metal layers are at different distances from the reference plane, so the parasitic capacitance to ground carried by the same trace on different metal layers is different.

[0115] Figure 8 The diagram shows the signal line routing of two adjacent logic blocks, Block 1 and Block 2, and their corresponding display areas. Figure 8Within the display area corresponding to Block 1, the signal lines of the three control signals are routed on different metal layers. Some signal lines are routed on layer M2, while others are routed on layer M3 (i.e., M2 spans across M3). Within the adjacent display area corresponding to Block 2, the metal layers used for the signal lines of the same group of control signals are completely opposite to those in Block 1. That is, signal lines routed on layer M2 in Block 1 are reversed to use layer M3 in Block 2, and vice versa (i.e., M3 spans across M2).

[0116] In the specific implementation, the aforementioned demultiplexing switch array is divided into at least two logic blocks, each logic block corresponding to a display area in the display panel. Control signals are derived from the timing controller and extend horizontally to the display area corresponding to each logic block. Between adjacent logic blocks, the signal lines of the control signals are arranged on different metal layers, and the metal layers used for the same set of control signals within adjacent logic blocks are mirror images of each other.

[0117] By mirroring and alternating the metal layers of control signal lines between adjacent logic blocks and by setting the crossing direction at the boundaries, the parasitic capacitance of each signal line across the entire screen no longer exhibits a periodic repetition in space. Because the distances of layers M2 and M3 relative to the reference plane are different, the parasitic capacitance to ground of the same signal line differs when it is located on different metal layers within different logic blocks. Taking a CKH1 signal line as an example, the parasitic capacitance value when it is deployed on layer M2 within Block 1 is not equal to the parasitic capacitance value when it is deployed on layer M3 within Block 2. This alteration of the periodic distribution of parasitic capacitance across the entire screen means that the RC delay of each channel no longer has a fixed repetition period in space, thereby further reducing the generation of vertical stripes at the physical level.

[0118] For ease of understanding, the following explanations are provided through examples, but these examples do not impose specific limitations on this embodiment. (Refer to...) Figure 3As shown, assume that within Block 1, the CKH1 signal line is routed on layer M2, the CKH2 signal line on layer M3, and the CKH3 signal line on layer M2. At the boundary between Block 1 and Block 2, the CKH1 signal line crosses from layer M2 to layer M3, i.e., "M2 across M3". Upon entering Block 2, the CKH1 signal line reverses and is routed on layer M3, the CKH2 signal line reverses and is routed on layer M2, and the CKH3 signal line reverses and is routed on layer M3. At the boundary between Block 2 and Block 3, the CKH1 signal line routed on layer M3 crosses from layer M3 to layer M2, i.e., "M3 across M2". Assuming the parasitic capacitance to ground of the M2 layer trace is approximately 0.8pF and that of the M3 layer trace is approximately 1.2pF, then the parasitic capacitance of the CKH1 signal line is 0.8pF in Block 1, jumps to 1.2pF in Block 2, and then jumps back to 0.8pF in Block 3. This alternating jump of parasitic capacitance between adjacent logic blocks means that the RC delay of each channel across the entire screen does not have a fixed spatial period, thereby further reducing the generation of vertical stripes at the physical level.

[0119] Furthermore, considering that in the existing demultiplexed display driver architecture, the number of vias at each intersection node is set in a consistent manner (e.g., a fixed 4 vias across the entire screen), this uniform setting causes the contact resistance of each channel to exhibit periodic repetition across the entire screen, resulting in a fixed spatial periodic distribution of the total resistance of each channel, which also easily generates vertical stripes. Therefore, in this embodiment, the following... Figure 7 As shown, the display panel further includes: an interlayer insulating layer; An interlayer insulating layer is provided between two adjacent metal layers, and a via region is provided at the intersection node of the signal lines of different metal layers in adjacent display areas, and a via is provided in the via region to penetrate the interlayer insulating layer; The number of vias in adjacent via regions is different.

[0120] It should be noted that the aforementioned interlayer insulation layer can refer to an insulating dielectric layer disposed between adjacent metal layers, such as an interlayer dielectric layer. Interlayer insulation layers can be used to isolate signal lines between different metal layers, preventing electrical short circuits between them.

[0121] It should also be noted that the aforementioned intersection node can refer to the location where control signal lines laid on different metal layers cross each other in space in the boundary area of ​​different display areas. At this location, a signal line jumps from one metal layer to another metal layer through a via to cross another trace.

[0122] Understandably, the aforementioned via region can refer to the physical area at the crossover node used to house vias. Within this region, the interlayer insulation is partially removed, and a conductive material (such as tungsten or copper) is filled to form vias, enabling electrical interconnection between different metal layers. The aforementioned number of vias can refer to the total number of conductive vias housed within a via region. A higher number of vias results in a lower total contact resistance at the crossover node; conversely, a lower number of vias results in a higher contact resistance.

[0123] In its implementation, the aforementioned display panel incorporates an interlayer insulating layer between adjacent metal layers, which vertically separates the signal lines from different metal layers. At signal line intersections where adjacent display areas meet, control signal lines need to jump from one metal layer to another to cross other signal lines. At these intersections, the interlayer insulating layer is selectively etched away, and conductive material is filled at the removal location to form vias, thereby achieving electrical connection between the upper and lower metal layers.

[0124] It is important to emphasize that the number of vias placed at different intersection nodes along the channel arrangement direction within the same logic block is spatially non-uniformly distributed. Specifically, this could refer to the number of vias placed at the signal line intersection node of the i-th physical channel. The number of vias placed at the signal line intersection node with the (i+1)th physical channel The numbers are not equal, and the number of vias between each channel is also different. It can be arranged non-periodicly in space. The number of vias in adjacent via regions is different. For example, different integer numbers of vias can be set sequentially along the channel arrangement direction. The specific number of vias can be set according to the actual situation. This embodiment does not limit this.

[0125] Because the contact resistance of vias has a definite value (e.g., the contact resistance of each via is approximately 0.5Ω to 2Ω), the total contact resistance at the intersection (e.g., denoted as...) R_via_i is equal to the contact resistance of a single via (e.g., denoted as R_via_i). Multiply by the number of vias at that node. ,Right now = × When the number of vias varies between different crossover nodes, the total resistance of the signal transmission path for each channel (e.g., denoted as...) ) = + This exhibits inconsistency related to the number of vias. Let be the resistance of the metal trace in the i-th channel. The microscopic difference in the total resistance causes a picosecond to nanosecond time discrepancy in the charging leading edge of the pixel capacitor, which is much smaller than the main charging cycle.

[0126] Therefore, through the non-uniform distribution of the number of vias, the charging and discharging transient response of each channel is introduced into non-correlated discretization at the physical level, and the spatial periodic distribution of the full-screen parasitic resistance is broken, thereby further reducing the generation of vertical stripes at the physical level.

[0127] For ease of understanding, please refer to Figure 9 , Figure 9 This is a schematic diagram of the via regions in the first embodiment of the display device of this application. For example... Figure 9 As shown, the number of vias at different intersection nodes is not equal, meaning the number of vias is spatially non-uniformly distributed. For example, different integer numbers of vias are set sequentially along the channel arrangement direction. Figure 9 The image shows 2, 5, 3, 6, and 8 vias from left to right. A black dot represents a via, and a rectangle represents a via area.

[0128] Furthermore, considering that the existing architecture does not have any parasitic capacitance compensation structure on the side of the straight signal line, the parasitic capacitance of each channel depends entirely on the geometry of the signal trace itself and the position of the metal layer. It is impossible to independently adjust the capacitance deviation caused by the asymmetrical trace and differential via layout, which results in the total parasitic capacitance of each channel exhibiting a periodic distribution consistent with the trace layout across the entire screen, and also produces vertical stripes.

[0129] Therefore, continue as follows Figure 9 As shown, in this embodiment, the display panel further includes a parasitic balancing unit; The parasitic balancing unit is disposed on the side of at least one of the straight signal lines in the display area, and is spaced apart along the extension direction of the straight signal lines. The parasitic balancing unit is electrically connected to a constant reference potential and is used to form a parasitic capacitance with the adjacent signal lines.

[0130] It should be noted that the aforementioned parasitic balance unit (i.e. Figure 9 The term "dummy pattern" can refer to an auxiliary conductive pattern placed on the side of a signal trace. This pattern can be used to introduce additional parasitic capacitance to compensate for the deviation in the average capacitance of each trace caused by asymmetrical traces, differentiated via layouts, and mirrored metal layer arrangements.

[0131] In this embodiment, the parasitic balancing unit can be a metal block or metal strip with a certain projected area and geometric shape, such as a rectangular metal block, an L-shaped metal strip, or a comb-shaped metal pattern. This embodiment does not limit this.

[0132] It should also be noted that the aforementioned straight signal lines can refer to signal traces that extend horizontally on the same metal layer and do not cross or change layers with other signal lines. Straight signal lines do not cross metal layers with other signal lines, and there are no metal layer jumps at the intersection nodes.

[0133] It is understood that the aforementioned constant reference potential can refer to a fixed potential node in the display panel where the potential remains unchanged, such as the common electrode voltage VCOM or the ground potential GND. In this embodiment, the parasitic balancing unit can be electrically connected to the constant reference potential, so that the parasitic balancing unit is always kept at a stable reference potential. Thus, the parasitic balancing unit acts as one plate of a capacitor, and the nearby signal line acts as the other plate of the capacitor. The two are capacitively coupled through the interlayer insulation layer or air gap, thereby adding an additional parasitic capacitance value to the signal line.

[0134] It should be emphasized that the specific location of the parasitic balance unit can be set according to the actual situation, and this embodiment does not impose any restrictions on it.

[0135] In a specific implementation, parasitic balancing units are also provided on the array substrate of the aforementioned display panel. These parasitic balancing units can be located to the side of a straight signal line in at least one display area, i.e., positioned beside the edge of a straight signal trace where no metal layer crossover occurs. The parasitic balancing units can be arranged at intervals along the extension direction of the straight signal line; that is, an independent parasitic balancing unit can be placed at regular intervals along the extension path of the same signal line, or they can be continuously arranged along the extension direction. Furthermore, the parasitic balancing units can be electrically connected to a constant reference potential (e.g., common electrode voltage VCOM or ground potential GND) so that the parasitic balancing units remain at a fixed reference potential during operation.

[0136] Because the parasitic balancing unit and the nearby signal line are capacitively coupled through the interlayer insulation layer, a parasitic capacitance is formed. The magnitude of this parasitic capacitance depends on the projected area of ​​the parasitic balancing unit and the coupling distance between the parasitic balancing unit and the signal line. Therefore, the parasitic balancing unit compensates for the total parasitic capacitance of the channel.

[0137] Within the same logic block, the projected area and coupling spacing of the parasitic balancing cells corresponding to each channel are different, meaning that the dummy pattern parameters of each channel are spatially heterogeneous. By selecting different parasitic balancing cell parameters, the total parasitic capacitance of each channel can be adjusted independently to ensure that the average total parasitic capacitance of all channels within the same logic block is approximately equal, thereby avoiding large-area color shifts caused by asymmetrical physical layer traces and differentiated via layouts. At the same time, the different parasitic balancing cell parameters of each channel make the AC transient impedance characteristics of each channel independent of each other, further eliminating the generation of vertical stripes.

[0138] Other embodiments or specific implementations of the display device described in this application can be found in the above-described method embodiments, and will not be repeated here.

[0139] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or system that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or system. Unless otherwise specified, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or system that includes that element.

[0140] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0141] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as a read-only memory image (ROM) / random access memory (RAM), magnetic disk, optical disk), and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods described in the various embodiments of this application.

[0142] The above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A driving method, characterized in that, The method is applied to a timing controller in a display device, the display device further including a source driver, a demultiplexing switch array, and a display panel having a plurality of rows of pixels, the method comprising: At the start of the scanning cycle of the current row of pixels, the conduction order of the sub-pixels of each pixel in the current row of pixels during the scanning cycle is randomly generated. According to the conduction sequence, the corresponding control signals are sequentially output to the demultiplexing switch array, so that the demultiplexing switch array sequentially controls the conduction of the corresponding sub-pixels according to the corresponding control signals; The conduction sequence is transmitted to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence, and outputs the corresponding color data to the corresponding sub-pixel for charging and display according to the output order. The output order and the conduction sequence correspond one-to-one in the time domain. The step of sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction sequence includes: The corresponding initial signals are generated sequentially according to the conduction sequence, and the fine-tuning duration corresponding to each initial signal is obtained according to the second preset mapping relationship. The corresponding initial signal is phase-adjusted according to the fine-tuning duration to obtain the corresponding control signal; The step of transmitting the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence includes: The conduction sequence and each of the fine-tuning durations are transmitted to the source driver so that the source driver determines the output timing and output order of the color data of each sub-pixel according to the conduction sequence and the fine-tuning duration.

2. The method as described in claim 1, characterized in that, The step of randomly generating the conduction order of sub-pixels of each pixel within the current row during the scan cycle includes: A first-order pseudo-random vector is randomly generated for each pixel in the current row of pixels, and the conduction sequence corresponding to the first-order pseudo-random vector is determined according to a first preset mapping relationship. The conduction sequence is used to characterize the conduction order of the sub-pixels of each pixel in the current row of pixels in the scanning period. The step of sequentially outputting corresponding control signals to the demultiplexing switch array according to the conduction sequence includes: According to the conduction sequence, the corresponding control signals are sequentially output to the demultiplexing switch array; The step of transmitting the conduction sequence to the source driver so that the source driver determines the color data output order of each sub-pixel according to the conduction sequence includes: The conduction sequence is transmitted to the source driver so that the source driver determines the color data output order of each sub-pixel based on the conduction sequence.

3. The method as described in claim 1, characterized in that, The demultiplexing switch array includes at least two logic blocks, and each logic block includes at least two sets of demultiplexing switches. The control terminal of each demultiplexing switch in each group is connected to the output terminal of the control signal corresponding to the timing controller. The input terminal of each demultiplexing switch in each group is connected to the output terminal of the color data corresponding to the source driver. The output terminal of each demultiplexing switch in each group is connected to the data line of the corresponding column pixel in the display panel. A group of demultiplexing switches is used to control the on / off state of a sub-pixel within a pixel. Wherein, at least one set of two adjacent demultiplexing switches within a logic block have different width-to-length ratios, wherein the width-to-length ratio is the ratio of the channel width to the channel length of the demultiplexing switch.

4. The method as described in claim 3, characterized in that, Within the same logic block, the width-to-length ratio of each group of demultiplexed switches is set non-linearly.

5. The method as described in claim 4, characterized in that, Within the same logic block, among the M groups of demultiplexing switches, the width-to-length ratio of the i-th group of demultiplexing switches is... ; in, Based on the width-to-length ratio, is the spatial size perturbation coefficient, and M is the total number of groups of demultiplexed switches within the same logic block.

6. A display device, characterized in that, The display device includes: a source driver, a demultiplexing switch array, a timing controller, and a display panel with several rows of pixels; The timing controller includes: a memory, a processor, and a computer program stored in the memory and executable on the processor, the computer program being configured to implement the steps of the driving method as described in any one of claims 1 to 5.

7. The display device as claimed in claim 6, characterized in that, The demultiplexing switch array includes at least two logic blocks, and each logic block includes at least two sets of demultiplexing switches. The display panel includes: a liquid crystal layer and at least two metal layers. The liquid crystal layer includes at least two display areas. Each display area has a plurality of rows of pixels. Each display area corresponds to each logic block. The demultiplexing switch in each logic block is used to control the on / off state of the pixels in the corresponding display area. The signal lines of control signals for at least two adjacent display areas are located on different metal layers.

8. The display device as claimed in claim 7, characterized in that, The display panel further includes: an interlayer insulating layer; An interlayer insulating layer is provided between two adjacent metal layers, and a via region is provided at the intersection node of the signal lines of different metal layers in adjacent display areas, and a via is provided in the via region to penetrate the interlayer insulating layer; The number of vias in adjacent via regions is different.

9. The display device as claimed in any one of claims 6 to 8, characterized in that, The display panel further includes: a parasitic balancing unit; The parasitic balancing unit is disposed on the side of at least one of the straight signal lines in the display area, and is spaced apart along the extension direction of the straight signal lines. The parasitic balancing unit is electrically connected to a constant reference potential and is used to form a parasitic capacitance with the adjacent signal lines.

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