A gate driving circuit and a display panel

Abstract

The application belongs to the technical field of display driving, and particularly relates to a gate driving circuit and a display panel. The nth stage gate driving unit comprises: a pull-up module configured to charge a pull-up node of a current stage; a stage transmission output module configured to output a stage transmission signal; a first local brush control module configured to control electrical connection between the pull-up node of the current stage and a driving control node of the current stage under the action of a voltage of a pull-up node of the nth-j stage; a second local brush control module configured to: if the nth-d stage is a non-refresh row and the current stage is a refresh row, control electrical connection between a first local brush control node of the current stage and the driving control node of the current stage; if the current stage is a refresh row and the n+d stage is a non-refresh row, control disconnection between the first local brush control node of the current stage and the driving control node of the current stage; and a driving output module configured to output a gate driving signal. The application can avoid display abnormalities in a refresh edge area.

Description

Technical Field

[0001] This application belongs to the field of display driver technology, specifically relating to a gate driving circuit and a display panel. Background Technology

[0002] In related technologies, for display panel driving circuits that include multiple CK clock signals, partial refresh of the display panel is achieved by controlling whether the gate driving signal is output. When the refresh line and the non-refresh line switch between each other, the clock signals between adjacent gate driving lines may overlap, which will cause the non-refresh line to output the gate driving signal incorrectly, resulting in abnormal display of the edge area of ​​the partial refresh.

[0003] Therefore, how to prevent abnormal edge display in the local refresh area of ​​the display panel is an urgent problem to be solved. Summary of the Invention

[0004] This application provides a gate driving circuit and a display panel, which solves the problem of abnormal edge display in the local refresh area of ​​the display panel.

[0005] In a first aspect, this application provides a gate driving circuit, comprising N cascaded gate driving units. The nth gate driving unit includes: a pull-up module connected to the pull-up node of the current stage, configured to charge the pull-up node of the current stage in response to the output signal of the nth gate driving unit; a stage transmission output module connected to the pull-up node of the current stage and the clock signal line of the current stage, configured to output a stage transmission signal under the action of the voltage of the pull-up node of the current stage and the clock signal line of the current stage; and a first local refresh control module connected to the pull-up node of the current stage, the first local refresh control node of the current stage, and the pull-up node of the njth stage, configured to control the pull-up node of the current stage to charge the pull-up node of the current stage in response to the voltage of the pull-up node of the njth stage in local refresh mode. Electrical connections are made between the drive control nodes; wherein j is greater than i; the second local refresh control module is connected to the first local refresh control node and the drive control node of the current level, respectively, and is configured to: in the local refresh mode, if the nd level is a non-refresh line and the current level is a refresh line, control the first local refresh control node of the current level to be electrically connected to the drive control node of the current level; if the current level is a refresh line and the n+d level is a non-refresh line, control the first local refresh control node of the current level to be disconnected from the drive control node of the current level; wherein d is less than i; the drive output module is connected to the clock signal line of the drive control node and the current level, respectively, and is configured to: output a gate drive signal under the action of the voltage on the drive control node of the current level and the clock signal of the current level.

[0006] Optionally, the second refresh control module includes: a first control submodule connected to the second refresh control node of the current level, configured to: generate a first switch control signal at the second refresh control node of the current level if the current level is a refresh row and the (n+d)th level is a non-refresh row; a second control submodule connected to the second refresh control node of the current level, configured to: generate a second switch control signal at the second refresh control node of the current level if the (nd)th level is a non-refresh row and the current level is a refresh row; and a switch control submodule connected to the first refresh control node, the second refresh control node, and the drive control node of the current level, respectively, configured to: disconnect the connection between the first refresh control node and the drive control node of the current level according to the first switch control signal; and electrically connect the first refresh control node and the drive control node of the current level according to the second switch control signal and the voltage on the first refresh control node of the current level.

[0007] Optionally, the first local refresh control module includes: a first transistor; the control terminal of the first transistor is connected to the pull-up node of the njth stage, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the first local refresh control node of the current stage.

[0008] Optionally, the first control submodule includes: a second transistor; the control terminal of the second transistor is connected to the first brush control terminal, the first terminal of the second transistor is connected to the pull-up node of the njth stage, and the second terminal of the second transistor is connected to the second brush control node of the current stage.

[0009] Optionally, the second control submodule includes: a third transistor; the control terminal of the third transistor is connected to the second brush control terminal, the first terminal of the third transistor is connected to the second brush control node of the current stage, and the second terminal of the third transistor is connected to a low-level terminal.

[0010] Optionally, the switch control submodule includes: a fourth transistor and a fifth transistor; the control terminal of the fourth transistor is connected to the second brush control node of the current stage, the first terminal of the fourth transistor and the second terminal of the fifth transistor are connected to the drive control node of the current stage, and the second terminal of the fourth transistor is connected to a low-level terminal; the control terminal of the fifth transistor and the first terminal of the fifth transistor are connected to the first brush control node of the current stage.

[0011] Optionally, the first local refresh control module includes: a first transistor and a sixth transistor; the control terminal of the first transistor is connected to the second terminal of the sixth transistor, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the first local refresh control node of the current stage; the control terminal of the sixth transistor is connected to the first terminal of the sixth transistor and the pull-up node of the njth stage.

[0012] Optionally, the switch control submodule includes: a fourth transistor, a fifth transistor, a seventh transistor, and an eighth transistor; the control terminal of the fourth transistor and the control terminal of the seventh transistor are connected to the second brush control node of the current stage; the first terminal of the fourth transistor is connected to the second terminal of the fifth transistor and the control terminal of the eighth transistor, respectively; the second terminal of the fourth transistor and the second terminal of the seventh transistor are connected to a low-level terminal; the control terminal of the fifth transistor, the first terminal of the fifth transistor, and the first terminal of the eighth transistor are connected to the first brush control node; the first terminal of the seventh transistor and the second terminal of the eighth transistor are connected to the drive control node.

[0013] Optionally, the stage output module includes: a ninth transistor and a first capacitor; the control terminal of the ninth transistor and the first terminal of the first capacitor are connected to the pull-up node of the current stage, the first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor is connected to the second terminal of the first capacitor.

[0014] Secondly, this application provides a display panel including a display area and a non-display area, the display area including a plurality of scan lines, the non-display area including a gate driving circuit as described in any one of the first aspects, and the driving output module of the gate driving circuit being connected to at least one of the scan lines.

[0015] The technical solution provided in this application has at least the following beneficial effects:

[0016] In this application, the first brush control module is connected to the pull-up node of the current stage and the brush control node of the current stage. Under the voltage of the pull-up node of the nj stage, the pull-up node of the current stage is controlled to be connected to the first brush control node of the current stage. The second brush control module is connected to the drive control node of the current stage. If the nd stage is not a refresh row and the current stage is a refresh row, the first brush control node of the current stage is electrically connected to the drive control node of the current stage. When the current stage outputs a gate drive signal, the pull-up node of the nd stage and the nd... If the first refresh control node of the current stage is disconnected and there is no precharge voltage on the drive control node of the n+d stage, the n+d stage will not output a gate drive signal, thus avoiding display abnormalities in the n+d stage. If the current stage is a refresh row and the n+d stage is a non-refresh row, the connection between the first refresh control node of the current stage and the drive control node of the current stage will be disconnected, and the drive control node of the n+d stage will not be precharged. When the current stage outputs a gate drive signal, the n+d stage will not output a gate drive signal, thus avoiding display abnormalities in the n+d stage. Attached Figure Description

[0017] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0018] Figure 1 A schematic diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0019] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown.

[0020] Figure 3 A timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0021] Figure 4 Another timing diagram of a gate drive circuit provided in an embodiment of this application is shown.

[0022] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown.

[0023] Explanation of reference numerals in the attached figures: 100 Gate drive unit; 110 Pull-up module; 120 Stage output module; 130 First brush control module; 140 Second brush control module; 141 First control submodule; 142 Second control submodule; 143 Switch control submodule; 150 Drive output module; 160 Noise reduction module; 170 Pull-down module.

[0024] T1, first transistor; T2, second transistor; T3, third transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; T11, eleventh transistor; T12, twelfth transistor; T13, thirteenth transistor; T14, fourteenth transistor; T15, fifteenth transistor; C1, first capacitor; C2, second capacitor; VSS, low-level terminal; SW1, first brush control terminal; SW2, second brush control terminal. Detailed Implementation

[0025] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0026] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0027] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0028] Figure 1 A schematic diagram of a gate driving circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 1As shown, the gate driving circuit includes N cascaded gate driving units 100. The nth stage gate driving unit 100 includes: a pull-up module 110, a stage output module 120, a first brush control module 130, a second brush control module 140, and a drive output module 150. The pull-up module 110 is connected to the pull-up node Qn of the current stage. The stage output module 120 is connected to the pull-up node Qn of the current stage and the clock signal line CKm of the current stage. The first brush control module 130 is connected to the pull-up node Qn of the current stage, the first brush control node An of the current stage, and the pull-up node Qn-j of the njth stage. The second brush control module 140 is connected to the first brush control node An of the current stage and the drive control node Qsn of the current stage.

[0029] In the diagram, CKm-1, CKm, and CKm+1 represent clock signal lines, with overlap between clock signals of adjacent stages. Fn-i represents the output terminal of the stage output module of stage ni, Fn represents the output terminal of the stage output module of the current stage, and Gn represents the output terminal of the driver output module of the current stage. Qn represents the pull-up node of the current stage, Qn-j represents the pull-up node of stage nj, An represents the first brush control node of the current stage, and Qsn represents the driver control node of the current stage.

[0030] In some embodiments, the pull-up module 110 is configured to charge the pull-up node Qn of the current stage in response to the output signal of the nth stage gate drive unit 100.

[0031] For example, the output signal of the ni-th stage gate drive unit 100 can be a stage transmission signal. After receiving the ni-th stage transmission signal, the pull-up module 110 charges the pull-up node to generate a voltage on the pull-up node Qn of the current stage.

[0032] In some embodiments, the stage output module 120 is configured to output a stage transmission signal under the action of the voltage of the pull-up node Qn of the current stage and the clock signal of the current stage.

[0033] For example, the stage transmission output module 120 is connected to the pull-up node Qn of the current stage. When a voltage is generated on the pull-up node Qn of the current stage, and when the clock signal of the current stage arrives, the stage transmission output module 120 will output the stage transmission signal of the current stage. The stage transmission signal acts on the gate driving unit 100 adjacent to the current stage, such as the (n+i)th stage or the njth stage, etc.; i can be 2 and j can be 3.

[0034] In some embodiments, the first refresh control module 130 is configured to: in partial refresh mode, under the voltage action of the pull-up node of the njth level, control the current level pull-up node Qn to be electrically connected with the current level first refresh control node An; where j is greater than i.

[0035] For example, when the first brush module receives the drive voltage of the (n+i)th stage pull-up node, it will be turned on, thereby realizing the electrical connection between the pull-up node Qn of the current stage and the drive control node Qsn of the current stage, so as to transmit the voltage on the pull-up node Qn of the current stage to the first brush control node An of the current stage.

[0036] In some embodiments, the second refresh control module 140 is configured to: in partial refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the first refresh control node An of the current level to be electrically connected with the driver control node Qsn of the current level; if the current level is a refresh line and the (n+d)-th level is a non-refresh line, control the first refresh control node An of the current level to be disconnected from the driver control node Qsn of the current level; where d is less than i.

[0037] For example, d can be 1. If the nd-th stage is a non-refreshing row and the current stage is a refreshing row, it means that the nd-th stage does not output a gate drive signal to refresh the pixel. The current stage needs to output a gate drive signal to refresh the pixel. When the first refresh control node An of the current stage is connected to the drive control node Qsn of the current stage, the precharge voltage of the pull-up node Qn of the current stage will be transmitted to the drive control node of the current stage. When the clock signal of the current stage arrives, the gate drive signal of the current stage will be output to refresh the pixel. For the nd-th stage, the voltage of the pull-up node of the ndj-th stage has been pulled down to a low potential. The first refresh control module 130 will control the pull-up node of the nd-th stage to be disconnected from the first refresh control node of the nd-th stage. Since the nd-th stage is a non-refreshing row and the drive control node of the nd-th stage has no precharge voltage, the nd-th stage will not output a gate drive signal, thus not refreshing the pixel of the nd-th stage, and the nd-th stage will not display any abnormalities.

[0038] For example, if the current level is a refresh row and the (n+d)th level is a non-refresh row, it means that the current level outputs a gate drive signal and the (n+d)th level outputs a gate drive signal. When the connection between the first refresh control node An and the current level's drive control node Qsn is disconnected, the current level is a refresh row. Since there is a pre-charge voltage on the current level's drive control node Qsn, when the clock signal of the current level arrives, the drive output module 150 will output the gate drive signal of the current level to refresh the pixels of the current level. For the (n+d)th level, the first refresh control node An+d of the (n+d)th level is in a disconnected state, and there will be no pre-charge voltage on the drive control node Qsn+d of the (n+d)th level. When the clock signal of the (n+d)th level arrives, no gate drive signal will be output to refresh the pixels, and the (n+d)th level will not display any abnormalities.

[0039] In some embodiments, the drive output module 150 is configured to output a gate drive signal under the action of the voltage on the drive control node Qsn of the current stage and the clock signal of the current stage.

[0040] For example, when there is voltage on the current stage's drive control node Qsn, a gate drive signal will be output when the clock signal of the current stage arrives to refresh the pixels of the current stage.

[0041] Figure 2 A circuit diagram of a gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 As shown, the second brush control module 140 includes: a first control submodule 141, a second control submodule 142, and a switch control submodule 143. The first control submodule 141 is connected to the current level's second brush control node Bn, the second control submodule 142 is connected to the current level's second brush control node Bn, and the switch control submodule 143 is connected to the current level's first brush control node An, the current level's second brush control node Bn, and the current level's drive control node Qsn, respectively.

[0042] In some embodiments, the first control submodule 141 is configured to generate a first switch control signal at the second refresh control node Bn of the current level if the current level is a refresh row and the n+d level is a non-refresh row.

[0043] For example, if the current level is a refresh row and the (n+d)th level is a non-refresh row, the first control submodule 141 generates a first switch control signal at the second refresh control node Bn of the current level, causing the switch control submodule 143 to be turned off. The switch control submodule 143 will disconnect the connection between the first refresh control node and the drive control node. Since there is a pre-charge voltage on the drive control node Qsn of the current level, the current level can output a gate drive signal to refresh the pixel, so that the (n+d)th level does not output a gate drive signal to avoid display abnormalities in the ndth level.

[0044] In some embodiments, the second control submodule 142 is configured to generate a second switch control signal at the second refresh control node Bn of the current level if the nd level is a non-refresh line and the current level is a refresh line.

[0045] For example, if the nd level is a non-refreshing row and the current level is a non-refreshing row, the first control submodule 141 generates a second switch control signal at the second refresh control node. When there is voltage on the first refresh control node An of the current level, the switch control submodule 143 is turned on. The switch control submodule 143 controls the electrical connection between the first refresh control node and the drive control node. The drive control node Qsn of the current level will receive the voltage of the pull-up node Qn of the current level. The current level outputs a gate drive signal to refresh the pixel. The first refresh control module 130 of the nd level controls the disconnect between the pull-up node Qn-d of the nd level and the first refresh control node An-d of the nd level. The nd level does not output a gate drive signal to avoid display abnormalities in the current level.

[0046] In some embodiments, the switch control submodule 143 is configured to disconnect the first local brush control node An of the current stage from the drive control node Qsn of the current stage according to a first switch control signal, and to electrically connect the first local brush control node An of the current stage from the drive control node Qsn of the current stage according to a second switch control signal.

[0047] For example, the voltage signals of the first switch control signal and the second switch control signal have opposite polarities. When the first switch control signal is a high-level signal, the second switch control signal is a low-level signal; when the first switch control signal is a low-level signal, the second switch signal is a high-level signal.

[0048] In some embodiments, please refer to Figure 2 As shown, the first brush control module 130 includes: a first transistor T1; the control terminal of the first transistor T1 is connected to the pull-up node of the njth stage, the first terminal of the first transistor T1 is connected to the pull-up node Qn of the current stage, and the second terminal of the first transistor T1 is connected to the first brush control node An of the current stage.

[0049] In some embodiments, please refer to Figure 2 As shown, the first control submodule 141 includes: a second transistor T2; the control terminal of the second transistor T2 is connected to the first brush control terminal SW1, the first terminal of the second transistor T2 is connected to the pull-up node Qn-j of the njth stage, and the second terminal of the second transistor T2 is connected to the second brush control node Bn of the current stage.

[0050] In some embodiments, please refer to Figure 2 As shown, the second control submodule 142 includes: a third transistor T3; the control terminal of the third transistor T3 is connected to the second brush control terminal SW2, the first terminal of the third transistor T3 is connected to the second brush control node Bn of the current stage, and the second terminal of the third transistor T3 is connected to the low-level terminal VSS.

[0051] In some embodiments, please refer to Figure 2 As shown, the switch control submodule 143 includes: a fourth transistor T4 and a fifth transistor T5; the control terminal of the fourth transistor T4 is connected to the second brush control node Bn of the current stage, the first terminal of the fourth transistor T4 and the second terminal of the fifth transistor T5 are connected to the drive control node Qsn of the current stage, and the second terminal of the fourth transistor T4 is connected to the low-level terminal VSS; the control terminal of the fifth transistor T5 and the first terminal of the fifth transistor T5 are connected to the first brush control node An of the current stage.

[0052] For example, Figure 3 A timing diagram of a gate drive circuit according to an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 3As shown, if the nd-th stage is a non-refresh line and the current stage is a refresh line, that is, the nd-th stage does not output a gate drive signal, while the current stage needs to output a gate drive signal. When i is 2, d is 0, and q is 3, for the (n-1)-th stage, the first transistor T1 will be turned on under the voltage of the pull-up node Qn-4 of the (n-4)-th stage. The pull-up node Qn-4 of the (n-4)-th stage is a high-level signal during the period from t2 to t7, and the first transistor T1 will be turned on. The pull-up node Qn-1 of the (n-1)-th stage and the first brush control node An-1 of the (n-1)-th stage are electrically connected. However, during the period from t1 to t7, the first brush control terminal SW1 outputs a high-level signal, and the second brush control terminal SW2 outputs a low-level signal. The high-level signal output by the first brush control terminal SW1 of the second transistor T2 and the pull-up node Qn-4 of the (n-4)-th stage are connected. When the voltage is applied, the third transistor T3 is turned on. When the control terminal of the third transistor T3 receives a low-level signal, it is turned off. The second refresh control node Bn-1 of the n-1 stage is pulled up to a high potential. The control terminal of the fourth transistor T4 will be turned on. The drive control node Qsn-1 of the n-1 stage will be pulled down to a low potential by the fourth transistor T4. The drive control node Qsn-1 of the n-1 stage will have no pre-charge voltage. The voltage of the pull-up node of the n-1 stage will not be transmitted to the drive control node of the n-1 stage. During the working period of the n-1 stage (t7~t9), when the clock signal of the n-1 stage arrives, no gate drive signal will be output, so the pixel of the n-1 stage will not be refreshed. For the current stage, the pull-up node Qn-3 of the (n-3)th stage is a high-level signal during the period t3~t8. The first transistor T1 of the current stage will be turned on, and the pull-up node Qn of the current stage will be electrically connected to the first brush control node An of the current stage. During the working period of the current stage (t8~t10), the first brush control terminal SW1 outputs a low-level signal, and the second brush control terminal SW2 outputs a high-level signal. The second brush control node Bn of the current stage generates a second switching control signal, the fourth transistor T4 will be turned off, and the fifth transistor T... 5 will be turned on, and the voltage of the pull-up node Qn of the current stage will be transmitted to the drive control node Qsn of the current stage to act on the eleventh transistor T11. When the clock signal of the current stage arrives, the gate drive signal of the current stage will be output to refresh the pixel. During the working period of the current stage (t8~t10), the pull-up node Qn-4 of the n-4th stage has been pulled down to a low potential by the pull-down module 170, the first transistor T1 of the n-1th stage will be turned off, and the n-1th stage will not output a gate drive signal, so there will be no display abnormality.

[0053] For example, Figure 4 Another timing diagram of a gate drive circuit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 2 and Figure 4As shown, if the current stage is a refresh row and the (n+d)th stage is a non-refresh row, that is, the current stage outputs a gate drive signal, and the (n+d)th stage does not output a gate drive signal. When i is 2, d is 0, and q is 3, for the current stage, the control terminal of the first transistor T1 receives the voltage of the pull-up node Qn-3 of the (n-3)th stage and is turned on. During the period t2~t7, the pull-up node Qn of the current stage will be electrically connected to the first refresh control node An of the current stage; during the period t1~t7, the first refresh control terminal SW1 outputs a low-level signal, the second refresh control terminal SW2 outputs a high-level signal, and the fourth transistor T4 will receive a low-level signal and be turned off. During the period t5~t7, the voltage of the pull-up node Qn of the current stage will be transmitted to the drive control node of the current stage. Qsn precharges the current stage's drive control node Qsn. During the period t7~t9, the first brush control terminal SW1 outputs a high-level signal, and the second brush control terminal SW2 outputs a low-level signal. The second brush control node Bn of the current stage generates the first switch control signal, and the fourth transistor T4 will be turned on. The first brush control node An of the current stage will remain disconnected from the current stage's drive control node Qsn. However, since there is voltage on the current stage's drive control node Qsn, when the clock signal of the current stage arrives, the gate drive signal of the current stage will be output to refresh the pixel. For stage n+d, during the time interval t7~t9, the first brush control terminal SW1 sends a high-level signal, and the second brush control terminal SW2 sends a low-level signal. This will generate the first switch control signal at the second brush control node Bn+1 of stage n+1. The control terminal of the second transistor T2 receives the high-level signal, and the first terminal of the second transistor T2 receives the voltage of the pull-up node Qn-2 of stage n-2. The control terminal of the fourth transistor T4 will be turned on, thereby pulling down the drive control node of stage n+1 to a low potential. Stage n+1 will not output a gate drive signal, will not refresh the pixels of the current stage, and will not display any abnormalities.

[0054] In some embodiments, please refer to Figure 2 As shown, the pull-up module 110 includes: a tenth transistor T10; the control terminal and the first terminal of the tenth transistor T10 are respectively connected to the output terminal of the ni-th stage output module 120, and the second terminal of the tenth transistor T10 is connected to the pull-up node Qn of the current stage.

[0055] For example, when the control terminal and the first terminal of the tenth transistor T10 receive the stage transmission signal of the ni stage, they will be turned on, thereby charging the pull-up node Qn of the current stage and generating a voltage at the pull-up node Qn of the current stage.

[0056] In some embodiments, please refer to Figure 2As shown, the stage output module 120 includes: a ninth transistor T9 and a first capacitor C1; the control terminal of the ninth transistor T9 and the first terminal of the first capacitor C1 are connected to the pull-up node Qn of the current stage, the first terminal of the ninth transistor T9 is connected to the clock signal line CKm of the current stage, and the second terminal of the ninth transistor T9 is connected to the second terminal of the first capacitor C1.

[0057] For example, when the pull-up module 110 precharges the current stage's drive control node Qsn, the first capacitor C1 stores the precharged voltage. When the clock signal of the current stage arrives, the first capacitor C1 bootstraps the control terminal of the ninth transistor T9 to ensure that the ninth transistor T9 is turned on and outputs the current stage's transmission signal. By setting the first capacitor C1, even when the pull-up node Qn of the current stage is disconnected from the first brush control node, the current stage's transmission signal can still be output without affecting the transmission process.

[0058] In some embodiments, please refer to Figure 2 As shown, the drive output module 150 includes: an eleventh transistor T11 and a second capacitor C2. The control terminal of the eleventh transistor T11 is connected to the first terminal of the second capacitor C2. The first terminal of the eleventh transistor T11 is connected to the clock signal line CKm of the current stage. The second terminal of the eleventh transistor T11 is connected to the second terminal of the second capacitor C2.

[0059] For example, when the pull-up node Qn of the current stage is electrically connected to the drive control node Qsn of the current stage through the first refresh control node An of the current stage, and the drive control node Qsn of the current stage is pre-charged, the second capacitor C2 can store the pre-charged voltage. When the clock signal of the current stage arrives, even if the drive control node Qsn of the current stage is disconnected from the first refresh control node An of the current stage, the twelfth transistor T12 can be turned on to output the gate drive signal of the current stage and refresh the pixel of the current stage.

[0060] In some embodiments, the nth-stage gate driving unit 100 further includes a pull-down module 170, which includes a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, and a fifteenth transistor T15. The control terminal of the twelfth transistor T12 is connected to the control terminals of the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the output terminal of the (n+i)th stage transmission output module 120, respectively. The first terminal of the twelfth transistor T12 is connected to the drive control node Qsn of the current stage, and the second terminal of the twelfth transistor T12 is connected to the second terminals of the thirteenth transistor T13, the fourteenth transistor T14, the fifteenth transistor T15, and the low-level terminal VSS, respectively. The first terminal of the thirteenth transistor T13 is connected to the output terminal of the current stage transmission output module 120, the first terminal of the fourteenth transistor T14 is connected to the pull-up node Qn of the current stage, and the first terminal of the fifteenth transistor T15 is connected to the output terminal of the current stage drive output module 150. By setting the pull-down module 170 to pull down under the action of the stage transmission signal of the (n+j)th stage, it is ensured that during the working period of the current stage, the pull-up node Qn of the current stage is disconnected from the first brush control node An of the current stage.

[0061] For example, when the control terminals of the twelfth transistor T12, the thirteenth transistor T13, the fourteenth transistor T14, and the fifteenth transistor T15 receive the stage transmission signal of the (n+j)th stage, they will be turned on. This will pull down the current stage's drive control node Qsn, the output terminal of the current stage's stage transmission output module 120, the pull-up node Qn of the current stage, and the output terminal of the current stage's drive output module 150 to a low potential, respectively. This ensures that the output of the current stage's stage transmission signal and the current stage's gate drive signal is stopped, so that when the next frame signal arrives, the pull-up node Qn and the drive control node Qsn of the current stage will be precharged again.

[0062] In some embodiments, please refer to Figure 2 As shown, the nth stage gate drive unit 100 further includes a noise reduction module 160, which is connected to the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the output terminal of the stage output module 120 of the current stage, and the output terminal of the drive control output module of the current stage, respectively.

[0063] For example, by setting the noise reduction module 160, when the pull-up node Qn of the current stage is a low-level signal, the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the stage transmission output module 120, and the drive output module 150 are pulled down to a low potential, thereby reducing noise for the pull-up node Qn of the current stage, the drive control node Qsn of the current stage, the stage transmission output module 120, and the drive output module 150.

[0064] Figure 5 A circuit diagram of another gate driving unit provided in an embodiment of this application is shown. Please refer to [link / reference]. Figure 5 As shown, the first brush control module 130 includes: a first transistor T1 and a sixth transistor T6; the control terminal of the first transistor T1 is connected to the second terminal of the sixth transistor T6, the first terminal of the first transistor T1 is connected to the pull-up node Qn of the current stage, and the second terminal of the first transistor T1 is connected to the first brush control node An of the current stage; the control terminal of the sixth transistor T6 is connected to the first terminal of the sixth transistor T6 and the pull-up node Qn-j of the njth stage.

[0065] In some embodiments, please refer to Figure 5 As shown, the switch control submodule 143 includes: a fourth transistor T4, a fifth transistor T5, a seventh transistor T7, and an eighth transistor T8; the control terminal of the fourth transistor T4 and the control terminal of the seventh transistor T7 are connected to the second brush control node Bn of the current stage; the first terminal of the fourth transistor T4 is connected to the second terminal of the fifth transistor T5 and the control terminal of the eighth transistor T8, respectively; the second terminal of the fourth transistor T4 and the second terminal of the seventh transistor T7 are connected to the low-level terminal VSS; the control terminal of the fifth transistor T5, the first terminal of the fifth transistor T5, and the first terminal of the eighth transistor T8 are connected to the first brush control node; the first terminal of the seventh transistor T7 and the second terminal of the eighth transistor T8 are connected to the drive control node.

[0066] For example, please refer to Figure 5 and Figure 3As shown, if the nd stage is a non-refresh line and the current stage is a refresh line, that is, the nd stage does not output a gate drive signal, and the current stage needs to output a gate drive signal. When i is 2, d is 0, and q is 3, for the (n-1)th stage, the sixth transistor T6 will be turned on under the voltage of the pull-up node Qn-4 of the (n-4)th stage. The pull-up node Qn-4 of the (n-4)th stage is a high-level signal during the period from t2 to t7. The turn-on of the sixth transistor T6 will control the first transistor T1 to be turned on. The pull-up node Qn-1 of the (n-1)th stage and the first brush control node An-1 of the (n-1)th stage are electrically connected. However, during the period from t1 to t7, the first brush control terminal SW1 outputs a high-level signal, and the second brush control terminal SW2 outputs a low-level signal. The second transistor T2 is turned on under the high-level signal output by the first brush control terminal SW1 and the voltage of the pull-up node of the (n-4)th stage. The third transistor... When the control terminal of T3 receives a low-level signal, it is cut off. The second refresh control node Bn-1 of the (n-1)th stage is pulled up to a high potential. The fourth transistor T4 and the seventh transistor T7 will be turned on. The drive control node Qsn-1 of the (n-1)th stage will be pulled down to a low potential by the fourth transistor T4 and the seventh transistor T7. The eighth transistor T8 will be in the off state. The drive control node Qsn-1 of the (n-1)th stage will have no pre-charge voltage. The voltage of the pull-up node Qn-1 of the (n-1)th stage will not be transmitted to the drive control node Qsn-1 of the (n-1)th stage. During the working period of the (n-1)th stage (t7~t9), when the clock signal of the (n-1)th stage arrives, no gate drive signal will be output, so the pixel of the (n-1)th stage will not be refreshed. For the current stage, the pull-up node Qn-3 of the (n-3)th stage is a high-level signal during the period t3~t8. The first transistor T1 and the sixth transistor T6 of the current stage will be turned on. The pull-up node Qn of the current stage will be electrically connected to the first brush control node An of the current stage. During the working period of the current stage (t8~t10), the first brush control terminal SW1 outputs a low-level signal, and the second brush control terminal SW2 outputs a high-level signal. The second brush control node Bn of the current stage generates a second switching control signal, and the fourth transistor T4 and the seventh transistor T7 will be turned off. The fifth transistor T... Transistor 5 and the eighth transistor T8 will be turned on. The voltage of the pull-up node Qn of the current stage will be transmitted to the drive control node Qsn of the current stage to act on the eleventh transistor T11. When the clock signal of the current stage arrives, the gate drive signal of the current stage will be output to refresh the pixel. During the working period of the current stage (t8~t10), the pull-up node Qn-4 of the n-4th stage has been pulled down to a low potential by the pull-down module 170. The sixth transistor T6 and the first transistor T1 of the n-1th stage will be turned off. The n-1th stage will not output the gate drive signal, so there will be no display abnormality.

[0067] For example, please refer to Figure 4 and Figure 5 As shown, if the current stage is a refresh row and the (n+d)th stage is a non-refresh row, that is, the current stage outputs a gate drive signal, and the (n+d)th stage does not output a gate drive signal. When i is 2, d is 0, and q is 3, for the current stage, the control terminal of the first transistor T1 receives the voltage of the pull-up node Qn-3 of the (n-3)th stage and is turned on. During the period t2~t7, the pull-up node Qn of the current stage will be electrically connected to the first refresh control node An of the current stage; during the period t1~t7, the first refresh control terminal SW1 outputs a low-level signal, the second refresh control terminal SW2 outputs a high-level signal, and the fourth transistor T4 will receive a low-level signal and be turned off. During the period t5~t7, the voltage of the pull-up node Qn of the current stage will be transmitted to the drive control node Qsn of the current stage. The current stage's drive control node Qsn is pre-charged. During the period t7~t9, the first brush control terminal SW1 outputs a high-level signal, and the second brush control terminal SW2 outputs a low-level signal. The first switch control signal is generated at the second brush control node Bn of the current stage, and the fourth transistor T4 and the seventh transistor T7 will be turned on. The first brush control node An of the current stage will remain disconnected from the current stage's drive control node Qsn. However, since there is voltage on the current stage's drive control node Qsn, when the clock signal of the current stage arrives, the gate drive signal of the current stage will be output to refresh the pixel. For stage n+1, during the time interval t7~t9, the first brush control terminal SW1 sends a high-level signal, and the second brush control terminal SW2 sends a low-level signal. This will generate the first switch control signal at the second brush control node Bn+1 of stage n+1. The control terminal of the second transistor T2 receives the high-level signal, and the first terminal of the second transistor T2 receives the voltage of the pull-up node Qn-2 of stage n-2. The fourth transistor T4 and the seventh transistor T7 will be turned on, thereby pulling down the drive control node Qsn+1 of stage n+1 to a low potential. Stage n+1 will not output a gate drive signal, will not refresh the pixels of the current stage, and will not display any abnormalities.

[0068] It should be noted that both the first brush control terminal SW1 and the second brush control terminal SW2 can be control terminals of the controller, and the controller can specifically be a timing controller.

[0069] In some embodiments, this application provides a display panel including a display area and a non-display area. The display area includes multiple scan lines, and the non-display area includes the aforementioned gate driving circuit. The drive output module of the gate driving circuit is connected to at least one scan line.

[0070] Furthermore, the terms "first," "second," and "third," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0071] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0072] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A gate drive circuit characterized by comprising: The gate driving circuit includes N cascaded gate driving units, and the nth gate driving unit includes: The pull-up module, connected to the pull-up node of the current stage, is configured to charge the pull-up node of the current stage in response to the output signal of the nith stage gate drive unit. The stage transmission module is connected to the pull-up node of the current stage and the clock signal line of the current stage, and is configured to output the stage transmission signal under the action of the voltage of the pull-up node of the current stage and the clock signal of the current stage. The first refresh control module, which is connected to the pull-up node of the current level, the first refresh control node of the current level, and the pull-up node of the nj level, is configured to: in partial refresh mode, under the voltage action of the pull-up node of the nj level, control the electrical connection between the pull-up node of the current level and the drive control node of the current level; wherein, j is greater than i; The second refresh control module, connected to the first refresh control node and the current level's driver control node respectively, is configured to: in the local refresh mode, if the nd-th level is a non-refresh line and the current level is a refresh line, control the first refresh control node and the current level's driver control node to be electrically connected; if the current level is a refresh line and the n+d-th level is a non-refresh line, control the first refresh control node and the current level's driver control node to be disconnected; wherein, d is less than i; The drive output module is connected to the drive control node and the clock signal line of the current stage, respectively, and is configured to output a gate drive signal under the action of the voltage on the drive control node of the current stage and the clock signal of the current stage.

2. The gate drive circuit according to claim 1, characterized by The second-round brush control module includes: The first control submodule, connected to the second refresh control node of the current level, is configured to generate a first switch control signal at the second refresh control node of the current level if the current level is a refresh row and the n+d level is a non-refresh row. The second control submodule, connected to the second refresh control node of the current level, is configured to generate a second switch control signal at the second refresh control node of the current level if the nd level is a non-refresh line and the current level is a refresh line. The switch control submodule, connected to the first brush control node, the second brush control node, and the drive control node of the current level, is configured to: disconnect the first brush control node and the drive control node of the current level according to the first switch control signal; and electrically connect the first brush control node and the drive control node of the current level according to the second switch control signal and the voltage on the first brush control node.

3. The gate drive circuit according to claim 1, characterized by The first refresh control module includes: a first transistor; The control terminal of the first transistor is connected to the pull-up node of the njth stage, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the first brush control node of the current stage.

4. The gate drive circuit according to claim 2, characterized by The first control submodule includes: a second transistor; The control terminal of the second transistor is connected to the first brush control terminal, the first terminal of the second transistor is connected to the pull-up node of the njth stage, and the second terminal of the second transistor is connected to the second brush control node of the current stage.

5. The gate drive circuit according to claim 2, characterized by The second control submodule includes: a third transistor; The control terminal of the third transistor is connected to the control terminal of the second brush, the first terminal of the third transistor is connected to the second brush control node of the current stage, and the second terminal of the third transistor is connected to the low-level terminal.

6. The gate driving circuit according to claim 2, characterized in that, The switch control submodule includes: a fourth transistor and a fifth transistor; The control terminal of the fourth transistor is connected to the second brush control node of the current stage, the first terminal of the fourth transistor and the second terminal of the fifth transistor are connected to the drive control node of the current stage, and the second terminal of the fourth transistor is connected to the low-level terminal. The control terminal of the fifth transistor and the first terminal of the fifth transistor are connected to the first brush control node of the current stage.

7. The gate driving circuit according to claim 1, characterized in that, The first local refresh control module includes: a first transistor and a sixth transistor; The control terminal of the first transistor is connected to the second terminal of the sixth transistor, the first terminal of the first transistor is connected to the pull-up node of the current stage, and the second terminal of the first transistor is connected to the first brush control node of the current stage. The control terminal of the sixth transistor is connected to the first terminal of the sixth transistor and the pull-up node of the njth stage, respectively.

8. The gate driving circuit according to claim 2, characterized in that, The switch control submodule includes: a fourth transistor, a fifth transistor, a seventh transistor, and an eighth transistor; The control terminal of the fourth transistor and the control terminal of the seventh transistor are connected to the second brush control node of the current stage. The first terminal of the fourth transistor is connected to the second terminal of the fifth transistor and the control terminal of the eighth transistor, respectively. The second terminal of the fourth transistor and the second terminal of the seventh transistor are connected to the low-level terminal. The control terminal of the fifth transistor, the first terminal of the fifth transistor, and the first terminal of the eighth transistor are connected to the first local brush control node; The first terminal of the seventh transistor and the second terminal of the eighth transistor are connected to the drive control node.

9. The gate driving circuit according to claim 1, characterized in that, The stage transmission module includes: a ninth transistor and a first capacitor; The control terminal of the ninth transistor is connected to the first terminal of the first capacitor at the pull-up node of the current stage. The first terminal of the ninth transistor is connected to the clock signal line of the current stage, and the second terminal of the ninth transistor is connected to the second terminal of the first capacitor.

10. A display panel comprising a display area and a non-display area, wherein the display area includes a plurality of scan lines, characterized in that, The non-display area includes the gate driving circuit according to any one of claims 1-9, wherein the driving output module of the gate driving circuit is connected to at least one of the scan lines.

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