A capacitor-based in-memory computing method and array based on voltage clamping

Abstract

This invention provides a capacitive-clamp-based, operational amplifier-free in-memory computing method and array, belonging to the field of in-memory computing. This method utilizes programmable field-effect transistors with high memory windows to implement memory capacitor weighted cells with large windows and high on / off ratios. Clamping capacitors achieve capacitive clamping in high-capacitance states, allowing the in-memory computing cells to exhibit voltage-independent high-capacitance and low-capacitance states over a wide range. Furthermore, complementary memory configurations maintain a constant total load capacitance on the output lines. This invention achieves high-linearity capacitive-type in-memory computing through capacitive coupling, while eliminating the need for high-power operational amplifiers, providing a high-energy-efficiency hardware solution for edge AI devices.

Description

Technical Field

[0001] This invention relates to the field of in-memory computing, specifically to a capacitor-free in-memory computing method and array based on capacitance clamping. Background Technology

[0002] The deployment of artificial intelligence on edge devices is becoming a mainstream trend due to its faster response times, better privacy, and lower operating costs, requiring high-efficiency, high-throughput, and high-reliability computing equipment as hardware support. To overcome the energy efficiency and latency bottlenecks of traditional von Neumann architectures in data movement, in-memory computing (CIM) technology can significantly reduce the frequent movement of data between the processor and memory by directly performing generalized matrix-vector multiplication (GEMV) operations at high throughput within the storage array. Among these technologies, capacitive in-memory computing (C-CIM) based on three-dimensionally stackable memory containers overcomes the heat dissipation and IR drop problems of traditional resistive in-memory computing (R-CIM) technology due to the absence of DC paths in the array, demonstrating the potential to achieve high computing density and high energy efficiency, making it highly suitable for edge devices.

[0003] Existing memcells mainly fall into two categories: metal-ferroelectric-metal (MFM) capacitors, whose capacitance-capacitance (CV) relationship follows a double-butterfly curve; and MOS capacitors controlled by charge-trapping gates or ferroelectric gates, whose high capacitance state (HCS) capacitance is voltage-dependent. Since C-CIM calculates the charge Q by integrating the change in voltage V over capacitance C, the voltage dependence of the capacitance value in existing memcells leads to a non-linear QV relationship. This results in a significant decrease in computational linearity when using the output line voltage of the capacitor array as the C-CIM calculation result via capacitive coupling. To avoid this problem, existing C-CIM often uses an operational amplifier (Op-Amp) to clamp the output line voltage of the capacitor array, transferring the charge Q to a reference capacitor as the output result. However, the high power consumption of the Op-Amp limits the overall energy efficiency of C-CIM. Therefore, existing C-CIM struggles to achieve both high energy efficiency and high linearity, hindering its application in edge-side artificial intelligence devices. Summary of the Invention

[0004] To address the problems in the prior art described above, the present invention aims to propose a capacitance-type in-memory computation method and array based on capacitance clamping without operational amplifiers. This method can achieve capacitance-type in-memory computation with both high energy efficiency and high linearity based on capacitive coupling, providing a highly promising hardware solution for edge artificial intelligence devices.

[0005] To achieve the above objectives, the present invention provides the following technical solution:

[0006] A capacitorless in-memory computation method based on capacitance clamping is disclosed. Each in-memory computation unit consists of a memory container, a clamping capacitor, and a gating transistor. The first port of the memory container is connected to the first port of the clamping capacitor and the source terminal of the gating transistor. The second port of the clamping capacitor is connected to the drain terminal of the gating transistor and connected to the input word line (WL). The gate terminal of the gating transistor is connected to the control line (CL). The second port of the memory container is connected to the output bit line (BL).

[0007] Furthermore, the in-memory computing units are repeated in a horizontal and vertical manner to form an in-memory computing array; in the array, WL is parallel to CL and perpendicular to BL; WL is controlled by the WL decoding and driving module; BL is connected to an analog-to-digital converter (ADC); each BL is connected to the drain of a reset transistor, the gate of the reset transistor is controlled by a reset signal (RST), and the source of the reset transistor is connected to a voltage source -V0.

[0008] When writing weights, the in-memory computing array sets CL high to turn on the selection transistor, thereby short-circuiting the clamping capacitor and effectively forming a cross-dot array of the memory container. Weights are written using WL and BL according to the conventional V / 2 or V / 3 anti-crosstalk scheme of memory arrays.

[0009] The in-memory computing array's operation process is divided into two stages: reset and calculation. First, in the reset stage, RST is set high to turn on the reset transistor, initializing the BL voltage to -V0. Simultaneously, the WL voltage is initialized to 0 via the WL decoding and driving module. Then, in the calculation stage, RST is set low to turn off the reset transistor, CL is set low to turn off the selection transistor, and the input voltage is applied from WL, representing the WL value of the i-th row of input. i Voltage change The clamping capacitor and the memory capacitor, which are connected in series, are coupled to BL, and the voltage change of BL is... This represents the output result, which is obtained after ADC quantization; where C represents the total load capacitance of BL. i Let be the capacitance value of the capacitor connected in the i-th row of BL, where i is a positive integer.

[0010] Furthermore, the in-memory computing array has an even number of rows of in-memory computing units, and the in-memory computing array adopts complementary storage and differential input: two adjacent in-memory computing units on the same BL (clamping capacitor and memory container connected in series, with equivalent capacitance values ​​denoted as C) w With C wb Store a binary signed weight (±1); C w C is in a high capacitance state H C wb C is in a low capacitance state L , indicating a weight of 1; C wC is in a low capacitance state L C wb C is in a high capacitance state H The weight is -1; a binary signed input (±1) is applied to the word lines corresponding to the two adjacent in-memory computing units (denoted as WL and WLB, respectively); the voltage change of WL is the calculated voltage (V). r A WLB voltage change of 0 indicates an input of 1; a WL voltage change of 0 and a WLB voltage change of V r , indicating that the input is -1.

[0011] Furthermore, the high-capacitance state C of the memory container H 'Much higher than its low capacitance state C' L And C L Regardless of voltage; the capacitance C0 of the clamping capacitor is lower than C. H But far higher than C L In the CV curve of the equivalent capacitance of the in-memory computing unit, the high capacitance state C H With low capacitance state C L The voltage range that is independent of voltage is denoted as V. L ~ V H , satisfying V0 = (V H + V L ) / 2、V r = (V H – V L ) / 2.

[0012] Preferably, the memory capacitor is a programmable field-effect transistor with a high storage window, its first port being the gate terminal of the transistor, and its second port being the source and drain terminals of the transistor shorted together; when the transistor channel is in the inversion state, the source and drain are connected to the channel, corresponding to the high capacitance state (C) of the memory capacitor. H '), C H Generally related to voltage; when the transistor channel is in the accumulation state, there is no conduction between the source / drain and the channel, corresponding to the low capacitance state (C) of the memory capacitor. L ), C L Generally, it is unrelated to voltage. Because C L Proportional to the overlap area of ​​the transistor's gate stack and source / drain, thus allowing C to... H 'Far higher than C' L The switching ratio of the memory container to C H ' / C L It can be very high.

[0013] Preferably, the clamping capacitor value (C0) is lower than C. H This is to "clamp" the equivalent capacitance of the in-memory computing unit by C0 in the high-capacitance state, thus enhancing voltage independence. Its value is denoted as C.H C0 is preferably much higher than C. L To ensure that the equivalent capacitance of the in-memory computing unit still maintains a high switching ratio C H / C L Because the transistor has a high storage window, the voltage range V L ~ V H Very wide, V r Correspondingly higher.

[0014] Furthermore, the programmable field-effect transistor is a floating-gate transistor, a charge-trapping transistor, or a ferroelectric transistor. The ferroelectric transistor employs a metal-ferroelectric-semiconductor (MFS), a metal-ferroelectric-channel-side dielectric-semiconductor (MFIS), a metal-ferroelectric-metal-channel-side dielectric-semiconductor (MFMIS), or a metal-gate-side dielectric-ferroelectric-channel-side dielectric-semiconductor (MIFIS). The ferroelectric material in the ferroelectric transistor is a perovskite ferroelectric material, a two-dimensional ferroelectric material, an organic ferroelectric material, a group III-V nitride ferroelectric material, or a hafnium oxide-doped ferroelectric material.

[0015] The beneficial technical effects of this invention are as follows:

[0016] This invention utilizes a programmable field-effect transistor with a large memory window to realize a memory capacitor with a large window and a high on / off ratio, and uses a preferred clamping capacitor to achieve capacitance clamping in the high-capacitance state, so that C H With C L It exhibits enhanced voltage independence over a wide voltage range and boasts a high output dynamic range due to its high computation voltage and high switching ratio. Furthermore, by utilizing complementary memory configurations to maintain a constant total load capacitance on the BL, it achieves high-linearity capacitive in-memory computation through capacitive coupling, while eliminating the need for high-power operational amplifiers, thus providing a high-efficiency hardware solution for edge AI devices. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the principle of the capacitor-type memory calculation method without operational amplifier based on capacitance clamping at the cell level of the present invention.

[0018] Figure 2 This is a schematic diagram of an array system based on the capacitor-free memory calculation method for operational amplifiers using capacitance clamping, as described in this invention. Detailed Implementation

[0019] The present invention will be further clearly and completely described below with reference to the accompanying drawings and specific embodiments.

[0020] This embodiment uses capacitance clamping to achieve operational amplifier-free capacitor-type in-memory computation at the cell level, as follows: Figure 1As shown: By selecting a programmable field-effect transistor with a large memory window, using its gate terminal as the first port (int), and shorting its source and drain together as the second port, a memory container with a large window and high on / off ratio can be realized; C H ' represents the high-capacitance state of the memory capacitor, which is generally voltage-dependent; C L The memory capacitor is in a low-capacitance state, generally independent of voltage; furthermore, a clamping capacitor C0 is connected in series at the int port as part of the cell, and its capacitance value satisfies C0 < C H '、 This allows the high capacitance state C of the equivalent capacitance of the in-memory computing unit to be achieved. H With low capacitance state C L All in V L ~ V H = 0 ~ 2V r (V) r The voltage range for calculating voltage has enhanced voltage independence, which is beneficial for achieving high linearity calculations based on capacitive coupling.

[0021] This embodiment implements an array system for operational amplifier-less capacitor-type in-memory computation based on capacitance clamping, such as... Figure 2 As shown:

[0022] 1) Each in-memory computing unit consists of a memory capacitor, a clamping capacitor C0, and a gate transistor; the first port of the memory capacitor is connected to the first port of the clamping capacitor and the source terminal of the gate transistor; the second port of the clamping capacitor is connected to the drain terminal of the gate transistor, and connected to WL; the gate terminal of the gate transistor is connected to CL; the second port of the memory capacitor is connected to BL; the in-memory computing units are repeated in a horizontal and vertical configuration to form an in-memory computing array; in the array, WL is parallel to CL and perpendicular to BL; WL is controlled by the WL decoding / driving module; BL is connected to the ADC; each BL is connected to the drain terminal of a reset transistor, the gate terminal of the reset transistor is controlled by RST, and the source terminal of the reset transistor is connected to a voltage source -V0 = -V r .

[0023] 2) The operation process is divided into two stages: reset and calculation. First, in the reset stage, RST is set high to turn on the reset transistor, so that the BL voltage is initialized to -V. r Simultaneously, the WL voltage is initialized to 0 via the WL driver module; then, during the calculation phase, RST is set low to turn off the reset transistor, and CL is set low to turn off the gating transistor; the input voltage is applied from WL, representing the WL value of the i-th row of input. i Voltage change The voltage change in BL is coupled to BL via the unit's equivalent capacitance. This represents the output result, which is obtained after ADC quantization; where C represents the total load capacitance of BL. i Let C be the capacitance value of the capacitor mounted in the i-th row of the array; the array uses complementary storage, and the equivalent capacitance value of two adjacent cells on the same array is denoted as C. w With C wb Store a binary signed weight W (±1), C w C H C wb C L This indicates that the weight is 1, C w C L C wb C H The weight is -1; the array uses differential input, and a binary signed input X (±1) is applied to the word lines corresponding to the two adjacent cells (denoted as WL and WLB respectively), and the voltage change of WL is V. r A WLB voltage change of 0 indicates an input of 1; a WL voltage change of 0 and a WLB voltage change of V indicate an input of 1. r This indicates that the input is -1.

[0024] Finally, it should be noted that the purpose of disclosing the embodiments is to help further understand the present invention. However, those skilled in the art will understand that various substitutions and modifications are possible without departing from the spirit and scope of the present invention and the appended claims. Therefore, the present invention should not be limited to the content disclosed in the embodiments, and the scope of protection of the present invention is defined by the scope of the claims.

Claims

1. A method for calculating the memory capacity of an operational amplifier-less capacitor-type memory based on capacitance clamping, characterized in that, Each in-memory computing unit consists of a memory container, a clamping capacitor, and a gating transistor. The first port of the memory container is connected to the first port of the clamping capacitor and the source terminal of the gating transistor. The second port of the clamping capacitor is connected to the drain terminal of the gating transistor and is connected to the input word line. The gate terminal of the gating transistor is connected to the control line. The second port of the memory container is connected to the output bit line. The in-memory computing units are repeated in a horizontal and vertical configuration to form an in-memory computing array. In the array, the word lines are parallel to the control lines and perpendicular to the bit lines. The word lines are controlled by a word line decoding and driving module. The bit lines are connected to an analog-to-digital converter. Each bit line is connected to the drain terminal of a reset transistor, the gate terminal of which is controlled by a reset signal, and the source terminal of the reset transistor is connected to a voltage source -V0. When writing weights, the control line is set high to turn on the selection transistor, thereby short-circuiting the clamping capacitor, which is equivalent to forming a cross-dot array of the memory container. Weights are written through word lines and bit lines according to the anti-crosstalk scheme of the memory array. A single operation consists of two phases: reset and calculation. First, in the reset phase, the reset signal is set high to turn on the reset transistor, initializing the bit line voltage to -V0. Simultaneously, the word line voltage is initialized to 0 via the word line decoding and driving module. Then, in the calculation phase, the reset signal is set low to turn off the reset transistor, the control line is set low to turn off the selection transistor, and the input voltage is applied from the word line, representing the WL value of the i-th row of input. i Voltage change The clamping capacitor and memory capacitor, which are connected in series, are coupled to the bit line, and the change in bit line voltage... This indicates the output result, which is obtained by quantization using an analog-to-digital converter; where... C is the total load capacitance of the bit line. i Let be the capacitance value of the capacitor connected to the i-th row of the bit line, where i is a positive integer.

2. The capacitor-type memory calculation method as described in claim 1, characterized in that, The in-memory computing array employs complementary storage and differential input: two adjacent in-memory computing units on the same bit line store a binary signed weight, and the equivalent capacitance values ​​of the two adjacent in-memory computing units are denoted as C. w With C wb C w C is in a high capacitance state H C wb C is in a low capacitance state L When C represents a weight of 1, w C is in a low capacitance state L C wb C is in a high capacitance state H The weight is -1; a binary signed input is applied to the word lines corresponding to the two adjacent in-memory computing units. These two word lines are denoted as WL and WLB, respectively, and the voltage change of WL is the calculated voltage V. r When the WLB voltage change is 0, it indicates that the input is 1. When the WL voltage change is 0, the WLB voltage change is V. r The time indicates that the input is -1.

3. The capacitive memory calculation method as described in claim 2, characterized in that, The high capacitance state C of the memory container H 'Much higher than its low capacitance state C' L And C L Regardless of voltage; the capacitance C0 of the clamping capacitor is lower than C. H But far higher than C L In the CV curve of the equivalent capacitance of the in-memory computing unit, the high capacitance state C H With low capacitance state C L The voltage range that is independent of voltage is denoted as V. L ~ V H , satisfying V0 = (V H + V L ) / 2、V r = (V H – V L ) / 2.

4. The capacitive memory calculation method as described in claim 1, characterized in that, The memory capacitor is a programmable field-effect transistor with a high storage window. Its first port is the gate terminal of the transistor, and its second port is the source and drain terminals of the transistor shorted together. When the transistor channel is in the inversion state, the source and drain are connected to the channel, corresponding to the high capacitance state C of the memory capacitor. H ', C H 'Voltage-dependent; when the transistor channel is in the accumulation state, there is no conduction between the source / drain and the channel, corresponding to the low capacitance state C of the memory capacitor.' L C L Independent of voltage; C H 'Far higher than C' L This enables the memory container to have a high on / off ratio C. H ' / C L The capacitance C0 of the clamping capacitor is lower than C. H This is to "clamp" the equivalent capacitance of the in-memory computing unit by C0 in the high-capacitance state, thus enhancing voltage independence. Its value is denoted as C. H C0 is much higher than C L To maintain a high on / off ratio C for the equivalent capacitance of the in-memory computing unit. H / C L .

5. The capacitor-type memory calculation method as described in claim 4, characterized in that, The programmable field-effect transistor is a floating-gate transistor, a charge-trapping transistor, or a ferroelectric transistor.

6. A capacitor-type in-memory computing array without operational amplifiers, characterized in that, Each in-memory computing unit consists of a memory container, a clamping capacitor, and a gating transistor. The first port of the memory container is connected to the first port of the clamping capacitor and the source terminal of the gating transistor. The second port of the clamping capacitor is connected to the drain terminal of the gating transistor and is connected to the input word line. The gate terminal of the gating transistor is connected to the control line. The second port of the memory container is connected to the output bit line. These in-memory computing units are repeated horizontally and vertically to form an in-memory computing array. In the array, the word lines are parallel to the control lines and perpendicular to the bit lines. The word lines are controlled by a word line decoding and driving module. The bit lines are connected to an analog-to-digital converter. Each bit line is connected to the drain terminal of a reset transistor, the gate terminal of which is controlled by a reset signal, and the source terminal of the reset transistor is connected to a voltage source -V0.

7. The capacitor-type in-memory computing array as described in claim 6, characterized in that, In the in-memory computing unit, the memory container's high-capacitance state C H 'Much higher than its low capacitance state C' L And C L Regardless of voltage; the capacitance C0 of the clamping capacitor is lower than C. H But far higher than C L .

8. The capacitor-type in-memory computing array as described in claim 7, characterized in that, The memory capacitor is a programmable field-effect transistor with a high storage window. Its first port is the gate terminal of the transistor, and its second port is the source and drain terminals of the transistor shorted together. When the transistor channel is in the inversion state, the source and drain are connected to the channel, corresponding to the high capacitance state C of the memory capacitor. H ', C H 'Voltage-dependent; when the transistor channel is in the accumulation state, there is no conduction between the source / drain and the channel, corresponding to the low capacitance state C of the memory capacitor.' L C L It is independent of voltage.

9. The capacitor-type in-memory computing array as described in claim 8, characterized in that, The programmable field-effect transistor is a floating-gate transistor, a charge-trapping transistor, or a ferroelectric transistor.

10. The capacitor-type in-memory computing array as described in claim 9, characterized in that, The ferroelectric transistor adopts an MFS, MFIS, MFMIS, or MIFIS structure; the ferroelectric material in the ferroelectric transistor adopts perovskite ferroelectric material, two-dimensional ferroelectric material, organic ferroelectric material, III-V group nitride ferroelectric material, or doped hafnium oxide-based ferroelectric material.

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