A current transfer breaker control method, system, medium, and device

Abstract

A current transfer circuit breaker control method, system, medium and device are used for low-frequency short-circuit current breaking in a pumped storage unit back-to-back starting process. In the method, three-phase voltage signals and three-phase current signals of a driving side and a driven side in the back-to-back starting process are collected. Based on a fault discrimination algorithm of multi-electric quantity fusion and the collected three-phase voltage signals and three-phase current signals of the driving side and the driven side, it is judged whether short-circuit faults occur in the driving side and the driven side. A fault removal process is executed. After it is judged that short-circuit faults occur in the driving side and the driven side in the back-to-back starting process, the main break command sending time, the transfer thyristor conduction time and the disconnector disconnection time are calculated according to the collected current signals, and signals are sent at the corresponding times to complete the removal of the fault current.

Description

Technical Field

[0001] This invention relates to the field of short-circuit fault interruption technology for pumped storage units, and particularly to a current transfer circuit breaker control method, system, medium, and equipment for interrupting low-frequency short-circuit currents during back-to-back startup of pumped storage units. Background Technology

[0002] Back-to-back start of pumped storage units refers to the process of using another unit within the same power station that is already connected to the grid or has power supply capabilities to provide electrical energy and frequency support to the unit to be started, under conditions where there is no external power source or the external power source is limited. This allows the unit to establish its electrical operating condition and gradually increase its speed to a state ready for operation. This process typically relies on the stator-side electrical coupling and coordinated control of the excitation / speed regulation systems of the two units. The "driving unit" provides starting power to the "driven unit," achieving controlled speed-up in the low-speed range, establishing synchronization conditions, and subsequent grid connection or operating condition transition. As an important starting and recovery method for pumped storage power stations, back-to-back start can significantly improve the overall level of the power station in terms of black start, rapid recovery after system accidents, peak and frequency regulation support, and unit self-recovery capabilities. Its starting reliability and controllability are directly related to the availability of the power station, the system stability support capability, and the recovery efficiency after major disturbances. Therefore, it has outstanding engineering application value and safety significance.

[0003] In the early stages of back-to-back startup, the driven unit operates at low speed and low electrical frequency, with the electrical frequencies of its stator voltage and current significantly lower than the power frequency as the speed changes. Under these conditions, if a stator-side short circuit, phase-to-phase fault, or electrical abnormality related to the starting circuit occurs, a typical low-frequency short-circuit current will be generated. Short-circuit faults occurring at different times during startup will produce low-frequency short-circuit fault currents with different characteristics. Due to factors such as the electromagnetic transient process of the motor, flux linkage establishment / decay, and excitation system regulation, the fault current is often accompanied by a significant DC component with a relatively large decay time constant. Under low-frequency conditions, this makes it easier for the current waveform to deviate from a symmetrical sine wave for a prolonged period, manifesting as increased current peak value and longer zero-crossing time. These characteristics further exacerbate electromagnetic force impact, mechanical stress in the stator windings and end structures, and thermal and electrical stress in the rotor and excitation circuit. They may also trigger a chain reaction of problems such as voltage drops, protection maloperation or failure to operate, and control system instability. Especially during the back-to-back startup phase, when the unit's inertial system is in the process of accelerating, the fault current and electromagnetic torque fluctuations are coupled with each other, which may cause sudden changes in the power of the driven unit and abnormal electromagnetic braking torque, thereby expanding the scope of the accident and significantly increasing the risk of equipment damage and operational safety.

[0004] Existing medium- and high-voltage AC circuit breakers are primarily designed and tested for short-circuit breaking under power frequency conditions. Their arc extinguishing and dielectric recovery capabilities are highly dependent on the natural zero-crossing of the fault current and the reconstruction of dielectric strength after the zero-crossing. Therefore, when facing low-frequency short-circuit currents of 45Hz and below, the breaking capacity of commercially available medium- and high-voltage AC circuit breakers is usually severely reduced, or even unable to break the fault. Taking ABB's HECPS-3S circuit breaker as an example, when dealing with low-frequency short-circuit currents of 20-45Hz, the circuit breaker's breaking capacity is only 65% ​​of that at power frequency. When dealing with low-frequency short-circuit currents below 20Hz, the circuit breaker cannot break the fault current. When the fault current is at a low frequency and has a large DC component, the current zero-crossing interval is significantly lengthened, leading to a prolonged arc sustaining time, increased arc energy accumulation, and intensified contact erosion and thermal shock. At the same time, reignition and repeated breakdown are more likely to occur before the dielectric recovers, making it difficult for conventional circuit breakers to reliably clear low-frequency short-circuit current faults within the expected time. One common engineering approach is to simultaneously trip the excitation circuit breakers (GCBs) of both units, allowing the electromagnetic torque to decay rapidly. This is achieved by waiting for the rotor to stop or its speed to drop significantly before disconnecting the GCB, thus mitigating the challenge to breaking capacity posed by low-frequency fault currents with a large DC component. However, this method inherently relies on the premise that both excitation circuit breakers can be reliably disconnected as instructed. If a single excitation circuit breaker fails to disconnect or is not synchronized, the electromagnetic torque of the driven unit may suddenly be lost, system damping may decrease, and the unit may continuously accelerate under mechanical input and inertia, leading to overspeeding or even runaway, posing a significant safety hazard. Therefore, existing traditional disconnection techniques and control strategies are insufficient for disconnecting low-frequency short-circuit faults during back-to-back startup. There is an urgent need for a technical solution that can controllably transfer and reliably disconnect low-frequency short-circuit currents during the low-speed phase of back-to-back startup, while reducing reliance on the single prerequisite of excitation disconnection, to meet the pressing engineering needs of safe startup of pumped storage units and improved reliability of the power plant system.

[0005] The information disclosed in the background section is only for enhancing the understanding of the background of this invention, and therefore may contain information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a current-transfer circuit breaker control method, system, medium, and device for interrupting low-frequency short-circuit currents during the back-to-back startup process of pumped-storage units. Specifically, during the low-speed phase of back-to-back startup, to address the problem of difficulty in zero-crossing of low-frequency short-circuit currents due to superimposed DC components and the unreliable interruption by conventional circuit breakers, a "prediction-trigger-transfer" collaborative control of a current-transfer circuit breaker is introduced. The strategy uses weighted fusion and confidence-based voting for dual-sided redundant short-circuit discrimination as the startup condition. It captures the current peak value in real time and linearly fits the falling segment for prediction. Before the current approaches the transferable threshold, the main circuit breaker is tripped in advance. At the predicted moment, the transfer thyristor is triggered to inject a high-frequency oscillating current into the LC circuit to counteract the main circuit breaker current, promoting zero-crossing arc extinguishing. The fault current is then transferred to a current-limiting branch before being disconnected and isolated, achieving rapid and safe low-frequency short-circuit clearing.

[0007] A current transfer circuit breaker control method, the method being used for interrupting low-frequency short-circuit current during back-to-back startup of pumped storage units, includes the following steps:

[0008] Step 1: Collect the three-phase voltage signal U on the drive side during the back-to-back start-up process using the current transformer and voltage transformer devices configured at the pumped-storage unit site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ;

[0009] Step 2: The fault discrimination algorithm based on the fusion of multiple electrical quantities processes the collected voltage and current signals on the drive side to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, return to Step 1 to continue the acquisition and monitoring.

[0010] Step 3: The fault discrimination algorithm based on the fusion of multiple electrical quantities processes the collected voltage and current signals on the driven side to determine whether a short circuit fault has occurred on the driven side; if a short circuit fault is not confirmed on the driven side, return to step 1 to continue the acquisition and monitoring.

[0011] Step 4: Execute the fault clearing process: After determining that a short circuit fault has occurred on both the driving side and the driven side during the back-to-back start-up process, the timing of sending the main disconnection command, the timing of the transfer thyristor conduction, and the timing of the disconnection switch opening are calculated based on the collected current signals. Signals are sent at the corresponding times to complete the clearing of the fault current.

[0012] In the method described, step 2 includes,

[0013] Step 2.1: Process the acquired voltage and current signals on the drive side to calculate the phase voltage difference U between phase A and phase B. AB1 The phase voltage difference U between phase A and phase C AC1 The phase voltage difference U between phase B and phase C BC1 The zero-sequence current I of phase A is calculated. 0A1 Phase B zero-sequence current I 0B1 C-phase zero-sequence current I 0C1 Phase A negative sequence current I 2A1 Phase B negative sequence current I 2B1 C-phase negative sequence current I 2C1 ;

[0014] Step 2.2: Calculate the fault confidence level (fault_core) based on the collected electrical signals from the drive side. When a phase voltage meets the near-zero condition, a single-phase ground-to-ground metallic short-circuit fault is identified, and the fault confidence level (fault_core) increases by 1. When two phase voltages simultaneously meet the near-zero condition, the fault range is wider and the short-circuit probability is higher, increasing the fault confidence level (fault_core) by 2. When all three phase voltages meet the near-zero condition, the most severe three-phase short-circuit fault is likely, indicating a higher fault severity, and the fault confidence level (fault_core) increases by 3. When any phase-to-phase voltage difference meets the near-zero condition, an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit is considered, increasing the fault confidence level (fault_core) by 1. When any phase current exceeds the setting threshold, an overcurrent-type short circuit is considered to have occurred, increasing the fault confidence level (fault_core) by 1. When zero-sequence current or negative-sequence current exceeds its respective setting threshold, ground-related or asymmetrical enhanced fault characteristics are identified, respectively, increasing the fault confidence level (fault_core) by 1.

[0015] The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error.

[0016] Step 2.3: Determine whether the fault confidence score fault_core exceeds the threshold. Set the fault confidence score threshold fault_thread according to the simulation calculation. If the calculated fault confidence score fault_core is greater than the fault confidence score threshold fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out.

[0017] Step 2.4, anti-bouncing measures to prevent algorithm misjudgment: After detecting that the fault confidence level fault_core exceeds the fault confidence level threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, it is confirmed that a short circuit fault has occurred on the drag-side line.

[0018] In the method described, step 3 includes,

[0019] Step 3.1: The fault detection algorithm employs dual-sided redundant criteria to increase reliability. Only after the driving side determines that a short-circuit fault has occurred will the driven side be assessed.

[0020] Step 3.2: Process the acquired voltage and current signals on the driven side to calculate the phase voltage difference U between phase A and phase B. AB2 The phase voltage difference U between phase A and phase C AC2 The phase voltage difference U between phase B and phase C BC2 The zero-sequence current I of phase A is calculated. 0A2 Phase B zero-sequence current I 0B2 C-phase zero-sequence current I 0C2 Phase A negative sequence current I 2A2 Phase B negative sequence current I 2B2 C-phase negative sequence current I 2C2 ,

[0021] Step 3.3: Calculate the fault confidence level (fault_core) based on the collected electrical signals from the driven side. When a phase voltage is detected to meet the near-zero condition, a single-phase ground-to-ground metallic short-circuit fault is determined, and the fault confidence level (fault_core) increases by 1. When two phase voltages simultaneously meet the near-zero condition, it indicates a wider fault range and a higher probability of short circuit, and the fault confidence level (fault_core) increases by 2. When all three phase voltages meet the near-zero condition, it indicates the most severe three-phase short-circuit fault is likely, and the fault severity is higher. The fault confidence level (fault_core) increases by 3. Simultaneously, when any phase-to-phase voltage difference is detected to meet the near-zero condition, it is considered an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit, and the fault confidence level (fault_core) increases by 1. When any phase current is detected to exceed the setting threshold, it is considered an overcurrent-type short circuit, and the fault confidence level (fault_core) increases by 1. When zero-sequence current or negative-sequence current is detected to exceed its respective setting threshold, it represents ground-related or asymmetric enhanced fault characteristics, and the fault confidence level (fault_core) increases by 1.

[0022] The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error.

[0023] Step 3.4: Determine whether the fault confidence score fault_core exceeds the threshold. Set the fault confidence score threshold fault_thread according to the simulation calculation. If the calculated fault confidence score fault_core is greater than the fault confidence score threshold fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out.

[0024] Step 3.5, anti-bouncing measures to prevent algorithm misjudgment: After detecting that the fault confidence score fault_core exceeds the fault confidence score threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, it is confirmed that a short circuit fault has occurred on the dragged side line.

[0025] In the method described, step 4 includes,

[0026] Step 4.1: Set up a scrolling window for current acquisition. Set up a current acquisition window with three current points, denoted as i1, i2, and i3. Acquire i1, i2, and i3 sequentially according to time. i3 represents the latest current data acquired in real-time. When an updated current point i4 is acquired, discard current point i1, assign the value of current point i2 back to current point i1, assign the value of current point i3 back to current point i2, and assign the updated current point i4 back to current point i3. This completes one scrolling of the window, ensuring that the acquisition window always stores the three latest current points.

[0027] Step 4.2, determine the peak current I max Determine if there is a peak point among the three current points within the current acquisition window. If the three current points satisfy |i1|<|i2| and |i2|>|i3|, then current point i2 is determined to be the current peak value I. max ,

[0028] Step 4.3: Perform linear fitting on the falling edge of the current. Starting from the current peak value, collect a preset number of current points according to the time sequence as raw data for linear fitting to obtain the falling edge current data.

[0029] Step 4.4: Find the transfer current threshold in the fitted data and obtain the transfer time t. zy The fitted current data is iterated to find the transfer current threshold, and the transfer time corresponding to the transfer current threshold point is recorded. The transfer current threshold is tuned by the inductance and capacitance parameters of the transfer branch.

[0030] Step 4.5, calculate the main circuit breaker tripping time t. zdk Time t of disconnection switch s1 The main circuit breaker tripping time t zdk It should be earlier than the transition time t zy A preset delay Δt1, the disconnecting switch opening time t s1 It should be later than the transition time t zy A preset delay Δt2, Δt1 and Δt2 should be adjusted according to the actual site conditions.

[0031] Step 4.6, according to the chronological order, at the main disconnection time t zdk The controller sends a main circuit breaker tripping command at transfer time t. zy The controller sends a transfer branch conduction command at the disconnecting switch opening time t. s1 The controller sends the S1 trip command.

[0032] In the method described, the preset number of current points collected in step 4.3 is 50.

[0033] In the method described, the preset delay Δt1 is used to ensure that the main break obtains the necessary opening distance and medium recovery conditions before the transfer action occurs.

[0034] In the method described, the preset delay Δt2 is used to ensure that the fault current is completely transferred to the current-limiting resistor branch and attenuated before isolation is performed.

[0035] A current transfer circuit breaker control system, the system being used for interrupting low-frequency short-circuit current during back-to-back startup of pumped storage units, comprising:

[0036] The data acquisition module is used to acquire the three-phase voltage signal U on the drive side during the back-to-back start-up process of the pumped-storage unit through the current transformers and voltage transformers configured at the site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ;

[0037] The drive-side fault detection module is used to process the acquired voltage and current signals of the drive side based on a fault detection algorithm that integrates multiple electrical quantities, and to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, the acquisition module is triggered to continue acquisition and monitoring.

[0038] The driven-side fault discrimination module is used to process the acquired voltage and current signals of the driven side based on a multi-electrical quantity fusion fault discrimination algorithm after the driven-side fault discrimination module confirms that a short-circuit fault has occurred on the driven side, and to determine whether a short-circuit fault has occurred on the driven side; if a short-circuit fault has not been confirmed on the driven side, the acquisition module is triggered to continue acquisition and monitoring.

[0039] The fault clearance execution module is used to calculate the main disconnection command sending time, the transfer thyristor conduction time, and the disconnection switch opening time based on the collected current signal after the fault discrimination module on the driven side confirms that a short circuit fault has occurred on the driven side and the fault discrimination module on the driven side confirms that a short circuit fault has occurred on the driven side. Then, it sends signals at the corresponding times to complete the clearance of the fault current.

[0040] A computer storage medium including computer instructions that, when run on a computer, cause the computer to perform the method.

[0041] An electronic device, the electronic device comprising:

[0042] A memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the method when executing the program.

[0043] Compared with the prior art, the present invention has the following advantages:

[0044] This invention achieves controllable zero-crossing and reliable interruption of low-frequency short-circuit current: by triggering the transfer thyristor to release high-frequency oscillating current in the transfer LC circuit, the current at the main break point is instantaneously canceled and forced to form a current zero-crossing. This fundamentally eliminates the reliance on natural zero-crossing at low frequencies, solving the interruption problem of "long zero-crossing time, arc extinguishing failure, and high risk of reignition" caused by the superimposed DC component during the low-speed phase of back-to-back startup. The interruption timing is prediction-driven, significantly improving the success rate and consistency of the action: after detecting the current peak, the falling segment is linearly fitted to predict the moment when the current reaches the transferable threshold in advance, and the main break point is opened before this moment. The transfer branch is triggered synchronously at the predicted moment, achieving coordinated control of "establishing the opening gap first, then promoting zero-crossing," solving the problem of traditional fixed-delay strategies being sensitive to operating conditions and prone to missing. The problem of optimal interruption window; multi-electrical quantity fusion to improve short-circuit discrimination sensitivity and robustness: comprehensively considering the phase voltage zeroing degree, phase-to-phase voltage difference, three-phase current RMS value, zero-sequence component, and negative-sequence component characteristics, the fault confidence is calculated in a weighted fusion form, avoiding the problem of misjudgment and missed judgment under low frequency, waveform distortion, or DC bias conditions by a single current threshold, and improving the adaptability to various short-circuit modes; dual-sided redundancy verification to reduce the risk of single-sided misjudgment: when both the driving side and the driven side have measurement conditions, a consistency check is introduced. The subsequent control logic is only executed when both the driving side and the driven side determine that a fault has occurred, so that the sensitive interruption action no longer depends on a single-sided signal, solving the risk of misjudgment caused by single-sided measurement anomalies or transient distortions, thereby improving the overall safety margin of the back-to-back start-up process. This strategy addresses the problems of traditional practices, such as simultaneously tripping two excitation circuit breakers to wait for the rotor to stop before opening the GCB (Generator Circuit Breaker), which can lead to the loss of electromagnetic torque in the driven unit and continuous acceleration, potentially causing runaway when a single-sided excitation disconnection fails. It offers advantages such as reliable interruption under low-frequency conditions, reduced reliance on the low-frequency interruption capability of the circuit breaker itself, rapid prediction and timing control, reduced system risk, and compatibility with current-transfer circuit breaker hardware. This overcomes the shortcomings of existing technologies in short-circuit clearing during back-to-back startup of pumped-storage units.

[0045] Various other advantages and benefits of the present invention will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiments below. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. It is obvious that the drawings described below are merely some embodiments of the invention, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort. Furthermore, the same reference numerals denote the same parts throughout the drawings. Attached Figure Description

[0046] Figure 1 This is a schematic diagram of a simulation model of the start-up and grid connection of a pumped storage unit for a current transfer circuit breaker control method disclosed in this invention;

[0047] Figure 2 This is a schematic diagram of a current-transfer circuit breaker topology applicable to a current-transfer circuit breaker control method disclosed in this invention.

[0048] Figure 3 This is a general flowchart of a current transfer circuit breaker control method disclosed in this invention;

[0049] Figure 4 This is a flowchart of a short-circuit fault discrimination algorithm in a current transfer circuit breaker control method disclosed in this invention;

[0050] Figure 5 This is a flowchart of the fault clearing process in a current transfer circuit breaker control method disclosed in this invention;

[0051] Figure 6 This is a schematic diagram of the transfer of oscillating current in a current transfer circuit breaker control method disclosed in this invention;

[0052] Figure 7 This is a schematic diagram of the interrupting current in a current transfer circuit breaker control method disclosed in this invention.

[0053] The present invention will be further explained below with reference to the accompanying drawings and embodiments. Detailed Implementation

[0054] Specific embodiments of the invention will now be described in more detail with reference to the accompanying drawings. While specific embodiments of the invention are shown in the drawings, it should be understood that the invention may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0055] It should be noted that certain terms are used in the specification and claims to refer to specific components. Those skilled in the art will understand that different terms may be used to refer to the same component. This specification and claims do not distinguish components based on differences in terminology, but rather on differences in function. The terms "comprising" or "including" used throughout the specification and claims are open-ended and should be interpreted as "comprising but not limited to." The following descriptions are preferred embodiments for carrying out the invention; however, these descriptions are for the purpose of understanding the general principles of the specification and are not intended to limit the scope of the invention. The scope of protection of this invention is determined by the appended claims.

[0056] To facilitate understanding of the embodiments of the present invention, further explanations and descriptions will be provided below with reference to the accompanying drawings and specific embodiments. The accompanying drawings do not constitute a limitation on the embodiments of the present invention.

[0057] like Figures 1 to 7 As shown, a current transfer circuit breaker control method is used for interrupting low-frequency short-circuit current during the back-to-back startup process of pumped storage units, comprising the following steps:

[0058] Step 1: Collect the three-phase voltage signal U on the drive side during the back-to-back start-up process using the current transformer and voltage transformer devices configured at the pumped-storage unit site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ;

[0059] Step 2: The fault discrimination algorithm based on the fusion of multiple electrical quantities processes the collected voltage and current signals on the drive side to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, return to Step 1 to continue the acquisition and monitoring.

[0060] Step 3: The fault discrimination algorithm based on the fusion of multiple electrical quantities processes the collected voltage and current signals on the driven side to determine whether a short circuit fault has occurred on the driven side; if a short circuit fault is not confirmed on the driven side, return to step 1 to continue the acquisition and monitoring.

[0061] Step 4: Execute the fault clearing procedure: After determining that a short-circuit fault has occurred on both the driving side and the driven side during the back-to-back startup process, the timing of sending the main disconnector tripping command, the timing of the transfer thyristor conduction, and the timing of the disconnector switch tripping are calculated based on the collected current signals. Signals are then sent at the corresponding times to complete the fault current clearing. The low-frequency short-circuit current is 20-45Hz.

[0062] In a preferred embodiment of the method, step 2 includes,

[0063] Step 2.1: Process the acquired voltage and current signals on the drive side to calculate the phase voltage difference U between phase A and phase B. AB1 The phase voltage difference U between phase A and phase C AC1 The phase voltage difference U between phase B and phase C BC1 The zero-sequence current I of phase A is calculated. 0A1 Phase B zero-sequence current I 0B1 C-phase zero-sequence current I 0C1 Phase A negative sequence current I 2A1 Phase B negative sequence current I 2B1 C-phase negative sequence current I 2C1 ;

[0064] Step 2.2: Calculate the fault confidence level (fault_core) based on the collected electrical signals on the drive side. When a phase voltage is detected to meet the near-zero condition, that is, when the signs of two consecutive voltage signals change and the product of two adjacent voltage signals is negative, it is determined that a single-phase grounding metallic short circuit fault has occurred, and a phase is grounded through a very small resistor that is approximately equal to zero. The fault confidence score increases by 1. When two phase voltages simultaneously meet the near-zero condition, the fault range is wider and the short circuit probability is higher, increasing the fault confidence score by 2. When all three phase voltages meet the near-zero condition, the most severe three-phase short circuit fault is likely, indicating a higher fault severity, increasing the fault confidence score by 3. When any phase-to-phase voltage difference meets the near-zero condition, it is considered an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit, increasing the fault confidence score by 1. When any phase current exceeds the setting threshold, it is considered an overcurrent-type short circuit, increasing the fault confidence score by 1. When zero-sequence current or negative-sequence current exceeds its respective setting threshold, it indicates ground-related or asymmetrical enhanced fault characteristics, increasing the fault confidence score by 1.

[0065] The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error.

[0066] Step 2.3: Determine whether the fault confidence score fault_core exceeds the threshold. Set the fault confidence score threshold fault_thread according to the simulation calculation. If the calculated fault confidence score fault_core is greater than the fault confidence score threshold fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out.

[0067] Step 2.4, anti-bouncing measures to prevent algorithm misjudgment: After detecting that the fault confidence level fault_core exceeds the fault confidence level threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, it is confirmed that a short circuit fault has occurred on the drag-side line.

[0068] In a preferred embodiment of the method, step 3 includes,

[0069] Step 3.1: The fault detection algorithm employs dual-sided redundant criteria to increase reliability. Only after the driving side determines that a short-circuit fault has occurred will the driven side be assessed.

[0070] Step 3.2: Process the acquired voltage and current signals on the driven side to calculate the phase voltage difference U between phase A and phase B. AB2 The phase voltage difference U between phase A and phase C AC2 The phase voltage difference U between phase B and phase C BC2 The zero-sequence current I of phase A is calculated. 0A2 Phase B zero-sequence current I 0B2 C-phase zero-sequence current I 0C2 Phase A negative sequence current I 2A2 Phase B negative sequence current I 2B2 C-phase negative sequence current I 2C2 ,

[0071] Step 3.3: Calculate the fault confidence level (fault_core) based on the collected electrical signals from the driven side. When a phase voltage is detected to meet the near-zero condition, a single-phase ground-to-ground metallic short-circuit fault is determined, and the fault confidence level (fault_core) increases by 1. When two phase voltages simultaneously meet the near-zero condition, it indicates a wider fault range and a higher probability of short circuit, and the fault confidence level (fault_core) increases by 2. When all three phase voltages meet the near-zero condition, it indicates the most severe three-phase short-circuit fault is likely, and the fault severity is higher. The fault confidence level (fault_core) increases by 3. Simultaneously, when any phase-to-phase voltage difference is detected to meet the near-zero condition, it is considered an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit, and the fault confidence level (fault_core) increases by 1. When any phase current is detected to exceed the setting threshold, it is considered an overcurrent-type short circuit, and the fault confidence level (fault_core) increases by 1. When zero-sequence current or negative-sequence current is detected to exceed its respective setting threshold, it represents ground-related or asymmetric enhanced fault characteristics, and the fault confidence level (fault_core) increases by 1.

[0072] The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error.

[0073] Step 3.4: Determine whether the fault confidence score fault_core exceeds the threshold. Set the fault confidence score threshold fault_thread according to the simulation calculation. If the calculated fault confidence score fault_core is greater than the fault confidence score threshold fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out.

[0074] Step 3.5, anti-bouncing measures to prevent algorithm misjudgment: After detecting that the fault confidence score fault_core exceeds the fault confidence score threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, it is confirmed that a short circuit fault has occurred on the dragged side line.

[0075] In a preferred embodiment of the method, step 4 includes,

[0076] Step 4.1: Set up a scrolling window for current acquisition. Set up a current acquisition window with three current points, denoted as i1, i2, and i3. Acquire i1, i2, and i3 sequentially according to time. i3 represents the latest current data acquired in real-time. When an updated current point i4 is acquired, discard current point i1, assign the value of current point i2 back to current point i1, assign the value of current point i3 back to current point i2, and assign the updated current point i4 back to current point i3. This completes one scrolling of the window, ensuring that the acquisition window always stores the three latest current points.

[0077] Step 4.2, determine the peak current I max Determine if there is a peak point among the three current points within the current acquisition window. If the three current points satisfy |i1|<|i2| and |i2|>|i3|, then current point i2 is determined to be the current peak value I. max ,

[0078] Step 4.3: Perform linear fitting on the falling edge of the current. Starting from the current peak value, collect a preset number of current points according to the time sequence as raw data for linear fitting to obtain the falling edge current data.

[0079] Step 4.4: Find the transfer current threshold in the fitted data and obtain the transfer time t. zy The fitted current data is iterated to find the transfer current threshold, and the transfer time corresponding to the transfer current threshold point is recorded. The transfer current threshold is tuned by the inductance and capacitance parameters of the transfer branch.

[0080] Step 4.5, calculate the main circuit breaker tripping time t. zdk Time t of disconnection switch s1 The main circuit breaker tripping time t zdk It should be earlier than the transition time t zy A preset delay Δt1, the disconnecting switch opening time t s1 It should be later than the transition time t zy A preset delay Δt2, Δt1 and Δt2 should be adjusted according to the actual site conditions.

[0081] Step 4.6, according to the chronological order, at the main disconnection time t zdk The controller sends a main circuit breaker tripping command at transfer time t. zy The controller sends a transfer branch conduction command at the disconnecting switch opening time t. s1 The controller sends an S1 trip command. The schematic diagram of the transfer oscillation current and the corresponding signal transmission for executing the above steps are shown below. Figure 6 As shown in the diagram, the interrupting current is as follows: Figure 7 As shown.

[0082] In a preferred embodiment of the method, the preset number of current points collected in step 4.3 is 50.

[0083] In a preferred embodiment of the method, the preset delay Δt1 is used to ensure that the main break obtains the necessary opening distance and medium recovery conditions before the transfer action occurs.

[0084] In a preferred embodiment of the method, the preset delay Δt2 is used to ensure that the fault current is completely transferred to the current-limiting resistor branch and attenuated before isolation is performed.

[0085] In one embodiment, the present invention also discloses a current transfer circuit breaker control system for interrupting low-frequency short-circuit currents during back-to-back startup of pumped storage units, comprising:

[0086] The data acquisition module is used to acquire the three-phase voltage signal U on the drive side during the back-to-back start-up process of the pumped-storage unit through the current transformers and voltage transformers configured at the site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ;

[0087] The drive-side fault detection module is used to process the acquired voltage and current signals of the drive side based on a fault detection algorithm that integrates multiple electrical quantities, and to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, the acquisition module is triggered to continue acquisition and monitoring.

[0088] The driven-side fault discrimination module is used to process the acquired voltage and current signals of the driven side based on a multi-electrical quantity fusion fault discrimination algorithm after the driven-side fault discrimination module confirms that a short-circuit fault has occurred on the driven side, and to determine whether a short-circuit fault has occurred on the driven side; if a short-circuit fault has not been confirmed on the driven side, the acquisition module is triggered to continue acquisition and monitoring.

[0089] The fault clearance execution module is used to calculate the main disconnector tripping command sending time, the transfer thyristor conduction time, and the disconnector tripping time based on the collected current signal after the fault discrimination module on the driven side confirms a short-circuit fault on the driven side and the fault discrimination module on the driven side confirms a short-circuit fault on the driven side, and then send signals at the corresponding times to complete the fault current clearance. Furthermore, this invention also discloses a system for executing the method described in any of the preceding embodiments, comprising:

[0090] The main circuit breaker is used to carry normal operating current and to perform tripping operation in case of a fault.

[0091] The current transfer branch, connected in parallel with the main break, consists of a transfer capacitor, a transfer inductor, and two anti-parallel transfer thyristors forming a high-frequency oscillation circuit, used to release high-frequency oscillation current into the main circuit during the transfer operation;

[0092] A current-limiting resistor branch is connected in parallel with the current transfer branch to dissipate fault current energy after the current transfer is completed.

[0093] The disconnecting switch S1 is connected in series in the current-limiting resistor branch and is used to perform complete isolation after the current transfer is completed.

[0094] The controller, electrically connected to the main disconnect, the transfer thyristor, and the disconnect switch S1, is used to execute the method described.

[0095] A computer storage medium including computer instructions that, when executed on a computer, cause the computer to perform the methods described in any of the preceding embodiments.

[0096] An electronic device, the electronic device comprising:

[0097] Memory, processor, and computer programs stored in memory and executable on the processor, wherein,

[0098] When the processor executes the program, it implements the method described in any of the preceding embodiments.

[0099] In one embodiment, this invention proposes a current-transfer circuit breaker control method for back-to-back startup of pumped storage units. This method enables controllable zero-crossing and reliable interruption of low-frequency fault currents during the low-speed phase of unit startup when a short circuit occurs. The hardware topology employs a parallel structure of the main circuit breaker and the current transfer branch. The transfer branch consists of a transfer capacitor, a transfer inductor, and two anti-parallel transfer thyristors forming a high-frequency oscillation circuit. A current-limiting resistor branch and a series disconnect switch S1 are configured to achieve complete isolation and energy dissipation after the current transfer is complete. The controller first establishes a short-circuit criterion, employing a multi-electrical quantity fusion short-circuit discrimination algorithm: it collects and calculates the three-phase voltage, phase-to-phase voltage difference, three-phase current RMS value, and zero / negative sequence component characteristics, and calculates the fault confidence score (fault_score) according to a preset threshold. A short-time confirmation window (T_confirm) is set, requiring the fault_score to continuously exceed the threshold within the window before a short-circuit fault is determined. Furthermore, electrical signals are measured and collected on both the driving and driven sides, introducing consistent redundant verification logic on both sides. After confirming a short circuit, the controller tracks the fault current waveform in real time: upon detecting a current peak, it selects a sample of the falling segment for linear fitting and extrapolates to predict the future current trajectory; simultaneously, based on the parameters of the transfer capacitor and transfer inductor, it calculates the transfer current threshold that can effectively offset the fault current. After predicting the time when the current will reach its peak, the controller issues a main circuit breaker tripping command at a preset time Δt1 before the transfer time, ensuring that the main circuit breaker has the necessary opening distance and dielectric recovery conditions before the transfer action occurs; at the transfer time, it synchronously triggers transfer thyristor 1 and transfer thyristor 2, causing the LC branch to release a high-frequency oscillating current into the main circuit, instantaneously offsetting the main circuit breaker current and forcing it to cross zero, thereby achieving rapid arc extinguishing and interruption. The fault current then transfers to the current-limiting resistor branch and is significantly reduced. Subsequently, after a delay of approximately Δt2, it issues an S1 tripping command, completely cutting off the remaining current and completing isolation, thus achieving rapid, controllable, and safe clearing of the back-to-back low-frequency short-circuit current. The above strategy reduces the reliance on natural zero crossing by coordinating the timing of "reliable discrimination - current prediction - early tripping - transfer to zero - subsequent isolation", and adapts to the short-circuit current interruption requirements of low frequency and significant DC bias.

[0100] A simulation model of the pumped storage unit's startup and grid connection was built in the MATLAB / Simulink environment. A schematic diagram of the simulation model is shown below. Figure 1 As shown, its core components include: a synchronous generator module simulating a pumped-storage unit, a three-phase current and voltage acquisition module, a GCB-X module (X=A, B, C) integrating the main break, transfer branch, and S1, a transformer module, a fault module, and an infinite system module.

[0101] In this simulation embodiment, the present invention provides a current transfer circuit breaker control method for interrupting low-frequency short-circuit current during the back-to-back startup process of pumped storage units, comprising the following steps:

[0102] Step 1: Collect the three-phase voltage signal U on the drive side during the back-to-back start-up process using the current transformer and voltage transformer devices configured at the pumped-storage unit site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ;

[0103] Step 1.1: The three-phase current and voltage data are measured by the three-phase current and voltage acquisition module. The three-phase current and voltage acquisition module is connected in series to the outlet of the pumped storage unit to measure the three-phase current and voltage data of the pumped storage unit.

[0104] Step 1.2: Acquire three-phase current and voltage data through the scope module. Input the three-phase voltage and current data measured by the three-phase current and voltage acquisition module into the scope module. Set the data recording to the work area in the scope module. This can realize the acquisition of three-phase voltage and current data as a time-based structure to the MATLAB work area for subsequent algorithm use.

[0105] Step 2: Set up a fault module to simulate a short-circuit fault during the startup of the pumped-storage unit in the synchronous generator module, generating a short-circuit current.

[0106] Step 3: Based on the fault discrimination algorithm of multi-electrical quantity fusion, process the collected raw voltage and current signals to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, return to step 1 to continue the acquisition and monitoring.

[0107] Step 4: Based on the fault discrimination algorithm of multi-electrical quantity fusion, process the collected raw voltage and current signals to determine whether a short circuit fault has occurred on the driven side; if a short circuit fault is not confirmed on the driven side, return to step 1 to continue the acquisition and monitoring.

[0108] Step 5: Execute the fault clearing process: After determining that a short circuit fault has occurred on both the driving side and the driven side during the back-to-back start-up process, the timing of sending the main disconnection command, the timing of the transfer thyristor conduction, and the timing of the disconnection switch opening are calculated based on the collected current signals. Signals are sent at the corresponding times to complete the clearing of the fault current.

[0109] Step 5.1: Set the action time of the breaker module simulating the main breakpoint inside the GCB-X module to the variable t. zdk , where t zdk These are variables calculated in the fault clearance process algorithm.

[0110] Step 5.2: Set the operating time of the thyristor VT module, which simulates the thyristor inside the GCB-X module, to the variable t. zy , where t zy These are variables calculated in the fault clearance process algorithm.

[0111] Step 5.3, set the action time of the breaker module of the simulated isolating switch S1 inside the GCB-X module to the variable t. s1 , where t s1 These are variables calculated in the fault clearance process algorithm.

[0112] See Figure 3 In another embodiment, the fault discrimination algorithm based on multi-electrical quantity fusion includes the following steps:

[0113] Step 1: Process the acquired raw voltage and current signals from the drive side.

[0114] The phase voltage difference U between phase A and phase B is calculated. AB1 The phase voltage difference U between phase A and phase C AC1 The phase voltage difference U between phase B and phase C BC1 The zero-sequence current I of phase A is calculated. 0A1 Phase B zero-sequence current I 0B1 C-phase zero-sequence current I 0C1 Phase A negative sequence current I 2A1 Phase B negative sequence current I 2B1 C-phase negative sequence current I 2C1 .

[0115] Step 2: Calculate the fault confidence level (fault_core) based on the collected electrical signals from the drive side.

[0116] When a phase voltage is detected to meet the near-zero condition, a single-phase-to-ground metallic short-circuit fault is determined, and the fault confidence score (fault_core) increases by 1. When two phase voltages simultaneously meet the near-zero condition, it indicates a wider fault range and a higher probability of a short circuit, increasing the fault confidence score by 2. When all three phase voltages meet the near-zero condition, it indicates the most severe three-phase short-circuit fault, with a higher fault severity, and the fault confidence score increases by 3. Simultaneously, when any phase-to-phase voltage difference is detected to meet the near-zero condition, it is considered an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit, increasing the fault confidence score by 1. Furthermore, when any phase current exceeds the set threshold, it is considered an overcurrent-type short circuit, increasing the fault confidence score by 1. When zero-sequence current or negative-sequence current exceeds its respective set threshold, it indicates ground-related or asymmetrical enhanced fault characteristics, respectively, increasing the fault confidence score by 1. The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error.

[0117] Step 3: Determine whether the fault confidence score (fault_core) exceeds the threshold.

[0118] A fault confidence threshold, fault_thread, is set based on a large number of simulation calculations. If the calculated fault confidence score, fault_core, is greater than the fault confidence threshold, fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out.

[0119] Step 4: Debouncing measures to prevent algorithm misjudgment

[0120] After detecting that the fault confidence level fault_core exceeds the fault confidence level threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, a short circuit fault is confirmed to have occurred on the drag-side line.

[0121] Figure 4 This is a flowchart of the fault clearing process in the control strategy described in this invention. The fault clearing process is as follows:

[0122] Step 1, Set up a scrolling window to collect current.

[0123] Three current points are set up as a current acquisition window, denoted as i1, i2, and i3 respectively. i1, i2, and i3 are acquired sequentially in chronological order, with i3 representing the latest real-time current data. When an updated current point i4 is acquired, current point i1 is discarded, and the values ​​of current points i2 and i3 are assigned back to i1. The updated current point i4 is then assigned back to i3, completing one window scrolling cycle and ensuring that the acquisition window always stores the three latest current points.

[0124] Step 2, determine the peak current I max

[0125] Determine if there is a peak point among the three current points within the current acquisition window. If the three current points satisfy |i1|<|i2| and |i2|>|i3|, then current point i2 is determined to be the current peak value I. max .

[0126] Step 3: Perform linear fitting on the falling edge of the current.

[0127] Starting from the peak current, 50 current points were collected in sequence as raw data for linear fitting to obtain the falling edge current data.

[0128] Step 4: Find the transfer current threshold in the fitted data and obtain the transfer time t. zy

[0129] The fitted current data is iterated to find the transfer current threshold and the transfer time corresponding to the transfer current threshold is recorded. The transfer current threshold needs to be tuned by the inductance and capacitance parameters of the transfer branch.

[0130] Step 5, calculate the main circuit breaker tripping time t. zdk Time t of disconnection switch s1

[0131] Main circuit breaker tripping time t zdk It should be earlier than the transition time t zy A preset delay Δt1, the disconnecting switch opening time t s1 It should be later than the transition time t zy A preset delay Δt2, Δt1 and Δt2 should be adjusted according to the actual situation on site.

[0132] Step 6: Send the signal described in the above steps at the corresponding time.

[0133] In chronological order, at the moment t of the main circuit breaker tripping... zdk The controller sends a main circuit breaker tripping command at transfer time t. zy The controller sends a transfer branch conduction command at the disconnecting switch opening time t. s1The controller sends the S1 trip command.

[0134] Furthermore, traditional short-circuit detection methods based on a single current threshold are prone to misjudgment or missed detection under low-frequency, severely distorted waveform, or DC bias conditions. This invention comprehensively collects multi-dimensional electrical characteristics such as the degree of phase voltage returning to zero, phase-to-phase voltage difference, effective phase current value, zero-sequence current, and negative-sequence current, and assigns different weights to calculate the fault confidence score (fault_core). This method significantly improves the sensitivity and robustness of short-circuit fault identification, accurately distinguishing short-circuit faults from normal operating fluctuations in the harsh electrical environment of low speed and strong transient interference during the early stages of back-to-back startup, avoiding protection maloperation or failure to operate. During back-to-back startup, electrical signal measurement conditions exist on both the driving and driven sides. This invention introduces a redundant criterion with bi-sided consistency, executing the subsequent disconnection procedure only when both sides determine that a short-circuit fault has occurred. This method effectively overcomes the risk of misjudgment caused by transient distortion, acquisition jitter, or local faults in single-sided measuring devices, fundamentally eliminating the possibility of erroneous circuit breaker operation due to signal abnormalities, and significantly improving the overall safety margin and reliability of the control strategy. The time window between the peak occurrence and zero-crossing moment of low-frequency short-circuit current is long and uncertain, making fixed-delay strategies difficult to adapt to changes in operating conditions. This invention employs a rolling window of three current points to detect the current peak value (Imax) in real time, and then uses the peak value as a starting point to collect 50 subsequent current points for linear fitting, extrapolating and predicting the moment when the current drops to the transfer current threshold (tzy). This method achieves rapid and accurate prediction of the future trajectory of the fault current, providing an accurate time reference for subsequent timing control and solving the problems of poor action consistency and missed breaking opportunities caused by the inability to predict the optimal breaking window in traditional methods. Based on the predicted transfer moment (tzy), the controller issues a main break tripping command in advance with a first preset delay (Δt1) before that moment, allowing the main break to obtain the necessary opening distance and prepare for dielectric recovery; simultaneously, at the predicted moment (tzy), two anti-parallel transfer thyristors are triggered, injecting high-frequency oscillating current into the LC circuit, forcing the main break current to cross zero and extinguish the arc. This method achieves precise timing coordination of "establishing the opening gap first, then forcing zero crossing," ensuring that the arc has sufficient arc-extinguishing gap when the transfer action occurs, avoiding arc reignition or interruption failure caused by forced transfer when the opening gap is insufficient. Addressing the core pain points of long natural zero-crossing intervals for low-frequency short-circuit currents and the difficulty of arc extinguishing in conventional circuit breakers, this invention utilizes an LC circuit composed of a transfer capacitor and a transfer inductor to release a high-frequency oscillating current at the moment of thyristor triggering. This oscillating current is superimposed on the main circuit current to form an instantaneous zero-crossing point. This method fundamentally eliminates the dependence on low-frequency natural zero crossings, enabling rapid and controllable current zero-crossing arc extinguishing even under extreme conditions where the current waveform deviates from a symmetrical sine wave for a long time and the DC component decays significantly and slowly, smoothly transferring the fault current to the current-limiting resistor branch.After the current is successfully transferred, the fault current flows through the current-limiting resistor branch, and its amplitude is significantly reduced. Then, after a second preset delay (Δt2), the disconnecting switch S1 is given a tripping command, achieving complete disconnection and isolation. This tiered processing method utilizes the current-limiting resistor to quickly dissipate fault energy, reducing the thermal and electrical stress impact on the circuit breaker. On the other hand, the delayed isolation ensures that the transfer process is completely completed, avoiding the disconnecting switch being tripped under load before the current has fully decayed, thereby protecting the equipment and extending its service life.

[0135] Although embodiments of the present invention have been described above in conjunction with the accompanying drawings, the present invention is not limited to the specific embodiments and application fields described above. The specific embodiments described above are merely illustrative and instructive, and not restrictive. Those skilled in the art can make many other forms based on the guidance of this specification and without departing from the scope of protection of the claims of the present invention, and all of these are within the scope of protection of the present invention.

Claims

1. A current transfer circuit breaker control method, characterized in that, The method is used for interrupting low-frequency short-circuit current during the back-to-back startup process of pumped storage units, and includes the following steps: Step 1: Collect the three-phase voltage signal U on the drive side during the back-to-back start-up process using the current transformer and voltage transformer devices configured at the pumped-storage unit back-to-back start-up site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ; Step 2: The fault discrimination algorithm based on the fusion of multiple electrical quantities processes the collected voltage and current signals on the drive side to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, return to Step 1 to continue the acquisition and monitoring. Step 3: After a short circuit fault occurs on the driven side, the voltage and current signals of the driven side are processed based on the fault discrimination algorithm of multi-electrical quantity fusion to determine whether a short circuit fault has occurred on the driven side; if a short circuit fault is not confirmed on the driven side, return to step 1 to continue the acquisition and monitoring. Step 4: Execute the fault clearing process: After confirming that a short circuit fault has occurred on both the driven side and the driven side, calculate the time when the main disconnector trips, the time when the transfer thyristor turns on, and the time when the disconnector trips based on the collected current signals, and send signals at the corresponding times to complete the clearing of the fault current.

2. The method according to claim 1, characterized in that, Step 2 includes, Step 2.1: Process the acquired voltage and current signals on the drive side to calculate the phase voltage difference U between phase A and phase B. AB1 The phase voltage difference U between phase A and phase C AC1 The phase voltage difference U between phase B and phase C BC1 The zero-sequence current I of phase A is calculated. 0A1 Phase B zero-sequence current I 0B1 C-phase zero-sequence current I 0C1 Phase A negative sequence current I 2A1 Phase B negative sequence current I 2B1 C-phase negative sequence current I 2C1 ; Step 2.2: Calculate the fault confidence level (fault_core) based on the collected electrical signals from the drive side. When a phase voltage is detected to meet the near-zero condition, a single-phase ground-to-ground metallic short-circuit fault is determined, and the fault confidence level (fault_core) increases by 1. When two phase voltages are detected to simultaneously meet the near-zero condition, it indicates a wider fault range and a higher probability of short circuit, and the fault confidence level (fault_core) increases by 2. When all three phase voltages meet the near-zero condition, it indicates the most severe three-phase short-circuit fault is likely, and the fault severity is higher, and the fault confidence level (fault_core) increases by 3. When any phase voltage difference is detected to meet the near-zero condition, it is considered an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit, and the fault confidence level (fault_core) increases by 1. When any phase current is detected to exceed the setting threshold, it is considered an overcurrent short circuit, and the fault confidence level (fault_core) increases by 1. When zero-sequence current or negative-sequence current is detected to exceed its respective setting threshold, it represents ground-related or asymmetric enhanced fault characteristics, and the fault confidence level fault_core increases by 1. The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error. Step 2.3: Determine whether the fault confidence score fault_core exceeds the threshold. Set the fault confidence score threshold fault_thread according to the simulation calculation. If the calculated fault confidence score fault_core is greater than the fault confidence score threshold fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out. Step 2.4, anti-bouncing measures to prevent algorithm misjudgment: After detecting that the fault confidence level fault_core exceeds the fault confidence level threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, it is confirmed that a short circuit fault has occurred on the drag-side line.

3. The method according to claim 1, characterized in that, Step 3 includes, Step 3.1: The fault detection algorithm employs dual-sided redundant criteria to increase reliability. Only after the driving side determines that a short-circuit fault has occurred will the driven side be assessed. Step 3.2: Process the acquired voltage and current signals on the driven side to calculate the phase voltage difference U between phase A and phase B. AB2 The phase voltage difference U between phase A and phase C AC2 The phase voltage difference U between phase B and phase C BC2 The zero-sequence current I of phase A is calculated. 0A2 Phase B zero-sequence current I 0B2 C-phase zero-sequence current I 0C2 Phase A negative sequence current I 2A2 Phase B negative sequence current I 2B2 C-phase negative sequence current I 2C2 , Step 3.3: Calculate the fault confidence level (fault_core) based on the collected electrical signals from the driven side. When a phase voltage is detected to meet the near-zero condition, a single-phase ground-to-ground metallic short-circuit fault is determined, and the fault confidence level (fault_core) increases by 1. When two phase voltages are detected to simultaneously meet the near-zero condition, it indicates a wider fault range and a higher probability of short circuit, and the fault confidence level (fault_core) increases by 2. When all three phase voltages meet the near-zero condition, it indicates the most severe three-phase short-circuit fault is likely, and the fault severity is higher, and the fault confidence level (fault_core) increases by 3. Simultaneously, when any phase-to-phase voltage difference is detected to meet the near-zero condition, it is considered an indication of a phase-to-phase short circuit or a two-phase-to-ground short circuit, and the fault confidence level (fault_core) increases by 1. When any phase current is detected to exceed the setting threshold, it is considered an overcurrent-type short circuit, and the fault confidence level (fault_core) increases by 1. When zero-sequence current or negative-sequence current is detected to exceed its respective setting threshold, it represents ground-related or asymmetric enhanced fault characteristics, and the fault confidence level fault_core increases by 1. The near-zero condition refers to the absolute value of the sampled value of the detected phase voltage or phase-to-phase voltage difference being less than a preset near-zero voltage threshold, and this state is maintained for at least three consecutive sampling points; the near-zero voltage threshold is preset based on the system's rated phase voltage and measurement error. Step 3.4: Determine whether the fault confidence score fault_core exceeds the threshold. Set the fault confidence score threshold fault_thread according to the simulation calculation. If the calculated fault confidence score fault_core is greater than the fault confidence score threshold fault_thread, it is considered that a short circuit fault may have occurred. However, at this time, the possibility of misjudging the fault due to jitter or missed data collection by the secondary monitoring equipment on the drag side cannot be ruled out. Step 3.5, anti-bouncing measures to prevent algorithm misjudgment: After detecting that the fault confidence score fault_core exceeds the fault confidence score threshold fault_thread, a timer is started. When the timer exceeds the preset time t_confirm, it is confirmed that a short circuit fault has occurred on the dragged side line.

4. The method according to claim 1, characterized in that, Step 4 includes, Step 4.1: Set up a scrolling window for current acquisition. Set up a current acquisition window with three current points, denoted as i1, i2, and i3. Acquire i1, i2, and i3 sequentially according to time. i3 represents the latest current data acquired in real-time. When a newer current point i4 is acquired, discard current point i1, assign the value of current point i2 back to current point i1, assign the value of current point i3 back to current point i2, and assign the updated current point i4 back to current point i3. This completes one scrolling of the window, ensuring that the acquisition window always stores the three latest current points. Step 4.2, determine the peak current I max Determine if there is a peak point among the three current points within the current acquisition window. If the three current points satisfy |i1|<|i2| and |i2|>|i3|, then current point i2 is determined to be the current peak value I. max , Step 4.3: Perform linear fitting on the falling edge of the current. Starting from the current peak value, collect a preset number of current points according to the time sequence as raw data for linear fitting to obtain the falling edge current data. Step 4.4: Find the transfer current threshold in the fitted data and obtain the transfer time t. zy The fitted current data is iterated to find the transfer current threshold, and the transfer time corresponding to the transfer current threshold point is recorded. The transfer current threshold is tuned by the inductance and capacitance parameters of the transfer branch. Step 4.5, calculate the main circuit breaker tripping time t. zdk Time t of disconnection switch s1 The main circuit breaker tripping time t zdk It should be earlier than the transition time t zy A preset delay Δt1, the disconnecting switch opening time t s1 It should be later than the transition time t zy A preset delay Δt2, Δt1 and Δt2 should be adjusted according to the actual site conditions. Step 4.6, according to the chronological order, at the main disconnection time t zdk The controller sends a main circuit breaker tripping command at transfer time t. zy The controller sends a transfer branch conduction command at the disconnecting switch opening time t. s1 The controller sends the S1 trip command.

5. The method according to claim 4, characterized in that, The preset number of current points collected in step 4.3 is 50.

6. The method according to claim 4, characterized in that, The preset delay Δt1 is used to ensure that the main break obtains the necessary opening distance and medium recovery conditions before the transfer action occurs.

7. The method according to claim 4, characterized in that, The preset delay Δt2 is used to ensure that the fault current is completely transferred to the current-limiting resistor branch and attenuated before isolation is performed.

8. A current transfer circuit breaker control system, characterized in that, The system is used for interrupting low-frequency short-circuit current during the back-to-back startup process of pumped storage units, including: The data acquisition module is used to acquire the three-phase voltage signal U on the drive side during the back-to-back start-up process of the pumped-storage unit through the current transformers and voltage transformers configured at the site. A1 U B1 U C1 The three-phase voltage signal U on the driven side A2 U B2 U C2 and the three-phase current signal I on the drive side. A1 I B1 I C1 The three-phase current signal I on the driven side A2 I B2 I C2 ; The drive-side fault detection module is used to process the acquired voltage and current signals of the drive side based on a fault detection algorithm that integrates multiple electrical quantities, and to determine whether a short circuit fault has occurred on the drive side; if a short circuit fault is not confirmed on the drive side, the acquisition module is triggered to continue acquisition and monitoring. The driven-side fault discrimination module is used to process the acquired voltage and current signals of the driven side based on a multi-electrical quantity fusion fault discrimination algorithm after the driven-side fault discrimination module confirms that a short-circuit fault has occurred on the driven side, and to determine whether a short-circuit fault has occurred on the driven side; if a short-circuit fault has not been confirmed on the driven side, the acquisition module is triggered to continue acquisition and monitoring. The fault clearance execution module is used to calculate the main disconnection command sending time, the transfer thyristor conduction time, and the disconnection switch opening time based on the collected current signal after the fault discrimination module on the driven side confirms that a short circuit fault has occurred on the driven side and the fault discrimination module on the driven side confirms that a short circuit fault has occurred on the driven side. The module then sends signals at the corresponding times to complete the clearance of the fault current.

9. A computer storage medium, characterized in that, The storage medium includes computer instructions that, when executed on a computer, cause the computer to perform the method as described in any one of claims 1-7.

10. An electronic device, characterized in that, The electronic device includes: Memory, processor, and computer programs stored in memory and executable on the processor, wherein, When the processor executes the program, it implements the method as described in any one of claims 1-7.

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