Battery voltage measurement and current equalization circuit based on two-wire system, battery management chip and power system

Abstract

The application discloses a battery voltage measurement and current equalization circuit based on two-wire system, a battery management chip and a power supply system. The battery voltage measurement and current equalization circuit comprises a voltage preprocessing module (31), a PWM module (32), a voltage measurement module (33) and a control module (34). The voltage preprocessing module (31) divides the voltage output by a battery (1) to generate a divided voltage signal, the PWM module (32) generates and outputs a PWM signal according to the divided voltage signal, and the control module (34) processes the PWM signal and then sends the PWM signal to a first controllable switch (21) of a controllable load module (2) to control the on-off duty ratio of the controllable load module (2), and controls the voltage measurement module (33) according to the PWM signal so that the voltage measurement module (33) only measures the divided voltage signal during the low level of the PWM signal. The application can ensure that the battery equalization current and the battery voltage have a high-reliability linear relationship.

Description

Technical Field

[0001] This invention belongs to the field of battery management technology, and in particular relates to battery voltage measurement and current balancing circuits or power management chips in power management systems of space systems such as satellites and spacecraft. Specifically, it refers to battery voltage measurement and current balancing circuits, battery management chips, and power systems that achieve a highly reliable linear relationship between battery balancing current and battery voltage under a two-wire system. Background Technology

[0002] A primary function of battery management is battery balancing. Currently, the most common balancing method is passive balancing, which involves connecting a rated load between the positive and negative terminals of the battery as needed to reduce the voltage. Typically, in the power management systems of space systems such as satellites and spacecraft, the batteries are located far from the battery management chip, requiring long wires to connect the positive and negative terminals of the battery to the chip.

[0003] Some existing battery management systems have designed special balancing algorithms to ensure that the average value of the balancing current is linearly related to the battery voltage, thereby ensuring the high efficiency of battery balancing.

[0004] Battery management chips need to be connected to the positive and negative terminals of the battery via long wires for voltage sampling and equalization. One existing method is the four-wire method, which uses two wires to connect each terminal to the battery management chip. One wire is used for battery equalization, and the other is used for battery voltage measurement. However, this method has the disadvantage of doubling the number of wires, increasing the number of wires and wiring complexity, and increasing material usage and the weight of the device.

[0005] Another existing method is to use a 2-wire connection, such as... Figure 1As shown, a power supply system with battery balancing function includes a battery 1, a controllable load module 2, and a battery voltage measurement and current balancing circuit 3. The battery voltage measurement and current balancing circuit 3 includes a voltage preprocessing module 31, a PWM module 32, and a voltage measurement module 33. In this scheme, the battery voltage measurement and current balancing circuit 3 is implemented in the battery management chip. A long wire connects the positive terminal of the battery 1 to one pin of the battery management chip, and another wire connects the negative terminal of the battery to another pin of the battery management chip. The voltage preprocessing module 31 is used to divide and filter the battery voltage. The PWM module 32 is used to generate a PWM signal based on the divided battery voltage signal. This PWM signal is used to control the duty cycle of the first controllable switch 21 of the controllable load module 2, thereby controlling the magnitude of the balancing current. In this case, voltage sampling and battery balancing share the same wire, which saves wire resources and simplifies wiring. However, due to the large balancing current and the long wire, if the voltage is measured simultaneously during the balancing period, the sampling terminal of the battery management chip will have an error introduced by the current IRdrop. This current IRdrop also affects the voltage value seen by the PWM module, thus affecting the balancing current.

[0006] To address this issue, equalization is typically stopped actively during voltage measurement and then restarted after the measurement is complete. However, in high-reliability power management systems, a highly reliable linear relationship between the equalization current and battery voltage is essential. Arbitrarily stopping battery equalization will disrupt this linear relationship, leading to algorithm errors. Summary of the Invention

[0007] (a) Technical problems to be solved The main purpose of this invention is to solve the problem of how to maintain a highly reliable linear relationship between the balanced current and the battery voltage in applications such as satellites and other space systems, where the distance between the battery and the battery management chip is relatively large, without increasing the wiring complexity. (II) Technical Solution To address the aforementioned technical problems, this invention proposes a battery voltage measurement and current balancing circuit, comprising a voltage preprocessing module, a PWM module, and a voltage measurement module. The voltage preprocessing module divides the battery output voltage to generate a voltage divider signal. The PWM module generates and outputs a PWM signal based on the voltage divider signal. The voltage measurement module measures the voltage of the voltage divider signal. According to this invention, the battery voltage measurement and current balancing circuit further includes a control module. The control module conditions and adapts the PWM signal for power drive and then sends it to a first controllable switch of the controllable load module to control the on / off duty cycle of the controllable load module, thereby adjusting the magnitude of the battery's output balancing current. The control module also controls the voltage measurement module based on the PWM signal so that it measures the voltage divider signal only during the low-level period of the PWM signal.

[0008] According to a preferred embodiment of the present invention, the PWM module includes a comparator, which includes a first input terminal, a second input terminal, and an output terminal. The second input terminal is connected to a ramp signal, and the output terminal is connected to the control module. The voltage preprocessing module includes a second controllable switch and a sample-and-hold unit. One end of the second controllable switch is connected to the voltage divider signal, and the other end is connected to the first input terminal of the comparator via the sample-and-hold unit. The control module is also used to control the on / off duty cycle of the second controllable switch in order to control the operation of the sample-and-hold unit.

[0009] According to a preferred embodiment of the present invention, the sampling period of the sample-and-hold unit is shorter than the period of the PWM signal.

[0010] According to a preferred embodiment of the present invention, the control module controls the on / off duty cycle of the second controllable switch, such that the sample-and-hold unit is turned on when the PWM signal changes from high level to low level and turned off when the PWM signal changes from low level to high level.

[0011] According to a preferred embodiment of the present invention, when the control module detects that the PWM signal has multiple consecutive low levels of insufficient duration, it inserts a low level of one cycle into the PWM signal, wherein the insufficient duration means that it is not enough to complete one sampling and holding operation.

[0012] According to a preferred embodiment of the present invention, when the control module detects that the PWM signal has more than n low levels of insufficient duration within a specific duration, it inserts a low level of one cycle into the PWM signal, where n≥2.

[0013] A second aspect of the present invention provides a battery management chip, including the aforementioned battery voltage measurement and current balancing circuit.

[0014] A third aspect of the present invention provides a power supply system comprising a battery, a controllable load module, and a battery management chip, wherein the positive terminal of the battery is connected to a pin of the battery management chip via a wire, and the negative terminal of the battery is connected to another pin of the battery management chip via another wire; the battery management chip is the aforementioned battery management chip.

[0015] According to a preferred embodiment of the present invention, there are multiple batteries and controllable load modules, each corresponding to a battery, and the battery management chip is connected to each battery. (III) Beneficial Effects This invention can ensure a highly reliable linear relationship between the battery equalization current and the battery voltage. Attached Figure Description

[0016] Figure 1 This is a modular architecture diagram of an existing power system with battery balancing function.

[0017] Figure 2 This is a schematic diagram of the voltage divider signal, ramp signal, and PWM signal in an existing power supply system with battery balancing function.

[0018] Figure 3 This is a module architecture diagram of an embodiment of the power system with battery balancing function of the present invention.

[0019] Figure 4 This is a schematic diagram of the signal waveform of a power system with battery balancing function according to the first embodiment of the present invention.

[0020] Figure 5 This is a schematic diagram of the signal waveform of a power system with battery balancing function according to the second embodiment of the present invention.

[0021] Figure 6 This is a schematic diagram of the signal waveform of a power system with battery balancing function according to the third embodiment of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the present invention clearer, the present invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0023] As mentioned above, Figure 1 This is a modular architecture diagram of an existing power system with battery balancing functionality. For example... Figure 1As shown, the voltage provided by battery 1 is connected to the battery voltage measurement and current balancing circuit 3 in the battery management chip via a long wire. The voltage preprocessing module 31 performs voltage division and filtering on the voltage provided by battery 1 to generate a voltage-divided signal. This voltage-divided signal is sent to the PWM module 32 and the voltage measurement module 33 respectively. The PWM module 32 includes a comparator 321 and a ramp signal generator (not shown). The voltage-divided signal is compared with a ramp signal generated by the ramp signal generator in the comparator to generate a PWM signal (pulse width modulation signal). The comparator 321 includes a first input terminal, a second input terminal, and an output terminal. The first input terminal is connected to the voltage-divided signal, the second input terminal is connected to the ramp signal, and the output terminal is connected to the first controllable switch 21 of the controllable load module 2.

[0024] Figure 2 This is a schematic diagram of the voltage divider signal, ramp signal, and PWM signal in an existing power supply system with battery balancing function. (Example) Figure 2 As shown, if the low level of the ramp signal is VL and the high level is VH, then within the range of VL to VH, the duty cycle of the PWM signal output by the comparator is... k The voltage of the voltage divider signal it receives V in A linear relationship, that is k = aV in + offset Where a is a coefficient, offset This is the bias constant.

[0025] exist Figure 1 In the illustrated scheme, a PWM signal is used to control the on / off state of the first controllable switch 21 of a controllable load module 2. If the voltage of battery 1 is relatively constant and changes very little within one cycle of the PWM signal, the load current and duty cycle of the controllable load module 2 will be relatively constant. k This proportionality achieves a linear relationship between the battery's balanced current and battery voltage.

[0026] Figure 3 This is a module architecture diagram of an embodiment of the power system with battery balancing function of the present invention. Figure 3 As shown, the voltage preprocessing module 31 in this embodiment also includes a second controllable switch 311 and a sample-and-hold unit 312. One end of the second controllable switch 311 is connected to the voltage divider signal, and the other end is connected to the first input terminal of the comparator 321 via the sample-and-hold unit 312. This invention takes into account that in actual circuits, when the equalization current is activated, the load current of the controllable load module 2 may change significantly, and the battery voltage may also change significantly, experiencing drops or oscillations. This will cause the waveform of the PWM signal to oscillate, affecting the duty cycle. kThe linear relationship is no longer satisfied. Therefore, the present invention requires a sample-and-hold unit to sample the voltage when it is unbalanced and hold it when it is balanced before the comparator 321 performs the comparison.

[0027] The sample-and-hold unit 312 can be implemented using a switched-capacitor circuit, but its drawback is that the capacitor has leakage current, requiring periodic updates even if the battery voltage changes slowly. Alternatively, the sample-and-hold unit 312 can be implemented using an ADC sampling circuit, employing digital circuitry for holding and converting the signal to a digital PWM signal. Because digital circuitry is used for holding, periodic refreshing is unnecessary, and the sampling period only needs to consider the frequency of the battery voltage change. The disadvantage is that the circuit size increases.

[0028] Regardless of the implementation of the sample-and-hold unit 312, there is a sampling period, which is typically equal to or longer than the period of the PWM signal. However, sampling needs to be maintained for a predetermined sampling duration. Therefore, this invention proposes to make the sampling period shorter than the period of the PWM signal.

[0029] like Figure 3 As shown, to make the startup of the sample-and-hold unit 312 controllable, the battery voltage measurement and current balancing circuit 3 of this embodiment of the invention includes a control module 34. This control module 34 processes the PWM signal and then sends it to the first controllable switch 21 of the controllable load module 2 to control the on / off duty cycle of the controllable load module 2, so that the average current on the controllable load module 2 is controlled to balance the output current of the battery 1. Simultaneously, the control module 34 also controls the voltage measurement module 33 according to the PWM signal, so that it only measures the voltage divider signal during the low level period of the PWM signal. The "certain processing" refers to PWM signal conditioning and power drive adaptation processing, including level conversion, enhancing the driving capability of the gate driver chip, and adding gate resistors and protection circuits.

[0030] Furthermore, this invention proposes that, in order to mitigate or eliminate the impact of the equalization current IR drop on the sampled battery voltage, the voltage preprocessing module includes a second controllable switch 311 before the sample-and-hold unit 312. To ensure that the battery measurement is unaffected by the equalization current, the control module 34 controls the second controllable switch 311 to turn on, aligning the start-up of the sample-and-hold unit 312 with the timing of the high-level to low-level transition of the PWM signal. Thus, as long as the low-level time of the PWM signal is long enough, one sample-and-hold cycle can be completed.

[0031] More specifically, the control module 34 controls the on / off duty cycle of the second controllable switch 311 to control the sampling start and end periods of the sample-and-hold unit 312. That is, by controlling the second controllable switch 311, the sample-and-hold unit 312 is turned on when the PWM signal transitions from high to low and turned off when it transitions from low to high. However, if the voltage of battery 1 rises to a certain level, the low-level time of the PWM signal becomes too short, making it impossible to complete one sample-and-hold cycle.

[0032] Figure 4 This is a schematic diagram of the signal waveforms of a power system with battery balancing function according to the first embodiment of the present invention. Figure 4 As shown, the rated sampling time in this embodiment is set to 1 / 2 of the PWM signal period. The top waveform in the figure shows the ramp signal and the simple sample-and-hold signal. The so-called "simple sample-and-hold signal" refers to the waveform when the second controllable switch 311 is not considered to be on or off (normally closed). The control signal is generated by the control module 34 based on the PWM signal. It is used to control the duty cycle of the second controllable switch 311 on one hand, and to control the start and stop of the voltage measurement module 33 on the other hand. As can be seen from the figure, it is basically a signal with the opposite level of the PWM signal. Therefore, the actual output of the sample-and-hold unit 312 is Figure 4 The bottommost waveform is the controlled sample-and-hold signal.

[0033] In this embodiment, if the voltage of the voltage divider signal V in If the level remains consistently high, insufficient sampling time will occur for several consecutive cycles. For example... Figure 4 As shown, the controlled sampling signal suffers from insufficient sampling duration across four consecutive cycles. To address this issue, this invention further proposes an improved solution.

[0034] Figure 5 This is a schematic diagram of the signal waveforms of a power system with battery balancing function according to the second embodiment of the present invention. Figure 5 As shown, unlike the first embodiment, when the control module 34 detects that the PWM signal has more than n low levels of insufficient duration within a certain period of time, it inserts a low level of one cycle into the PWM signal, where n≥2.

[0035] In one scenario, when the control module 34 detects multiple consecutive low-level signals in the PWM signal with insufficient duration (meaning insufficient to complete one sampling and holding cycle), the corresponding control signal will exhibit multiple consecutive high-level signals with insufficient duration, resulting in continuous insufficient sampling duration. Therefore, in this embodiment, inserting a low-level signal of one cycle into the PWM signal is equivalent to inserting a high-level signal of one cycle into the control signal, i.e., forcing the sampling period.

[0036] In this embodiment, "consecutive multiples" refers to three consecutive numbers. However, those skilled in the art should understand that "consecutive multiples" can also be other numbers, typically 2 to 10 consecutive numbers.

[0037] In other embodiments, it is also possible to detect whether the number of times the PWM signal with insufficient duration low level occurs within a certain period of time reaches a threshold. For example, if two or more low level with insufficient duration occurs consecutively within 10 cycles, then a low level of one cycle is inserted into the PWM signal.

[0038] In the above embodiments, considering that the sample-and-hold operation occupies a certain amount of the high-level time of the PWM signal, the duty cycle can be compensated to a certain extent when the sample-and-hold operation is not working through negative feedback.

[0039] Figure 6 This is a schematic diagram of the signal waveforms of a power system with battery balancing function according to the third embodiment of the present invention. Figure 6 As shown, unlike the second embodiment, this embodiment takes into account the actual circuit conditions. A significant spike occurs during the transition of the PWM signal from high to low, which takes time to decay. Therefore, the current balancing circuit 3 in this embodiment also includes a Snubber module 35 to suppress this spike. The Snubber module 35 is connected in parallel with the voltage preprocessing module 31 and includes a resistor and a capacitor.

[0040] Preferably, in the specific circuit design of the sample-and-hold function, it is also necessary to ensure that no sampling is performed for a period of time after the high-low switching, thereby adding a suppression period so that the sample-and-hold unit 312 updates the sampled value if and only if the conduction duration of the second controllable switch 311 meets the threshold requirement.

[0041] The above scheme describes a single-cell battery. However, it can be easily extended to multiple batteries. In a multi-cell scheme, the controllable load module 2 corresponds one-to-one with each battery 1, and the battery management chip is connected to each battery 1. However, the balancing scheme for multiple batteries needs to take into account the characteristics of multiple batteries and cannot balance adjacent batteries simultaneously.

[0042] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A battery voltage measurement and current balancing circuit, comprising a voltage preprocessing module (31), a PWM module (32), and a voltage measurement module (33). The voltage preprocessing module (31) is used to divide the voltage output by the battery (1) to generate a voltage divider signal. The PWM module (32) is used to generate and output a PWM signal according to the voltage divider signal. The voltage measurement module (33) is used to measure the voltage of the voltage divider signal. Its features are: The battery voltage measurement and current balancing circuit (3) also includes a control module (34). The control module (34) conditions and adapts the PWM signal to power drive and then sends it to the first controllable switch (21) of the controllable load module (2) to control the on / off duty cycle of the controllable load module (2) so as to adjust the output equalization current of the battery (1). The controllable load module (2) is connected in parallel with the battery (1). The control module (34) also controls the voltage measurement module (33) according to the PWM signal so that it measures the voltage divider signal only during the low level of the PWM signal; The PWM module (32) includes a comparator (321), which includes a first input terminal, a second input terminal and an output terminal. The second input terminal is connected to a ramp signal, and the output terminal is connected to the control module (34). The voltage preprocessing module (31) includes a second controllable switch (311) and a sample-and-hold unit (312). One end of the second controllable switch (311) is connected to the voltage divider signal, and the other end is connected to the first input terminal of the comparator (321) via the sample-and-hold unit (312). The control module (34) is also used to control the on / off duty cycle of the second controllable switch (311) so as to control the operation of the sample and hold unit (312); The control module (34) controls the on / off duty cycle of the second controllable switch (311), so that the sample and hold unit (312) is turned on when the PWM signal changes from high level to low level and is turned off when the low level changes to high level; When the control module (34) detects that the PWM signal has multiple consecutive low levels with insufficient duration, it inserts a low level of one cycle into the PWM signal. The insufficient duration means that it is not enough to complete one sampling and holding cycle.

2. The battery voltage measurement and current balancing circuit according to claim 1, characterized in that, The sampling period of the sample-and-hold unit (312) is shorter than the period of the PWM signal.

3. The battery voltage measurement and current balancing circuit according to claim 2, characterized in that, When the control module (34) detects that the PWM signal has more than n low levels with insufficient duration within a certain period of time, it inserts a low level of one cycle into the PWM signal, where n≥2.

4. A battery management chip, characterized in that, The battery voltage measurement and current balancing circuit includes any one of claims 1 to 3.

5. A power supply system, comprising a battery (1), a controllable load module (2), and a battery management chip, characterized in that: Connect the positive terminal of the battery (1) to one pin of the battery management chip via one wire, and connect the negative terminal of the battery (1) to another pin of the battery management chip via another wire; The battery management chip is the battery management chip according to claim 4.

6. The power supply system according to claim 5, characterized in that, There are multiple batteries (1) and controllable load modules (2), and each controllable load module (2) corresponds to a battery (1). The battery management chip is connected to each battery (1).

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