Control method of three-phase chb circuit and chb circuit

Abstract

The application provides a control method and device of a three-phase CHB circuit, a CHB circuit and a power supply device, and relates to the technical field of power supply. For each phase circuit of the three-phase CHB circuit, the phase circuit comprises a series branch formed by M*N H-bridge units, and the series branch is divided into N H-bridge pairs. For each H-bridge pair, if the DC voltages of each H-bridge unit in the bridge pair are not equal, the duty cycle of a specific level in the H-bridge pair is adjusted according to the current flow direction of the H-bridge pair and the total control signal, so as to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair. In the application, the duty cycle of the specific level in the bridge pair is fine-tuned, so that high-precision and adaptive voltage-sharing control of the H-bridge units in the three-phase CHB circuit is realized. A plurality of H-bridge units are grouped and paired to form H-bridge pairs, the total voltage of the phase is evenly divided into the H-bridge pairs, the control logic is simplified, slight imbalance in the H-bridge pair does not affect the balance between the H-bridge pairs, and the balance response speed is obviously improved.

Description

Technical Field

[0001] This application relates to the field of power supply technology, and in particular to a control method and a three-phase CHB circuit. Background Technology

[0002] In the field of power electronic conversion, the CHB (Cascaded H-Bridge) circuit, comprising multiple H-bridge units connected in series, is a highly modular and scalable multilevel power electronic topology. The modular structure of the CHB circuit facilitates expansion of the number of levels, and the consistent structure of each H-bridge unit facilitates mass production, redundant configuration, and fault replacement. CHB circuits are widely used in medium- and high-voltage high-power frequency converters, power quality management devices, and new energy grid-connected systems. In related technologies, the control methods for CHB circuits often suffer from three-phase DC voltage imbalance, meaning that the DC voltages of each phase differ significantly. If a load is connected to the DC side, it will lead to an imbalance in the load power on the DC side of each phase, causing system instability. Besides phase-to-phase imbalance, imbalances can also exist between different H-bridge units within the same phase. Prolonged phase-to-phase imbalance can cause voltage concentration in some H-bridge units, leading to overvoltage, excessive device stress, protection tripping, and accelerated aging of individual H-bridge units, resulting in decreased reliability. Summary of the Invention

[0003] This application provides a control method and a CHB circuit for a three-phase CHB circuit to solve the problem of unbalanced DC voltage within the phases of the CHB circuit.

[0004] In a first aspect, embodiments of this application provide a control method for a three-phase CHB circuit, including: For each phase of the three-phase CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, and each M H-bridge unit is paired to form an H-bridge pair; M and N are both positive integers. Obtain the current direction of the first phase and the DC voltage of each H-bridge unit in the group of each H-bridge pair of the first phase, wherein the first phase is any one of phase A, phase B and phase C; If the DC voltage of each H-bridge unit in the H-bridge pair is not equal, the duty cycle of a specific level in the H-bridge pair is adjusted according to the current flow direction of the H-bridge pair and the overall control signal to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair.

[0005] In one possible implementation, when the total control signal of the first phase switches between level P and level O, level P is the specific level; when the total control signal of the first phase switches between level N and level O, level N is the specific level.

[0006] In one possible implementation, adjusting the duty cycle of a specific level within the H-bridge pair based on the current flow direction and the overall control signal specifically includes: If the current flows into the CHB circuit, and the total control signal switches between level P and level O, then the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage in the target H-bridge pair should be greater than the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage. If the current flows out of the CHB circuit, and the total control signal switches between level P and level O, then the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage in the target H-bridge pair should be greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage. If the current flows into the CHB circuit, and the total control signal switches between level N and level O, then the duty cycle of level N of the control signal of the H-bridge unit with a larger DC voltage in the target H-bridge pair should be greater than the duty cycle of level N of the control signal of the H-bridge unit with a smaller DC voltage. If the current flows out of the CHB circuit, and the total control signal switches between levels N and O, then the duty cycle of level N of the control signal of the H-bridge unit with the smaller DC voltage in the target H-bridge pair should be greater than the duty cycle of level N of the control signal of the H-bridge unit with the larger DC voltage.

[0007] One possible implementation also includes: One H-bridge pair is selected from each of the three phases to form the three-phase H-bridge pair group; Determine the target base vector required to synthesize the target voltage vector, wherein the common-mode voltage of the target base vector is zero; Based on the target basic vector, determine the total control signal corresponding to each individual H-bridge pair in each phase; Based on the total control signal corresponding to each individual H-bridge pair in each phase, the control signal corresponding to each H-bridge unit in each phase is determined; wherein, the control signals of the two H-bridge units in the same H-bridge pair are combined to form the total control signal of the H-bridge pair, and the control signals of the two H-bridge units in the same H-bridge pair are different. The control signals corresponding to each H-bridge unit of each phase are used to control each H-bridge unit of each phase.

[0008] In one possible implementation, the number of level switching of the total control signal of a single H-bridge pair of the first phase in one cycle is the first number, and the number of level switching of the total control signal of a single H-bridge pair of the second and third phases in one cycle is the second number, wherein the first number is twice the second number; The first phase, the second phase, and the third phase are different phases, and are randomly assigned to be phase A, phase B, and phase C. The sum of the number of level switching times of the control signals of the two H-bridge units of the same H-bridge pair within one cycle is equal to the total number of level switching times of the control signals of the H-bridge pair within one cycle.

[0009] In one possible implementation, determining the control signal corresponding to each H-bridge unit of each phase based on the total control signal corresponding to each individual H-bridge pair of each phase includes: The modulation wave, first carrier, and second carrier of each phase are acquired; wherein, for each phase, the first carrier and second carrier of that phase have the same frequency and are out of phase; the frequency of the first carrier of the first phase is twice the frequency of the first carrier of the second and third phases; the phase difference between the first carrier of the second phase and the first carrier of the third phase is 90 degrees; the first phase, the second phase, and the third phase are different phases and are randomly assigned to phase A, phase B, and phase C. The modulated wave of each phase is compared with the first carrier wave to generate the first control signal for each phase; The modulated wave of each phase is compared with the second carrier wave to generate the second control signal for each phase; Among them, the first control signal and the second control signal of each phase are the control signals corresponding to the two H-bridge units of the same H-bridge pair of each phase, respectively.

[0010] In one possible implementation, the method further includes: obtaining the DC voltage of each phase in the three-phase CHB circuit; Based on the DC voltage of each phase, the target phase is determined, and the category of the target phase is determined; the target phase is the phase with the largest DC voltage deviation, and the category is the phase with the largest DC voltage or the phase with the smallest DC voltage. The zero-sequence injection amount is determined based on the type of the target phase and the current flow direction of the target phase; Based on the zero-sequence injection amount, zero-sequence injection control is performed on the three-phase CHB circuit to reduce the DC voltage deviation between the target phase and other phases.

[0011] In one possible implementation, determining the zero-sequence injection amount based on the type of the target phase and the current flow direction of the target phase includes: If the category is the DC voltage maximum phase, then when the current flow direction is current flowing into the CHB circuit, the zero-sequence injection amount is determined as the first zero-sequence component, and when the current flow direction is current flowing out of the CHB circuit, the zero-sequence injection amount is determined as the second zero-sequence component. If the category is the minimum phase of DC voltage, then when the current flow direction is current flowing into the CHB circuit, the zero-sequence injection amount is determined to be the second zero-sequence component, and when the current flow direction is current flowing out of the CHB circuit, the zero-sequence injection amount is determined to be the first zero-sequence component. The first zero-order component is -1 / 3, and the second zero-order component is 1 / 3.

[0012] Secondly, embodiments of this application provide a control device for a three-phase CHB circuit, comprising: for each phase of the three-phase CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, and each M H-bridge units are paired to form an H-bridge pair; M and N are both positive integers; The acquisition module is used to acquire the current direction of the first phase and the DC voltage of each H-bridge unit in each H-bridge pair group of the first phase, wherein the first phase is any one of phase A, phase B and phase C; The adjustment module is used to adjust the duty cycle of a specific level within the H-bridge pair according to the current flow direction and the overall control signal when the DC voltage of each H-bridge unit in the H-bridge pair is uneven, so as to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair.

[0013] Thirdly, embodiments of this application provide a CHB circuit, including circuits corresponding to each of the three phases and a control device; the control device is used to execute the control method of any implementation of the first aspect; the circuits corresponding to each of the three phases are all controlled by the control device.

[0014] In this embodiment, for each phase of the three-phase CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, and the series branch is divided into N H-bridge pairs. For each H-bridge pair, if the DC voltage of each H-bridge unit within the pair is uneven, the duty cycle of a specific level within the H-bridge pair is adjusted according to the current flow direction and the overall control signal to reduce the DC voltage deviation between each H-bridge unit within the pair. This invention achieves high-precision, adaptive voltage equalization control of the H-bridge units within a phase of the three-phase CHB circuit by fine-tuning the duty cycle of a specific level within the bridge pair. By grouping and pairing multiple H-bridges to form H-bridge pairs, the total voltage of the phase is evenly distributed among the H-bridge pairs, simplifying the control logic. Slight imbalances within a H-bridge pair do not affect the balance between H-bridge pairs, significantly improving the equalization response speed. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 This is a schematic diagram of the CHB circuit provided in the embodiments of this application; Figure 2 This is a flowchart illustrating the implementation of the control method for the three-phase CHB circuit provided in the embodiments of this application; Figure 3 This is a spatial vector diagram of the three-phase H-bridge pair provided in the embodiments of this application; Figure 4 This is a schematic diagram of the total control signals corresponding to each individual H-bridge pair of each phase provided in the embodiments of this application; Figure 5 This is a schematic diagram of the total control signal of a single H-bridge pair of each phase, the control signal of each H-bridge unit, the first carrier and the second carrier provided in the embodiments of this application; Figure 6 This is a schematic diagram of the first spatial vector hexagon and the first triangle provided in the embodiments of this application; Figure 7 This is a schematic diagram of the structure of the control device for the three-phase CHB circuit provided in the embodiments of this application; Figure 8 This is a schematic diagram of the control device provided in the embodiments of this application. Detailed Implementation

[0017] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0018] To make the objectives, technical solutions, and advantages of this application clearer, the following description will be provided in conjunction with the accompanying drawings and specific embodiments.

[0019] See Figure 1 This illustrates a schematic diagram of the CHB circuit provided in an embodiment of this application. Figure 1 As shown, the CHB circuit can also be called a three-phase CHB circuit, which includes circuits corresponding to each of the three phases.

[0020] In some possible implementations, each phase of a three-phase CHB circuit comprises a series branch consisting of 2N H-bridge units, where N is a positive integer. Each H-bridge unit includes four switching transistors, and the connections between these transistors are as follows: Figure 1 As shown, further details will not be repeated. This application does not impose specific limitations on the type of switching transistor; any feasible type is acceptable. In this embodiment, the H-bridge pair includes two H-bridge units. In other embodiments, the H-bridge pair may include other numbers, such as three, four, five, or M (positive integer) H-bridge units, etc., which are not limited here.

[0021] CHB circuits are used to convert AC to DC. They can perform bidirectional conversion, such as converting DC to AC (i.e., operating in inverter mode) or AC to DC (i.e., operating in rectification mode).

[0022] like Figure 1 As shown, A0, B0, and C0 represent the AC terminals of phase A, phase B, and phase C of the CHB circuit, respectively, with O as the midpoint. DCA1+ and DCA1- are the positive and negative DC terminals of the first H-bridge unit of phase A, respectively; DCA2+ and DCA2- are the positive and negative DC terminals of the second H-bridge unit of phase A, respectively; ..., DCA2N+ and DCA2N- are the positive and negative DC terminals of the 2Nth H-bridge unit of phase A, respectively. Similarly, DCB1+ and DCB1- are the positive and negative DC terminals of the first H-bridge unit of phase B, respectively; DCB2+ and DCB2- are the positive and negative DC terminals of the second H-bridge unit of phase B, respectively; ..., DCB2N+ and DCB2N- are the positive and negative DC terminals of the 2Nth H-bridge unit of phase B, respectively. DCC1+ and DCC1- are the positive and negative DC terminals of the first H-bridge unit of phase C, respectively; DCC2+ and DCC2- are the positive and negative DC terminals of the second H-bridge unit of phase C, respectively; ..., DCC2N+ and DCC2N- are the positive and negative DC terminals of the 2Nth H-bridge unit of phase C, respectively.

[0023] See Figure 1 For each phase of a three-phase CHB circuit, the AC terminals of the 2N H-bridge units in that phase are connected in series. The first terminal of the series connection of the AC terminals of the 2N H-bridge units is the AC terminal of that phase, and the second terminal of the series connection of the AC terminals of the 2N H-bridge units is connected to the midpoint O.

[0024] When the three-phase CHB circuit is in rectification mode, that is, when AC power is converted to DC power, the AC terminals of each phase can be used to connect to an AC power source, and the positive and negative DC terminals of each H-bridge unit can be used to connect to a DC load or a DC power source; when the three-phase CHB circuit is in inverter mode, that is, when DC power is converted to AC power, the AC terminals of each phase can be used to connect to an AC load, and the positive and negative DC terminals of each H-bridge unit can be used to connect to a DC power source.

[0025] In some embodiments provided later, to achieve zero common-mode control, for each phase of the three-phase CHB circuit, the 2N H-bridge units included in that phase circuit are paired up to form N H-bridge pairs. Exemplarily, the 2N H-bridge units of each phase can be paired up in series or randomly; no specific restrictions are placed here. For example, the first and second H-bridge units can form one H-bridge pair, the third and fourth H-bridge units another, and so on, up to the (2N-1)th and 2Nth H-bridge units; or, the first and third H-bridge units another, the second and fourth H-bridge units another, and so on, up to the (2N-2)th and 2Nth H-bridge units; and so on. However, it should be noted that each H-bridge unit cannot be paired repeatedly; that is, each H-bridge pair must contain two different H-bridge units.

[0026] See Figure 2 The flowchart illustrating the implementation of the control method for the three-phase CHB circuit provided in the embodiments of this application is described in detail below: In 201, the current direction of the first phase and the DC voltage of each H-bridge unit in the first phase are obtained.

[0027] In this circuit, the first phase can be any one of phases A, B, and C. The alternating current in each phase has a direction. Based on the alternating current of the first phase, we can determine whether the current flow in the first phase is into or out of the CHB circuit. Specifically, the current flow direction of the first phase can be understood as the direction of the alternating current within that phase. A current flow into the CHB circuit means the alternating current flows from the AC terminal of the first phase to the H-bridge unit contained in the first phase of the CHB circuit; a current flow out of the CHB circuit means the alternating current flows from the H-bridge unit contained in the first phase of the CHB circuit to the AC terminal of the first phase.

[0028] In S202, if the DC voltage of each H-bridge unit in the H-bridge pair is not equal, the duty cycle of a specific level in the H-bridge pair is adjusted according to the current flow direction of the H-bridge pair and the total control signal to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair.

[0029] Unequal DC voltages in each H-bridge unit within an H-bridge pair are a prerequisite for phase-to-phase equalization. If the DC voltages of each H-bridge unit within the H-bridge pair are equal, no adjustment is needed; control can be performed according to the original modulation output. In three-phase modulation, each phase corresponds to a level-flipping waveform. The total control signal here can be understood as the level-flipping waveform after modulation of the first phase, such as POP, OPO, NON, or ONO within one cycle. If the total control signal for the first phase switches between levels P and O, level P is the specific level; when the total control signal for the first phase switches between levels N and O, level N is the specific level. By adjusting the duty cycles of the specific levels of the control signals of the two H-bridge units in a single H-bridge pair, the duty cycle of level P or level N of which H-bridge unit in the pair is larger can be controlled based on the magnitude of the DC voltage of the two H-bridge units, thus balancing the DC voltages of the two H-bridge units.

[0030] The specific adjustment rules are as follows: If the current flows into the CHB circuit, and the total control signal switches between level P and level O, then the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage in the target H-bridge pair should be greater than the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage. If the current flows out of the CHB circuit, and the total control signal switches between level P and level O, then the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage in the target H-bridge pair should be greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage. If the current flows into the CHB circuit, and the total control signal switches between level N and level O, then the duty cycle of level N of the control signal of the H-bridge unit with a larger DC voltage in the target H-bridge pair should be greater than the duty cycle of level N of the control signal of the H-bridge unit with a smaller DC voltage. If the current flows out of the CHB circuit, and the total control signal switches between levels N and O, then the duty cycle of level N of the control signal of the H-bridge unit with the smaller DC voltage in the target H-bridge pair should be greater than the duty cycle of level N of the control signal of the H-bridge unit with the larger DC voltage.

[0031] By adjusting the duty cycle as described above, the DC-side voltage of the two H-bridge units can be dynamically balanced by utilizing the relationship between current flow and voltage difference without changing the total output voltage of the H-bridge.

[0032] To further address zero common-mode control, the control method for the three-phase CHB circuit in the above embodiments may further include the following steps: In S203, the target voltage vector corresponding to the three-phase H-bridge pair group is obtained; wherein, one H-bridge pair is selected from each of the three phases to form a three-phase H-bridge pair group.

[0033] One H-bridge pair is selected from each of the three phases (A, B, and C) to form a three-phase H-bridge pair group. The entire three-phase CHB circuit can be divided into N three-phase H-bridge pair groups. Each three-phase H-bridge pair group is equivalent to a small three-phase CHB circuit with its own target voltage vector. Different three-phase H-bridge pair groups can have the same target voltage vector.

[0034] The target voltage vector corresponding to the three-phase H-bridge pair can be understood as the expected voltage vector of the three-phase H-bridge pair, which can be determined based on the voltage vector corresponding to the expected three-phase voltage of the three-phase CHB circuit and the value of N. For example, the target voltage vector corresponding to the three-phase H-bridge pair can be the ratio of the voltage vector corresponding to the expected three-phase voltage of the three-phase CHB circuit to N.

[0035] In S204, the target base vector required to synthesize the target voltage vector is determined, and the common-mode voltage of the target base vector is zero.

[0036] Figure 3 The spatial vector diagram of the three-phase H-bridge pair is shown; see [link / reference]. Figure 3 There are 27 basic voltage vectors for a single H-bridge pair in three phases, namely PPP, OOO, NNN, POO, PPO, OPO, OPP, OOP, POP, ONN, OON, NON, NOO, NNO, ONO, PON, OPN, NPO, NOP, ONP, PNO, PNN, PPN, NPN, NPP, NNP, and PNP. These 27 basic voltage vectors include 3 zero vectors, 12 small vectors, 6 medium vectors, and 6 large vectors. The 3 zero vectors are PPP, OOO, and NNN; the 12 small vectors are POO, PPO, OPO, OPP, OOP, POP, ONN, OON, NON, NOO, NNO, and ONO; the 6 medium vectors are PON, OPN, NPO, NOP, ONP, and PNO; and the 6 large vectors are PNN, PPN, NPN, NPP, NNP, and PNP.

[0037] Among them, small vectors can also be called short vectors, and large vectors can also be called long vectors.

[0038] The spatial vector map is divided into six sectors at 60° intervals. Figure 3 The sectors are I, II, III, IV, V, and VI, with each sector having an angle of 60°.

[0039] The common-mode voltages of the 27 basic voltage vectors mentioned above can be positive, negative, or zero. There are 7 basic voltage vectors with zero common-mode voltage: PON, OPN, NPO, NOP, ONP, PNO, and OOO, which includes six medium-mode vectors and one zero-mode vector.

[0040] In order to achieve zero common-mode control of the three-phase CHB circuit, the embodiments of this application require zero common-mode control of each individual H-bridge pair of the three phases. Therefore, it is necessary to use the basic voltage vector with zero common-mode voltage to synthesize the target voltage vector corresponding to the individual H-bridge pair of the three phases.

[0041] In this embodiment, the basic voltage vector required to synthesize the target voltage vector is referred to as the target basic vector. The number of target basic vectors is typically three.

[0042] In S205, based on the target basic vector, the total control signal corresponding to each individual H-bridge pair in each phase is determined.

[0043] The embodiments of this application can determine the total control signal corresponding to each individual H-bridge pair in each phase based on the target basic vector required for synthesizing the target voltage vector. This process is a mature technology in related fields and will not be described in detail here.

[0044] For example, assuming the target basic vectors required to synthesize the target voltage vector are PON, OOO, and PNO, then the total control signals corresponding to individual H-bridge pairs in each phase (phases A, B, and C) (i.e., the total control signals of individual H-bridge pairs in phase A, phase B, and phase C) are as follows: Figure 4 As shown, they are POPOP, OONOO, and NOOON, respectively.

[0045] In S206, the control signals corresponding to each H-bridge unit of each phase are determined according to the total control signals corresponding to each individual H-bridge pair of each phase; wherein, the control signals of the two H-bridge units of the same H-bridge pair are combined to form the total control signal of the H-bridge pair, and the control signals of the two H-bridge units of the same H-bridge pair are different.

[0046] This application embodiment can synthesize the total control signal of an H-bridge pair based on the control signals of two H-bridge units within the same H-bridge pair, and the control signals of the two H-bridge units within the same H-bridge pair are different. Based on the total control signal corresponding to each individual H-bridge pair in each phase, the control signal corresponding to each H-bridge unit in each phase is determined. Specifically, synthesizing the total control signal of an H-bridge pair from the control signals of two H-bridge units within the same H-bridge pair can be understood as obtaining the total control signal of the H-bridge pair by superimposing the control signals of the two H-bridge units within the same H-bridge pair.

[0047] For a given H-bridge pair within the same phase, the control signals of its two H-bridge units correspond one-to-one with the control signals of the two H-bridge units in other H-bridge pairs within the same phase. For example, assuming an H-bridge pair includes a first H-bridge unit and a second H-bridge unit, the control signals of the first H-bridge units in all H-bridge pairs within the same phase can be the same, and the control signals of the second H-bridge units in all H-bridge pairs within the same phase can also be the same. However, the control signals of the H-bridge units in different H-bridge pairs across different phases are typically different.

[0048] This application does not impose specific limitations on the means of determining the control signals corresponding to each H-bridge unit of each phase based on the total control signals corresponding to each individual H-bridge pair of each phase; any feasible means are acceptable.

[0049] In S207, each H-bridge unit of each phase is controlled according to the control signal corresponding to each H-bridge unit of each phase.

[0050] Based on the control signals corresponding to each H-bridge unit of each phase determined in the aforementioned steps, the corresponding H-bridge units of each phase can be controlled to achieve zero common-mode control of the three-phase CHB circuit.

[0051] In the embodiments of this application, the H-bridge units in each phase of the CHB circuit are paired up to form H-bridge pairs. By controlling the two H-bridge units in each H-bridge pair, the total control signal of a single H-bridge pair of the three phases is constructed based on the target fundamental vector with zero common-mode voltage. This enables zero common-mode control of a single H-bridge pair of the three phases, and each H-bridge pair of the three phases can achieve zero common-mode control, thereby enabling zero common-mode control of the three-phase CHB circuit. This can alleviate or eliminate leakage current caused by common-mode voltage in the three-phase CHB circuit, reduce electromagnetic interference, reduce the possibility of normal operation of the three-phase CHB circuit due to electromagnetic interference, and reduce electromagnetic compatibility (EMC) costs.

[0052] The foregoing embodiments have introduced the overall implementation process of the control method for a three-phase CHB circuit. The following will further define or expand the steps or related content.

[0053] In some embodiments, the number of level switching of the total control signal of a single H-bridge pair of the first phase in one cycle is the first number, and the number of level switching of the total control signal of a single H-bridge pair of the second and third phases in one cycle is the second number, and the first number is twice the second number; The first, second, and third phases are different phases, and are randomly assigned to phases A, B, and C. The sum of the number of level switching times of the control signals of the two H-bridge units of the same H-bridge pair within one cycle is equal to the total number of level switching times of the control signals of the H-bridge pair within one cycle.

[0054] In the embodiments of this application, the first phase, the second phase, and the third phase are different phases, and are randomly assigned to phases A, B, and C. For example, the first phase is phase A, the second phase is phase B, and the third phase is phase C; or, the first phase is phase A, the second phase is phase C, and the third phase is phase B; or, the first phase is phase B, the second phase is phase A, and the third phase is phase C; or, the first phase is phase B, the second phase is phase C, and the third phase is phase A; or, the first phase is phase C, the second phase is phase A, and the third phase is phase B; and so on.

[0055] For example, see Figure 5 It provides an example of the total control signal for a single H-bridge pair in each phase and the control signals for the two H-bridge units included in that single H-bridge pair. Among them, Figure 5 The total control signal of each phase's individual H-bridge pair shown is... Figure 4 Same. Figure 5 In the diagram, X1 is the total control signal for a single H-bridge pair in the first phase, and X11 and X12 are the control signals corresponding to the two H-bridge units included in the single H-bridge pair in the first phase, respectively; X2 is the total control signal for a single H-bridge pair in the second phase, and X21 and X22 are the control signals corresponding to the two H-bridge units included in the single H-bridge pair in the second phase, respectively; X3 is the total control signal for a single H-bridge pair in the third phase, and X31 and X32 are the control signals corresponding to the two H-bridge units included in the single H-bridge pair in the third phase, respectively.

[0056] It should be noted that, Figure 5 This is merely an example of the total control signal for a single H-bridge pair in each phase and the control signals for the two H-bridge units included in that single H-bridge pair. The total control signal for a single H-bridge pair in each phase can also be derived in other ways to obtain the control signals for the two H-bridge units it includes. For example, Figure 5 The control signals of the two H-bridge units corresponding to X1 (POPOPPOPOP) can also be POPOOPOPOO and OOOOPOOOOP, or OOPOPOOPOP and POOOOPOOOO, or POPOPOOOOO and OOOOOPOPOP, etc. Figure 5 The control signals for the two H-bridge units corresponding to X3 (NOOONNOOON) can also be NOOONOOOOO and OOOOONOOON, or NOOOONOOOO and OOOONOOOON, etc.

[0057] like Figure 5As shown, the total number of level switching of the control signal for a single H-bridge pair in the first phase is 4 times in one cycle, i.e., the first count is 4; the total number of level switching of the control signal for a single H-bridge pair in the second and third phases is 2 times in one cycle, i.e., the second count is 2. The first count is twice the second count.

[0058] The total control signal level of a single H-bridge pair in the first phase changes 4 times in one cycle. The control signals of the two H-bridge units within the same H-bridge pair in the first phase each change 2 times in one cycle. Therefore, the sum of the level changes of the control signals of the two H-bridge units within the same H-bridge pair in the first phase within one cycle equals the total level change of the control signal of that H-bridge pair in the first phase within one cycle. Similarly, the total control signal level of a single H-bridge pair in the second phase changes 2 times in one cycle. The control signals of the two H-bridge units within the same H-bridge pair in the second phase change 0 times and 2 times in one cycle, respectively. Therefore, the sum of the level changes of the control signals of the two H-bridge units within the same H-bridge pair in the second phase within one cycle equals the total level change of the control signal of that H-bridge pair in the second phase within one cycle. The total control signal level switching count of a single H-bridge pair in the third phase is 2 times in one cycle. The control signals of the two H-bridge units contained in the single H-bridge pair in the third phase are each switched once in one cycle. Therefore, the sum of the level switching counts of the control signals of the two H-bridge units contained in the same H-bridge pair in the third phase in one cycle is equal to the total level switching count of the control signal of the H-bridge pair in the third phase in one cycle.

[0059] Therefore, regardless of the phase, the sum of the number of level switching times of the control signals of the two H-bridge units of the same H-bridge pair within one cycle is equal to the total number of level switching times of the control signals of the H-bridge pair within one cycle.

[0060] In this embodiment, the number of level switching times of the total control signal of a single H-bridge pair in the first phase within one cycle is twice the number of level switching times of the total control signal of a single H-bridge pair in the second or third phase within one cycle. Furthermore, the sum of the level switching times of the control signals of the two H-bridge units within the same H-bridge pair within one cycle equals the total level switching times of the total control signal of that H-bridge pair within one cycle. This allows for precise allocation and transfer of switching losses among the three phases and between the two H-bridge units within the same H-bridge pair, enabling centralized management of switching losses. For example, high switching frequencies can be concentrated on specific phases or specific units, laying the foundation for subsequent system-level efficiency optimization based on current magnitude. Additionally, the sum of the level switching times of the control signals of the two H-bridge units within one cycle equals the total level switching times of the total control signal of that H-bridge pair within one cycle. This means that the total control signal is shared by the two H-bridge units, which significantly reduces switching losses and improves efficiency compared to directly using the total control signal to control two H-bridge units in related technologies.

[0061] In some embodiments, in S206, determining the control signal corresponding to each H-bridge unit of each phase based on the total control signal corresponding to each individual H-bridge pair of each phase includes: Acquire the modulation wave, first carrier, and second carrier of each phase; wherein, for each phase, the first carrier and second carrier of that phase have the same frequency and are out of phase; the frequency of the first carrier of the first phase is twice the frequency of the first carrier of the second and third phases; the phase difference between the first carrier of the second phase and the first carrier of the third phase is 90 degrees; the first, second, and third phases are different phases and are randomly assigned to be phase A, phase B, and phase C. The modulated wave of each phase is compared with the first carrier wave to generate the first control signal for each phase; The modulated wave of each phase is compared with the second carrier wave to generate the second control signal for each phase; Among them, the first control signal and the second control signal of each phase are the control signals corresponding to the two H-bridge units of the same H-bridge pair of each phase, respectively.

[0062] See Figure 5 In this context, the two triangular waves of each phase are the first and second carrier waves of that phase. For example... Figure 5 As shown, the first and second carriers of the same phase have the same frequency, and the first and second carriers of the same phase are out of phase, that is, they are 180 degrees out of phase.

[0063] The frequency of the first carrier of the first phase is twice the frequency of the first carrier of the second phase, and also twice the frequency of the first carrier of the third phase. The frequency of the first carrier of the second phase is the same as the frequency of the first carrier of the third phase. Since the frequencies of the first and second carriers of the same phase are the same, the frequency of the second carrier of the first phase is twice the frequency of the second carrier of the second phase, and also twice the frequency of the second carrier of the third phase. The frequency of the second carrier of the second phase is the same as the frequency of the second carrier of the third phase. In other words, the period of the first carrier of the first phase is half the period of the first carrier of the second phase, and also half the period of the first carrier of the third phase; the period of the second carrier of the first phase is half the period of the second carrier of the second phase, and also half the period of the second carrier of the third phase; the period of the first carrier of the second phase is the same as the period of the first carrier of the third phase, and the period of the second carrier of the second phase is the same as the period of the second carrier of the third phase.

[0064] The phase difference between the first carrier of the second phase and the first carrier of the third phase is 90 degrees (i.e., π / 2), and the phase difference between the second carrier of the second phase and the second carrier of the third phase is 90 degrees (i.e., π / 2).

[0065] Wherein, the modulation wave of the first phase is M1=Msinwt, the modulation wave of the second phase is M2=Msin(wt+2*π / 3), and the modulation wave of the third phase is M3=Msin(wt-2*π / 3), where M is the modulation ratio, w is the angular frequency, and t is the time.

[0066] After the modulated wave of each phase is compared with the first carrier wave of each phase, a first control signal for each phase is generated. After the modulated wave of each phase is compared with the second carrier wave of each phase, a second control signal for each phase is generated. The first and second control signals of each phase are the control signals corresponding to the two H-bridge units of the same H-bridge pair for each phase.

[0067] In other words, the modulated wave of the first phase is compared with the first carrier wave of the first phase to generate the first control signal of the first phase, and the modulated wave of the first phase is compared with the second carrier wave of the first phase to generate the second control signal of the first phase. For each H-bridge pair of the first phase, the control signals corresponding to the two H-bridge units are the first control signal and the second control signal of the first phase, respectively. Similarly, the modulated wave of the second phase is compared with the first carrier wave of the second phase to generate the first control signal of the second phase, and the modulated wave of the second phase is compared with the second carrier wave of the second phase to generate the second control signal of the second phase. For each H-bridge pair of the second phase, the control signals corresponding to the two H-bridge units are the first control signal and the second control signal of the second phase, respectively. Likewise, the modulated wave of the third phase is compared with the first carrier wave of the third phase to generate the first control signal of the third phase, and the modulated wave of the third phase is compared with the second carrier wave of the third phase to generate the second control signal of the third phase. For each H-bridge pair of the third phase, the control signals corresponding to the two H-bridge units are the first control signal and the second control signal of the third phase, respectively.

[0068] It should be noted that the relationship between the carriers of the above phases can be determined by synthesizing the total control signal of the H-bridge pair based on the control signals of the two H-bridge units of the same H-bridge pair, and the control signals of the two H-bridge units of the same H-bridge pair are different.

[0069] Furthermore, this application provides a specific implementation method for determining the control signals corresponding to each H-bridge unit of each phase based on the total control signals corresponding to each individual H-bridge pair of each phase. However, in related technologies, any feasible method can be used to implement the above-mentioned method of determining the control signals corresponding to each H-bridge unit of each phase based on the total control signals corresponding to each individual H-bridge pair of each phase, and no specific limitations are imposed here.

[0070] This embodiment of the application, by making the carrier frequency of the first phase twice that of the other two phases, and by using a 90-degree phase difference between the second and third phase carriers, and employing anti-phase carrier pairs, can accurately generate control signals for controlling each H-bridge unit that meet the switching frequency requirements and have good synchronization. This method has clear logic, is easy to implement with a digital processor, and can guarantee the symmetry of the output waveform and harmonic quality without increasing hardware complexity.

[0071] In some embodiments, the duty cycles of the same level of the control signals of the two H-bridge units in a single H-bridge pair of the first phase are different; The duty cycle of the same level of the control signal of the two H-bridge units in a single H-bridge pair of the second phase is the same; The duty cycle of the same level of the control signal of the two H-bridge units in a single H-bridge pair of the third phase is the same.

[0072] Specifically, if the total control signal of a single H-bridge pair in the first phase switches between level P and level O, then the duty cycles of the control signals of the two H-bridge units in the single H-bridge pair in the first phase are different, and the duty cycles of the control signals of the two H-bridge units in the single H-bridge pair in the first phase are different; if the total control signal of a single H-bridge pair in the first phase switches between level N and level O, then the duty cycles of the control signals of the two H-bridge units in the single H-bridge pair in the first phase are different, and the duty cycles of the control signals of the two H-bridge units in the single H-bridge pair in the first phase are different.

[0073] If the total control signal for a single H-bridge pair in the second phase switches between levels P and O, then the duty cycles of the control signals at levels P and O of the two H-bridge units in the single H-bridge pair in the second phase are the same. If the total control signal for a single H-bridge pair in the second phase switches between levels N and O, then the duty cycles of the control signals at levels N and O of the two H-bridge units in the single H-bridge pair in the second phase are the same.

[0074] If the total control signal for a single H-bridge pair in the third phase switches between levels P and O, then the duty cycles of the control signals at levels P and O of the two H-bridge units in the single H-bridge pair in the third phase are the same. If the total control signal for a single H-bridge pair in the third phase switches between levels N and O, then the duty cycles of the control signals at levels N and O of the two H-bridge units in the single H-bridge pair in the third phase are the same.

[0075] For example, see Figure 5 In the first phase, the control signals X11 and X12 of the two H-bridge units in a single H-bridge pair have different duty cycles at the same level. That is, X11 and X12 switch between levels P and O, with different duty cycles for both levels P and O. In the second phase, the control signals X21 and X22 of the two H-bridge units in a single H-bridge pair have the same duty cycle at the same level. That is, X21 and X22 switch between levels N and O, with the same duty cycle for both levels N and O. In the third phase, the control signals X31 and X32 of the two H-bridge units in a single H-bridge pair have the same duty cycle at the same level. That is, X31 and X32 switch between levels N and O, with the same duty cycle for both levels N and O.

[0076] This application further refines the configuration principle of the duty cycle of the control signals for the two H-bridge units within a three-phase H-bridge: the duty cycles of the two H-bridge units are different only in the first phase, which switches frequently, while the duty cycles of the other two phases, which switch less frequently, remain the same. This differentiated configuration decouples or coordinates the impact of duty cycle adjustment (such as the redistribution of conduction losses) with the allocation strategy of switching frequency. While achieving centralized switching losses, it simplifies the control complexity of the second and third phases and allows for targeted adjustment of the conduction losses of the two H-bridge units within the first phase, achieving more refined thermal management.

[0077] As mentioned earlier, the duty cycles of the same level of the control signals of the two H-bridge units in a single H-bridge pair of the first phase are different. Therefore, the duty cycle of level P or level N of which H-bridge unit in the H-bridge pair is larger can be controlled based on the current flow direction of the first phase and the magnitude of the DC voltage of the two H-bridge units in the single H-bridge pair. Because if the DC voltages of the two H-bridge units are different, but the switching signals are still distributed in an average manner, it will lead to a serious imbalance in the DC power of the two H-bridge units. Therefore, the DC power of the two H-bridge units can be balanced in the above manner.

[0078] In this circuit, the alternating current in each phase has a direction. Based on the alternating current of the first phase, we can determine whether the current flow in the first phase is into or out of the CHB circuit. The direction of the current flow in the first phase can be understood as the direction of the alternating current in the first phase. A current flow into the CHB circuit means the alternating current flows from the AC terminal of the first phase to the H-bridge unit contained in the first phase of the CHB circuit; a current flow out of the CHB circuit means the alternating current flows from the H-bridge unit contained in the first phase of the CHB circuit to the AC terminal of the first phase.

[0079] Specifically, if the total control signal for a single H-bridge pair in the first phase switches between levels P and O, and the current flow in the first phase is into the CHB circuit, then the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage in the single H-bridge pair of the first phase is greater than the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage. Figure 5 For example, the duty cycle of level P of X11 is greater than the duty cycle of level P of X12. Therefore, under this operating condition, the control signal of the H-bridge unit with smaller DC voltage in the single H-bridge pair of the first phase is X11, and the control signal of the H-bridge unit with larger DC voltage in the single H-bridge pair of the first phase is X12.

[0080] In this embodiment, the total control signal for a single H-bridge pair in the first phase switches between levels P and O, and the current flow in the first phase is into the CHB circuit, indicating that the AC side is charging the DC side. At this time, the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage is greater than the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage. In other words, the duration of level P of the H-bridge unit with the smaller DC voltage in one cycle is longer than the duration of level P of the H-bridge unit with the larger DC voltage in one cycle. This is equivalent to the H-bridge unit with the smaller DC voltage charging the DC side for a longer period of time in one cycle, resulting in a much higher DC side voltage. This makes it easier to maintain a balance with the DC voltage of the H-bridge unit with the larger DC voltage, thereby achieving DC side power balance between the two H-bridge units.

[0081] If the total control signal for a single H-bridge pair in the first phase switches between levels P and O, and the current flow in the first phase is outflow from the CHB circuit, then the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage in the single H-bridge pair of the first phase is greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage. Figure 5 For example, the duty cycle of level P of X11 is greater than the duty cycle of level P of X12. Therefore, under this operating condition, the control signal of the H-bridge unit with a larger DC voltage in the single H-bridge pair of the first phase is X11, and the control signal of the H-bridge unit with a smaller DC voltage in the single H-bridge pair of the first phase is X12.

[0082] In this system, the total control signal for a single H-bridge pair in the first phase switches between levels P and O, and the current flow in the first phase is out of the CHB circuit, indicating that the DC side is discharging. At this time, the duty cycle of the control signal level P of the H-bridge unit with a larger DC voltage is greater than that of the control signal level P of the H-bridge unit with a smaller DC voltage. In other words, the duration of level P of the H-bridge unit with a larger DC voltage in one cycle is longer than that of the H-bridge unit with a smaller DC voltage in one cycle. This means that the H-bridge unit with a larger DC voltage discharges on the DC side for a longer period of time in one cycle, and its DC side voltage drops more, making it easier to maintain a balance with the DC voltage of the H-bridge unit with a smaller DC voltage, thereby achieving DC side power balance between the two H-bridge units.

[0083] Similarly, if the total control signal for a single H-bridge pair in the first phase switches between levels N and O, and the current flow in the first phase is into the CHB circuit, then this is the opposite of the case where the total control signal for a single H-bridge pair in the first phase switches between levels P and O, and the current flow in the first phase is into the CHB circuit. In this case, the duty cycle of level N of the control signal for the H-bridge unit with the larger DC voltage in the single H-bridge pair of the first phase is greater than the duty cycle of level N of the control signal for the H-bridge unit with the smaller DC voltage. That is, the duration of level N of the H-bridge unit with the larger DC voltage in one cycle is longer than the duration of level N of the H-bridge unit with the smaller DC voltage in one cycle, so as to achieve DC-side power balance between the two H-bridge units.

[0084] If the total control signal for a single H-bridge pair in the first phase switches between levels N and O, and the current flow in the first phase is out of the CHB circuit, then this is the opposite of the case where the total control signal for a single H-bridge pair in the first phase switches between levels P and O, and the current flow in the first phase is out of the CHB circuit. In this case, the duty cycle of level N of the control signal for the H-bridge unit with the smaller DC voltage in the single H-bridge pair of the first phase is greater than the duty cycle of level N of the control signal for the H-bridge unit with the larger DC voltage. That is, the duration of level N of the H-bridge unit with the smaller DC voltage in one cycle is longer than the duration of level N of the H-bridge unit with the larger DC voltage in one cycle, so as to achieve DC-side power balance between the two H-bridge units.

[0085] The embodiments of this application can optimize the energy distribution among different H-bridge units through the above method, avoid a certain H-bridge unit reaching its power limit or voltage imbalance too early, and effectively balance the DC-side load of each H-bridge unit, thereby improving overall reliability.

[0086] In some embodiments, the first phase is the phase with the minimum current, the phase with the maximum current, or the phase where the DC voltage of the two H-bridge units in a single H-bridge pair is unbalanced.

[0087] In this embodiment, the phase with the lowest current, the phase with the highest current, or the phase with the DC voltage imbalance between two H-bridge units in a single H-bridge pair can be selected as the phase with the most switching times in one cycle, i.e., the first phase. The number of switching times in one cycle can be understood as the number of times O and P are switched or the number of times O and N are switched in one cycle. Here, the cycle can be the switching cycle.

[0088] In one implementation, the phase with the lowest current among the three phases can be selected as the first phase. Since a larger current results in greater switching losses, selecting the phase with the lowest current as the phase that switches the most times in one cycle (i.e., the first phase) can reduce switching losses and achieve optimal efficiency. The aforementioned phase with the lowest current can be the phase with the smallest instantaneous current value among the three phases.

[0089] In another implementation, the phase with the highest current among the three phases can be selected as the phase with the most switching times in one cycle (i.e., the first phase). This minimizes the current ripple of that phase, thereby optimizing the quality of the output current. Specifically, the point of maximum current ripple amplitude is usually at the current peak value, and the phase with the highest current has a larger ripple due to the high saturation of the magnetic powder core inductance. Therefore, selecting the phase with the highest current as the phase with the most switching times in one cycle can optimize the current ripple of that phase, thereby optimizing the quality of the output current. The aforementioned phase with the highest current can be the phase with the largest instantaneous current value among the three phases.

[0090] In another embodiment, the phase with unbalanced DC voltages between the two H-bridge units in a single H-bridge pair can be selected as the first phase. Unbalanced DC voltages between the two H-bridge units in a single H-bridge pair can be understood as the DC voltages of the two H-bridge units being unequal or the absolute value of the difference being greater than a certain value. As mentioned earlier, the duty cycles of the same level of the control signals of the two H-bridge units in the first phase's single H-bridge pair are different. Based on the current flow direction of the first phase and the magnitude of the DC voltages of the two H-bridge units in the single H-bridge pair, the duty cycle of which H-bridge unit's level P or level N is larger can be controlled to balance the DC voltages of the two H-bridge units. Therefore, in this embodiment, the phase with unbalanced DC voltages between the two H-bridge units in a single H-bridge pair can be selected as the first phase to achieve DC voltage balance among the H-bridge units.

[0091] The specific choice of the phase with the largest current, the phase with the smallest current, or the phase with the unbalanced DC voltage between the two H-bridge units in a single H-bridge pair as the first phase can be determined based on actual needs.

[0092] In some embodiments, in S205, determining the target base vector required to synthesize the target voltage vector includes: Obtain the first target region where the target voltage vector is located; The target fundamental vectors required to determine the synthesized target voltage vector are the three fundamental voltage vectors corresponding to the first target region where the common-mode voltage is zero. Among them, the points where the six non-zero basic voltage vectors with zero common-mode voltage are located are used as vertices to form a first spatial vector hexagon; based on the zero basic voltage vector with zero common-mode voltage, the first spatial vector hexagon is divided into six first triangles; the first target region is the region where one of the first triangles is located.

[0093] As mentioned earlier, there are seven basic voltage vectors with zero common-mode voltage: PON, OPN, NPO, NOP, ONP, PNO, and OOO, which include six intermediate vectors and one zero vector. The six intermediate vectors are the six non-zero basic voltage vectors with zero common-mode voltage, and the zero vector is the zero basic voltage vector with zero common-mode voltage.

[0094] See Figure 6 , Figure 6 The spatial vector diagram shown is Figure 3 The difference between the spatial vector diagrams shown is that... Figure 6 The spatial vector diagram in the image shows 25 basic voltage vectors. Figure 6 The zero vector in the middle only contains OOO, and the zero vectors PPP and NNN are removed. That is, only the zero vector with a common-mode voltage of 0 is retained among the three zero vectors. Figure 6 The A-axis, B-axis, and C-axis in the figure are the three coordinate axes of the three-phase stationary coordinate system.

[0095] See Figure 6 The six non-zero fundamental voltage vectors with zero common-mode voltage, i.e., the six median vectors, serve as six vertices, forming the first spatial vector hexagon. That is, the first spatial vector hexagon is a hexagon with the aforementioned six median vectors with zero common-mode voltage as its vertices. The first spatial vector hexagon is a regular hexagon, and its center point is the aforementioned zero vector OOO with zero common-mode voltage.

[0096] Based on the zero fundamental voltage vector OOO, where the common-mode voltage is zero, the first spatial vector hexagon is divided into six first triangles by dividing it into 60-degree segments. Each first triangle has three vertices: two adjacent vertices of the first spatial vector hexagon and the center point OOO. The six first triangles are: the triangle with PON, OPN, and OOO as three vertices; the triangle with NPO, OPN, and OOO as three vertices; the triangle with NPO, NOP, and OOO as three vertices; the triangle with NOP, ONP, and OOO as three vertices; the triangle with ONP, PNO, and OOO as three vertices; and the triangle with PNO, PON, and OOO as three vertices.

[0097] In this embodiment, the region where the target voltage vector is located within the aforementioned first spatial vector hexagon is referred to as the first target region. The first target region can be any region containing a first triangle, determined based on the position of the target voltage vector. The three basic voltage vectors corresponding to the first target region with zero common-mode voltage are the basic voltage vectors corresponding to the three vertices of the first triangle corresponding to the first target region.

[0098] For example, assuming the first target region is a triangle with PON, OPN, and OOO as its three vertices, then the three basic voltage vectors with zero common-mode voltages corresponding to the first target region are PON, OPN, and OOO; assuming the first target region is a triangle with NPO, OPN, and OOO as its three vertices, then the three basic voltage vectors with zero common-mode voltages corresponding to the first target region are NPO, OPN, and OOO; assuming the first target region is a triangle with PNO, PON, and OOO as its three vertices, then the three basic voltage vectors with zero common-mode voltages corresponding to the first target region are PNO, PON, and OOO; and so on.

[0099] This application's embodiments utilize all fundamental vectors with zero common-mode voltage to construct a dedicated first spatial vector hexagon, and divide it into triangular target regions. This method transforms the complex common-mode voltage suppression problem into simple geometric positioning within a subspace, enabling rapid and accurate determination of the three target fundamental vectors required to synthesize the target voltage vector. It ensures that the common-mode voltage is always strictly clamped to zero during dynamic processes, while simultaneously ensuring that voltage utilization and modulation accuracy are not reduced. The method is simple and easy to implement in engineering.

[0100] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0101] Another specific implementation method for controlling CHB is provided, which includes: In S208, the DC voltage of each phase in the three-phase CHB circuit is obtained, the target phase is determined, and the category of the target phase is determined.

[0102] In a three-phase CHB circuit, the DC voltage of each phase is the sum of the DC-side voltages of the H-bridge units in that phase. For example, the DC voltage of phase A is the sum of the DC-side voltages of all the H-bridge units contained in phase A. Figure 1 For example, the DC voltage of phase A is the sum of the voltages between DCA1+ and DCA1-, between DCA2+ and DCA2-, ..., and between DCA2N+ and DCA2N-; the DC voltage of phase B is the sum of the DC-side voltages of all H-bridge units contained in phase B, and so on. Figure 1For example, the DC voltage of phase B is the sum of the voltages between DCB1+ and DCB1-, between DCB2+ and DCB2-, ..., and between DCB2N+ and DCB2N-; the DC voltage of phase C is the sum of the DC-side voltages of all H-bridge units included in phase C, with... Figure 1 For example, the DC voltage of phase C is the sum of the voltage between DCC1+ and DCC1-, the voltage between DCC2+ and DCC2-, ..., and the voltage between DCC2N+ and DCC2N-.

[0103] Based on the DC voltage of each phase, the phase with the largest DC voltage deviation can be identified as the target phase. The target phase can be understood as the phase whose DC voltage deviates the largest from the average DC voltage of all phases. It is categorized as either the phase with the largest DC voltage deviation or the phase with the smallest DC voltage deviation.

[0104] In S209, the zero-sequence injection amount is determined based on the type of the target phase and the current flow direction of the target phase.

[0105] The AC current of the target phase can be understood as the current on the AC side of the target phase. The root cause of phase-to-phase voltage imbalance is the unequal power absorbed or released by each phase, and the convergence direction of the voltage deviation directly depends on the polarity of the AC current. Obtaining the AC current information of the target phase can provide the most direct basis for subsequent control direction decisions.

[0106] In S210, zero-sequence injection control is performed on the three-phase CHB circuit based on the zero-sequence injection amount to reduce the DC voltage deviation between the target phase and other phases.

[0107] This application embodiment can determine the zero-sequence injection amount by using the DC voltage and AC current of the target phase. Based on the zero-sequence injection amount, zero-sequence injection control is performed on the three-phase CHB circuit, thereby reducing the DC voltage deviation between the target phase and other phases and achieving DC voltage balance among the phases. "Other phases" refers to all phases other than the target phase.

[0108] Specifically, by injecting zero sequence, it can interact with the original phase current to generate an additional zero sequence power, which is equivalent to creating a power transfer path between the unbalanced three phases. This allows the phase with the highest DC voltage to reduce its power absorption or increase its output power, while the phase with the lowest DC voltage increases its power absorption or decreases its output power, thereby achieving DC voltage balance among the phases.

[0109] This application first determines the target phase, i.e., the phase with the largest DC voltage deviation, based on the DC voltage of each phase of the three-phase CHB circuit. This allows for the focus of control resources, as not all phases require immediate intervention. This application concentrates computational and execution capabilities on the target phase that poses the greatest threat to system equilibrium. This results in a faster response speed than a control scheme that simultaneously adjusts all three phases indiscriminately, and avoids overshoot or oscillations that may be caused by mutual interference between the three-phase adjustment quantities. Then, based on the target phase and its AC current, the zero-sequence injection quantity is determined. Finally, zero-sequence injection control is performed on the three-phase CHB circuit according to the zero-sequence injection quantity, thereby reducing the DC voltage deviation between the target phase and the other two phases, so that the DC voltage of each phase is in a balanced or near-balanced state. Specifically, the root cause of DC voltage imbalance between phases is the unequal power absorbed or output by each phase. In this embodiment, by injecting zero sequence, a power transfer path can be created between the unbalanced three phases to control the phase with the highest DC voltage to reduce power absorption or increase power output, and to control the phase with the lowest DC voltage to increase power absorption or reduce power output. This achieves DC voltage balance between phases, ensuring that the DC load power of each phase is balanced when the DC side is connected to a load, thus avoiding system instability. When the DC side is used as the power supply side, it can make the voltage and current of the three phases on the AC side symmetrical, avoiding the generation of a large number of harmonics. At the same time, the voltage stress of the power switching devices in each phase is balanced, which can improve system reliability.

[0110] The foregoing embodiments have introduced the overall implementation process of the control method for a three-phase CHB circuit. The following will further define or expand the steps or related content.

[0111] In one possible implementation, S208 may specifically include: Based on the DC voltage of the target phase, determine the category of the target phase; the category is either the phase with the maximum DC voltage or the phase with the minimum DC voltage. Based on the AC current of the target phase, determine the current flow direction of the target phase; the current flow direction is either current flowing into the CHB circuit or current flowing out of the CHB circuit. Determine the zero-sequence injection amount based on the category and current flow direction.

[0112] In this embodiment, the average DC voltage of each phase can be calculated. If the DC voltage of the target phase is greater than the average value, the target phase can be classified as the phase with the highest DC voltage; if the DC voltage of the target phase is less than the average value, the target phase can be classified as the phase with the lowest DC voltage. Alternatively, the DC voltages of each phase can be compared to determine whether the target phase is classified as the phase with the highest or lowest DC voltage.

[0113] Each phase of the alternating current has a direction. Based on the AC current of the target phase, the direction of current flow in the target phase can be determined as either current flowing into or out of the CHB circuit. The direction of current flow in the target phase can be understood as the direction of AC current flow in that phase. Current flowing into the CHB circuit means the AC current flows from the AC terminal of the target phase to the H-bridge unit contained in the target phase of the CHB circuit; current flowing out of the CHB circuit means the AC current flows from the H-bridge unit contained in the target phase of the CHB circuit to the AC terminal of the target phase.

[0114] The embodiments of this application can determine the zero-sequence injection amount based on the type of the target phase and the current flow direction of the target phase. Based on the zero-sequence injection amount, zero-sequence injection control is performed on the three-phase CHB circuit to reduce the DC voltage deviation between the target phase and other phases and achieve DC voltage balance.

[0115] This application's embodiments determine the zero-sequence injection amount based on the target phase category and the target phase current direction, thereby abstracting a physically complex power balance problem into two simple logical variables: the target phase category and the target phase current direction. This dimensionality reduction decomposition can significantly simplify the design and implementation of the control algorithm, avoid solving complex nonlinear equations in real-time control, save computational resources, and improve the real-time performance of the control response.

[0116] In some embodiments, determining the zero-sequence injection amount based on category and current flow direction includes: If the category is the maximum DC voltage phase, then when the current flows into the CHB circuit, the zero-sequence injection amount is determined as the first zero-sequence component, and when the current flows out of the CHB circuit, the zero-sequence injection amount is determined as the second zero-sequence component. If the category is the minimum phase of DC voltage, then when the current flows into the CHB circuit, the zero-sequence injection amount is determined to be the second zero-sequence component, and when the current flows out of the CHB circuit, the zero-sequence injection amount is determined to be the first zero-sequence component. The first zero-order component is less than 0, and the second zero-order component is greater than 0.

[0117] In this embodiment, if the target phase has the highest DC voltage, its DC voltage needs to be reduced to achieve DC voltage balance with other phases. This means the target phase has excess energy, requiring either a reduction in its absorbed power or an increase in its output power. If the current in the target phase flows into the CHB circuit, it indicates the target phase is absorbing power from the AC side, causing its DC voltage to rise continuously. Injecting a negative first zero-sequence component reduces the target phase voltage, thus decreasing the power absorbed. When the absorbed power is less than the consumed power, the target phase's DC voltage decreases. Conversely, if the current in the target phase flows into the CHB circuit, it indicates the target phase is outputting power to the AC side, causing its DC voltage to decrease. However, since it has the highest DC voltage, its voltage needs to drop faster. Injecting a positive second zero-sequence component increases the target phase voltage, thereby increasing its output power. The higher the output power, the faster its DC voltage drops, rapidly reducing the deviation from other phases.

[0118] If the target phase has the lowest DC voltage, it's the opposite of the phase with the highest DC voltage. To achieve DC voltage balance with other phases, the target phase's DC voltage needs to be increased, meaning its absorbed power needs to be increased or its output power needs to be decreased. If the target phase's current flows into the CHB circuit, it means the target phase is absorbing power from the AC side, and its DC voltage will rise. However, since it's the phase with the lowest DC voltage, its voltage needs to rise faster. Injecting a positive second zero-sequence component will increase the target phase's phase voltage, thereby increasing its absorbed power and causing its DC voltage to rise faster, quickly reducing the deviation from other phases. If the target phase's current flows out of the CHB circuit, it means the target phase is outputting power to the AC side, and its DC voltage will decrease. Injecting a negative first zero-sequence component will decrease the target phase's phase voltage, thereby decreasing its output power and causing its DC voltage to rise.

[0119] This application further defines the zero-sequence injection amount under different categories and current flow directions based on the aforementioned embodiments, providing a directly implementable engineering solution that solves the problem of unclear zero-sequence injection direction in traditional methods. In this application, when the target phase is the phase with the highest DC voltage and current flows into the CHB circuit, injecting a negative zero-sequence component can reduce the modulation amplitude of that phase, decreasing its absorbed power and thus lowering the DC voltage. When current flows out of the CHB circuit, injecting a positive zero-sequence component can increase the modulation amplitude of that phase, increasing its output power, similarly achieving the goal of lowering the DC voltage. Conversely, for the phase with the lowest DC voltage, injecting a zero-sequence component of the opposite sign can increase its power, causing the DC voltage to rise. This sign rule fully conforms to the law of conservation of energy, ensuring the correctness of the adjustment in principle. Compared with traditional methods that require dynamic calculation of the injection amplitude based on the voltage deviation, this application determines the injection direction simply by judging the sign, with minimal computational load and extremely fast response speed, enabling adjustment to be completed within a microsecond-level control cycle. Meanwhile, this method is extremely robust, unaffected by changes in system parameters, load fluctuations, and power grid disturbances, and can maintain stable regulation even under extreme conditions.

[0120] In another possible implementation, S208 may specifically include: Based on the DC voltage of the target phase, determine the category of the target phase; the category is either the phase with the maximum DC voltage or the phase with the minimum DC voltage. Based on the AC current of the target phase, determine the current state of the target phase; the current state is either in the positive half-cycle or in the negative half-cycle. Obtain the operating mode of the three-phase CHB circuit; the operating mode is either inverter mode or rectifier mode. Determine the zero-sequence injection amount based on the category, operating mode, and current state.

[0121] The specific implementation process for determining the category of the target phase based on the DC voltage of the target phase can be found in the relevant descriptions in the foregoing embodiments, and will not be repeated here.

[0122] This application embodiment determines whether the current state of the target phase is in the positive or negative half-cycle based on whether the AC current of the target phase is greater than or less than 0. When the AC current of the target phase is 0, the current state can be considered to be in the positive half-cycle or the negative half-cycle. For example, if the AC current of the target phase is greater than or equal to 0, the current state is determined to be in the positive half-cycle; if the AC current of the target phase is less than 0, the current state is determined to be in the negative half-cycle. Alternatively, if the AC current of the target phase is greater than 0, the current state is determined to be in the positive half-cycle; if the AC current of the target phase is less than or equal to 0, the current state is determined to be in the negative half-cycle.

[0123] In addition, it is necessary to obtain the operating mode of the three-phase CHB circuit. Inverter mode means that it converts DC power to AC power, and the DC side is the power source; rectifier mode means that it converts AC power to DC power, and the AC side is the power source.

[0124] The embodiments of this application can determine the zero-sequence injection amount based on the type of the target phase, the current state of the target phase, and the operating mode of the three-phase CHB circuit. Based on the zero-sequence injection amount, the three-phase CHB circuit can be controlled by zero-sequence injection to reduce the DC voltage deviation between the target phase and other phases and achieve DC voltage balance.

[0125] This application provides an alternative technical approach for determining zero-sequence injection quantity. By employing a ternary judgment system based on the target phase category, the target phase current state, and the operating mode of the three-phase CHB circuit, the engineering feasibility of the control logic is further optimized. This approach is particularly suitable for application in three-phase CHB systems with clearly defined operating modes. Compared to the current direction-based judgment method in the previous embodiments, this scheme utilizes the equivalence between operating mode + current state and current direction, avoiding direct calculation of the instantaneous current direction. In practical engineering, the operating mode (rectifier mode or inverter mode) of the three-phase CHB circuit is usually explicitly given by the upper-level control system and is a stable, slow variable. The positive and negative half-cycles of the current can be easily obtained through simple zero-crossing detection circuits or software judgment, offering far stronger anti-interference capabilities than judging the direction of the instantaneous current value. This judgment method effectively avoids misjudgment of the flow direction caused by current sampling noise, significantly improving the reliability of the control system. The two different judgment logics provide engineers with flexible choices, allowing them to select the most suitable implementation method based on specific hardware conditions and application scenarios.

[0126] In some embodiments, determining the zero-sequence injection amount based on category, operating mode, and current state includes: If the category is the maximum DC voltage phase, then when the operating mode is rectification mode and the current state is in the positive half cycle, or when the operating mode is inverter mode and the current state is in the negative half cycle, the zero-sequence injection amount is determined as the first zero-sequence component; when the operating mode is rectification mode and the current state is in the negative half cycle, or when the operating mode is inverter mode and the current state is in the positive half cycle, the zero-sequence injection amount is determined as the second zero-sequence component. If the category is the minimum phase of DC voltage, then when the operating mode is rectification mode and the current state is in the positive half cycle, or when the operating mode is inverter mode and the current state is in the negative half cycle, the zero-sequence injection amount is determined as the second zero-sequence component; when the operating mode is rectification mode and the current state is in the negative half cycle, or when the operating mode is inverter mode and the current state is in the positive half cycle, the zero-sequence injection amount is determined as the first zero-sequence component. The first zero-order component is less than 0, and the second zero-order component is greater than 0.

[0127] In a three-phase CHB circuit, in rectification mode, power flows from the AC side to the DC side. The positive half-cycle of the current is equivalent to current flowing into the CHB circuit, and the negative half-cycle is equivalent to current flowing out of the CHB circuit. In inverter mode, power flows from the DC side to the AC side. The positive half-cycle of the current is equivalent to current flowing out of the CHB circuit, and the negative half-cycle is equivalent to current flowing into the CHB circuit.

[0128] Therefore, in rectification mode and during the positive half-cycle, or in inverter mode and during the negative half-cycle, current flows into the CHB circuit. If the target phase is the phase with the maximum DC voltage, based on the principle analysis of the aforementioned embodiment, a negative first zero-sequence component needs to be injected. If the target phase is the phase with the minimum DC voltage, based on the principle analysis of the aforementioned embodiment, a positive second zero-sequence component needs to be injected. In rectification mode and during the negative half-cycle, or in inverter mode and during the positive half-cycle, current flows out of the CHB circuit. If the target phase is the phase with the maximum DC voltage, based on the principle analysis of the aforementioned embodiment, a positive first zero-sequence component needs to be injected. If the target phase is the phase with the minimum DC voltage, based on the principle analysis of the aforementioned embodiment, a negative first zero-sequence component needs to be injected.

[0129] Based on the aforementioned embodiments, this application specifies in detail the zero-sequence injection sign rules for eight subdivided control scenarios, enabling precise equalization control across the entire current cycle. Traditional zero-sequence injection methods based on average values ​​often neglect the impact of the current half-cycle on the regulation effect, resulting in the zero-sequence injection direction being opposite to the expected direction during the negative current half-cycle. This not only fails to reduce voltage deviation but may also exacerbate the imbalance. This application, through in-depth analysis of the influence of zero-sequence voltage on phase power under different operating modes and current states, derives a clear sign mapping relationship. This precise full-cycle adjustment ensures that zero-sequence injection always proceeds in the direction of reducing voltage deviation throughout the entire current cycle, significantly improving equalization speed and regulation accuracy. Furthermore, this method is logically clear and easy to implement, requiring only simple conditional judgments and requiring no additional hardware resources, allowing for direct upgrades to existing controllers.

[0130] In some embodiments, the first zero-sequence component is -1 / 3 and the second zero-sequence component is 1 / 3.

[0131] This application specifies an optimal injection amplitude with a first zero-sequence component of -1 / 3 and a second zero-sequence component of 1 / 3. This achieves the fastest inter-phase voltage equalization speed without overmodulation, while significantly simplifying the control algorithm. This application selects ±1 / 3 as a fixed injection amplitude, fully utilizing the entire margin of the linear modulation region. This enables maximum inter-phase power transfer within each control cycle, resulting in the fastest equalization speed. Compared to the traditional method of dynamically adjusting the injection amplitude based on the voltage deviation, the fixed-amplitude injection method eliminates the need for proportional-integral calculations or deviation calculations, greatly reducing the controller's computational burden and improving system real-time performance. Furthermore, fixed-amplitude injection avoids problems caused by excessive or insufficient injection amounts due to deviation calculation errors, eliminating parameter tuning in the control system, reducing debugging difficulty, and improving system stability and robustness.

[0132] In some embodiments, for each phase of a three-phase CHB circuit, the phase circuit includes a series branch formed by 2N H-bridge units, which are paired up to form N H-bridge pairs; N is a positive integer. If the category is the phase with the largest DC voltage and the zero-sequence injection amount is the first zero-sequence component, then the duty cycle of the control signal level N of the H-bridge unit with the larger DC voltage in a single H-bridge pair of the target phase is greater than the duty cycle of the control signal level N of the H-bridge unit with the smaller DC voltage. If the category is the phase with the largest DC voltage and the zero-sequence injection amount is the second zero-sequence component, then the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage in a single H-bridge pair of the target phase is greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage. If the category is the minimum phase of DC voltage and the zero-sequence injection quantity is the second zero-sequence component, then the duty cycle of the control signal level P of the H-bridge unit with smaller DC voltage in a single H-bridge pair of the target phase is greater than the duty cycle of the control signal level P of the H-bridge unit with larger DC voltage. If the category is the minimum DC voltage phase and the zero-sequence injection quantity is the first zero-sequence component, then the duty cycle of the control signal level N of the H-bridge unit with the smaller DC voltage in a single H-bridge pair of the target phase is greater than the duty cycle of the control signal level N of the H-bridge unit with the larger DC voltage.

[0133] For the first case: the category is the phase with the largest DC voltage and the zero-sequence injection is the first zero-sequence component. In this case, if level N is dominant, the duty cycle of level N of the control signal of the H-bridge unit with the larger DC voltage in the single H-bridge pair of the target phase is greater than the duty cycle of level N of the control signal of the H-bridge unit with the smaller DC voltage.

[0134] Specifically, based on the aforementioned embodiments, when the target phase is the phase with the maximum DC voltage and the zero-sequence injection amount is the first zero-sequence component, the current flow direction of the target phase is current flowing into the CHB circuit, which is equivalent to a current greater than 0. Since level N represents a voltage less than 0, the power is less than 0, which is equivalent to DC-side discharge and a decrease in DC voltage. At this time, the duty cycle of level N of the control signal of the H-bridge unit with the larger DC voltage is greater than the duty cycle of level N of the control signal of the H-bridge unit with the smaller DC voltage. This means that the H-bridge unit with the larger DC voltage has a longer discharge time and a greater DC voltage drop, which narrows the DC voltage difference with the H-bridge unit with the smaller DC voltage, achieving DC voltage balance between the two H-bridge units in a single H-bridge pair of the target phase.

[0135] For the second case: the category is the phase with the largest DC voltage and the zero-sequence injection is the second zero-sequence component. In this case, if level P is dominant, the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage in the single H-bridge pair of the target phase is greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage.

[0136] Specifically, based on the aforementioned embodiments, when the target phase is the phase with the maximum DC voltage and the zero-sequence injection quantity is the second zero-sequence component, the current flow direction of the target phase is current flowing out of the CHB circuit, which is equivalent to the current being less than 0. Since the level P represents a voltage greater than 0, the power is less than 0, which is equivalent to DC-side discharge and a decrease in DC voltage. At this time, the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage is greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage. This means that the H-bridge unit with the larger DC voltage has a longer discharge time and a greater DC voltage drop, which narrows the DC voltage difference with the H-bridge unit with the smaller DC voltage, thus achieving DC voltage balance between the two H-bridge units in a single H-bridge pair of the target phase.

[0137] For the third case: the category is the minimum phase of DC voltage and the zero-sequence injection quantity is the second zero-sequence component. In this case, if level P is dominant, the duty cycle of the control signal level P of the H-bridge unit with smaller DC voltage in a single H-bridge pair of the target phase is greater than the duty cycle of the control signal level P of the H-bridge unit with larger DC voltage.

[0138] Specifically, based on the aforementioned embodiments, when the target phase is the phase with the lowest DC voltage and the zero-sequence injection is the second zero-sequence component, the current flow of the target phase is into the CHB circuit, which is equivalent to a current greater than 0. Since level P represents a voltage greater than 0, the power is greater than 0, which is equivalent to charging the DC side and increasing the DC voltage. At this time, the duty cycle of the control signal level P of the H-bridge unit with the lower DC voltage is greater than the duty cycle of the control signal level P of the H-bridge unit with the higher DC voltage. This means that the H-bridge unit with the lower DC voltage charges the DC side for a longer time, resulting in a greater DC voltage increase. This reduces the DC voltage difference with the H-bridge unit with the higher DC voltage, achieving DC voltage balance between the two H-bridge units in a single H-bridge pair of the target phase.

[0139] For the fourth case: the category is the minimum DC voltage phase and the zero-sequence injection quantity is the first zero-sequence component. In this case, if level N is dominant, the duty cycle of level N of the control signal of the H-bridge unit with smaller DC voltage in a single H-bridge pair of the target phase is greater than the duty cycle of level N of the control signal of the H-bridge unit with larger DC voltage.

[0140] Specifically, based on the aforementioned embodiments, when the target phase is the phase with the lowest DC voltage and the zero-sequence injection is the first zero-sequence component, the current flow direction of the target phase is outflow from the CHB circuit, which is equivalent to a current less than 0. Since level N indicates a voltage less than 0, the power is greater than 0, which is equivalent to charging the DC side and increasing the DC voltage. At this time, the duty cycle of level N of the control signal of the H-bridge unit with the lower DC voltage is greater than the duty cycle of level N of the control signal of the H-bridge unit with the higher DC voltage. This means that the H-bridge unit with the lower DC voltage charges the DC side for a longer time, resulting in a greater rise in DC voltage. This reduces the difference in DC voltage between the H-bridge unit and the H-bridge unit with the higher DC voltage, achieving DC voltage balance between the two H-bridge units in a single H-bridge pair of the target phase.

[0141] This application innovatively combines inter-phase voltage balancing with intra-phase H-bridge unit voltage balancing. Without adding extra control loops, it simultaneously solves the two core voltage balancing problems of a three-phase CHB circuit, significantly improving the overall system performance. Traditional control methods typically treat inter-phase and intra-phase balancing as two independent control tasks, designing separate control loops. This not only increases controller resource consumption but also easily leads to mutual interference between the two loops, affecting the regulation effect. This application's embodiment, through a clever H-bridge unit pairing strategy and duty cycle allocation rules, achieves decoupling of the two balancing control methods: while regulating inter-phase power through zero-sequence injection, it balances the DC voltage of each unit within a phase by adjusting the P-level and N-level duty cycles of two units in the same H-bridge pair, without changing the total output voltage of that phase. This method requires no additional sensors or hardware circuits, and can be implemented solely through software algorithms, significantly reducing system costs. Furthermore, the simultaneous operation of inter-phase and intra-phase balancing greatly shortens the overall system balancing time and improves the system's dynamic response performance. This method is particularly suitable for three-phase CHB circuits with a large number of cascaded units, and can effectively solve the voltage balance problem caused by multiple cascaded units.

[0142] In some embodiments, the target phase is the phase whose absolute value of the difference between the DC voltage and the average value is the largest and the absolute value is greater than a preset threshold; the average value is the average value of the DC voltage of each phase.

[0143] In this embodiment, the average DC voltage of each phase can be calculated first, and then the absolute value of the difference between the DC voltage of each phase and the average value can be calculated. The phase with the largest absolute value, which is greater than a preset threshold, is selected as the target phase. If the number of target phases is greater than one, one of the multiple target phases can be randomly selected as the final target phase.

[0144] The preset threshold value can be set according to actual needs, such as 10V or 20V, etc.

[0145] This application optimizes the target phase determination criteria. By introducing a preset threshold, it enables on-demand activation of phase-to-phase voltage balancing control, avoiding frequent control system actions and significantly improving system stability and device lifespan. Traditional balancing control methods often initiate adjustment whenever a voltage deviation exists, leading to frequent modulation wave adjustments within small deviation ranges, increasing unnecessary switching losses and electromagnetic interference, and potentially causing system oscillations. This application only determines a phase as the target phase and activates balancing control when the absolute value of the difference between its DC voltage and the average value is the largest and exceeds the preset threshold. This keeps the three-phase voltage deviation within acceptable limits and avoids ineffective adjustments under small deviations. Furthermore, selecting the phase with the largest absolute difference as the sole target phase ensures that each adjustment prioritizes addressing the most severe imbalance, improving adjustment efficiency. When multiple phase deviations exceed the preset threshold, only one phase is processed at a time, avoiding mutual interference between multiple adjustment actions and simplifying control logic. The preset threshold can be flexibly set according to the accuracy requirements of the actual application, exhibiting strong versatility and adaptability.

[0146] In some embodiments, after performing zero-sequence injection control on the three-phase CHB circuit based on the zero-sequence injection amount, the method further includes: Reacquire the DC voltage of each phase and jump to the step of determining the target phase based on the DC voltage of each phase to continue execution until the target phase no longer exists.

[0147] After adjusting based on the target phase to reduce the DC voltage deviation between the target phase and other phases, in order to further determine whether the DC voltage of each phase has reached equilibrium, the DC voltage of each phase can be reacquired and the process can jump to S202 to continue execution. If the target phase still exists, the adjustment based on the target phase continues. If the target phase does not exist, it means that the DC voltage of each phase has been balanced and the adjustment can be stopped.

[0148] The above-mentioned S201-S207 mainly solve the problems of intra-phase H-bridge unit equalization and common-mode voltage, while S208-S209 mainly solve the inter-phase equalization problem. Both can be implemented independently or in combination. For example, when determining the control signals for each phase in S207, if the target phase is the first phase, the equalization effect of the H-bridge units within the target phase can be further optimized by combining the zero-sequence injection amount determined in S212 and the duty cycle adjustment rule in S203.

[0149] The following are device embodiments of this application. For details not described in detail, please refer to the corresponding method embodiments described above.

[0150] Figure 7 A schematic diagram of the control device for a three-phase CHB circuit provided in an embodiment of this application is shown. For ease of explanation, only the parts related to the embodiment of this application are shown, and are described in detail below: For each phase of a three-phase CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, with each M H-bridge unit paired to form an H-bridge pair; M and N are positive integers. For example... Figure 7 As shown, the control device 4 of the three-phase CHB circuit includes: an acquisition module 41 and an adjustment module 42.

[0151] The acquisition module 41 is used to acquire the current direction of the first phase and the DC voltage of each H-bridge unit in each H-bridge pair group of the first phase, wherein the first phase is any one of phase A, phase B and phase C; The adjustment module 42 is used to adjust the duty cycle of a specific level within the H-bridge pair according to the current flow direction and the overall control signal when the DC voltage of each H-bridge unit in the H-bridge pair is uneven, so as to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair.

[0152] Figure 8 This is a schematic diagram of the control device provided in an embodiment of this application. Figure 8 As shown, the control device 5 in this embodiment includes a processor 50 and a memory 51. The memory 51 stores a computer program 52. When the processor 50 executes the computer program 52, it implements the steps in the various method embodiments described above. Alternatively, when the processor 50 executes the computer program 52, it implements the functions of each module / unit in the various device embodiments described above.

[0153] For example, computer program 52 may be divided into one or more modules / units, which are stored in memory 51 and executed by processor 50 to complete this application. The one or more modules / units may be a series of computer program instruction segments capable of performing a specific function, which describe the execution process of computer program 52 in control device 5.

[0154] The control device 5 may include, but is not limited to, a processor 50 and a memory 51. Those skilled in the art will understand that... Figure 8 This is merely an example of control device 5 and does not constitute a limitation on control device 5. It may include more or fewer components than shown, or combine certain components, or different components. For example, control device 5 may also include input / output devices, network access devices, buses, etc.

[0155] The processor 50 can be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0156] The memory 51 can be an internal storage unit of the control device 5, such as a hard disk or RAM of the control device 5. The memory 51 can also be an external storage device of the control device 5, such as a plug-in hard disk, Smart Media Card (SMC), Secure Digital (SD) card, or Flash Card equipped on the control device 5. Furthermore, the memory 51 can include both internal and external storage units of the control device 5. The memory 51 is used to store the computer program 52 and other programs and data required by the control device 5. The memory 51 can also be used to temporarily store data that has been output or will be output.

[0157] For the sake of simplicity and clarity, only the above-described functional modules / units are used as examples. In practical applications, the functions described above can be assigned to different functional modules / units as needed. These modules / units can be implemented in hardware, software, or a combination of both.

[0158] This application embodiment also provides a CHB circuit, including circuits corresponding to the three phases and the control device as described above; For each phase of the CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, and every M H-bridge units are paired to form an H-bridge pair; M and N are both positive integers. The circuits corresponding to each of the three phases are all controlled by the control equipment.

[0159] This application also provides a power supply device including the CHB circuit described above.

[0160] This application also provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the methods described in the above-described method embodiments.

[0161] This application also provides a computer program product, including a computer program. When the computer program is executed by a processor, it implements the methods in the above-described method embodiments.

[0162] Computer programs include computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. Computer-readable media can include: any entity or device capable of carrying computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc.

[0163] In the above embodiments, the descriptions of each embodiment have their own emphasis. Parts not detailed or described in a particular embodiment can be referred to in the relevant descriptions of other embodiments. Unless otherwise specified or in conflict with logic, the terminology and / or descriptions between different embodiments are consistent and can be referenced interchangeably. Technical features in different embodiments can be combined to form new embodiments based on their inherent logical relationships.

[0164] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A control method for a three-phase CHB circuit, characterized in that, For each phase of the three-phase CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, and each M H-bridge unit is paired to form an H-bridge pair; M and N are both positive integers. Obtain the current direction of the first phase and the DC voltage of each H-bridge unit in the group of each H-bridge pair of the first phase, wherein the first phase is any one of phase A, phase B and phase C; If the DC voltage of each H-bridge unit in the H-bridge pair is not equal, the duty cycle of a specific level in the H-bridge pair is adjusted according to the current flow direction of the H-bridge pair and the overall control signal to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair.

2. The control method for a three-phase CHB circuit according to claim 1, characterized in that, When the total control signal of the first phase switches between level P and level O, level P is the specific level; When the total control signal of the first phase switches between level N and level O, level N is the specific level.

3. The control method for a three-phase CHB circuit according to claim 1, characterized in that, The adjustment of the duty cycle of a specific level within the H-bridge pair based on the current flow direction and the overall control signal specifically includes: If the current flows into the CHB circuit, and the total control signal switches between level P and level O, then the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage in the target H-bridge pair should be greater than the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage. If the current flows out of the CHB circuit, and the total control signal switches between level P and level O, then the duty cycle of the control signal level P of the H-bridge unit with the larger DC voltage in the target H-bridge pair should be greater than the duty cycle of the control signal level P of the H-bridge unit with the smaller DC voltage. If the current flows into the CHB circuit, and the total control signal switches between level N and level O, then the duty cycle of level N of the control signal of the H-bridge unit with a larger DC voltage in the target H-bridge pair should be greater than the duty cycle of level N of the control signal of the H-bridge unit with a smaller DC voltage. If the current flows out of the CHB circuit, and the total control signal switches between levels N and O, then the duty cycle of level N of the control signal of the H-bridge unit with the smaller DC voltage in the target H-bridge pair should be greater than the duty cycle of level N of the control signal of the H-bridge unit with the larger DC voltage.

4. The control method for the three-phase CHB circuit according to any one of claims 1-3, characterized in that, The method further includes: One H-bridge pair is selected from each of the three phases to form the three-phase H-bridge pair group; Determine the target base vector required to synthesize the target voltage vector, wherein the common-mode voltage of the target base vector is zero; Based on the target basic vector, determine the total control signal corresponding to each individual H-bridge pair in each phase; Based on the total control signal corresponding to each individual H-bridge pair in each phase, the control signal corresponding to each H-bridge unit in each phase is determined; wherein, the control signals of the two H-bridge units in the same H-bridge pair are combined to form the total control signal of the H-bridge pair, and the control signals of the two H-bridge units in the same H-bridge pair are different. The control signals corresponding to each H-bridge unit of each phase are used to control each H-bridge unit of each phase.

5. The control method for a three-phase CHB circuit according to claim 4, characterized in that, The number of level switching of the total control signal of a single H-bridge pair in the first phase within one cycle is the first count, and the number of level switching of the total control signal of a single H-bridge pair in the second and third phases within one cycle is the second count. The first count is twice the second count. The first phase, the second phase, and the third phase are different phases, and are randomly assigned to be phase A, phase B, and phase C. The sum of the number of level switching times of the control signals of the two H-bridge units of the same H-bridge pair within one cycle is equal to the total number of level switching times of the control signals of the H-bridge pair within one cycle.

6. The control method for a three-phase CHB circuit according to claim 4, characterized in that, The step of determining the control signal corresponding to each H-bridge unit of each phase based on the total control signal corresponding to each individual H-bridge pair of each phase includes: The modulation wave, first carrier, and second carrier of each phase are acquired; wherein, for each phase, the first carrier and second carrier of that phase have the same frequency and are out of phase; the frequency of the first carrier of the first phase is twice the frequency of the first carrier of the second and third phases; the phase difference between the first carrier of the second phase and the first carrier of the third phase is 90 degrees; the first phase, the second phase, and the third phase are different phases and are randomly assigned to phase A, phase B, and phase C. The modulated wave of each phase is compared with the first carrier wave to generate the first control signal for each phase; The modulated wave of each phase is compared with the second carrier wave to generate the second control signal for each phase; Among them, the first control signal and the second control signal of each phase are the control signals corresponding to the two H-bridge units of the same H-bridge pair of each phase, respectively.

7. The control method for a three-phase CHB circuit according to any one of claims 1-3, characterized in that, The method further includes: Obtain the DC voltage of each phase in the three-phase CHB circuit; Based on the DC voltage of each phase, the target phase is determined, and the category of the target phase is determined; the target phase is the phase with the largest DC voltage deviation, and the category is the phase with the largest DC voltage or the phase with the smallest DC voltage. The zero-sequence injection amount is determined based on the type of the target phase and the current flow direction of the target phase; Based on the zero-sequence injection amount, zero-sequence injection control is performed on the three-phase CHB circuit to reduce the DC voltage deviation between the target phase and other phases.

8. The control method for a three-phase CHB circuit according to claim 7, characterized in that, The step of determining the zero-sequence injection amount based on the type of the target phase and the current flow direction of the target phase includes: If the category is the DC voltage maximum phase, then when the current flow direction is current flowing into the CHB circuit, the zero-sequence injection amount is determined as the first zero-sequence component, and when the current flow direction is current flowing out of the CHB circuit, the zero-sequence injection amount is determined as the second zero-sequence component. If the category is the minimum phase of DC voltage, then when the current flow direction is current flowing into the CHB circuit, the zero-sequence injection amount is determined to be the second zero-sequence component, and when the current flow direction is current flowing out of the CHB circuit, the zero-sequence injection amount is determined to be the first zero-sequence component. Wherein, the first zero-sequence component is -1 / 3, and the second zero-sequence component is 1 / 3.

9. A control device for a three-phase CHB circuit, characterized in that, For each phase of the three-phase CHB circuit, the phase circuit includes a series branch formed by M*N H-bridge units, and each M H-bridge unit is paired to form an H-bridge pair; M and N are both positive integers. The acquisition module is used to acquire the current direction of the first phase and the DC voltage of each H-bridge unit in each H-bridge pair group of the first phase, wherein the first phase is any one of phase A, phase B and phase C; The adjustment module is used to adjust the duty cycle of a specific level within the H-bridge pair according to the current flow direction and the overall control signal when the DC voltage of each H-bridge unit in the H-bridge pair is uneven, so as to reduce the DC voltage deviation between each H-bridge unit in the H-bridge pair.

10. A CHB circuit, characterized in that, This includes the circuits and control equipment corresponding to each of the three phases; The control device is used to execute the control method for the three-phase CHB circuit as described in any one of claims 1 to 9; the circuits corresponding to the three phases are all controlled by the control device.

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